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Source at commit 79eda5bb5ffae55f05b99691c9070993a12d507f created 10 years 11 months ago. By Lars-Peter Clausen, slcd: Use generic dmaengine interface | |
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1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * Copyright (C) 2010, Maarten ter Huurne <maarten@treewalker.org> |
4 | * JZ4720/JZ4740 SoC LCD framebuffer driver |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms of the GNU General Public License as published by the |
8 | * Free Software Foundation; either version 2 of the License, or (at your |
9 | * option) any later version. |
10 | * |
11 | * You should have received a copy of the GNU General Public License along |
12 | * with this program; if not, write to the Free Software Foundation, Inc., |
13 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
14 | * |
15 | */ |
16 | |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> |
19 | #include <linux/mutex.h> |
20 | #include <linux/platform_device.h> |
21 | |
22 | #include <linux/clk.h> |
23 | #include <linux/delay.h> |
24 | |
25 | #include <linux/console.h> |
26 | #include <linux/fb.h> |
27 | |
28 | #include <linux/interrupt.h> |
29 | #include <linux/dma-mapping.h> |
30 | |
31 | #include <asm/mach-jz4740/dma.h> |
32 | #include <asm/mach-jz4740/gpio.h> |
33 | #include <asm/mach-jz4740/jz4740_fb.h> |
34 | |
35 | #include "jz4740_lcd.h" |
36 | #include "jz4740_slcd.h" |
37 | |
38 | #define FB_A320TV_OFF 0 |
39 | #define FB_A320TV_NTSC 1 |
40 | #define FB_A320TV_PAL50 2 |
41 | #define FB_A320TV_PAL60 3 |
42 | #define FB_A320TV_PAL_M 4 |
43 | #define FB_A320TV_LAST 4 |
44 | |
45 | static const char *jzfb_tv_out_norm[] = { |
46 | "off", "ntsc", "pal", "pal-60", "pal-m", |
47 | }; |
48 | |
49 | static struct fb_fix_screeninfo jzfb_fix = { |
50 | .id = "JZ4740 SLCD FB", |
51 | .type = FB_TYPE_PACKED_PIXELS, |
52 | .visual = FB_VISUAL_TRUECOLOR, |
53 | .xpanstep = 0, |
54 | .ypanstep = 1, |
55 | .ywrapstep = 0, |
56 | .accel = FB_ACCEL_NONE, |
57 | }; |
58 | |
59 | const static struct jz_gpio_bulk_request jz_slcd_ctrl_pins[] = { |
60 | JZ_GPIO_BULK_PIN(LCD_PCLK), |
61 | JZ_GPIO_BULK_PIN(SLCD_RS), |
62 | JZ_GPIO_BULK_PIN(SLCD_CS), |
63 | }; |
64 | |
65 | const static struct jz_gpio_bulk_request jz_slcd_data_pins[] = { |
66 | JZ_GPIO_BULK_PIN(LCD_DATA0), |
67 | JZ_GPIO_BULK_PIN(LCD_DATA1), |
68 | JZ_GPIO_BULK_PIN(LCD_DATA2), |
69 | JZ_GPIO_BULK_PIN(LCD_DATA3), |
70 | JZ_GPIO_BULK_PIN(LCD_DATA4), |
71 | JZ_GPIO_BULK_PIN(LCD_DATA5), |
72 | JZ_GPIO_BULK_PIN(LCD_DATA6), |
73 | JZ_GPIO_BULK_PIN(LCD_DATA7), |
74 | JZ_GPIO_BULK_PIN(LCD_DATA8), |
75 | JZ_GPIO_BULK_PIN(LCD_DATA9), |
76 | JZ_GPIO_BULK_PIN(LCD_DATA10), |
77 | JZ_GPIO_BULK_PIN(LCD_DATA11), |
78 | JZ_GPIO_BULK_PIN(LCD_DATA12), |
79 | JZ_GPIO_BULK_PIN(LCD_DATA13), |
80 | JZ_GPIO_BULK_PIN(LCD_DATA14), |
81 | JZ_GPIO_BULK_PIN(LCD_DATA15), |
82 | JZ_GPIO_BULK_PIN(LCD_DATA16), |
83 | JZ_GPIO_BULK_PIN(LCD_DATA17), |
84 | }; |
85 | |
86 | static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb) |
87 | { |
88 | return ARRAY_SIZE(jz_slcd_ctrl_pins); |
89 | } |
90 | |
91 | static unsigned int jzfb_num_data_pins(struct jzfb *jzfb) |
92 | { |
93 | switch (jzfb->pdata->lcd_type) { |
94 | case JZ_LCD_TYPE_SMART_PARALLEL_8_BIT: |
95 | return 8; |
96 | case JZ_LCD_TYPE_SMART_PARALLEL_16_BIT: |
97 | return 16; |
98 | case JZ_LCD_TYPE_SMART_PARALLEL_18_BIT: |
99 | return 18; |
100 | default: |
101 | return 0; |
102 | } |
103 | } |
104 | |
105 | static void jzfb_free_gpio_pins(struct jzfb *jzfb) |
106 | { |
107 | jz_gpio_bulk_free(jz_slcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
108 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
109 | /* serial */ |
110 | jz_gpio_bulk_free(&jz_slcd_data_pins[15], 1); |
111 | } else { |
112 | /* parallel */ |
113 | jz_gpio_bulk_free(jz_slcd_data_pins, |
114 | jzfb_num_data_pins(jzfb)); |
115 | } |
116 | } |
117 | |
118 | static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, |
119 | unsigned blue, unsigned transp, struct fb_info *fb) |
120 | { |
121 | if (regno >= 16) |
122 | return -EINVAL; |
123 | |
124 | red = (red * ((1 << fb->var.red.length ) - 1)) / ((1 << 16) - 1); |
125 | green = (green * ((1 << fb->var.green.length) - 1)) / ((1 << 16) - 1); |
126 | blue = (blue * ((1 << fb->var.blue.length ) - 1)) / ((1 << 16) - 1); |
127 | |
128 | ((uint32_t *)fb->pseudo_palette)[regno] = |
129 | (red << fb->var.red.offset ) | |
130 | (green << fb->var.green.offset) | |
131 | (blue << fb->var.blue.offset ); |
132 | |
133 | return 0; |
134 | } |
135 | |
136 | static int jzfb_get_controller_bpp(struct jzfb *jzfb) |
137 | { |
138 | switch (jzfb->pdata->bpp) { |
139 | case 18: |
140 | case 24: |
141 | return 32; |
142 | case 15: |
143 | return 16; |
144 | default: |
145 | return jzfb->pdata->bpp; |
146 | } |
147 | } |
148 | |
149 | static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb, struct fb_var_screeninfo *var) |
150 | { |
151 | size_t i; |
152 | struct fb_videomode *mode = jzfb->pdata->modes; |
153 | |
154 | for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) { |
155 | if (mode->xres == var->xres && mode->yres == var->yres) |
156 | return mode; |
157 | } |
158 | |
159 | return NULL; |
160 | } |
161 | |
162 | static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb) |
163 | { |
164 | struct jzfb *jzfb = fb->par; |
165 | struct fb_videomode *mode; |
166 | |
167 | if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) && |
168 | var->bits_per_pixel != jzfb->pdata->bpp) |
169 | return -EINVAL; |
170 | |
171 | mode = jzfb_get_mode(jzfb, var); |
172 | if (mode == NULL) |
173 | return -EINVAL; |
174 | |
175 | fb_videomode_to_var(var, mode); |
176 | |
177 | /* Reserve space for double buffering. */ |
178 | var->yres_virtual = var->yres * 2; |
179 | |
180 | switch (jzfb->pdata->bpp) { |
181 | case 8: |
182 | break; |
183 | case 15: |
184 | var->red.offset = 10; |
185 | var->red.length = 5; |
186 | var->green.offset = 5; |
187 | var->green.length = 5; |
188 | var->blue.offset = 0; |
189 | var->blue.length = 5; |
190 | break; |
191 | case 16: |
192 | var->red.offset = 11; |
193 | var->red.length = 5; |
194 | var->green.offset = 5; |
195 | var->green.length = 6; |
196 | var->blue.offset = 0; |
197 | var->blue.length = 5; |
198 | break; |
199 | case 18: |
200 | var->red.offset = 16; |
201 | var->red.length = 6; |
202 | var->green.offset = 8; |
203 | var->green.length = 6; |
204 | var->blue.offset = 0; |
205 | var->blue.length = 6; |
206 | var->bits_per_pixel = 32; |
207 | break; |
208 | case 32: |
209 | case 24: |
210 | var->transp.offset = 24; |
211 | var->transp.length = 8; |
212 | var->red.offset = 16; |
213 | var->red.length = 8; |
214 | var->green.offset = 8; |
215 | var->green.length = 8; |
216 | var->blue.offset = 0; |
217 | var->blue.length = 8; |
218 | var->bits_per_pixel = 32; |
219 | break; |
220 | default: |
221 | break; |
222 | } |
223 | |
224 | return 0; |
225 | } |
226 | |
227 | static void jzfb_refresh_work_complete(void *param) |
228 | { |
229 | struct jzfb *jzfb = param; |
230 | complete_all(&jzfb->dma_completion); |
231 | } |
232 | |
233 | static void jzfb_disable_dma(struct jzfb *jzfb) |
234 | { |
235 | dmaengine_terminate_all(jzfb->dma); |
236 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
237 | writeb(readb(jzfb->base + JZ_REG_SLCD_CTRL) & ~SLCD_CTRL_DMA_EN, |
238 | jzfb->base + JZ_REG_SLCD_CTRL); |
239 | } |
240 | |
241 | static void jzfb_upload_frame_dma(struct jzfb *jzfb) |
242 | { |
243 | struct fb_info *fb = jzfb->fb; |
244 | struct fb_videomode *mode = fb->mode; |
245 | __u32 offset = fb->fix.line_length * fb->var.yoffset; |
246 | __u32 size = fb->fix.line_length * mode->yres; |
247 | struct dma_async_tx_descriptor *desc; |
248 | |
249 | /* Ensure that the data to be uploaded is in memory. */ |
250 | dma_cache_sync(fb->device, jzfb->vidmem + offset, size, |
251 | DMA_TO_DEVICE); |
252 | |
253 | desc = dmaengine_prep_slave_single(jzfb->dma, DMA_MEM_TO_DEV, |
254 | jzfb->vidmem_phys + offset, size, DMA_PREP_INTERRUPT); |
255 | if (!desc) |
256 | return; |
257 | |
258 | desc->callback = jzfb_refresh_work_complete; |
259 | desc->callback_param = jzfb; |
260 | dmaengine_submit(desc); |
261 | |
262 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
263 | writeb(readb(jzfb->base + JZ_REG_SLCD_CTRL) | SLCD_CTRL_DMA_EN, |
264 | jzfb->base + JZ_REG_SLCD_CTRL); |
265 | dma_async_issue_pending(jzfb->dma); |
266 | } |
267 | |
268 | static void jzfb_upload_frame_cpu(struct jzfb *jzfb) |
269 | { |
270 | const int num_pixels = jzfb->fb->mode->xres * jzfb->fb->mode->yres; |
271 | uint16_t *p = jzfb->vidmem; |
272 | int i; |
273 | |
274 | jzfb_disable_dma(jzfb); |
275 | for (i = 0; i < num_pixels; i++) { |
276 | uint16_t rgb = *p++; |
277 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
278 | writel(SLCD_DATA_RS_DATA | rgb, jzfb->base + JZ_REG_SLCD_DATA); |
279 | } |
280 | } |
281 | |
282 | static void jzfb_refresh_work(struct work_struct *work) |
283 | { |
284 | struct jzfb *jzfb = container_of(work, struct jzfb, refresh_work.work); |
285 | |
286 | mutex_lock(&jzfb->lock); |
287 | if (jzfb->is_enabled) { |
288 | if (1) { |
289 | int interval; |
290 | |
291 | if (jzfb->dma_completion.done) { |
292 | if (jzfb->refresh_on_pan) |
293 | interval = HZ / 5; |
294 | else |
295 | interval = HZ / 60; |
296 | jzfb->refresh_on_pan = 0; |
297 | |
298 | INIT_COMPLETION(jzfb->dma_completion); |
299 | jzfb_upload_frame_dma(jzfb); |
300 | } else |
301 | interval = HZ / 250; |
302 | |
303 | schedule_delayed_work(&jzfb->refresh_work, interval); |
304 | } else { |
305 | jzfb_upload_frame_cpu(jzfb); |
306 | schedule_delayed_work(&jzfb->refresh_work, HZ / 10); |
307 | } |
308 | } |
309 | mutex_unlock(&jzfb->lock); |
310 | } |
311 | |
312 | static int jzfb_set_par(struct fb_info *info) |
313 | { |
314 | struct jzfb *jzfb = info->par; |
315 | struct fb_var_screeninfo *var = &info->var; |
316 | struct fb_videomode *mode; |
317 | uint16_t slcd_cfg; |
318 | |
319 | mode = jzfb_get_mode(jzfb, var); |
320 | if (mode == NULL) |
321 | return -EINVAL; |
322 | |
323 | info->mode = mode; |
324 | |
325 | slcd_cfg = SLCD_CFG_BURST_8_WORD; |
326 | /* command size */ |
327 | slcd_cfg |= (jzfb->pdata->lcd_type & 3) << SLCD_CFG_CWIDTH_BIT; |
328 | /* data size */ |
329 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
330 | /* serial */ |
331 | unsigned int num_bits; |
332 | switch (jzfb->pdata->lcd_type) { |
333 | case JZ_LCD_TYPE_SMART_SERIAL_8_BIT: |
334 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x1; |
335 | num_bits = 8; |
336 | break; |
337 | case JZ_LCD_TYPE_SMART_SERIAL_16_BIT: |
338 | slcd_cfg |= SLCD_CFG_DWIDTH_16; |
339 | num_bits = 16; |
340 | break; |
341 | case JZ_LCD_TYPE_SMART_SERIAL_18_BIT: |
342 | slcd_cfg |= SLCD_CFG_DWIDTH_18; |
343 | num_bits = 18; |
344 | break; |
345 | default: |
346 | num_bits = 0; |
347 | break; |
348 | } |
349 | if (num_bits != jzfb->pdata->bpp) { |
350 | dev_err(&jzfb->pdev->dev, |
351 | "Data size (%d) does not match bpp (%d)\n", |
352 | num_bits, jzfb->pdata->bpp); |
353 | } |
354 | slcd_cfg |= SLCD_CFG_TYPE_SERIAL; |
355 | } else { |
356 | /* parallel */ |
357 | switch (jzfb->pdata->bpp) { |
358 | case 8: |
359 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x1; |
360 | break; |
361 | case 15: |
362 | case 16: |
363 | switch (jzfb->pdata->lcd_type) { |
364 | case JZ_LCD_TYPE_SMART_PARALLEL_8_BIT: |
365 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x2; |
366 | break; |
367 | default: |
368 | slcd_cfg |= SLCD_CFG_DWIDTH_16; |
369 | break; |
370 | } |
371 | break; |
372 | case 18: |
373 | switch (jzfb->pdata->lcd_type) { |
374 | case JZ_LCD_TYPE_SMART_PARALLEL_8_BIT: |
375 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x3; |
376 | break; |
377 | case JZ_LCD_TYPE_SMART_PARALLEL_16_BIT: |
378 | slcd_cfg |= SLCD_CFG_DWIDTH_9_x2; |
379 | break; |
380 | case JZ_LCD_TYPE_SMART_PARALLEL_18_BIT: |
381 | slcd_cfg |= SLCD_CFG_DWIDTH_18; |
382 | break; |
383 | default: |
384 | break; |
385 | } |
386 | break; |
387 | case 24: |
388 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x3; |
389 | break; |
390 | default: |
391 | dev_err(&jzfb->pdev->dev, |
392 | "Unsupported value for bpp: %d\n", |
393 | jzfb->pdata->bpp); |
394 | } |
395 | slcd_cfg |= SLCD_CFG_TYPE_PARALLEL; |
396 | } |
397 | if (!jzfb->pdata->chip_select_active_low) |
398 | slcd_cfg |= SLCD_CFG_CS_ACTIVE_HIGH; |
399 | if (!jzfb->pdata->register_select_active_low) |
400 | slcd_cfg |= SLCD_CFG_RS_CMD_HIGH; |
401 | if (!jzfb->pdata->pixclk_falling_edge) |
402 | slcd_cfg |= SLCD_CFG_CLK_ACTIVE_RISING; |
403 | |
404 | #if 0 |
405 | // TODO(MtH): Compute rate from refresh or vice versa. |
406 | if (mode->pixclock) { |
407 | rate = PICOS2KHZ(mode->pixclock) * 1000; |
408 | mode->refresh = rate / vt / ht; |
409 | } else { |
410 | if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) |
411 | rate = mode->refresh * (vt + 2 * mode->xres) * ht; |
412 | else |
413 | rate = mode->refresh * vt * ht; |
414 | |
415 | mode->pixclock = KHZ2PICOS(rate / 1000); |
416 | } |
417 | #endif |
418 | |
419 | mutex_lock(&jzfb->lock); |
420 | if (!jzfb->is_enabled) |
421 | clk_prepare_enable(jzfb->ldclk); |
422 | |
423 | // TODO(MtH): We should not change config while DMA might be running. |
424 | writew(slcd_cfg, jzfb->base + JZ_REG_SLCD_CFG); |
425 | |
426 | if (!jzfb->is_enabled) |
427 | clk_disable_unprepare(jzfb->ldclk); |
428 | mutex_unlock(&jzfb->lock); |
429 | |
430 | // TODO(MtH): Use maximum transfer speed that panel can handle. |
431 | // ILI9325 can do 10 MHz. |
432 | clk_set_rate(jzfb->lpclk, 12000000); |
433 | clk_set_rate(jzfb->ldclk, 42000000); |
434 | |
435 | return 0; |
436 | } |
437 | |
438 | static void jzfb_enable(struct jzfb *jzfb) |
439 | { |
440 | uint32_t ctrl; |
441 | |
442 | clk_prepare_enable(jzfb->ldclk); |
443 | |
444 | jz_gpio_bulk_resume(jz_slcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
445 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
446 | /* serial */ |
447 | jz_gpio_bulk_resume(&jz_slcd_data_pins[15], 1); |
448 | } else { |
449 | /* parallel */ |
450 | jz_gpio_bulk_resume(jz_slcd_data_pins, |
451 | jzfb_num_data_pins(jzfb)); |
452 | } |
453 | jzfb_disable_dma(jzfb); |
454 | complete_all(&jzfb->dma_completion); |
455 | jzfb->panel->enable(jzfb); |
456 | |
457 | ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); |
458 | ctrl |= JZ_LCD_CTRL_ENABLE; |
459 | ctrl &= ~JZ_LCD_CTRL_DISABLE; |
460 | writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); |
461 | |
462 | schedule_delayed_work(&jzfb->refresh_work, 0); |
463 | } |
464 | |
465 | static void jzfb_disable(struct jzfb *jzfb) |
466 | { |
467 | /* It is safe but wasteful to call refresh_work() while disabled. */ |
468 | cancel_delayed_work_sync(&jzfb->refresh_work); |
469 | |
470 | /* Abort any DMA transfer that might be in progress and allow direct |
471 | writes to the panel. */ |
472 | jzfb_disable_dma(jzfb); |
473 | complete_all(&jzfb->dma_completion); |
474 | |
475 | jzfb->panel->disable(jzfb); |
476 | jz_gpio_bulk_suspend(jz_slcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
477 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
478 | /* serial */ |
479 | jz_gpio_bulk_suspend(&jz_slcd_data_pins[15], 1); |
480 | } else { |
481 | /* parallel */ |
482 | jz_gpio_bulk_suspend(jz_slcd_data_pins, |
483 | jzfb_num_data_pins(jzfb)); |
484 | } |
485 | |
486 | clk_disable_unprepare(jzfb->ldclk); |
487 | } |
488 | |
489 | static int jzfb_blank(int blank_mode, struct fb_info *info) |
490 | { |
491 | struct jzfb *jzfb = info->par; |
492 | int ret = 0; |
493 | int new_enabled = (blank_mode == FB_BLANK_UNBLANK); |
494 | |
495 | mutex_lock(&jzfb->lock); |
496 | if (new_enabled) { |
497 | if (!jzfb->is_enabled) |
498 | jzfb_enable(jzfb); |
499 | } else { |
500 | if (jzfb->is_enabled) { |
501 | /* No sleep in TV-out mode. */ |
502 | if (jzfb->tv_out == FB_A320TV_OFF) |
503 | jzfb_disable(jzfb); |
504 | else |
505 | ret = -EBUSY; |
506 | } |
507 | } |
508 | if (!ret) |
509 | jzfb->is_enabled = new_enabled; |
510 | mutex_unlock(&jzfb->lock); |
511 | |
512 | return ret; |
513 | } |
514 | |
515 | static int jzfb_wait_for_vsync(struct fb_info *info) |
516 | { |
517 | struct jzfb *jzfb = info->par; |
518 | |
519 | if (jzfb->tv_out != FB_A320TV_OFF && |
520 | !jzfb->tv_out_vsync) |
521 | return 0; |
522 | return wait_for_completion_interruptible(&jzfb->dma_completion); |
523 | } |
524 | |
525 | static int jzfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
526 | { |
527 | struct jzfb *jzfb = info->par; |
528 | info->var.yoffset = var->yoffset; |
529 | |
530 | /* Ensure that the data to be uploaded is in memory. */ |
531 | dma_cache_sync(&jzfb->pdev->dev, jzfb->vidmem |
532 | + info->fix.line_length * var->yoffset, |
533 | info->fix.line_length * var->yres, |
534 | DMA_TO_DEVICE); |
535 | |
536 | /* update frame start address for TV-out mode */ |
537 | (*jzfb->framedesc)[1].addr = jzfb->vidmem_phys |
538 | + info->fix.line_length * var->yoffset; |
539 | |
540 | jzfb_wait_for_vsync(info); |
541 | |
542 | jzfb->refresh_on_pan = 1; |
543 | flush_delayed_work(&jzfb->refresh_work); |
544 | return 0; |
545 | } |
546 | |
547 | static int jzfb_mmap(struct fb_info *info, struct vm_area_struct *vma) |
548 | { |
549 | const unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; |
550 | const unsigned long size = vma->vm_end - vma->vm_start; |
551 | |
552 | if (offset + size > info->fix.smem_len) |
553 | return -EINVAL; |
554 | |
555 | if (remap_pfn_range(vma, vma->vm_start, |
556 | (info->fix.smem_start + offset) >> PAGE_SHIFT, |
557 | size, vma->vm_page_prot)) |
558 | return -EAGAIN; |
559 | |
560 | return 0; |
561 | } |
562 | |
563 | static int jzfb_alloc_devmem(struct jzfb *jzfb) |
564 | { |
565 | int max_linesize = 0, max_framesize = 0; |
566 | int bytes_per_pixel; |
567 | struct fb_videomode *mode = jzfb->pdata->modes; |
568 | void *page; |
569 | int i; |
570 | |
571 | for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) { |
572 | if (max_linesize < mode->xres) |
573 | max_linesize = mode->xres; |
574 | if (max_framesize < mode->xres * mode->yres) |
575 | max_framesize = mode->xres * mode->yres; |
576 | } |
577 | |
578 | bytes_per_pixel = jzfb_get_controller_bpp(jzfb) >> 3; |
579 | max_linesize *= bytes_per_pixel; |
580 | max_framesize *= bytes_per_pixel; |
581 | |
582 | jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev, |
583 | sizeof(*jzfb->framedesc), |
584 | &jzfb->framedesc_phys, GFP_KERNEL); |
585 | if (!jzfb->framedesc) |
586 | return -ENOMEM; |
587 | |
588 | jzfb->blackline_size = max_linesize; |
589 | jzfb->blackline = dma_alloc_coherent(&jzfb->pdev->dev, |
590 | jzfb->blackline_size, |
591 | &jzfb->blackline_phys, GFP_KERNEL); |
592 | if (!jzfb->blackline) |
593 | goto err_free_framedesc; |
594 | |
595 | /* Set the black line to black... */ |
596 | memset(jzfb->blackline, 0, jzfb->blackline_size); |
597 | |
598 | /* reserve memory for two frames to allow double buffering */ |
599 | jzfb->vidmem_size = PAGE_ALIGN(max_framesize * 2); |
600 | jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev, |
601 | jzfb->vidmem_size, |
602 | &jzfb->vidmem_phys, GFP_KERNEL); |
603 | |
604 | if (!jzfb->vidmem) |
605 | goto err_free_blackline; |
606 | |
607 | for (page = jzfb->vidmem; |
608 | page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size); |
609 | page += PAGE_SIZE) { |
610 | SetPageReserved(virt_to_page(page)); |
611 | } |
612 | |
613 | for (i = 0; i < 3; i++) |
614 | (*jzfb->framedesc)[i].next = jzfb->framedesc_phys |
615 | + ((i + 1) % 3) * sizeof(struct jzfb_framedesc); |
616 | (*jzfb->framedesc)[0].addr = (*jzfb->framedesc)[2].addr = |
617 | jzfb->blackline_phys; |
618 | (*jzfb->framedesc)[0].id = 0xdadabeeb; |
619 | (*jzfb->framedesc)[2].id = 0xfadefeed; |
620 | (*jzfb->framedesc)[0].cmd = (*jzfb->framedesc)[2].cmd = |
621 | jzfb->blackline_size / 4; |
622 | (*jzfb->framedesc)[1].addr = jzfb->vidmem_phys; |
623 | (*jzfb->framedesc)[1].id = 0xdeafbead; |
624 | (*jzfb->framedesc)[1].cmd = (max_framesize / 4) |
625 | | JZ_LCD_CMD_EOF_IRQ | JZ_LCD_CMD_SOF_IRQ; |
626 | |
627 | return 0; |
628 | |
629 | err_free_blackline: |
630 | dma_free_coherent(&jzfb->pdev->dev, jzfb->blackline_size, |
631 | jzfb->blackline, jzfb->blackline_phys); |
632 | err_free_framedesc: |
633 | dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), |
634 | jzfb->framedesc, jzfb->framedesc_phys); |
635 | return -ENOMEM; |
636 | } |
637 | |
638 | static void jzfb_free_devmem(struct jzfb *jzfb) |
639 | { |
640 | dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size, |
641 | jzfb->vidmem, jzfb->vidmem_phys); |
642 | dma_free_coherent(&jzfb->pdev->dev, jzfb->blackline_size, |
643 | jzfb->blackline, jzfb->blackline_phys); |
644 | dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), |
645 | jzfb->framedesc, jzfb->framedesc_phys); |
646 | } |
647 | |
648 | static int jzfb_tv_out(struct jzfb *jzfb, unsigned int mode) |
649 | { |
650 | int blank = jzfb->is_enabled ? FB_BLANK_UNBLANK : FB_BLANK_POWERDOWN; |
651 | struct fb_event event = { |
652 | .info = jzfb->fb, |
653 | .data = &blank, |
654 | }; |
655 | |
656 | printk("A320 TV out: %d\n", mode); |
657 | if (mode > FB_A320TV_LAST) |
658 | return -EINVAL; |
659 | if (mode == jzfb->tv_out) |
660 | return 0; |
661 | |
662 | if (mode != FB_A320TV_OFF) { |
663 | cancel_delayed_work_sync(&jzfb->refresh_work); |
664 | /* Abort any DMA transfer that might be in progress and |
665 | allow direct writes to the panel. */ |
666 | jzfb_disable_dma(jzfb); |
667 | jzfb->panel->disable(jzfb); |
668 | complete_all(&jzfb->dma_completion); |
669 | |
670 | /* set up LCD controller for TV output */ |
671 | |
672 | writel(JZ_LCD_CFG_HSYNC_ACTIVE_LOW | |
673 | JZ_LCD_CFG_VSYNC_ACTIVE_LOW, |
674 | jzfb->base + JZ_REG_LCD_CFG); |
675 | |
676 | /* V-Sync pulse end position */ |
677 | writel(10, jzfb->base + JZ_REG_LCD_VSYNC); |
678 | |
679 | if (mode == FB_A320TV_PAL50) { |
680 | /* PAL 50 Hz */ |
681 | /* H-Sync pulse start position */ |
682 | writel(0x0000007d, jzfb->base + JZ_REG_LCD_HSYNC); |
683 | /* virtual area size */ |
684 | writel(0x036c0112, jzfb->base + JZ_REG_LCD_VAT); |
685 | /* horizontal start/end point */ |
686 | writel(0x02240364, jzfb->base + JZ_REG_LCD_DAH); |
687 | /* vertical start/end point */ |
688 | writel(0x001a010c, jzfb->base + JZ_REG_LCD_DAV); |
689 | } else { |
690 | /* NTSC and PAL 60 Hz */ |
691 | writel(0x0000003c, jzfb->base + JZ_REG_LCD_HSYNC); |
692 | writel(0x02e00110, jzfb->base + JZ_REG_LCD_VAT); |
693 | writel(0x019902d9, jzfb->base + JZ_REG_LCD_DAH); |
694 | writel(0x001c010e, jzfb->base + JZ_REG_LCD_DAV); |
695 | } |
696 | writel(0, jzfb->base + JZ_REG_LCD_PS); |
697 | writel(0, jzfb->base + JZ_REG_LCD_CLS); |
698 | writel(0, jzfb->base + JZ_REG_LCD_SPL); |
699 | writel(0, jzfb->base + JZ_REG_LCD_REV); |
700 | /* reset status register */ |
701 | writel(0, jzfb->base + JZ_REG_LCD_STATE); |
702 | |
703 | /* tell LCDC about the frame descriptor address */ |
704 | writel(jzfb->framedesc_phys, jzfb->base + JZ_REG_LCD_DA0); |
705 | |
706 | writel(JZ_LCD_CTRL_BURST_16 | JZ_LCD_CTRL_ENABLE | |
707 | JZ_LCD_CTRL_BPP_15_16 | |
708 | JZ_LCD_CTRL_EOF_IRQ | JZ_LCD_CTRL_SOF_IRQ, |
709 | jzfb->base + JZ_REG_LCD_CTRL); |
710 | } else { |
711 | /* disable EOF/SOF interrupts */ |
712 | unsigned long ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); |
713 | ctrl &= ~(JZ_LCD_CTRL_EOF_IRQ | JZ_LCD_CTRL_SOF_IRQ); |
714 | writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); |
715 | |
716 | /* disable LCD controller and re-enable SLCD */ |
717 | writel(JZ_LCD_CFG_SLCD, jzfb->base + JZ_REG_LCD_CFG); |
718 | jzfb->panel->enable(jzfb); |
719 | |
720 | jzfb->refresh_on_pan = 0; |
721 | complete_all(&jzfb->dma_completion); |
722 | schedule_delayed_work(&jzfb->refresh_work, 0); |
723 | } |
724 | |
725 | /* reaffirm the current blanking state, to trigger a backlight update */ |
726 | console_lock(); |
727 | fb_notifier_call_chain(FB_EVENT_BLANK, &event); |
728 | console_unlock(); |
729 | jzfb->tv_out = mode; |
730 | return 0; |
731 | } |
732 | |
733 | static ssize_t jzfb_tv_out_show(struct device *dev, struct device_attribute *attr, |
734 | char *buf) |
735 | { |
736 | struct jzfb *jzfb = dev_get_drvdata(dev); |
737 | |
738 | if (jzfb->tv_out > FB_A320TV_LAST) { |
739 | dev_err(dev, "Unknown norm for TV-out\n"); |
740 | return -1; |
741 | } |
742 | |
743 | return sprintf(buf, "%s\n", jzfb_tv_out_norm[jzfb->tv_out]); |
744 | } |
745 | |
746 | static ssize_t jzfb_tv_out_store(struct device *dev, struct device_attribute *attr, |
747 | const char *buf, size_t n) |
748 | { |
749 | size_t i; |
750 | struct jzfb *jzfb = dev_get_drvdata(dev); |
751 | |
752 | for (i = 0; i <= FB_A320TV_LAST; i++) { |
753 | if (sysfs_streq(jzfb_tv_out_norm[i], buf)) { |
754 | jzfb_tv_out(jzfb, i); |
755 | return n; |
756 | } |
757 | } |
758 | return -EINVAL; |
759 | } |
760 | |
761 | static DEVICE_ATTR(tv_out, 0644, jzfb_tv_out_show, jzfb_tv_out_store); |
762 | |
763 | static ssize_t jzfb_vsync_show(struct device *dev, struct device_attribute *attr, |
764 | char *buf) |
765 | { |
766 | struct jzfb *jzfb = dev_get_drvdata(dev); |
767 | return sprintf(buf, "%u\n", jzfb->tv_out_vsync); |
768 | } |
769 | |
770 | static ssize_t jzfb_vsync_store(struct device *dev, struct device_attribute *attr, |
771 | const char *buf, size_t n) |
772 | { |
773 | struct jzfb *jzfb = dev_get_drvdata(dev); |
774 | unsigned int vsync; |
775 | |
776 | if (sscanf(buf, "%u", &vsync) < 1) |
777 | return -EINVAL; |
778 | |
779 | jzfb->tv_out_vsync = vsync; |
780 | return n; |
781 | } |
782 | |
783 | static DEVICE_ATTR(tv_out_vsync, 0644, jzfb_vsync_show, jzfb_vsync_store); |
784 | |
785 | static ssize_t jzfb_panel_show(struct device *dev, struct device_attribute *attr, |
786 | char *buf) |
787 | { |
788 | struct jzfb *jzfb = dev_get_drvdata(dev); |
789 | return sprintf(buf, "%s\n", jzfb->panel->name); |
790 | } |
791 | |
792 | static ssize_t jzfb_panel_store(struct device *dev, struct device_attribute *attr, |
793 | const char *buf, size_t n) |
794 | { |
795 | struct jzfb *jzfb = dev_get_drvdata(dev); |
796 | const struct jz_slcd_panel *panel = jz_slcd_panel_from_name(buf); |
797 | |
798 | if (!panel) { |
799 | dev_err(dev, "Unknown SLCD panel: %s\n", buf); |
800 | return -EINVAL; |
801 | } |
802 | |
803 | if (panel != jzfb->panel) { |
804 | jzfb->panel->disable(jzfb); |
805 | jzfb->panel->exit(jzfb); |
806 | jzfb->panel = panel; |
807 | panel->init(jzfb); |
808 | panel->enable(jzfb); |
809 | } |
810 | return n; |
811 | } |
812 | |
813 | static DEVICE_ATTR(panel, 0644, jzfb_panel_show, jzfb_panel_store); |
814 | |
815 | static struct fb_ops jzfb_ops = { |
816 | .owner = THIS_MODULE, |
817 | .fb_check_var = jzfb_check_var, |
818 | .fb_set_par = jzfb_set_par, |
819 | .fb_setcolreg = jzfb_setcolreg, |
820 | .fb_blank = jzfb_blank, |
821 | .fb_pan_display = jzfb_pan_display, |
822 | .fb_fillrect = sys_fillrect, |
823 | .fb_copyarea = sys_copyarea, |
824 | .fb_imageblit = sys_imageblit, |
825 | .fb_mmap = jzfb_mmap, |
826 | }; |
827 | |
828 | static irqreturn_t jz4740_lcd_irq(int irq, void *dev_id) |
829 | { |
830 | struct jzfb *jzfb = dev_id; |
831 | unsigned long state = readl(jzfb->base + JZ_REG_LCD_STATE); |
832 | |
833 | if (state & JZ_LCD_STATE_SOF) { |
834 | INIT_COMPLETION(jzfb->dma_completion); |
835 | state &= ~JZ_LCD_STATE_SOF; |
836 | } else { |
837 | complete_all(&jzfb->dma_completion); |
838 | state &= ~JZ_LCD_STATE_EOF; |
839 | } |
840 | |
841 | /* Acknowledge the interrupt */ |
842 | writel(state, jzfb->base + JZ_REG_LCD_STATE); |
843 | return IRQ_HANDLED; |
844 | } |
845 | |
846 | static int jzfb_probe(struct platform_device *pdev) |
847 | { |
848 | int ret; |
849 | struct jzfb *jzfb; |
850 | struct fb_info *fb; |
851 | struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data; |
852 | struct dma_slave_config config; |
853 | struct resource *mem; |
854 | dma_cap_mask_t dma_mask; |
855 | |
856 | if (!pdata) { |
857 | dev_err(&pdev->dev, "Missing platform data\n"); |
858 | return -ENOENT; |
859 | } |
860 | |
861 | fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev); |
862 | |
863 | if (!fb) { |
864 | dev_err(&pdev->dev, "Failed to allocate framebuffer device\n"); |
865 | return -ENOMEM; |
866 | } |
867 | |
868 | fb->fbops = &jzfb_ops; |
869 | fb->flags = FBINFO_DEFAULT; |
870 | |
871 | jzfb = fb->par; |
872 | jzfb->pdata = pdata; |
873 | jzfb->pdev = pdev; |
874 | |
875 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
876 | jzfb->base = devm_ioremap_resource(&pdev->dev, mem); |
877 | if (IS_ERR(jzfb->base)) { |
878 | ret = PTR_ERR(jzfb->base); |
879 | goto err_framebuffer_release; |
880 | } |
881 | |
882 | jzfb->tv_out = FB_A320TV_OFF; |
883 | jzfb->tv_out_vsync = 1; |
884 | jzfb->refresh_on_pan = 0; |
885 | init_completion(&jzfb->dma_completion); |
886 | complete_all(&jzfb->dma_completion); |
887 | |
888 | dma_cap_zero(dma_mask); |
889 | dma_cap_set(DMA_SLAVE, dma_mask); |
890 | |
891 | jzfb->dma = dma_request_channel(dma_mask, NULL, NULL); |
892 | if (!jzfb->dma) { |
893 | dev_err(&pdev->dev, "Failed to get DMA channel\n"); |
894 | ret = -EBUSY; |
895 | goto err_framebuffer_release; |
896 | } |
897 | |
898 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
899 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
900 | config.dst_maxburst = 16; |
901 | config.slave_id = JZ4740_DMA_TYPE_SLCD; |
902 | config.dst_addr = mem->start + JZ_REG_SLCD_FIFO; |
903 | |
904 | dmaengine_slave_config(jzfb->dma, &config); |
905 | |
906 | jzfb->ldclk = clk_get(&pdev->dev, "lcd"); |
907 | if (IS_ERR(jzfb->ldclk)) { |
908 | ret = PTR_ERR(jzfb->ldclk); |
909 | dev_err(&pdev->dev, "Failed to get lcd clock: %d\n", ret); |
910 | goto err_free_dma; |
911 | } |
912 | |
913 | jzfb->lpclk = clk_get(&pdev->dev, "lcd_pclk"); |
914 | if (IS_ERR(jzfb->lpclk)) { |
915 | ret = PTR_ERR(jzfb->lpclk); |
916 | dev_err(&pdev->dev, "Failed to get lcd pixel clock: %d\n", ret); |
917 | goto err_put_ldclk; |
918 | } |
919 | |
920 | platform_set_drvdata(pdev, jzfb); |
921 | |
922 | fb_videomode_to_modelist(pdata->modes, pdata->num_modes, |
923 | &fb->modelist); |
924 | fb->mode = pdata->modes; |
925 | |
926 | fb_videomode_to_var(&fb->var, fb->mode); |
927 | fb->var.bits_per_pixel = pdata->bpp; |
928 | jzfb_check_var(&fb->var, fb); |
929 | |
930 | ret = jzfb_alloc_devmem(jzfb); |
931 | if (ret) { |
932 | dev_err(&pdev->dev, "Failed to allocate video memory\n"); |
933 | goto err_put_lpclk; |
934 | } |
935 | |
936 | fb->fix = jzfb_fix; |
937 | fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8; |
938 | fb->fix.mmio_start = mem->start; |
939 | fb->fix.mmio_len = resource_size(mem); |
940 | fb->fix.smem_start = jzfb->vidmem_phys; |
941 | fb->fix.smem_len = fb->fix.line_length * fb->var.yres_virtual; |
942 | fb->screen_base = jzfb->vidmem; |
943 | fb->pseudo_palette = jzfb->pseudo_palette; |
944 | |
945 | fb_alloc_cmap(&fb->cmap, 256, 0); |
946 | |
947 | mutex_init(&jzfb->lock); |
948 | |
949 | clk_prepare_enable(jzfb->ldclk); |
950 | jzfb->is_enabled = 1; |
951 | |
952 | writel(JZ_LCD_CFG_SLCD, jzfb->base + JZ_REG_LCD_CFG); |
953 | writeb(0, jzfb->base + JZ_REG_SLCD_CTRL); |
954 | |
955 | jzfb_set_par(fb); |
956 | |
957 | jz_gpio_bulk_request(jz_slcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
958 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
959 | /* serial */ |
960 | jz_gpio_bulk_request(&jz_slcd_data_pins[15], 1); |
961 | } else { |
962 | /* parallel */ |
963 | jz_gpio_bulk_request(jz_slcd_data_pins, |
964 | jzfb_num_data_pins(jzfb)); |
965 | } |
966 | |
967 | ret = request_irq(JZ4740_IRQ_LCD, jz4740_lcd_irq, 0, "LCD", jzfb); |
968 | if (ret) { |
969 | dev_err(&pdev->dev, "Failed to request IRQ\n"); |
970 | goto err_free_devmem; |
971 | } |
972 | |
973 | jzfb->panel = jz_slcd_panels_probe(jzfb); |
974 | if (!jzfb->panel) { |
975 | dev_err(&pdev->dev, "Failed to find panel driver\n"); |
976 | ret = -ENOENT; |
977 | goto err_free_irq; |
978 | } |
979 | jzfb_disable_dma(jzfb); |
980 | jzfb->panel->init(jzfb); |
981 | |
982 | jzfb->panel->enable(jzfb); |
983 | |
984 | ret = register_framebuffer(fb); |
985 | if (ret) { |
986 | dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret); |
987 | goto err_free_panel; |
988 | } |
989 | |
990 | jzfb->fb = fb; |
991 | fb_prepare_logo(jzfb->fb, 0); |
992 | fb_show_logo(jzfb->fb, 0); |
993 | |
994 | INIT_DELAYED_WORK(&jzfb->refresh_work, jzfb_refresh_work); |
995 | schedule_delayed_work(&jzfb->refresh_work, 0); |
996 | |
997 | ret = device_create_file(&pdev->dev, &dev_attr_panel); |
998 | if (ret) |
999 | goto err_cancel_work; |
1000 | |
1001 | ret = device_create_file(&pdev->dev, &dev_attr_tv_out); |
1002 | if (ret) |
1003 | goto err_remove_file_panel; |
1004 | |
1005 | ret = device_create_file(&pdev->dev, &dev_attr_tv_out_vsync); |
1006 | if (!ret) |
1007 | return 0; |
1008 | |
1009 | device_remove_file(&pdev->dev, &dev_attr_tv_out); |
1010 | err_remove_file_panel: |
1011 | device_remove_file(&pdev->dev, &dev_attr_panel); |
1012 | err_cancel_work: |
1013 | cancel_delayed_work_sync(&jzfb->refresh_work); |
1014 | err_free_panel: |
1015 | jzfb->panel->exit(jzfb); |
1016 | err_free_irq: |
1017 | free_irq(JZ4740_IRQ_LCD, jzfb); |
1018 | err_free_devmem: |
1019 | jzfb_free_gpio_pins(jzfb); |
1020 | |
1021 | fb_dealloc_cmap(&fb->cmap); |
1022 | jzfb_free_devmem(jzfb); |
1023 | err_put_lpclk: |
1024 | clk_put(jzfb->lpclk); |
1025 | err_put_ldclk: |
1026 | clk_put(jzfb->ldclk); |
1027 | err_free_dma: |
1028 | dma_release_channel(jzfb->dma); |
1029 | err_framebuffer_release: |
1030 | framebuffer_release(fb); |
1031 | return ret; |
1032 | } |
1033 | |
1034 | static int jzfb_remove(struct platform_device *pdev) |
1035 | { |
1036 | struct jzfb *jzfb = platform_get_drvdata(pdev); |
1037 | |
1038 | device_remove_file(&pdev->dev, &dev_attr_tv_out_vsync); |
1039 | device_remove_file(&pdev->dev, &dev_attr_tv_out); |
1040 | device_remove_file(&pdev->dev, &dev_attr_panel); |
1041 | jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb); |
1042 | |
1043 | free_irq(JZ4740_IRQ_LCD, jzfb); |
1044 | |
1045 | /* Blanking will prevent future refreshes from behind scheduled. |
1046 | Now wait for a possible refresh in progress to finish. */ |
1047 | cancel_delayed_work_sync(&jzfb->refresh_work); |
1048 | |
1049 | jzfb->panel->exit(jzfb); |
1050 | |
1051 | jzfb_free_gpio_pins(jzfb); |
1052 | |
1053 | dma_release_channel(jzfb->dma); |
1054 | |
1055 | fb_dealloc_cmap(&jzfb->fb->cmap); |
1056 | jzfb_free_devmem(jzfb); |
1057 | |
1058 | platform_set_drvdata(pdev, NULL); |
1059 | |
1060 | clk_put(jzfb->lpclk); |
1061 | clk_put(jzfb->ldclk); |
1062 | |
1063 | framebuffer_release(jzfb->fb); |
1064 | |
1065 | return 0; |
1066 | } |
1067 | |
1068 | #ifdef CONFIG_PM |
1069 | |
1070 | static int jzfb_suspend(struct device *dev) |
1071 | { |
1072 | struct jzfb *jzfb = dev_get_drvdata(dev); |
1073 | |
1074 | console_lock(); |
1075 | fb_set_suspend(jzfb->fb, 1); |
1076 | console_unlock(); |
1077 | |
1078 | mutex_lock(&jzfb->lock); |
1079 | if (jzfb->is_enabled) |
1080 | jzfb_disable(jzfb); |
1081 | mutex_unlock(&jzfb->lock); |
1082 | |
1083 | return 0; |
1084 | } |
1085 | |
1086 | static int jzfb_resume(struct device *dev) |
1087 | { |
1088 | struct jzfb *jzfb = dev_get_drvdata(dev); |
1089 | |
1090 | mutex_lock(&jzfb->lock); |
1091 | if (jzfb->is_enabled) |
1092 | jzfb_enable(jzfb); |
1093 | mutex_unlock(&jzfb->lock); |
1094 | |
1095 | console_lock(); |
1096 | fb_set_suspend(jzfb->fb, 0); |
1097 | console_unlock(); |
1098 | |
1099 | return 0; |
1100 | } |
1101 | |
1102 | static SIMPLE_DEV_PM_OPS(jzfb_pm_ops, jzfb_suspend, jzfb_resume); |
1103 | |
1104 | #define JZFB_PM_OPS (&jzfb_pm_ops) |
1105 | |
1106 | #else |
1107 | #define JZFB_PM_OPS NULL |
1108 | #endif |
1109 | |
1110 | static struct platform_driver jzfb_driver = { |
1111 | .probe = jzfb_probe, |
1112 | .remove = jzfb_remove, |
1113 | .driver = { |
1114 | .name = "jz4740-fb", |
1115 | .pm = JZFB_PM_OPS, |
1116 | }, |
1117 | }; |
1118 | module_platform_driver(jzfb_driver); |
1119 | |
1120 | MODULE_LICENSE("GPL"); |
1121 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>, Maarten ter Huurne <maarten@treewalker.org>"); |
1122 | MODULE_DESCRIPTION("JZ4740 SoC SLCD framebuffer driver"); |
1123 | MODULE_ALIAS("platform:jz4740-fb"); |
1124 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9