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Source at commit 7a667fb62041135bd64dc2a951094e906701d272 created 13 years 11 months ago. By Lars-Peter Clausen, Add jz4740 udc driver | |
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1 | /* |
2 | * linux/drivers/usb/gadget/jz4740_udc.c |
3 | * |
4 | * Ingenic JZ4740 on-chip high speed USB device controller |
5 | * |
6 | * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc. |
7 | * Author: <jlwei@ingenic.cn> |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or |
12 | * (at your option) any later version. |
13 | */ |
14 | |
15 | /* |
16 | * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint. |
17 | * |
18 | * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk. |
19 | * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints. |
20 | */ |
21 | |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> |
24 | #include <linux/platform_device.h> |
25 | #include <linux/delay.h> |
26 | #include <linux/ioport.h> |
27 | #include <linux/slab.h> |
28 | #include <linux/errno.h> |
29 | #include <linux/init.h> |
30 | #include <linux/list.h> |
31 | #include <linux/interrupt.h> |
32 | #include <linux/proc_fs.h> |
33 | #include <linux/usb.h> |
34 | #include <linux/usb/gadget.h> |
35 | #include <linux/clk.h> |
36 | |
37 | #include <asm/byteorder.h> |
38 | #include <asm/io.h> |
39 | #include <asm/irq.h> |
40 | #include <asm/mach-jz4740/clock.h> |
41 | |
42 | #include "jz4740_udc.h" |
43 | |
44 | #define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */ |
45 | #define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */ |
46 | #define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */ |
47 | #define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */ |
48 | #define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */ |
49 | #define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */ |
50 | #define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */ |
51 | #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */ |
52 | #define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */ |
53 | #define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */ |
54 | #define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */ |
55 | |
56 | #define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */ |
57 | #define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */ |
58 | #define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */ |
59 | #define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */ |
60 | |
61 | #define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */ |
62 | #define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */ |
63 | #define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */ |
64 | #define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */ |
65 | |
66 | #define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20) |
67 | |
68 | #define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */ |
69 | #define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */ |
70 | |
71 | #define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */ |
72 | #define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */ |
73 | #define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */ |
74 | #define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */ |
75 | #define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */ |
76 | #define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */ |
77 | #define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */ |
78 | |
79 | /* Power register bit masks */ |
80 | #define USB_POWER_SUSPENDM 0x01 |
81 | #define USB_POWER_RESUME 0x04 |
82 | #define USB_POWER_HSMODE 0x10 |
83 | #define USB_POWER_HSENAB 0x20 |
84 | #define USB_POWER_SOFTCONN 0x40 |
85 | |
86 | /* Interrupt register bit masks */ |
87 | #define USB_INTR_SUSPEND 0x01 |
88 | #define USB_INTR_RESUME 0x02 |
89 | #define USB_INTR_RESET 0x04 |
90 | |
91 | #define USB_INTR_EP0 0x0001 |
92 | #define USB_INTR_INEP1 0x0002 |
93 | #define USB_INTR_INEP2 0x0004 |
94 | #define USB_INTR_OUTEP1 0x0002 |
95 | |
96 | /* CSR0 bit masks */ |
97 | #define USB_CSR0_OUTPKTRDY 0x01 |
98 | #define USB_CSR0_INPKTRDY 0x02 |
99 | #define USB_CSR0_SENTSTALL 0x04 |
100 | #define USB_CSR0_DATAEND 0x08 |
101 | #define USB_CSR0_SETUPEND 0x10 |
102 | #define USB_CSR0_SENDSTALL 0x20 |
103 | #define USB_CSR0_SVDOUTPKTRDY 0x40 |
104 | #define USB_CSR0_SVDSETUPEND 0x80 |
105 | |
106 | /* Endpoint CSR register bits */ |
107 | #define USB_INCSRH_AUTOSET 0x80 |
108 | #define USB_INCSRH_ISO 0x40 |
109 | #define USB_INCSRH_MODE 0x20 |
110 | #define USB_INCSRH_DMAREQENAB 0x10 |
111 | #define USB_INCSRH_DMAREQMODE 0x04 |
112 | #define USB_INCSR_CDT 0x40 |
113 | #define USB_INCSR_SENTSTALL 0x20 |
114 | #define USB_INCSR_SENDSTALL 0x10 |
115 | #define USB_INCSR_FF 0x08 |
116 | #define USB_INCSR_UNDERRUN 0x04 |
117 | #define USB_INCSR_FFNOTEMPT 0x02 |
118 | #define USB_INCSR_INPKTRDY 0x01 |
119 | |
120 | #define USB_OUTCSRH_AUTOCLR 0x80 |
121 | #define USB_OUTCSRH_ISO 0x40 |
122 | #define USB_OUTCSRH_DMAREQENAB 0x20 |
123 | #define USB_OUTCSRH_DNYT 0x10 |
124 | #define USB_OUTCSRH_DMAREQMODE 0x08 |
125 | #define USB_OUTCSR_CDT 0x80 |
126 | #define USB_OUTCSR_SENTSTALL 0x40 |
127 | #define USB_OUTCSR_SENDSTALL 0x20 |
128 | #define USB_OUTCSR_FF 0x10 |
129 | #define USB_OUTCSR_DATAERR 0x08 |
130 | #define USB_OUTCSR_OVERRUN 0x04 |
131 | #define USB_OUTCSR_FFFULL 0x02 |
132 | #define USB_OUTCSR_OUTPKTRDY 0x01 |
133 | |
134 | /* DMA control bits */ |
135 | #define USB_CNTL_ENA 0x01 |
136 | #define USB_CNTL_DIR_IN 0x02 |
137 | #define USB_CNTL_MODE_1 0x04 |
138 | #define USB_CNTL_INTR_EN 0x08 |
139 | #define USB_CNTL_EP(n) ((n) << 4) |
140 | #define USB_CNTL_BURST_0 (0 << 9) |
141 | #define USB_CNTL_BURST_4 (1 << 9) |
142 | #define USB_CNTL_BURST_8 (2 << 9) |
143 | #define USB_CNTL_BURST_16 (3 << 9) |
144 | |
145 | |
146 | #ifndef DEBUG |
147 | # define DEBUG(fmt,args...) do {} while(0) |
148 | #endif |
149 | #ifndef DEBUG_EP0 |
150 | # define NO_STATES |
151 | # define DEBUG_EP0(fmt,args...) do {} while(0) |
152 | #endif |
153 | #ifndef DEBUG_SETUP |
154 | # define DEBUG_SETUP(fmt,args...) do {} while(0) |
155 | #endif |
156 | |
157 | static struct jz4740_udc jz4740_udc_controller; |
158 | |
159 | /* |
160 | * Local declarations. |
161 | */ |
162 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep); |
163 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr); |
164 | |
165 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, |
166 | int status); |
167 | static void pio_irq_enable(struct jz4740_ep *ep); |
168 | static void pio_irq_disable(struct jz4740_ep *ep); |
169 | static void stop_activity(struct jz4740_udc *dev, |
170 | struct usb_gadget_driver *driver); |
171 | static void nuke(struct jz4740_ep *ep, int status); |
172 | static void flush(struct jz4740_ep *ep); |
173 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address); |
174 | |
175 | /*-------------------------------------------------------------------------*/ |
176 | |
177 | /* inline functions of register read/write/set/clear */ |
178 | |
179 | static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg) |
180 | { |
181 | return readb(udc->base + reg); |
182 | } |
183 | |
184 | static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg) |
185 | { |
186 | return readw(udc->base + reg); |
187 | } |
188 | |
189 | static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg) |
190 | { |
191 | return readl(udc->base + reg); |
192 | } |
193 | |
194 | static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val) |
195 | { |
196 | writeb(val, udc->base + reg); |
197 | } |
198 | |
199 | static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val) |
200 | { |
201 | writew(val, udc->base + reg); |
202 | } |
203 | |
204 | static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val) |
205 | { |
206 | writel(val, udc->base + reg); |
207 | } |
208 | |
209 | static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
210 | { |
211 | usb_writeb(udc, reg, usb_readb(udc, reg) | mask); |
212 | } |
213 | |
214 | static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
215 | { |
216 | usb_writew(udc, reg, usb_readw(udc, reg) | mask); |
217 | } |
218 | |
219 | static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
220 | { |
221 | usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask); |
222 | } |
223 | |
224 | static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
225 | { |
226 | usb_writew(udc, reg, usb_readw(udc, reg) & ~mask); |
227 | } |
228 | |
229 | /*-------------------------------------------------------------------------*/ |
230 | |
231 | static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index) |
232 | { |
233 | usb_writeb(udc, JZ_REG_UDC_INDEX, index); |
234 | } |
235 | |
236 | static inline void jz_udc_select_ep(struct jz4740_ep *ep) |
237 | { |
238 | jz_udc_set_index(ep->dev, ep_index(ep)); |
239 | } |
240 | |
241 | static inline int write_packet(struct jz4740_ep *ep, |
242 | struct jz4740_request *req, unsigned int count) |
243 | { |
244 | uint8_t *buf; |
245 | unsigned int length; |
246 | void __iomem *fifo = ep->dev->base + ep->fifo; |
247 | |
248 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
249 | |
250 | buf = req->req.buf + req->req.actual; |
251 | |
252 | length = req->req.length - req->req.actual; |
253 | if (length > count) |
254 | length = count; |
255 | req->req.actual += length; |
256 | |
257 | DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo); |
258 | |
259 | writesl(fifo, buf, length >> 2); |
260 | writesb(fifo, &buf[length - (length & 3)], length & 3); |
261 | |
262 | return length; |
263 | } |
264 | |
265 | static int read_packet(struct jz4740_ep *ep, |
266 | struct jz4740_request *req, unsigned int count) |
267 | { |
268 | uint8_t *buf; |
269 | unsigned int length; |
270 | void __iomem *fifo = ep->dev->base + ep->fifo; |
271 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
272 | |
273 | buf = req->req.buf + req->req.actual; |
274 | |
275 | length = req->req.length - req->req.actual; |
276 | if (length > count) |
277 | length = count; |
278 | req->req.actual += length; |
279 | |
280 | DEBUG("Read %d, fifo %x\n", length, ep->fifo); |
281 | |
282 | readsl(fifo, buf, length >> 2); |
283 | readsb(fifo, &buf[length - (length & 3)], length & 3); |
284 | |
285 | return length; |
286 | } |
287 | |
288 | /*-------------------------------------------------------------------------*/ |
289 | |
290 | /* |
291 | * udc_disable - disable USB device controller |
292 | */ |
293 | static void udc_disable(struct jz4740_udc *dev) |
294 | { |
295 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
296 | |
297 | udc_set_address(dev, 0); |
298 | |
299 | /* Disable interrupts */ |
300 | usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
301 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
302 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0); |
303 | |
304 | /* Disable DMA */ |
305 | usb_writel(dev, JZ_REG_UDC_CNTL1, 0); |
306 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
307 | |
308 | /* Disconnect from usb */ |
309 | usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
310 | |
311 | /* Disable the USB PHY */ |
312 | clk_disable(dev->clk); |
313 | |
314 | dev->ep0state = WAIT_FOR_SETUP; |
315 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
316 | |
317 | return; |
318 | } |
319 | |
320 | /* |
321 | * udc_reinit - initialize software state |
322 | */ |
323 | static void udc_reinit(struct jz4740_udc *dev) |
324 | { |
325 | int i; |
326 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
327 | |
328 | /* device/ep0 records init */ |
329 | INIT_LIST_HEAD(&dev->gadget.ep_list); |
330 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); |
331 | dev->ep0state = WAIT_FOR_SETUP; |
332 | |
333 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
334 | struct jz4740_ep *ep = &dev->ep[i]; |
335 | |
336 | if (i != 0) |
337 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); |
338 | |
339 | INIT_LIST_HEAD(&ep->queue); |
340 | ep->desc = 0; |
341 | ep->stopped = 0; |
342 | } |
343 | } |
344 | |
345 | /* until it's enabled, this UDC should be completely invisible |
346 | * to any USB host. |
347 | */ |
348 | static void udc_enable(struct jz4740_udc *dev) |
349 | { |
350 | int i; |
351 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
352 | |
353 | /* UDC state is incorrect - Added by River */ |
354 | if (dev->state != UDC_STATE_ENABLE) { |
355 | return; |
356 | } |
357 | |
358 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
359 | |
360 | /* Flush FIFO for each */ |
361 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
362 | struct jz4740_ep *ep = &dev->ep[i]; |
363 | |
364 | jz_udc_select_ep(ep); |
365 | flush(ep); |
366 | } |
367 | |
368 | /* Set this bit to allow the UDC entering low-power mode when |
369 | * there are no actions on the USB bus. |
370 | * UDC still works during this bit was set. |
371 | */ |
372 | jz4740_clock_udc_enable_auto_suspend(); |
373 | |
374 | /* Enable the USB PHY */ |
375 | clk_enable(dev->clk); |
376 | |
377 | /* Disable interrupts */ |
378 | /* usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
379 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
380 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/ |
381 | |
382 | /* Enable interrupts */ |
383 | usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0); |
384 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET); |
385 | /* Don't enable rest of the interrupts */ |
386 | /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2); |
387 | usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */ |
388 | |
389 | /* Enable SUSPEND */ |
390 | /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */ |
391 | |
392 | /* Enable HS Mode */ |
393 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB); |
394 | |
395 | /* Let host detect UDC: |
396 | * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this |
397 | * transistor on and pull the USBDP pin HIGH. |
398 | */ |
399 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
400 | |
401 | return; |
402 | } |
403 | |
404 | /*-------------------------------------------------------------------------*/ |
405 | |
406 | /* keeping it simple: |
407 | * - one bus driver, initted first; |
408 | * - one function driver, initted second |
409 | */ |
410 | |
411 | /* |
412 | * Register entry point for the peripheral controller driver. |
413 | */ |
414 | |
415 | static int jz4740_udc_start(struct usb_gadget *gadget, |
416 | struct usb_gadget_driver *driver) |
417 | { |
418 | struct jz4740_udc *udc = container_of(gadget, struct jz4740_udc, gadget); |
419 | |
420 | /* hook up the driver */ |
421 | udc->driver = driver; |
422 | udc->gadget.dev.driver = &driver->driver; |
423 | |
424 | |
425 | /* then enable host detection and ep0; and we're ready |
426 | * for set_configuration as well as eventual disconnect. |
427 | */ |
428 | udc_enable(udc); |
429 | |
430 | DEBUG("%s: registered gadget driver '%s'\n", gadget->name, |
431 | driver->driver.name); |
432 | |
433 | return 0; |
434 | } |
435 | |
436 | static void stop_activity(struct jz4740_udc *dev, |
437 | struct usb_gadget_driver *driver) |
438 | { |
439 | int i; |
440 | |
441 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
442 | |
443 | /* don't disconnect drivers more than once */ |
444 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) |
445 | driver = 0; |
446 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
447 | |
448 | /* prevent new request submissions, kill any outstanding requests */ |
449 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
450 | struct jz4740_ep *ep = &dev->ep[i]; |
451 | |
452 | ep->stopped = 1; |
453 | |
454 | jz_udc_select_ep(ep); |
455 | nuke(ep, -ESHUTDOWN); |
456 | } |
457 | |
458 | /* report disconnect; the driver is already quiesced */ |
459 | if (driver) { |
460 | spin_unlock(&dev->lock); |
461 | driver->disconnect(&dev->gadget); |
462 | spin_lock(&dev->lock); |
463 | } |
464 | |
465 | /* re-init driver-visible data structures */ |
466 | udc_reinit(dev); |
467 | } |
468 | |
469 | |
470 | /* |
471 | * Unregister entry point for the peripheral controller driver. |
472 | */ |
473 | static int jz4740_udc_stop(struct usb_gadget *gadget, |
474 | struct usb_gadget_driver *driver) |
475 | { |
476 | struct jz4740_udc *udc = container_of(gadget, struct jz4740_udc, gadget); |
477 | unsigned long flags; |
478 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
479 | |
480 | spin_lock_irqsave(&udc->lock, flags); |
481 | udc->driver = NULL; |
482 | udc->gadget.dev.driver = NULL; |
483 | stop_activity(udc, driver); |
484 | spin_unlock_irqrestore(&udc->lock, flags); |
485 | |
486 | udc_disable(udc); |
487 | |
488 | DEBUG("unregistered driver '%s'\n", driver->driver.name); |
489 | |
490 | return 0; |
491 | } |
492 | |
493 | /*-------------------------------------------------------------------------*/ |
494 | |
495 | /** Write request to FIFO (max write == maxp size) |
496 | * Return: 0 = still running, 1 = completed, negative = errno |
497 | * NOTE: INDEX register must be set for EP |
498 | */ |
499 | static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
500 | { |
501 | struct jz4740_udc *dev = ep->dev; |
502 | uint32_t max, csr; |
503 | |
504 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
505 | max = le16_to_cpu(ep->desc->wMaxPacketSize); |
506 | |
507 | csr = usb_readb(dev, ep->csr); |
508 | |
509 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
510 | unsigned count; |
511 | int is_last, is_short; |
512 | |
513 | count = write_packet(ep, req, max); |
514 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
515 | |
516 | /* last packet is usually short (or a zlp) */ |
517 | if (unlikely(count != max)) |
518 | is_last = is_short = 1; |
519 | else { |
520 | if (likely(req->req.length != req->req.actual) |
521 | || req->req.zero) |
522 | is_last = 0; |
523 | else |
524 | is_last = 1; |
525 | /* interrupt/iso maxpacket may not fill the fifo */ |
526 | is_short = unlikely(max < ep_maxpacket(ep)); |
527 | } |
528 | |
529 | DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__, |
530 | ep->ep.name, count, |
531 | is_last ? "/L" : "", is_short ? "/S" : "", |
532 | req->req.length - req->req.actual, req); |
533 | |
534 | /* requests complete when all IN data is in the FIFO */ |
535 | if (is_last) { |
536 | done(ep, req, 0); |
537 | if (list_empty(&ep->queue)) { |
538 | pio_irq_disable(ep); |
539 | } |
540 | return 1; |
541 | } |
542 | } else { |
543 | DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep)); |
544 | } |
545 | |
546 | return 0; |
547 | } |
548 | |
549 | /** Read to request from FIFO (max read == bytes in fifo) |
550 | * Return: 0 = still running, 1 = completed, negative = errno |
551 | * NOTE: INDEX register must be set for EP |
552 | */ |
553 | static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
554 | { |
555 | struct jz4740_udc *dev = ep->dev; |
556 | uint32_t csr; |
557 | unsigned count, is_short; |
558 | |
559 | /* make sure there's a packet in the FIFO. */ |
560 | csr = usb_readb(dev, ep->csr); |
561 | if (!(csr & USB_OUTCSR_OUTPKTRDY)) { |
562 | DEBUG("%s: Packet NOT ready!\n", __FUNCTION__); |
563 | return -EINVAL; |
564 | } |
565 | |
566 | /* read all bytes from this packet */ |
567 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
568 | |
569 | is_short = (count < ep->ep.maxpacket); |
570 | |
571 | count = read_packet(ep, req, count); |
572 | |
573 | DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n", |
574 | ep->ep.name, csr, count, |
575 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
576 | |
577 | /* Clear OutPktRdy */ |
578 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
579 | |
580 | /* completion */ |
581 | if (is_short || req->req.actual == req->req.length) { |
582 | done(ep, req, 0); |
583 | |
584 | if (list_empty(&ep->queue)) |
585 | pio_irq_disable(ep); |
586 | return 1; |
587 | } |
588 | |
589 | /* finished that packet. the next one may be waiting... */ |
590 | return 0; |
591 | } |
592 | |
593 | /* |
594 | * done - retire a request; caller blocked irqs |
595 | * INDEX register is preserved to keep same |
596 | */ |
597 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status) |
598 | { |
599 | unsigned int stopped = ep->stopped; |
600 | uint32_t index; |
601 | |
602 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
603 | list_del_init(&req->queue); |
604 | |
605 | if (likely(req->req.status == -EINPROGRESS)) |
606 | req->req.status = status; |
607 | else |
608 | status = req->req.status; |
609 | |
610 | if (status && status != -ESHUTDOWN) |
611 | DEBUG("complete %s req %p stat %d len %u/%u\n", |
612 | ep->ep.name, &req->req, status, |
613 | req->req.actual, req->req.length); |
614 | |
615 | /* don't modify queue heads during completion callback */ |
616 | ep->stopped = 1; |
617 | /* Read current index (completion may modify it) */ |
618 | index = usb_readb(ep->dev, JZ_REG_UDC_INDEX); |
619 | spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags); |
620 | |
621 | req->req.complete(&ep->ep, &req->req); |
622 | |
623 | spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags); |
624 | /* Restore index */ |
625 | jz_udc_set_index(ep->dev, index); |
626 | ep->stopped = stopped; |
627 | } |
628 | |
629 | static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep) |
630 | { |
631 | if (ep_is_in(ep)) |
632 | return JZ_REG_UDC_INTRINE; |
633 | else |
634 | return JZ_REG_UDC_INTROUTE; |
635 | } |
636 | |
637 | /** Enable EP interrupt */ |
638 | static void pio_irq_enable(struct jz4740_ep *ep) |
639 | { |
640 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
641 | |
642 | usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep))); |
643 | } |
644 | |
645 | /** Disable EP interrupt */ |
646 | static void pio_irq_disable(struct jz4740_ep *ep) |
647 | { |
648 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
649 | |
650 | usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep))); |
651 | } |
652 | |
653 | /* |
654 | * nuke - dequeue ALL requests |
655 | */ |
656 | static void nuke(struct jz4740_ep *ep, int status) |
657 | { |
658 | struct jz4740_request *req; |
659 | |
660 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
661 | |
662 | /* Flush FIFO */ |
663 | flush(ep); |
664 | |
665 | /* called with irqs blocked */ |
666 | while (!list_empty(&ep->queue)) { |
667 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
668 | done(ep, req, status); |
669 | } |
670 | |
671 | /* Disable IRQ if EP is enabled (has descriptor) */ |
672 | if (ep->desc) |
673 | pio_irq_disable(ep); |
674 | } |
675 | |
676 | /** Flush EP FIFO |
677 | * NOTE: INDEX register must be set before this call |
678 | */ |
679 | static void flush(struct jz4740_ep *ep) |
680 | { |
681 | DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name); |
682 | |
683 | switch (ep->type) { |
684 | case ep_bulk_in: |
685 | case ep_interrupt: |
686 | usb_setb(ep->dev, ep->csr, USB_INCSR_FF); |
687 | break; |
688 | case ep_bulk_out: |
689 | usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF); |
690 | break; |
691 | case ep_control: |
692 | break; |
693 | } |
694 | } |
695 | |
696 | /** |
697 | * jz4740_in_epn - handle IN interrupt |
698 | */ |
699 | static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
700 | { |
701 | uint32_t csr; |
702 | struct jz4740_ep *ep = &dev->ep[ep_idx + 1]; |
703 | struct jz4740_request *req; |
704 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
705 | |
706 | jz_udc_select_ep(ep); |
707 | |
708 | csr = usb_readb(dev, ep->csr); |
709 | DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr); |
710 | |
711 | if (csr & USB_INCSR_SENTSTALL) { |
712 | DEBUG("USB_INCSR_SENTSTALL\n"); |
713 | usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL); |
714 | return; |
715 | } |
716 | |
717 | if (!ep->desc) { |
718 | DEBUG("%s: NO EP DESC\n", __FUNCTION__); |
719 | return; |
720 | } |
721 | |
722 | if (!list_empty(&ep->queue)) { |
723 | req = list_first_entry(&ep->queue, struct jz4740_request, queue); |
724 | write_fifo(ep, req); |
725 | } |
726 | } |
727 | |
728 | /* |
729 | * Bulk OUT (recv) |
730 | */ |
731 | static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
732 | { |
733 | struct jz4740_ep *ep = &dev->ep[ep_idx]; |
734 | struct jz4740_request *req; |
735 | |
736 | DEBUG("%s: %d\n", __FUNCTION__, ep_idx); |
737 | |
738 | jz_udc_select_ep(ep); |
739 | if (ep->desc) { |
740 | uint32_t csr; |
741 | |
742 | while ((csr = usb_readb(dev, ep->csr)) & |
743 | (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) { |
744 | DEBUG("%s: %x\n", __FUNCTION__, csr); |
745 | |
746 | if (csr & USB_OUTCSR_SENTSTALL) { |
747 | DEBUG("%s: stall sent, flush fifo\n", |
748 | __FUNCTION__); |
749 | /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */ |
750 | flush(ep); |
751 | } else if (csr & USB_OUTCSR_OUTPKTRDY) { |
752 | if (list_empty(&ep->queue)) |
753 | req = 0; |
754 | else |
755 | req = |
756 | list_entry(ep->queue.next, |
757 | struct jz4740_request, |
758 | queue); |
759 | |
760 | if (!req) { |
761 | DEBUG("%s: NULL REQ %d\n", |
762 | __FUNCTION__, ep_idx); |
763 | break; |
764 | } else { |
765 | read_fifo(ep, req); |
766 | } |
767 | } |
768 | } |
769 | } else { |
770 | /* Throw packet away.. */ |
771 | DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx); |
772 | flush(ep); |
773 | } |
774 | } |
775 | |
776 | /** Halt specific EP |
777 | * Return 0 if success |
778 | * NOTE: Sets INDEX register to EP ! |
779 | */ |
780 | static int jz4740_set_halt(struct usb_ep *_ep, int value) |
781 | { |
782 | struct jz4740_udc *dev; |
783 | struct jz4740_ep *ep; |
784 | unsigned long flags; |
785 | |
786 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
787 | |
788 | ep = container_of(_ep, struct jz4740_ep, ep); |
789 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
790 | DEBUG("%s, bad ep\n", __FUNCTION__); |
791 | return -EINVAL; |
792 | } |
793 | |
794 | dev = ep->dev; |
795 | |
796 | spin_lock_irqsave(&dev->lock, flags); |
797 | |
798 | jz_udc_select_ep(ep); |
799 | |
800 | DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value); |
801 | |
802 | if (ep_index(ep) == 0) { |
803 | /* EP0 */ |
804 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL); |
805 | } else if (ep_is_in(ep)) { |
806 | uint32_t csr = usb_readb(dev, ep->csr); |
807 | if (value && ((csr & USB_INCSR_FFNOTEMPT) |
808 | || !list_empty(&ep->queue))) { |
809 | /* |
810 | * Attempts to halt IN endpoints will fail (returning -EAGAIN) |
811 | * if any transfer requests are still queued, or if the controller |
812 | * FIFO still holds bytes that the host hasnÂ’t collected. |
813 | */ |
814 | spin_unlock_irqrestore(&dev->lock, flags); |
815 | DEBUG |
816 | ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n", |
817 | (csr & USB_INCSR_FFNOTEMPT), |
818 | !list_empty(&ep->queue)); |
819 | return -EAGAIN; |
820 | } |
821 | flush(ep); |
822 | if (value) { |
823 | usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL); |
824 | } else { |
825 | usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL); |
826 | usb_setb(dev, ep->csr, USB_INCSR_CDT); |
827 | } |
828 | } else { |
829 | |
830 | flush(ep); |
831 | if (value) { |
832 | usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
833 | } else { |
834 | usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
835 | usb_setb(dev, ep->csr, USB_OUTCSR_CDT); |
836 | } |
837 | } |
838 | |
839 | ep->stopped = value; |
840 | |
841 | spin_unlock_irqrestore(&dev->lock, flags); |
842 | |
843 | DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS"); |
844 | |
845 | return 0; |
846 | } |
847 | |
848 | |
849 | static int jz4740_ep_enable(struct usb_ep *_ep, |
850 | const struct usb_endpoint_descriptor *desc) |
851 | { |
852 | struct jz4740_ep *ep; |
853 | struct jz4740_udc *dev; |
854 | unsigned long flags; |
855 | uint32_t max, csrh = 0; |
856 | |
857 | DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name); |
858 | |
859 | if (!_ep || !desc) |
860 | return -EINVAL; |
861 | |
862 | ep = container_of(_ep, struct jz4740_ep, ep); |
863 | if (ep->desc || ep->type == ep_control |
864 | || desc->bDescriptorType != USB_DT_ENDPOINT |
865 | || ep->bEndpointAddress != desc->bEndpointAddress) { |
866 | DEBUG("%s, bad ep or descriptor\n", __FUNCTION__); |
867 | return -EINVAL; |
868 | } |
869 | |
870 | /* xfer types must match, except that interrupt ~= bulk */ |
871 | if (ep->bmAttributes != desc->bmAttributes |
872 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK |
873 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { |
874 | DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); |
875 | return -EINVAL; |
876 | } |
877 | |
878 | dev = ep->dev; |
879 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { |
880 | DEBUG("%s, bogus device state\n", __FUNCTION__); |
881 | return -ESHUTDOWN; |
882 | } |
883 | |
884 | max = le16_to_cpu(desc->wMaxPacketSize); |
885 | |
886 | spin_lock_irqsave(&ep->dev->lock, flags); |
887 | |
888 | /* Configure the endpoint */ |
889 | jz_udc_select_ep(ep); |
890 | if (ep_is_in(ep)) { |
891 | usb_writew(dev, JZ_REG_UDC_INMAXP, max); |
892 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
893 | case USB_ENDPOINT_XFER_BULK: |
894 | case USB_ENDPOINT_XFER_INT: |
895 | csrh &= ~USB_INCSRH_ISO; |
896 | break; |
897 | case USB_ENDPOINT_XFER_ISOC: |
898 | csrh |= USB_INCSRH_ISO; |
899 | break; |
900 | } |
901 | usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh); |
902 | } |
903 | else { |
904 | usb_writew(dev, JZ_REG_UDC_OUTMAXP, max); |
905 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
906 | case USB_ENDPOINT_XFER_BULK: |
907 | csrh &= ~USB_OUTCSRH_ISO; |
908 | break; |
909 | case USB_ENDPOINT_XFER_INT: |
910 | csrh &= ~USB_OUTCSRH_ISO; |
911 | csrh |= USB_OUTCSRH_DNYT; |
912 | break; |
913 | case USB_ENDPOINT_XFER_ISOC: |
914 | csrh |= USB_OUTCSRH_ISO; |
915 | break; |
916 | } |
917 | usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh); |
918 | } |
919 | |
920 | |
921 | ep->stopped = 0; |
922 | ep->desc = desc; |
923 | ep->ep.maxpacket = max; |
924 | |
925 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
926 | |
927 | /* Reset halt state (does flush) */ |
928 | jz4740_set_halt(_ep, 0); |
929 | |
930 | DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name); |
931 | |
932 | return 0; |
933 | } |
934 | |
935 | /** Disable EP |
936 | * NOTE: Sets INDEX register |
937 | */ |
938 | static int jz4740_ep_disable(struct usb_ep *_ep) |
939 | { |
940 | struct jz4740_ep *ep; |
941 | unsigned long flags; |
942 | |
943 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
944 | |
945 | ep = container_of(_ep, struct jz4740_ep, ep); |
946 | if (!_ep || !ep->desc) { |
947 | DEBUG("%s, %s not enabled\n", __FUNCTION__, |
948 | _ep ? ep->ep.name : NULL); |
949 | return -EINVAL; |
950 | } |
951 | |
952 | spin_lock_irqsave(&ep->dev->lock, flags); |
953 | |
954 | jz_udc_select_ep(ep); |
955 | |
956 | /* Nuke all pending requests (does flush) */ |
957 | nuke(ep, -ESHUTDOWN); |
958 | |
959 | /* Disable ep IRQ */ |
960 | pio_irq_disable(ep); |
961 | |
962 | ep->desc = 0; |
963 | ep->stopped = 1; |
964 | |
965 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
966 | |
967 | DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name); |
968 | return 0; |
969 | } |
970 | |
971 | static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
972 | { |
973 | struct jz4740_request *req; |
974 | |
975 | req = kzalloc(sizeof(*req), gfp_flags); |
976 | if (!req) |
977 | return NULL; |
978 | |
979 | INIT_LIST_HEAD(&req->queue); |
980 | |
981 | return &req->req; |
982 | } |
983 | |
984 | static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req) |
985 | { |
986 | struct jz4740_request *req; |
987 | |
988 | req = container_of(_req, struct jz4740_request, req); |
989 | WARN_ON(!list_empty(&req->queue)); |
990 | |
991 | kfree(req); |
992 | } |
993 | |
994 | /*--------------------------------------------------------------------*/ |
995 | |
996 | /** Queue one request |
997 | * Kickstart transfer if needed |
998 | * NOTE: Sets INDEX register |
999 | */ |
1000 | static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req, |
1001 | gfp_t gfp_flags) |
1002 | { |
1003 | struct jz4740_request *req; |
1004 | struct jz4740_ep *ep; |
1005 | struct jz4740_udc *dev; |
1006 | |
1007 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1008 | |
1009 | req = container_of(_req, struct jz4740_request, req); |
1010 | if (unlikely |
1011 | (!_req || !_req->complete || !_req->buf |
1012 | || !list_empty(&req->queue))) { |
1013 | DEBUG("%s, bad params\n", __FUNCTION__); |
1014 | return -EINVAL; |
1015 | } |
1016 | |
1017 | ep = container_of(_ep, struct jz4740_ep, ep); |
1018 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
1019 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1020 | return -EINVAL; |
1021 | } |
1022 | |
1023 | dev = ep->dev; |
1024 | if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { |
1025 | DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver); |
1026 | return -ESHUTDOWN; |
1027 | } |
1028 | |
1029 | DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length, |
1030 | _req->buf); |
1031 | |
1032 | spin_lock_irqsave(&dev->lock, dev->lock_flags); |
1033 | |
1034 | _req->status = -EINPROGRESS; |
1035 | _req->actual = 0; |
1036 | |
1037 | /* kickstart this i/o queue? */ |
1038 | DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue), |
1039 | ep->stopped); |
1040 | if (list_empty(&ep->queue) && likely(!ep->stopped)) { |
1041 | uint32_t csr; |
1042 | |
1043 | if (unlikely(ep_index(ep) == 0)) { |
1044 | /* EP0 */ |
1045 | list_add_tail(&req->queue, &ep->queue); |
1046 | jz4740_ep0_kick(dev, ep); |
1047 | req = 0; |
1048 | } |
1049 | else if (ep_is_in(ep)) { |
1050 | /* EP1 & EP2 */ |
1051 | jz_udc_select_ep(ep); |
1052 | csr = usb_readb(dev, ep->csr); |
1053 | pio_irq_enable(ep); |
1054 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
1055 | if (write_fifo(ep, req) == 1) |
1056 | req = 0; |
1057 | } |
1058 | } else { |
1059 | /* EP1 */ |
1060 | jz_udc_select_ep(ep); |
1061 | csr = usb_readb(dev, ep->csr); |
1062 | pio_irq_enable(ep); |
1063 | if (csr & USB_OUTCSR_OUTPKTRDY) { |
1064 | if (read_fifo(ep, req) == 1) |
1065 | req = 0; |
1066 | } |
1067 | } |
1068 | } |
1069 | |
1070 | /* pio or dma irq handler advances the queue. */ |
1071 | if (likely(req != 0)) |
1072 | list_add_tail(&req->queue, &ep->queue); |
1073 | |
1074 | spin_unlock_irqrestore(&dev->lock, dev->lock_flags); |
1075 | |
1076 | return 0; |
1077 | } |
1078 | |
1079 | /* dequeue JUST ONE request */ |
1080 | static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
1081 | { |
1082 | struct jz4740_ep *ep; |
1083 | struct jz4740_request *req; |
1084 | unsigned long flags; |
1085 | |
1086 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1087 | |
1088 | ep = container_of(_ep, struct jz4740_ep, ep); |
1089 | if (!_ep || ep->type == ep_control) |
1090 | return -EINVAL; |
1091 | |
1092 | spin_lock_irqsave(&ep->dev->lock, flags); |
1093 | |
1094 | /* make sure it's actually queued on this endpoint */ |
1095 | list_for_each_entry(req, &ep->queue, queue) { |
1096 | if (&req->req == _req) |
1097 | break; |
1098 | } |
1099 | if (&req->req != _req) { |
1100 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1101 | return -EINVAL; |
1102 | } |
1103 | done(ep, req, -ECONNRESET); |
1104 | |
1105 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1106 | return 0; |
1107 | } |
1108 | |
1109 | /** Return bytes in EP FIFO |
1110 | * NOTE: Sets INDEX register to EP |
1111 | */ |
1112 | static int jz4740_fifo_status(struct usb_ep *_ep) |
1113 | { |
1114 | uint32_t csr; |
1115 | int count = 0; |
1116 | struct jz4740_ep *ep; |
1117 | unsigned long flags; |
1118 | |
1119 | ep = container_of(_ep, struct jz4740_ep, ep); |
1120 | if (!_ep) { |
1121 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1122 | return -ENODEV; |
1123 | } |
1124 | |
1125 | DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep)); |
1126 | |
1127 | /* LPD can't report unclaimed bytes from IN fifos */ |
1128 | if (ep_is_in(ep)) |
1129 | return -EOPNOTSUPP; |
1130 | |
1131 | spin_lock_irqsave(&ep->dev->lock, flags); |
1132 | jz_udc_select_ep(ep); |
1133 | |
1134 | csr = usb_readb(ep->dev, ep->csr); |
1135 | if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN || |
1136 | csr & 0x1) { |
1137 | count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1138 | } |
1139 | |
1140 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1141 | |
1142 | return count; |
1143 | } |
1144 | |
1145 | /** Flush EP FIFO |
1146 | * NOTE: Sets INDEX register to EP |
1147 | */ |
1148 | static void jz4740_fifo_flush(struct usb_ep *_ep) |
1149 | { |
1150 | struct jz4740_ep *ep; |
1151 | unsigned long flags; |
1152 | |
1153 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1154 | |
1155 | ep = container_of(_ep, struct jz4740_ep, ep); |
1156 | if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) { |
1157 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1158 | return; |
1159 | } |
1160 | |
1161 | spin_lock_irqsave(&ep->dev->lock, flags); |
1162 | |
1163 | jz_udc_select_ep(ep); |
1164 | flush(ep); |
1165 | |
1166 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1167 | } |
1168 | |
1169 | /****************************************************************/ |
1170 | /* End Point 0 related functions */ |
1171 | /****************************************************************/ |
1172 | |
1173 | /* return: 0 = still running, 1 = completed, negative = errno */ |
1174 | static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1175 | { |
1176 | uint32_t max; |
1177 | unsigned count; |
1178 | int is_last; |
1179 | |
1180 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1181 | max = ep_maxpacket(ep); |
1182 | |
1183 | count = write_packet(ep, req, max); |
1184 | |
1185 | /* last packet is usually short (or a zlp) */ |
1186 | if (unlikely(count != max)) |
1187 | is_last = 1; |
1188 | else { |
1189 | if (likely(req->req.length != req->req.actual) || req->req.zero) |
1190 | is_last = 0; |
1191 | else |
1192 | is_last = 1; |
1193 | } |
1194 | |
1195 | DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__, |
1196 | ep->ep.name, count, |
1197 | is_last ? "/L" : "", req->req.length - req->req.actual, req); |
1198 | |
1199 | /* requests complete when all IN data is in the FIFO */ |
1200 | if (is_last) { |
1201 | done(ep, req, 0); |
1202 | return 1; |
1203 | } |
1204 | |
1205 | return 0; |
1206 | } |
1207 | |
1208 | static inline int jz4740_fifo_read(struct jz4740_ep *ep, |
1209 | unsigned char *cp, int max) |
1210 | { |
1211 | int bytes; |
1212 | int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1213 | |
1214 | if (count > max) |
1215 | count = max; |
1216 | bytes = count; |
1217 | while (count--) |
1218 | *cp++ = usb_readb(ep->dev, ep->fifo); |
1219 | |
1220 | return bytes; |
1221 | } |
1222 | |
1223 | static inline void jz4740_fifo_write(struct jz4740_ep *ep, |
1224 | unsigned char *cp, int count) |
1225 | { |
1226 | DEBUG("fifo_write: %d %d\n", ep_index(ep), count); |
1227 | while (count--) |
1228 | usb_writeb(ep->dev, ep->fifo, *cp++); |
1229 | } |
1230 | |
1231 | static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1232 | { |
1233 | struct jz4740_udc *dev = ep->dev; |
1234 | uint32_t csr; |
1235 | uint8_t *buf; |
1236 | unsigned bufferspace, count, is_short; |
1237 | |
1238 | DEBUG_EP0("%s\n", __FUNCTION__); |
1239 | |
1240 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1241 | if (!(csr & USB_CSR0_OUTPKTRDY)) |
1242 | return 0; |
1243 | |
1244 | buf = req->req.buf + req->req.actual; |
1245 | prefetchw(buf); |
1246 | bufferspace = req->req.length - req->req.actual; |
1247 | |
1248 | /* read all bytes from this packet */ |
1249 | if (likely(csr & USB_CSR0_OUTPKTRDY)) { |
1250 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
1251 | req->req.actual += min(count, bufferspace); |
1252 | } else /* zlp */ |
1253 | count = 0; |
1254 | |
1255 | is_short = (count < ep->ep.maxpacket); |
1256 | DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n", |
1257 | ep->ep.name, csr, count, |
1258 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
1259 | |
1260 | while (likely(count-- != 0)) { |
1261 | uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo); |
1262 | |
1263 | if (unlikely(bufferspace == 0)) { |
1264 | /* this happens when the driver's buffer |
1265 | * is smaller than what the host sent. |
1266 | * discard the extra data. |
1267 | */ |
1268 | if (req->req.status != -EOVERFLOW) |
1269 | DEBUG_EP0("%s overflow %d\n", ep->ep.name, |
1270 | count); |
1271 | req->req.status = -EOVERFLOW; |
1272 | } else { |
1273 | *buf++ = byte; |
1274 | bufferspace--; |
1275 | } |
1276 | } |
1277 | |
1278 | /* completion */ |
1279 | if (is_short || req->req.actual == req->req.length) { |
1280 | done(ep, req, 0); |
1281 | return 1; |
1282 | } |
1283 | |
1284 | /* finished that packet. the next one may be waiting... */ |
1285 | return 0; |
1286 | } |
1287 | |
1288 | /** |
1289 | * udc_set_address - set the USB address for this device |
1290 | * @address: |
1291 | * |
1292 | * Called from control endpoint function after it decodes a set address setup packet. |
1293 | */ |
1294 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address) |
1295 | { |
1296 | DEBUG_EP0("%s: %d\n", __FUNCTION__, address); |
1297 | |
1298 | usb_writeb(dev, JZ_REG_UDC_FADDR, address); |
1299 | } |
1300 | |
1301 | /* |
1302 | * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY) |
1303 | * - if error |
1304 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1305 | * - else |
1306 | * set USB_CSR0_SVDOUTPKTRDY bit |
1307 | if last set USB_CSR0_DATAEND bit |
1308 | */ |
1309 | static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart) |
1310 | { |
1311 | struct jz4740_request *req; |
1312 | struct jz4740_ep *ep = &dev->ep[0]; |
1313 | int ret; |
1314 | |
1315 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1316 | |
1317 | if (list_empty(&ep->queue)) |
1318 | req = 0; |
1319 | else |
1320 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1321 | |
1322 | if (req) { |
1323 | if (req->req.length == 0) { |
1324 | DEBUG_EP0("ZERO LENGTH OUT!\n"); |
1325 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1326 | dev->ep0state = WAIT_FOR_SETUP; |
1327 | return; |
1328 | } else if (kickstart) { |
1329 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY)); |
1330 | return; |
1331 | } |
1332 | ret = read_fifo_ep0(ep, req); |
1333 | if (ret) { |
1334 | /* Done! */ |
1335 | DEBUG_EP0("%s: finished, waiting for status\n", |
1336 | __FUNCTION__); |
1337 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1338 | dev->ep0state = WAIT_FOR_SETUP; |
1339 | } else { |
1340 | /* Not done yet.. */ |
1341 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1342 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1343 | } |
1344 | } else { |
1345 | DEBUG_EP0("NO REQ??!\n"); |
1346 | } |
1347 | } |
1348 | |
1349 | /* |
1350 | * DATA_STATE_XMIT |
1351 | */ |
1352 | static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr) |
1353 | { |
1354 | struct jz4740_request *req; |
1355 | struct jz4740_ep *ep = &dev->ep[0]; |
1356 | int ret, need_zlp = 0; |
1357 | |
1358 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1359 | |
1360 | if (list_empty(&ep->queue)) |
1361 | req = 0; |
1362 | else |
1363 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1364 | |
1365 | if (!req) { |
1366 | DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__); |
1367 | return 0; |
1368 | } |
1369 | |
1370 | if (req->req.length == 0) { |
1371 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1372 | dev->ep0state = WAIT_FOR_SETUP; |
1373 | return 1; |
1374 | } |
1375 | |
1376 | if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) { |
1377 | /* Next write will end with the packet size, */ |
1378 | /* so we need zero-length-packet */ |
1379 | need_zlp = 1; |
1380 | } |
1381 | |
1382 | ret = write_fifo_ep0(ep, req); |
1383 | |
1384 | if (ret == 1 && !need_zlp) { |
1385 | /* Last packet */ |
1386 | DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__); |
1387 | |
1388 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1389 | dev->ep0state = WAIT_FOR_SETUP; |
1390 | } else { |
1391 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1392 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1393 | } |
1394 | |
1395 | if (need_zlp) { |
1396 | DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__); |
1397 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1398 | dev->ep0state = DATA_STATE_NEED_ZLP; |
1399 | } |
1400 | |
1401 | return 1; |
1402 | } |
1403 | |
1404 | static int jz4740_handle_get_status(struct jz4740_udc *dev, |
1405 | struct usb_ctrlrequest *ctrl) |
1406 | { |
1407 | struct jz4740_ep *ep0 = &dev->ep[0]; |
1408 | struct jz4740_ep *qep; |
1409 | int reqtype = (ctrl->bRequestType & USB_RECIP_MASK); |
1410 | uint16_t val = 0; |
1411 | |
1412 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1413 | |
1414 | if (reqtype == USB_RECIP_INTERFACE) { |
1415 | /* This is not supported. |
1416 | * And according to the USB spec, this one does nothing.. |
1417 | * Just return 0 |
1418 | */ |
1419 | DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n"); |
1420 | } else if (reqtype == USB_RECIP_DEVICE) { |
1421 | DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n"); |
1422 | val |= (1 << 0); /* Self powered */ |
1423 | /*val |= (1<<1); *//* Remote wakeup */ |
1424 | } else if (reqtype == USB_RECIP_ENDPOINT) { |
1425 | int ep_num = (ctrl->wIndex & ~USB_DIR_IN); |
1426 | |
1427 | DEBUG_SETUP |
1428 | ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n", |
1429 | ep_num, ctrl->wLength); |
1430 | |
1431 | if (ctrl->wLength > 2 || ep_num > 3) |
1432 | return -EOPNOTSUPP; |
1433 | |
1434 | qep = &dev->ep[ep_num]; |
1435 | if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0) |
1436 | && ep_index(qep) != 0) { |
1437 | return -EOPNOTSUPP; |
1438 | } |
1439 | |
1440 | jz_udc_select_ep(qep); |
1441 | |
1442 | /* Return status on next IN token */ |
1443 | switch (qep->type) { |
1444 | case ep_control: |
1445 | val = |
1446 | (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) == |
1447 | USB_CSR0_SENDSTALL; |
1448 | break; |
1449 | case ep_bulk_in: |
1450 | case ep_interrupt: |
1451 | val = |
1452 | (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) == |
1453 | USB_INCSR_SENDSTALL; |
1454 | break; |
1455 | case ep_bulk_out: |
1456 | val = |
1457 | (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) == |
1458 | USB_OUTCSR_SENDSTALL; |
1459 | break; |
1460 | } |
1461 | |
1462 | /* Back to EP0 index */ |
1463 | jz_udc_set_index(dev, 0); |
1464 | |
1465 | DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num, |
1466 | ctrl->wIndex, val); |
1467 | } else { |
1468 | DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype); |
1469 | return -EOPNOTSUPP; |
1470 | } |
1471 | |
1472 | /* Clear "out packet ready" */ |
1473 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1474 | /* Put status to FIFO */ |
1475 | jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val)); |
1476 | /* Issue "In packet ready" */ |
1477 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1478 | |
1479 | return 0; |
1480 | } |
1481 | |
1482 | /* |
1483 | * WAIT_FOR_SETUP (OUTPKTRDY) |
1484 | * - read data packet from EP0 FIFO |
1485 | * - decode command |
1486 | * - if error |
1487 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1488 | * - else |
1489 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits |
1490 | */ |
1491 | static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr) |
1492 | { |
1493 | struct jz4740_ep *ep = &dev->ep[0]; |
1494 | struct usb_ctrlrequest ctrl; |
1495 | int i; |
1496 | |
1497 | DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr); |
1498 | |
1499 | /* Nuke all previous transfers */ |
1500 | nuke(ep, -EPROTO); |
1501 | |
1502 | /* read control req from fifo (8 bytes) */ |
1503 | jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8); |
1504 | |
1505 | DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n", |
1506 | ctrl.bRequestType, ctrl.bRequest, |
1507 | ctrl.wValue, ctrl.wIndex, ctrl.wLength); |
1508 | |
1509 | /* Set direction of EP0 */ |
1510 | if (likely(ctrl.bRequestType & USB_DIR_IN)) { |
1511 | ep->bEndpointAddress |= USB_DIR_IN; |
1512 | } else { |
1513 | ep->bEndpointAddress &= ~USB_DIR_IN; |
1514 | } |
1515 | |
1516 | /* Handle some SETUP packets ourselves */ |
1517 | switch (ctrl.bRequest) { |
1518 | case USB_REQ_SET_ADDRESS: |
1519 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1520 | break; |
1521 | |
1522 | DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue); |
1523 | udc_set_address(dev, ctrl.wValue); |
1524 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1525 | return; |
1526 | |
1527 | case USB_REQ_SET_CONFIGURATION: |
1528 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1529 | break; |
1530 | |
1531 | DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue); |
1532 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1533 | |
1534 | /* Enable RESUME and SUSPEND interrupts */ |
1535 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND)); |
1536 | break; |
1537 | |
1538 | case USB_REQ_SET_INTERFACE: |
1539 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1540 | break; |
1541 | |
1542 | DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue); |
1543 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1544 | break; |
1545 | |
1546 | case USB_REQ_GET_STATUS: |
1547 | if (jz4740_handle_get_status(dev, &ctrl) == 0) |
1548 | return; |
1549 | |
1550 | case USB_REQ_CLEAR_FEATURE: |
1551 | case USB_REQ_SET_FEATURE: |
1552 | if (ctrl.bRequestType == USB_RECIP_ENDPOINT) { |
1553 | struct jz4740_ep *qep; |
1554 | int ep_num = (ctrl.wIndex & 0x0f); |
1555 | |
1556 | /* Support only HALT feature */ |
1557 | if (ctrl.wValue != 0 || ctrl.wLength != 0 |
1558 | || ep_num > 3 || ep_num < 1) |
1559 | break; |
1560 | |
1561 | qep = &dev->ep[ep_num]; |
1562 | spin_unlock(&dev->lock); |
1563 | if (ctrl.bRequest == USB_REQ_SET_FEATURE) { |
1564 | DEBUG_SETUP("SET_FEATURE (%d)\n", |
1565 | ep_num); |
1566 | jz4740_set_halt(&qep->ep, 1); |
1567 | } else { |
1568 | DEBUG_SETUP("CLR_FEATURE (%d)\n", |
1569 | ep_num); |
1570 | jz4740_set_halt(&qep->ep, 0); |
1571 | } |
1572 | spin_lock(&dev->lock); |
1573 | |
1574 | jz_udc_set_index(dev, 0); |
1575 | |
1576 | /* Reply with a ZLP on next IN token */ |
1577 | usb_setb(dev, JZ_REG_UDC_CSR0, |
1578 | (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1579 | return; |
1580 | } |
1581 | break; |
1582 | |
1583 | default: |
1584 | break; |
1585 | } |
1586 | |
1587 | /* gadget drivers see class/vendor specific requests, |
1588 | * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, |
1589 | * and more. |
1590 | */ |
1591 | if (dev->driver) { |
1592 | /* device-2-host (IN) or no data setup command, process immediately */ |
1593 | spin_unlock(&dev->lock); |
1594 | |
1595 | i = dev->driver->setup(&dev->gadget, &ctrl); |
1596 | spin_lock(&dev->lock); |
1597 | |
1598 | if (unlikely(i < 0)) { |
1599 | /* setup processing failed, force stall */ |
1600 | DEBUG_SETUP |
1601 | (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n", |
1602 | i); |
1603 | jz_udc_set_index(dev, 0); |
1604 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL)); |
1605 | |
1606 | /* ep->stopped = 1; */ |
1607 | dev->ep0state = WAIT_FOR_SETUP; |
1608 | } |
1609 | else { |
1610 | DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength); |
1611 | /* if (!ctrl.wLength) { |
1612 | usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1613 | }*/ |
1614 | } |
1615 | } |
1616 | } |
1617 | |
1618 | /* |
1619 | * DATA_STATE_NEED_ZLP |
1620 | */ |
1621 | static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr) |
1622 | { |
1623 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1624 | |
1625 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1626 | dev->ep0state = WAIT_FOR_SETUP; |
1627 | } |
1628 | |
1629 | /* |
1630 | * handle ep0 interrupt |
1631 | */ |
1632 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr) |
1633 | { |
1634 | struct jz4740_ep *ep = &dev->ep[0]; |
1635 | uint32_t csr; |
1636 | |
1637 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1638 | /* Set index 0 */ |
1639 | jz_udc_set_index(dev, 0); |
1640 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1641 | |
1642 | DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]); |
1643 | |
1644 | /* |
1645 | * if SENT_STALL is set |
1646 | * - clear the SENT_STALL bit |
1647 | */ |
1648 | if (csr & USB_CSR0_SENTSTALL) { |
1649 | DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr); |
1650 | usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL); |
1651 | nuke(ep, -ECONNABORTED); |
1652 | dev->ep0state = WAIT_FOR_SETUP; |
1653 | return; |
1654 | } |
1655 | |
1656 | /* |
1657 | * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear |
1658 | * - fill EP0 FIFO |
1659 | * - if last packet |
1660 | * - set IN_PKT_RDY | DATA_END |
1661 | * - else |
1662 | * set IN_PKT_RDY |
1663 | */ |
1664 | if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) { |
1665 | DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n", |
1666 | __FUNCTION__); |
1667 | |
1668 | switch (dev->ep0state) { |
1669 | case DATA_STATE_XMIT: |
1670 | DEBUG_EP0("continue with DATA_STATE_XMIT\n"); |
1671 | jz4740_ep0_in(dev, csr); |
1672 | return; |
1673 | case DATA_STATE_NEED_ZLP: |
1674 | DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n"); |
1675 | jz4740_ep0_in_zlp(dev, csr); |
1676 | return; |
1677 | default: |
1678 | /* Stall? */ |
1679 | // DEBUG_EP0("Odd state!! state = %s\n", |
1680 | // state_names[dev->ep0state]); |
1681 | dev->ep0state = WAIT_FOR_SETUP; |
1682 | /* nuke(ep, 0); */ |
1683 | /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */ |
1684 | // break; |
1685 | return; |
1686 | } |
1687 | } |
1688 | |
1689 | /* |
1690 | * if SETUPEND is set |
1691 | * - abort the last transfer |
1692 | * - set SERVICED_SETUP_END_BIT |
1693 | */ |
1694 | if (csr & USB_CSR0_SETUPEND) { |
1695 | DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr); |
1696 | |
1697 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND); |
1698 | nuke(ep, 0); |
1699 | dev->ep0state = WAIT_FOR_SETUP; |
1700 | } |
1701 | |
1702 | /* |
1703 | * if USB_CSR0_OUTPKTRDY is set |
1704 | * - read data packet from EP0 FIFO |
1705 | * - decode command |
1706 | * - if error |
1707 | * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits |
1708 | * - else |
1709 | * set SVDOUTPKTRDY | DATAEND bits |
1710 | */ |
1711 | if (csr & USB_CSR0_OUTPKTRDY) { |
1712 | |
1713 | DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__, |
1714 | csr); |
1715 | |
1716 | switch (dev->ep0state) { |
1717 | case WAIT_FOR_SETUP: |
1718 | DEBUG_EP0("WAIT_FOR_SETUP\n"); |
1719 | jz4740_ep0_setup(dev, csr); |
1720 | break; |
1721 | |
1722 | case DATA_STATE_RECV: |
1723 | DEBUG_EP0("DATA_STATE_RECV\n"); |
1724 | jz4740_ep0_out(dev, csr, 0); |
1725 | break; |
1726 | |
1727 | default: |
1728 | /* send stall? */ |
1729 | DEBUG_EP0("strange state!! 2. send stall? state = %d\n", |
1730 | dev->ep0state); |
1731 | break; |
1732 | } |
1733 | } |
1734 | } |
1735 | |
1736 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep) |
1737 | { |
1738 | uint32_t csr; |
1739 | |
1740 | jz_udc_set_index(dev, 0); |
1741 | |
1742 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1743 | |
1744 | /* Clear "out packet ready" */ |
1745 | |
1746 | if (ep_is_in(ep)) { |
1747 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1748 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1749 | dev->ep0state = DATA_STATE_XMIT; |
1750 | jz4740_ep0_in(dev, csr); |
1751 | } else { |
1752 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1753 | dev->ep0state = DATA_STATE_RECV; |
1754 | jz4740_ep0_out(dev, csr, 1); |
1755 | } |
1756 | } |
1757 | |
1758 | /** Handle USB RESET interrupt |
1759 | */ |
1760 | static void jz4740_reset_irq(struct jz4740_udc *dev) |
1761 | { |
1762 | dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ? |
1763 | USB_SPEED_HIGH : USB_SPEED_FULL; |
1764 | |
1765 | DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0, |
1766 | (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" ); |
1767 | } |
1768 | |
1769 | /* |
1770 | * jz4740 usb device interrupt handler. |
1771 | */ |
1772 | static irqreturn_t jz4740_udc_irq(int irq, void *devid) |
1773 | { |
1774 | struct jz4740_udc *jz4740_udc = devid; |
1775 | uint8_t index; |
1776 | |
1777 | uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */ |
1778 | uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN); |
1779 | uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT); |
1780 | uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR); |
1781 | |
1782 | if (!intr_usb && !intr_in && !intr_out && !intr_dma) |
1783 | return IRQ_HANDLED; |
1784 | |
1785 | |
1786 | DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n", |
1787 | intr_out, intr_in, intr_usb); |
1788 | |
1789 | spin_lock(&jz4740_udc->lock); |
1790 | index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX); |
1791 | |
1792 | /* Check for resume from suspend mode */ |
1793 | if ((intr_usb & USB_INTR_RESUME) && |
1794 | (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) { |
1795 | DEBUG("USB resume\n"); |
1796 | jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */ |
1797 | } |
1798 | |
1799 | /* Check for system interrupts */ |
1800 | if (intr_usb & USB_INTR_RESET) { |
1801 | DEBUG("USB reset\n"); |
1802 | jz4740_reset_irq(jz4740_udc); |
1803 | } |
1804 | |
1805 | /* Check for endpoint 0 interrupt */ |
1806 | if (intr_in & USB_INTR_EP0) { |
1807 | DEBUG("USB_INTR_EP0 (control)\n"); |
1808 | jz4740_handle_ep0(jz4740_udc, intr_in); |
1809 | } |
1810 | |
1811 | /* Check for Bulk-IN DMA interrupt */ |
1812 | if (intr_dma & 0x1) { |
1813 | int ep_num; |
1814 | struct jz4740_ep *ep; |
1815 | ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf; |
1816 | ep = &jz4740_udc->ep[ep_num + 1]; |
1817 | jz_udc_select_ep(ep); |
1818 | usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY); |
1819 | /* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/ |
1820 | } |
1821 | |
1822 | /* Check for Bulk-OUT DMA interrupt */ |
1823 | if (intr_dma & 0x2) { |
1824 | int ep_num; |
1825 | ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf; |
1826 | jz4740_out_epn(jz4740_udc, ep_num, intr_out); |
1827 | } |
1828 | |
1829 | /* Check for each configured endpoint interrupt */ |
1830 | if (intr_in & USB_INTR_INEP1) { |
1831 | DEBUG("USB_INTR_INEP1\n"); |
1832 | jz4740_in_epn(jz4740_udc, 1, intr_in); |
1833 | } |
1834 | |
1835 | if (intr_in & USB_INTR_INEP2) { |
1836 | DEBUG("USB_INTR_INEP2\n"); |
1837 | jz4740_in_epn(jz4740_udc, 2, intr_in); |
1838 | } |
1839 | |
1840 | if (intr_out & USB_INTR_OUTEP1) { |
1841 | DEBUG("USB_INTR_OUTEP1\n"); |
1842 | jz4740_out_epn(jz4740_udc, 1, intr_out); |
1843 | } |
1844 | |
1845 | /* Check for suspend mode */ |
1846 | if ((intr_usb & USB_INTR_SUSPEND) && |
1847 | (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) { |
1848 | DEBUG("USB suspend\n"); |
1849 | jz4740_udc->driver->suspend(&jz4740_udc->gadget); |
1850 | /* Host unloaded from us, can do something, such as flushing |
1851 | the NAND block cache etc. */ |
1852 | } |
1853 | |
1854 | jz_udc_set_index(jz4740_udc, index); |
1855 | |
1856 | spin_unlock(&jz4740_udc->lock); |
1857 | |
1858 | return IRQ_HANDLED; |
1859 | } |
1860 | |
1861 | |
1862 | |
1863 | /*-------------------------------------------------------------------------*/ |
1864 | |
1865 | |
1866 | static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget) |
1867 | { |
1868 | return container_of(gadget, struct jz4740_udc, gadget); |
1869 | } |
1870 | |
1871 | static int jz4740_udc_get_frame(struct usb_gadget *_gadget) |
1872 | { |
1873 | DEBUG("%s, %p\n", __FUNCTION__, _gadget); |
1874 | return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME); |
1875 | } |
1876 | |
1877 | static int jz4740_udc_wakeup(struct usb_gadget *_gadget) |
1878 | { |
1879 | /* host may not have enabled remote wakeup */ |
1880 | /*if ((UDCCS0 & UDCCS0_DRWF) == 0) |
1881 | return -EHOSTUNREACH; |
1882 | udc_set_mask_UDCCR(UDCCR_RSM); */ |
1883 | return -ENOTSUPP; |
1884 | } |
1885 | |
1886 | static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on) |
1887 | { |
1888 | struct jz4740_udc *udc = gadget_to_udc(_gadget); |
1889 | unsigned long flags; |
1890 | |
1891 | local_irq_save(flags); |
1892 | |
1893 | if (on) { |
1894 | udc->state = UDC_STATE_ENABLE; |
1895 | udc_enable(udc); |
1896 | } else { |
1897 | udc->state = UDC_STATE_DISABLE; |
1898 | udc_disable(udc); |
1899 | } |
1900 | |
1901 | local_irq_restore(flags); |
1902 | |
1903 | return 0; |
1904 | } |
1905 | |
1906 | static const struct usb_gadget_ops jz4740_udc_ops = { |
1907 | .get_frame = jz4740_udc_get_frame, |
1908 | .wakeup = jz4740_udc_wakeup, |
1909 | .pullup = jz4740_udc_pullup, |
1910 | .udc_start = jz4740_udc_start, |
1911 | .udc_stop = jz4740_udc_stop, |
1912 | }; |
1913 | |
1914 | static struct usb_ep_ops jz4740_ep_ops = { |
1915 | .enable = jz4740_ep_enable, |
1916 | .disable = jz4740_ep_disable, |
1917 | |
1918 | .alloc_request = jz4740_alloc_request, |
1919 | .free_request = jz4740_free_request, |
1920 | |
1921 | .queue = jz4740_queue, |
1922 | .dequeue = jz4740_dequeue, |
1923 | |
1924 | .set_halt = jz4740_set_halt, |
1925 | .fifo_status = jz4740_fifo_status, |
1926 | .fifo_flush = jz4740_fifo_flush, |
1927 | }; |
1928 | |
1929 | |
1930 | /*-------------------------------------------------------------------------*/ |
1931 | |
1932 | static struct jz4740_udc jz4740_udc_controller = { |
1933 | .gadget = { |
1934 | .ops = &jz4740_udc_ops, |
1935 | .ep0 = &jz4740_udc_controller.ep[0].ep, |
1936 | .name = "jz4740-udc", |
1937 | .dev = { |
1938 | .init_name = "gadget", |
1939 | }, |
1940 | }, |
1941 | |
1942 | /* control endpoint */ |
1943 | .ep[0] = { |
1944 | .ep = { |
1945 | .name = "ep0", |
1946 | .ops = &jz4740_ep_ops, |
1947 | .maxpacket = EP0_MAXPACKETSIZE, |
1948 | }, |
1949 | .dev = &jz4740_udc_controller, |
1950 | |
1951 | .bEndpointAddress = 0, |
1952 | .bmAttributes = 0, |
1953 | |
1954 | .type = ep_control, |
1955 | .fifo = JZ_REG_UDC_EP_FIFO(0), |
1956 | .csr = JZ_REG_UDC_CSR0, |
1957 | }, |
1958 | |
1959 | /* bulk out endpoint */ |
1960 | .ep[1] = { |
1961 | .ep = { |
1962 | .name = "ep1out-bulk", |
1963 | .ops = &jz4740_ep_ops, |
1964 | .maxpacket = EPBULK_MAXPACKETSIZE, |
1965 | }, |
1966 | .dev = &jz4740_udc_controller, |
1967 | |
1968 | .bEndpointAddress = 1, |
1969 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
1970 | |
1971 | .type = ep_bulk_out, |
1972 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
1973 | .csr = JZ_REG_UDC_OUTCSR, |
1974 | }, |
1975 | |
1976 | /* bulk in endpoint */ |
1977 | .ep[2] = { |
1978 | .ep = { |
1979 | .name = "ep1in-bulk", |
1980 | .ops = &jz4740_ep_ops, |
1981 | .maxpacket = EPBULK_MAXPACKETSIZE, |
1982 | }, |
1983 | .dev = &jz4740_udc_controller, |
1984 | |
1985 | .bEndpointAddress = 1 | USB_DIR_IN, |
1986 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
1987 | |
1988 | .type = ep_bulk_in, |
1989 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
1990 | .csr = JZ_REG_UDC_INCSR, |
1991 | }, |
1992 | |
1993 | /* interrupt in endpoint */ |
1994 | .ep[3] = { |
1995 | .ep = { |
1996 | .name = "ep2in-int", |
1997 | .ops = &jz4740_ep_ops, |
1998 | .maxpacket = EPINTR_MAXPACKETSIZE, |
1999 | }, |
2000 | .dev = &jz4740_udc_controller, |
2001 | |
2002 | .bEndpointAddress = 2 | USB_DIR_IN, |
2003 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2004 | |
2005 | .type = ep_interrupt, |
2006 | .fifo = JZ_REG_UDC_EP_FIFO(2), |
2007 | .csr = JZ_REG_UDC_INCSR, |
2008 | }, |
2009 | }; |
2010 | |
2011 | static int jz4740_udc_probe(struct platform_device *pdev) |
2012 | { |
2013 | struct jz4740_udc *jz4740_udc = &jz4740_udc_controller; |
2014 | int ret; |
2015 | |
2016 | spin_lock_init(&jz4740_udc->lock); |
2017 | |
2018 | jz4740_udc->dev = &pdev->dev; |
2019 | jz4740_udc->gadget.dev.parent = &pdev->dev; |
2020 | jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask; |
2021 | |
2022 | ret = device_register(&jz4740_udc->gadget.dev); |
2023 | if (ret) |
2024 | return ret; |
2025 | |
2026 | jz4740_udc->clk = clk_get(&pdev->dev, "udc"); |
2027 | if (IS_ERR(jz4740_udc->clk)) { |
2028 | ret = PTR_ERR(jz4740_udc->clk); |
2029 | dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret); |
2030 | goto err_device_unregister; |
2031 | } |
2032 | |
2033 | platform_set_drvdata(pdev, jz4740_udc); |
2034 | |
2035 | jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2036 | |
2037 | if (!jz4740_udc->mem) { |
2038 | ret = -ENOENT; |
2039 | dev_err(&pdev->dev, "Failed to get mmio memory resource\n"); |
2040 | goto err_clk_put; |
2041 | } |
2042 | |
2043 | jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start, |
2044 | resource_size(jz4740_udc->mem), pdev->name); |
2045 | |
2046 | if (!jz4740_udc->mem) { |
2047 | ret = -EBUSY; |
2048 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
2049 | goto err_device_unregister; |
2050 | } |
2051 | |
2052 | jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem)); |
2053 | |
2054 | if (!jz4740_udc->base) { |
2055 | ret = -EBUSY; |
2056 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
2057 | goto err_release_mem_region; |
2058 | } |
2059 | |
2060 | jz4740_udc->irq = platform_get_irq(pdev, 0); |
2061 | ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name, |
2062 | jz4740_udc); |
2063 | if (ret) { |
2064 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
2065 | goto err_iounmap; |
2066 | } |
2067 | |
2068 | ret = usb_add_gadget_udc(&pdev->dev, &jz4740_udc->gadget); |
2069 | if (ret) { |
2070 | dev_err(&pdev->dev, "Failed to add gadget: %d\n", ret); |
2071 | goto err_free_irq; |
2072 | } |
2073 | |
2074 | udc_disable(jz4740_udc); |
2075 | udc_reinit(jz4740_udc); |
2076 | |
2077 | return 0; |
2078 | |
2079 | err_free_irq: |
2080 | free_irq(jz4740_udc->irq, pdev); |
2081 | err_iounmap: |
2082 | iounmap(jz4740_udc->base); |
2083 | err_release_mem_region: |
2084 | release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem)); |
2085 | err_clk_put: |
2086 | clk_put(jz4740_udc->clk); |
2087 | err_device_unregister: |
2088 | device_unregister(&jz4740_udc->gadget.dev); |
2089 | platform_set_drvdata(pdev, NULL); |
2090 | |
2091 | return ret; |
2092 | } |
2093 | |
2094 | static int jz4740_udc_remove(struct platform_device *pdev) |
2095 | { |
2096 | struct jz4740_udc *dev = platform_get_drvdata(pdev); |
2097 | |
2098 | usb_del_gadget_udc(&dev->gadget); |
2099 | if (dev->driver) |
2100 | return -EBUSY; |
2101 | |
2102 | udc_disable(dev); |
2103 | |
2104 | free_irq(dev->irq, dev); |
2105 | iounmap(dev->base); |
2106 | release_mem_region(dev->mem->start, resource_size(dev->mem)); |
2107 | clk_put(dev->clk); |
2108 | |
2109 | platform_set_drvdata(pdev, NULL); |
2110 | device_unregister(&dev->gadget.dev); |
2111 | |
2112 | return 0; |
2113 | } |
2114 | |
2115 | #ifdef CONFIG_PM |
2116 | |
2117 | static int jz4740_udc_suspend(struct device *dev) |
2118 | { |
2119 | struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev); |
2120 | |
2121 | if (jz4740_udc->state == UDC_STATE_ENABLE) |
2122 | udc_disable(jz4740_udc); |
2123 | |
2124 | return 0; |
2125 | } |
2126 | |
2127 | static int jz4740_udc_resume(struct device *dev) |
2128 | { |
2129 | struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev); |
2130 | |
2131 | if (jz4740_udc->state == UDC_STATE_ENABLE) |
2132 | udc_enable(jz4740_udc); |
2133 | |
2134 | return 0; |
2135 | } |
2136 | |
2137 | static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume); |
2138 | #define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops) |
2139 | |
2140 | #else |
2141 | #define JZ4740_UDC_PM_OPS NULL |
2142 | #endif |
2143 | |
2144 | static struct platform_driver udc_driver = { |
2145 | .probe = jz4740_udc_probe, |
2146 | .remove = jz4740_udc_remove, |
2147 | .driver = { |
2148 | .name = "jz-udc", |
2149 | .owner = THIS_MODULE, |
2150 | .pm = JZ4740_UDC_PM_OPS, |
2151 | }, |
2152 | }; |
2153 | |
2154 | /*-------------------------------------------------------------------------*/ |
2155 | |
2156 | static int __init udc_init (void) |
2157 | { |
2158 | return platform_driver_register(&udc_driver); |
2159 | } |
2160 | module_init(udc_init); |
2161 | |
2162 | static void __exit udc_exit (void) |
2163 | { |
2164 | platform_driver_unregister(&udc_driver); |
2165 | } |
2166 | module_exit(udc_exit); |
2167 | |
2168 | MODULE_DESCRIPTION("JZ4740 USB Device Controller"); |
2169 | MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>"); |
2170 | MODULE_LICENSE("GPL"); |
2171 |
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Tags:
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