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Source at commit 8d5052aafc1e54685596a31f534b0922e4451d36 created 12 years 9 months ago. By Lars-Peter Clausen, Fix MFD jz4740-ts entry | |
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1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 SoC ADC driver |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | * This driver synchronizes access to the JZ4740 ADC core between the |
15 | * JZ4740 battery and hwmon drivers. |
16 | */ |
17 | |
18 | #include <linux/err.h> |
19 | #include <linux/irq.h> |
20 | #include <linux/interrupt.h> |
21 | #include <linux/kernel.h> |
22 | #include <linux/module.h> |
23 | #include <linux/platform_device.h> |
24 | #include <linux/slab.h> |
25 | #include <linux/spinlock.h> |
26 | |
27 | #include <linux/clk.h> |
28 | #include <linux/mfd/core.h> |
29 | |
30 | #include <linux/jz4740-adc.h> |
31 | |
32 | |
33 | #define JZ_REG_ADC_ENABLE 0x00 |
34 | #define JZ_REG_ADC_CFG 0x04 |
35 | #define JZ_REG_ADC_CTRL 0x08 |
36 | #define JZ_REG_ADC_STATUS 0x0c |
37 | |
38 | #define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10 |
39 | #define JZ_REG_ADC_BATTERY_BASE 0x1c |
40 | #define JZ_REG_ADC_HWMON_BASE 0x20 |
41 | |
42 | #define JZ_ADC_ENABLE_TOUCH BIT(2) |
43 | #define JZ_ADC_ENABLE_BATTERY BIT(1) |
44 | #define JZ_ADC_ENABLE_ADCIN BIT(0) |
45 | |
46 | enum { |
47 | JZ_ADC_IRQ_ADCIN = 0, |
48 | JZ_ADC_IRQ_BATTERY, |
49 | JZ_ADC_IRQ_TS_DATA_READY, |
50 | JZ_ADC_IRQ_TS_PENUP, |
51 | JZ_ADC_IRQ_TS_PENDOWN, |
52 | }; |
53 | |
54 | struct jz4740_adc { |
55 | struct resource *mem; |
56 | void __iomem *base; |
57 | |
58 | int irq; |
59 | int irq_base; |
60 | |
61 | struct clk *clk; |
62 | atomic_t clk_ref; |
63 | |
64 | spinlock_t lock; |
65 | }; |
66 | |
67 | static inline void jz4740_adc_irq_set_masked(struct jz4740_adc *adc, int irq, |
68 | bool masked) |
69 | { |
70 | unsigned long flags; |
71 | uint8_t val; |
72 | |
73 | irq -= adc->irq_base; |
74 | |
75 | spin_lock_irqsave(&adc->lock, flags); |
76 | |
77 | val = readb(adc->base + JZ_REG_ADC_CTRL); |
78 | if (masked) |
79 | val |= BIT(irq); |
80 | else |
81 | val &= ~BIT(irq); |
82 | writeb(val, adc->base + JZ_REG_ADC_CTRL); |
83 | |
84 | spin_unlock_irqrestore(&adc->lock, flags); |
85 | } |
86 | |
87 | static void jz4740_adc_irq_mask(struct irq_data *data) |
88 | { |
89 | struct jz4740_adc *adc = irq_data_get_irq_chip_data(data); |
90 | jz4740_adc_irq_set_masked(adc, data->irq, true); |
91 | } |
92 | |
93 | static void jz4740_adc_irq_unmask(struct irq_data *data) |
94 | { |
95 | struct jz4740_adc *adc = irq_data_get_irq_chip_data(data); |
96 | jz4740_adc_irq_set_masked(adc, data->irq, false); |
97 | } |
98 | |
99 | static void jz4740_adc_irq_ack(struct irq_data *data) |
100 | { |
101 | struct jz4740_adc *adc = irq_data_get_irq_chip_data(data); |
102 | unsigned int irq = data->irq - adc->irq_base; |
103 | writeb(BIT(irq), adc->base + JZ_REG_ADC_STATUS); |
104 | } |
105 | |
106 | static struct irq_chip jz4740_adc_irq_chip = { |
107 | .name = "jz4740-adc", |
108 | .irq_mask = jz4740_adc_irq_mask, |
109 | .irq_unmask = jz4740_adc_irq_unmask, |
110 | .irq_ack = jz4740_adc_irq_ack, |
111 | }; |
112 | |
113 | static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc) |
114 | { |
115 | struct jz4740_adc *adc = irq_desc_get_handler_data(desc); |
116 | uint8_t status; |
117 | unsigned int i; |
118 | |
119 | status = readb(adc->base + JZ_REG_ADC_STATUS); |
120 | |
121 | for (i = 0; i < 5; ++i) { |
122 | if (status & BIT(i)) |
123 | generic_handle_irq(adc->irq_base + i); |
124 | } |
125 | } |
126 | |
127 | |
128 | /* Refcounting for the ADC clock is done in here instead of in the clock |
129 | * framework, because it is the only clock which is shared between multiple |
130 | * devices and thus is the only clock which needs refcounting */ |
131 | static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) |
132 | { |
133 | if (atomic_inc_return(&adc->clk_ref) == 1) |
134 | clk_enable(adc->clk); |
135 | } |
136 | |
137 | static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc) |
138 | { |
139 | if (atomic_dec_return(&adc->clk_ref) == 0) |
140 | clk_disable(adc->clk); |
141 | } |
142 | |
143 | static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine, |
144 | bool enabled) |
145 | { |
146 | unsigned long flags; |
147 | uint8_t val; |
148 | |
149 | spin_lock_irqsave(&adc->lock, flags); |
150 | |
151 | val = readb(adc->base + JZ_REG_ADC_ENABLE); |
152 | if (enabled) |
153 | val |= BIT(engine); |
154 | else |
155 | val &= ~BIT(engine); |
156 | writeb(val, adc->base + JZ_REG_ADC_ENABLE); |
157 | |
158 | spin_unlock_irqrestore(&adc->lock, flags); |
159 | } |
160 | |
161 | static int jz4740_adc_cell_enable(struct platform_device *pdev) |
162 | { |
163 | struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); |
164 | |
165 | jz4740_adc_clk_enable(adc); |
166 | jz4740_adc_set_enabled(adc, pdev->id, true); |
167 | |
168 | return 0; |
169 | } |
170 | |
171 | static int jz4740_adc_cell_disable(struct platform_device *pdev) |
172 | { |
173 | struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); |
174 | |
175 | jz4740_adc_set_enabled(adc, pdev->id, false); |
176 | jz4740_adc_clk_disable(adc); |
177 | |
178 | return 0; |
179 | } |
180 | |
181 | int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val) |
182 | { |
183 | struct jz4740_adc *adc = dev_get_drvdata(dev); |
184 | unsigned long flags; |
185 | uint32_t cfg; |
186 | |
187 | if (!adc) |
188 | return -ENODEV; |
189 | |
190 | spin_lock_irqsave(&adc->lock, flags); |
191 | |
192 | cfg = readl(adc->base + JZ_REG_ADC_CFG); |
193 | |
194 | cfg &= ~mask; |
195 | cfg |= val; |
196 | |
197 | writel(cfg, adc->base + JZ_REG_ADC_CFG); |
198 | |
199 | spin_unlock_irqrestore(&adc->lock, flags); |
200 | |
201 | return 0; |
202 | } |
203 | EXPORT_SYMBOL_GPL(jz4740_adc_set_config); |
204 | |
205 | static struct resource jz4740_hwmon_resources[] = { |
206 | { |
207 | .start = JZ_ADC_IRQ_ADCIN, |
208 | .flags = IORESOURCE_IRQ, |
209 | }, |
210 | { |
211 | .start = JZ_REG_ADC_HWMON_BASE, |
212 | .end = JZ_REG_ADC_HWMON_BASE + 3, |
213 | .flags = IORESOURCE_MEM, |
214 | }, |
215 | }; |
216 | |
217 | static struct resource jz4740_battery_resources[] = { |
218 | { |
219 | .start = JZ_ADC_IRQ_BATTERY, |
220 | .flags = IORESOURCE_IRQ, |
221 | }, |
222 | { |
223 | .start = JZ_REG_ADC_BATTERY_BASE, |
224 | .end = JZ_REG_ADC_BATTERY_BASE + 3, |
225 | .flags = IORESOURCE_MEM, |
226 | }, |
227 | }; |
228 | |
229 | static struct resource jz4740_ts_resources[] = { |
230 | { |
231 | .start = JZ_ADC_IRQ_TS_DATA_READY, |
232 | .flags = IORESOURCE_IRQ, |
233 | }, |
234 | { |
235 | .start = JZ_ADC_IRQ_TS_PENUP, |
236 | .flags = IORESOURCE_IRQ, |
237 | }, |
238 | { |
239 | .start = JZ_ADC_IRQ_TS_PENDOWN, |
240 | .flags = IORESOURCE_IRQ, |
241 | }, |
242 | { |
243 | .start = JZ_REG_ADC_TOUCHSCREEN_BASE, |
244 | .end = JZ_REG_ADC_TOUCHSCREEN_BASE + 0xb, |
245 | .flags = IORESOURCE_MEM, |
246 | }, |
247 | }; |
248 | |
249 | |
250 | const struct mfd_cell jz4740_adc_cells[] = { |
251 | { |
252 | .id = 0, |
253 | .name = "jz4740-hwmon", |
254 | .num_resources = ARRAY_SIZE(jz4740_hwmon_resources), |
255 | .resources = jz4740_hwmon_resources, |
256 | |
257 | .enable = jz4740_adc_cell_enable, |
258 | .disable = jz4740_adc_cell_disable, |
259 | }, |
260 | { |
261 | .id = 1, |
262 | .name = "jz4740-battery", |
263 | .num_resources = ARRAY_SIZE(jz4740_battery_resources), |
264 | .resources = jz4740_battery_resources, |
265 | |
266 | .enable = jz4740_adc_cell_enable, |
267 | .disable = jz4740_adc_cell_disable, |
268 | }, |
269 | { |
270 | .id = 2, |
271 | .name = "jz4740-ts", |
272 | .num_resources = ARRAY_SIZE(jz4740_ts_resources), |
273 | .resources = jz4740_ts_resources, |
274 | |
275 | .enable = jz4740_adc_cell_enable, |
276 | .disable = jz4740_adc_cell_disable, |
277 | }, |
278 | }; |
279 | |
280 | static int __devinit jz4740_adc_probe(struct platform_device *pdev) |
281 | { |
282 | int ret; |
283 | struct jz4740_adc *adc; |
284 | struct resource *mem_base; |
285 | int irq; |
286 | |
287 | adc = kmalloc(sizeof(*adc), GFP_KERNEL); |
288 | if (!adc) { |
289 | dev_err(&pdev->dev, "Failed to allocate driver structure\n"); |
290 | return -ENOMEM; |
291 | } |
292 | |
293 | adc->irq = platform_get_irq(pdev, 0); |
294 | if (adc->irq < 0) { |
295 | ret = adc->irq; |
296 | dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); |
297 | goto err_free; |
298 | } |
299 | |
300 | adc->irq_base = platform_get_irq(pdev, 1); |
301 | if (adc->irq_base < 0) { |
302 | ret = adc->irq_base; |
303 | dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret); |
304 | goto err_free; |
305 | } |
306 | |
307 | mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
308 | if (!mem_base) { |
309 | ret = -ENOENT; |
310 | dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); |
311 | goto err_free; |
312 | } |
313 | |
314 | /* Only request the shared registers for the MFD driver */ |
315 | adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, |
316 | pdev->name); |
317 | if (!adc->mem) { |
318 | ret = -EBUSY; |
319 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
320 | goto err_free; |
321 | } |
322 | |
323 | adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); |
324 | if (!adc->base) { |
325 | ret = -EBUSY; |
326 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
327 | goto err_release_mem_region; |
328 | } |
329 | |
330 | adc->clk = clk_get(&pdev->dev, "adc"); |
331 | if (IS_ERR(adc->clk)) { |
332 | ret = PTR_ERR(adc->clk); |
333 | dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); |
334 | goto err_iounmap; |
335 | } |
336 | |
337 | spin_lock_init(&adc->lock); |
338 | atomic_set(&adc->clk_ref, 0); |
339 | |
340 | platform_set_drvdata(pdev, adc); |
341 | |
342 | for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) { |
343 | irq_set_chip_data(irq, adc); |
344 | irq_set_chip_and_handler(irq, &jz4740_adc_irq_chip, |
345 | handle_level_irq); |
346 | } |
347 | |
348 | irq_set_handler_data(adc->irq, adc); |
349 | irq_set_chained_handler(adc->irq, jz4740_adc_irq_demux); |
350 | |
351 | writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); |
352 | writeb(0xff, adc->base + JZ_REG_ADC_CTRL); |
353 | |
354 | ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, |
355 | ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base); |
356 | if (ret < 0) |
357 | goto err_clk_put; |
358 | |
359 | return 0; |
360 | |
361 | err_clk_put: |
362 | clk_put(adc->clk); |
363 | err_iounmap: |
364 | platform_set_drvdata(pdev, NULL); |
365 | iounmap(adc->base); |
366 | err_release_mem_region: |
367 | release_mem_region(adc->mem->start, resource_size(adc->mem)); |
368 | err_free: |
369 | kfree(adc); |
370 | |
371 | return ret; |
372 | } |
373 | |
374 | static int __devexit jz4740_adc_remove(struct platform_device *pdev) |
375 | { |
376 | struct jz4740_adc *adc = platform_get_drvdata(pdev); |
377 | |
378 | mfd_remove_devices(&pdev->dev); |
379 | |
380 | irq_set_handler_data(adc->irq, NULL); |
381 | irq_set_chained_handler(adc->irq, NULL); |
382 | |
383 | iounmap(adc->base); |
384 | release_mem_region(adc->mem->start, resource_size(adc->mem)); |
385 | |
386 | clk_put(adc->clk); |
387 | |
388 | platform_set_drvdata(pdev, NULL); |
389 | |
390 | kfree(adc); |
391 | |
392 | return 0; |
393 | } |
394 | |
395 | struct platform_driver jz4740_adc_driver = { |
396 | .probe = jz4740_adc_probe, |
397 | .remove = __devexit_p(jz4740_adc_remove), |
398 | .driver = { |
399 | .name = "jz4740-adc", |
400 | .owner = THIS_MODULE, |
401 | }, |
402 | }; |
403 | |
404 | static int __init jz4740_adc_init(void) |
405 | { |
406 | return platform_driver_register(&jz4740_adc_driver); |
407 | } |
408 | module_init(jz4740_adc_init); |
409 | |
410 | static void __exit jz4740_adc_exit(void) |
411 | { |
412 | platform_driver_unregister(&jz4740_adc_driver); |
413 | } |
414 | module_exit(jz4740_adc_exit); |
415 | |
416 | MODULE_DESCRIPTION("JZ4740 SoC ADC driver"); |
417 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |
418 | MODULE_LICENSE("GPL"); |
419 | MODULE_ALIAS("platform:jz4740-adc"); |
420 |
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