Root/
Source at commit 92ca0b97ac0ecf8235cdb12380ac9daf71a62c0c created 11 years 9 months ago. By Paul Cercueil, MMC: JZ4740: Remove duplicated code. | |
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1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 SD/MMC controller driver |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | */ |
15 | |
16 | #include <linux/mmc/host.h> |
17 | #include <linux/err.h> |
18 | #include <linux/io.h> |
19 | #include <linux/irq.h> |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> |
22 | #include <linux/platform_device.h> |
23 | #include <linux/delay.h> |
24 | #include <linux/scatterlist.h> |
25 | #include <linux/clk.h> |
26 | #include <linux/cpufreq.h> |
27 | |
28 | #include <linux/bitops.h> |
29 | #include <linux/gpio.h> |
30 | #include <asm/mach-jz4740/gpio.h> |
31 | #include <asm/cacheflush.h> |
32 | #include <linux/dma-mapping.h> |
33 | |
34 | #include <asm/mach-jz4740/jz4740_mmc.h> |
35 | |
36 | #define JZ_REG_MMC_STRPCL 0x00 |
37 | #define JZ_REG_MMC_STATUS 0x04 |
38 | #define JZ_REG_MMC_CLKRT 0x08 |
39 | #define JZ_REG_MMC_CMDAT 0x0C |
40 | #define JZ_REG_MMC_RESTO 0x10 |
41 | #define JZ_REG_MMC_RDTO 0x14 |
42 | #define JZ_REG_MMC_BLKLEN 0x18 |
43 | #define JZ_REG_MMC_NOB 0x1C |
44 | #define JZ_REG_MMC_SNOB 0x20 |
45 | #define JZ_REG_MMC_IMASK 0x24 |
46 | #define JZ_REG_MMC_IREG 0x28 |
47 | #define JZ_REG_MMC_CMD 0x2C |
48 | #define JZ_REG_MMC_ARG 0x30 |
49 | #define JZ_REG_MMC_RESP_FIFO 0x34 |
50 | #define JZ_REG_MMC_RXFIFO 0x38 |
51 | #define JZ_REG_MMC_TXFIFO 0x3C |
52 | |
53 | #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) |
54 | #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) |
55 | #define JZ_MMC_STRPCL_START_READWAIT BIT(5) |
56 | #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) |
57 | #define JZ_MMC_STRPCL_RESET BIT(3) |
58 | #define JZ_MMC_STRPCL_START_OP BIT(2) |
59 | #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) |
60 | #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) |
61 | #define JZ_MMC_STRPCL_CLOCK_START BIT(1) |
62 | |
63 | |
64 | #define JZ_MMC_STATUS_IS_RESETTING BIT(15) |
65 | #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) |
66 | #define JZ_MMC_STATUS_PRG_DONE BIT(13) |
67 | #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) |
68 | #define JZ_MMC_STATUS_END_CMD_RES BIT(11) |
69 | #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) |
70 | #define JZ_MMC_STATUS_IS_READWAIT BIT(9) |
71 | #define JZ_MMC_STATUS_CLK_EN BIT(8) |
72 | #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) |
73 | #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) |
74 | #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) |
75 | #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) |
76 | #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) |
77 | #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) |
78 | #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) |
79 | #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) |
80 | |
81 | #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) |
82 | #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) |
83 | |
84 | |
85 | #define JZ_MMC_CMDAT_IO_ABORT BIT(11) |
86 | #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) |
87 | #define JZ_MMC_CMDAT_DMA_EN BIT(8) |
88 | #define JZ_MMC_CMDAT_INIT BIT(7) |
89 | #define JZ_MMC_CMDAT_BUSY BIT(6) |
90 | #define JZ_MMC_CMDAT_STREAM BIT(5) |
91 | #define JZ_MMC_CMDAT_WRITE BIT(4) |
92 | #define JZ_MMC_CMDAT_DATA_EN BIT(3) |
93 | #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) |
94 | #define JZ_MMC_CMDAT_RSP_R1 1 |
95 | #define JZ_MMC_CMDAT_RSP_R2 2 |
96 | #define JZ_MMC_CMDAT_RSP_R3 3 |
97 | |
98 | #define JZ_MMC_IRQ_SDIO BIT(7) |
99 | #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) |
100 | #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) |
101 | #define JZ_MMC_IRQ_END_CMD_RES BIT(2) |
102 | #define JZ_MMC_IRQ_PRG_DONE BIT(1) |
103 | #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) |
104 | |
105 | |
106 | #define JZ_MMC_CLK_RATE 24000000 |
107 | |
108 | enum jz4740_mmc_state { |
109 | JZ4740_MMC_STATE_READ_RESPONSE, |
110 | JZ4740_MMC_STATE_TRANSFER_DATA, |
111 | JZ4740_MMC_STATE_SEND_STOP, |
112 | JZ4740_MMC_STATE_DONE, |
113 | }; |
114 | |
115 | struct jz4740_mmc_host { |
116 | struct mmc_host *mmc; |
117 | struct platform_device *pdev; |
118 | struct jz4740_mmc_platform_data *pdata; |
119 | struct clk *clk; |
120 | |
121 | int irq; |
122 | int card_detect_irq; |
123 | |
124 | struct resource *mem; |
125 | void __iomem *base; |
126 | struct mmc_request *req; |
127 | struct mmc_command *cmd; |
128 | |
129 | unsigned long waiting; |
130 | |
131 | uint32_t cmdat; |
132 | |
133 | uint16_t irq_mask; |
134 | |
135 | spinlock_t lock; |
136 | |
137 | struct timer_list timeout_timer; |
138 | struct sg_mapping_iter miter; |
139 | enum jz4740_mmc_state state; |
140 | }; |
141 | |
142 | static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, |
143 | unsigned int irq, bool enabled) |
144 | { |
145 | unsigned long flags; |
146 | |
147 | spin_lock_irqsave(&host->lock, flags); |
148 | if (enabled) |
149 | host->irq_mask &= ~irq; |
150 | else |
151 | host->irq_mask |= irq; |
152 | spin_unlock_irqrestore(&host->lock, flags); |
153 | |
154 | writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK); |
155 | } |
156 | |
157 | static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, |
158 | bool start_transfer) |
159 | { |
160 | uint16_t val = JZ_MMC_STRPCL_CLOCK_START; |
161 | |
162 | if (start_transfer) |
163 | val |= JZ_MMC_STRPCL_START_OP; |
164 | |
165 | writew(val, host->base + JZ_REG_MMC_STRPCL); |
166 | } |
167 | |
168 | static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) |
169 | { |
170 | uint32_t status; |
171 | unsigned int timeout = 1000; |
172 | |
173 | writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); |
174 | do { |
175 | status = readl(host->base + JZ_REG_MMC_STATUS); |
176 | } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); |
177 | } |
178 | |
179 | static void jz4740_mmc_reset(struct jz4740_mmc_host *host) |
180 | { |
181 | uint32_t status; |
182 | unsigned int timeout = 1000; |
183 | |
184 | writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); |
185 | udelay(10); |
186 | do { |
187 | status = readl(host->base + JZ_REG_MMC_STATUS); |
188 | } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); |
189 | } |
190 | |
191 | static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) |
192 | { |
193 | struct mmc_request *req; |
194 | |
195 | req = host->req; |
196 | host->req = NULL; |
197 | |
198 | mmc_request_done(host->mmc, req); |
199 | } |
200 | |
201 | static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, |
202 | unsigned int irq) |
203 | { |
204 | unsigned int timeout = 0x800; |
205 | uint16_t status; |
206 | |
207 | do { |
208 | status = readw(host->base + JZ_REG_MMC_IREG); |
209 | } while (!(status & irq) && --timeout); |
210 | |
211 | if (timeout == 0) { |
212 | set_bit(0, &host->waiting); |
213 | mod_timer(&host->timeout_timer, jiffies + 5*HZ); |
214 | jz4740_mmc_set_irq_enabled(host, irq, true); |
215 | return true; |
216 | } |
217 | |
218 | return false; |
219 | } |
220 | |
221 | static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, |
222 | struct mmc_data *data) |
223 | { |
224 | int status; |
225 | |
226 | status = readl(host->base + JZ_REG_MMC_STATUS); |
227 | if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { |
228 | if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { |
229 | host->req->cmd->error = -ETIMEDOUT; |
230 | data->error = -ETIMEDOUT; |
231 | } else { |
232 | host->req->cmd->error = -EIO; |
233 | data->error = -EIO; |
234 | } |
235 | } |
236 | } |
237 | |
238 | static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, |
239 | struct mmc_data *data) |
240 | { |
241 | struct sg_mapping_iter *miter = &host->miter; |
242 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; |
243 | uint32_t *buf; |
244 | bool timeout; |
245 | size_t i, j; |
246 | |
247 | while (sg_miter_next(miter)) { |
248 | buf = miter->addr; |
249 | i = miter->length / 4; |
250 | j = i / 8; |
251 | i = i & 0x7; |
252 | while (j) { |
253 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); |
254 | if (unlikely(timeout)) |
255 | goto poll_timeout; |
256 | |
257 | writel(buf[0], fifo_addr); |
258 | writel(buf[1], fifo_addr); |
259 | writel(buf[2], fifo_addr); |
260 | writel(buf[3], fifo_addr); |
261 | writel(buf[4], fifo_addr); |
262 | writel(buf[5], fifo_addr); |
263 | writel(buf[6], fifo_addr); |
264 | writel(buf[7], fifo_addr); |
265 | buf += 8; |
266 | --j; |
267 | } |
268 | if (unlikely(i)) { |
269 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); |
270 | if (unlikely(timeout)) |
271 | goto poll_timeout; |
272 | |
273 | while (i) { |
274 | writel(*buf, fifo_addr); |
275 | ++buf; |
276 | --i; |
277 | } |
278 | } |
279 | data->bytes_xfered += miter->length; |
280 | } |
281 | sg_miter_stop(miter); |
282 | |
283 | return false; |
284 | |
285 | poll_timeout: |
286 | miter->consumed = (void *)buf - miter->addr; |
287 | data->bytes_xfered += miter->consumed; |
288 | sg_miter_stop(miter); |
289 | |
290 | return true; |
291 | } |
292 | |
293 | static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, |
294 | struct mmc_data *data) |
295 | { |
296 | struct sg_mapping_iter *miter = &host->miter; |
297 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; |
298 | uint32_t *buf; |
299 | uint32_t d; |
300 | uint16_t status; |
301 | size_t i, j; |
302 | unsigned int timeout; |
303 | |
304 | while (sg_miter_next(miter)) { |
305 | buf = miter->addr; |
306 | i = miter->length; |
307 | j = i / 32; |
308 | i = i & 0x1f; |
309 | while (j) { |
310 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); |
311 | if (unlikely(timeout)) |
312 | goto poll_timeout; |
313 | |
314 | buf[0] = readl(fifo_addr); |
315 | buf[1] = readl(fifo_addr); |
316 | buf[2] = readl(fifo_addr); |
317 | buf[3] = readl(fifo_addr); |
318 | buf[4] = readl(fifo_addr); |
319 | buf[5] = readl(fifo_addr); |
320 | buf[6] = readl(fifo_addr); |
321 | buf[7] = readl(fifo_addr); |
322 | |
323 | buf += 8; |
324 | --j; |
325 | } |
326 | |
327 | if (unlikely(i)) { |
328 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); |
329 | if (unlikely(timeout)) |
330 | goto poll_timeout; |
331 | |
332 | while (i >= 4) { |
333 | *buf++ = readl(fifo_addr); |
334 | i -= 4; |
335 | } |
336 | if (unlikely(i > 0)) { |
337 | d = readl(fifo_addr); |
338 | memcpy(buf, &d, i); |
339 | } |
340 | } |
341 | data->bytes_xfered += miter->length; |
342 | |
343 | /* This can go away once MIPS implements |
344 | * flush_kernel_dcache_page */ |
345 | flush_dcache_page(miter->page); |
346 | } |
347 | sg_miter_stop(miter); |
348 | |
349 | /* For whatever reason there is sometime one word more in the fifo then |
350 | * requested */ |
351 | timeout = 1000; |
352 | status = readl(host->base + JZ_REG_MMC_STATUS); |
353 | while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { |
354 | d = readl(fifo_addr); |
355 | status = readl(host->base + JZ_REG_MMC_STATUS); |
356 | } |
357 | |
358 | return false; |
359 | |
360 | poll_timeout: |
361 | miter->consumed = (void *)buf - miter->addr; |
362 | data->bytes_xfered += miter->consumed; |
363 | sg_miter_stop(miter); |
364 | |
365 | return true; |
366 | } |
367 | |
368 | static void jz4740_mmc_timeout(unsigned long data) |
369 | { |
370 | struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data; |
371 | |
372 | if (!test_and_clear_bit(0, &host->waiting)) |
373 | return; |
374 | |
375 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); |
376 | |
377 | host->req->cmd->error = -ETIMEDOUT; |
378 | jz4740_mmc_request_done(host); |
379 | } |
380 | |
381 | static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, |
382 | struct mmc_command *cmd) |
383 | { |
384 | int i; |
385 | uint16_t tmp; |
386 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; |
387 | |
388 | if (cmd->flags & MMC_RSP_136) { |
389 | tmp = readw(fifo_addr); |
390 | for (i = 0; i < 4; ++i) { |
391 | cmd->resp[i] = tmp << 24; |
392 | tmp = readw(fifo_addr); |
393 | cmd->resp[i] |= tmp << 8; |
394 | tmp = readw(fifo_addr); |
395 | cmd->resp[i] |= tmp >> 8; |
396 | } |
397 | } else { |
398 | cmd->resp[0] = readw(fifo_addr) << 24; |
399 | cmd->resp[0] |= readw(fifo_addr) << 8; |
400 | cmd->resp[0] |= readw(fifo_addr) & 0xff; |
401 | } |
402 | } |
403 | |
404 | static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, |
405 | struct mmc_command *cmd) |
406 | { |
407 | uint32_t cmdat = host->cmdat; |
408 | |
409 | host->cmdat &= ~JZ_MMC_CMDAT_INIT; |
410 | jz4740_mmc_clock_disable(host); |
411 | |
412 | host->cmd = cmd; |
413 | |
414 | if (cmd->flags & MMC_RSP_BUSY) |
415 | cmdat |= JZ_MMC_CMDAT_BUSY; |
416 | |
417 | switch (mmc_resp_type(cmd)) { |
418 | case MMC_RSP_R1B: |
419 | case MMC_RSP_R1: |
420 | cmdat |= JZ_MMC_CMDAT_RSP_R1; |
421 | break; |
422 | case MMC_RSP_R2: |
423 | cmdat |= JZ_MMC_CMDAT_RSP_R2; |
424 | break; |
425 | case MMC_RSP_R3: |
426 | cmdat |= JZ_MMC_CMDAT_RSP_R3; |
427 | break; |
428 | default: |
429 | break; |
430 | } |
431 | |
432 | if (cmd->data) { |
433 | cmdat |= JZ_MMC_CMDAT_DATA_EN; |
434 | if (cmd->data->flags & MMC_DATA_WRITE) |
435 | cmdat |= JZ_MMC_CMDAT_WRITE; |
436 | if (cmd->data->flags & MMC_DATA_STREAM) |
437 | cmdat |= JZ_MMC_CMDAT_STREAM; |
438 | |
439 | writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); |
440 | writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); |
441 | } |
442 | |
443 | writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); |
444 | writel(cmd->arg, host->base + JZ_REG_MMC_ARG); |
445 | writel(cmdat, host->base + JZ_REG_MMC_CMDAT); |
446 | |
447 | jz4740_mmc_clock_enable(host, 1); |
448 | } |
449 | |
450 | static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) |
451 | { |
452 | struct mmc_command *cmd = host->req->cmd; |
453 | struct mmc_data *data = cmd->data; |
454 | int direction; |
455 | |
456 | if (data->flags & MMC_DATA_READ) |
457 | direction = SG_MITER_TO_SG; |
458 | else |
459 | direction = SG_MITER_FROM_SG; |
460 | |
461 | sg_miter_start(&host->miter, data->sg, data->sg_len, direction); |
462 | } |
463 | |
464 | |
465 | static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) |
466 | { |
467 | struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; |
468 | struct mmc_command *cmd = host->req->cmd; |
469 | struct mmc_request *req = host->req; |
470 | bool timeout = false; |
471 | |
472 | if (cmd->error) |
473 | host->state = JZ4740_MMC_STATE_DONE; |
474 | |
475 | switch (host->state) { |
476 | case JZ4740_MMC_STATE_READ_RESPONSE: |
477 | if (cmd->flags & MMC_RSP_PRESENT) |
478 | jz4740_mmc_read_response(host, cmd); |
479 | |
480 | if (!cmd->data) |
481 | break; |
482 | |
483 | jz_mmc_prepare_data_transfer(host); |
484 | |
485 | case JZ4740_MMC_STATE_TRANSFER_DATA: |
486 | if (cmd->data->flags & MMC_DATA_READ) |
487 | timeout = jz4740_mmc_read_data(host, cmd->data); |
488 | else |
489 | timeout = jz4740_mmc_write_data(host, cmd->data); |
490 | |
491 | if (unlikely(timeout)) { |
492 | host->state = JZ4740_MMC_STATE_TRANSFER_DATA; |
493 | break; |
494 | } |
495 | |
496 | jz4740_mmc_transfer_check_state(host, cmd->data); |
497 | |
498 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); |
499 | if (unlikely(timeout)) { |
500 | host->state = JZ4740_MMC_STATE_SEND_STOP; |
501 | break; |
502 | } |
503 | writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG); |
504 | |
505 | case JZ4740_MMC_STATE_SEND_STOP: |
506 | if (!req->stop) |
507 | break; |
508 | |
509 | jz4740_mmc_send_command(host, req->stop); |
510 | |
511 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE); |
512 | if (timeout) { |
513 | host->state = JZ4740_MMC_STATE_DONE; |
514 | break; |
515 | } |
516 | case JZ4740_MMC_STATE_DONE: |
517 | break; |
518 | } |
519 | |
520 | if (!timeout) |
521 | jz4740_mmc_request_done(host); |
522 | |
523 | return IRQ_HANDLED; |
524 | } |
525 | |
526 | static irqreturn_t jz_mmc_irq(int irq, void *devid) |
527 | { |
528 | struct jz4740_mmc_host *host = devid; |
529 | struct mmc_command *cmd = host->cmd; |
530 | uint16_t irq_reg, status, tmp; |
531 | |
532 | irq_reg = readw(host->base + JZ_REG_MMC_IREG); |
533 | |
534 | tmp = irq_reg; |
535 | irq_reg &= ~host->irq_mask; |
536 | |
537 | tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | |
538 | JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); |
539 | |
540 | if (tmp != irq_reg) |
541 | writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG); |
542 | |
543 | if (irq_reg & JZ_MMC_IRQ_SDIO) { |
544 | writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG); |
545 | mmc_signal_sdio_irq(host->mmc); |
546 | irq_reg &= ~JZ_MMC_IRQ_SDIO; |
547 | } |
548 | |
549 | if (host->req && cmd && irq_reg) { |
550 | if (test_and_clear_bit(0, &host->waiting)) { |
551 | del_timer(&host->timeout_timer); |
552 | |
553 | status = readl(host->base + JZ_REG_MMC_STATUS); |
554 | |
555 | if (status & JZ_MMC_STATUS_TIMEOUT_RES) { |
556 | cmd->error = -ETIMEDOUT; |
557 | } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { |
558 | cmd->error = -EIO; |
559 | } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | |
560 | JZ_MMC_STATUS_CRC_WRITE_ERROR)) { |
561 | if (cmd->data) |
562 | cmd->data->error = -EIO; |
563 | cmd->error = -EIO; |
564 | } |
565 | |
566 | jz4740_mmc_set_irq_enabled(host, irq_reg, false); |
567 | writew(irq_reg, host->base + JZ_REG_MMC_IREG); |
568 | |
569 | return IRQ_WAKE_THREAD; |
570 | } |
571 | } |
572 | |
573 | return IRQ_HANDLED; |
574 | } |
575 | |
576 | static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) |
577 | { |
578 | int div = 0; |
579 | int real_rate; |
580 | |
581 | jz4740_mmc_clock_disable(host); |
582 | clk_set_rate(host->clk, JZ_MMC_CLK_RATE); |
583 | |
584 | real_rate = clk_get_rate(host->clk); |
585 | |
586 | while (real_rate > rate && div < 7) { |
587 | ++div; |
588 | real_rate >>= 1; |
589 | } |
590 | |
591 | writew(div, host->base + JZ_REG_MMC_CLKRT); |
592 | return real_rate; |
593 | } |
594 | |
595 | static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) |
596 | { |
597 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
598 | |
599 | host->req = req; |
600 | |
601 | writew(0xffff, host->base + JZ_REG_MMC_IREG); |
602 | |
603 | writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG); |
604 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); |
605 | |
606 | host->state = JZ4740_MMC_STATE_READ_RESPONSE; |
607 | set_bit(0, &host->waiting); |
608 | mod_timer(&host->timeout_timer, jiffies + 5*HZ); |
609 | jz4740_mmc_send_command(host, req->cmd); |
610 | } |
611 | |
612 | static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
613 | { |
614 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
615 | if (ios->clock) |
616 | jz4740_mmc_set_clock_rate(host, ios->clock); |
617 | |
618 | switch (ios->power_mode) { |
619 | case MMC_POWER_UP: |
620 | jz4740_mmc_reset(host); |
621 | if (gpio_is_valid(host->pdata->gpio_power)) |
622 | gpio_set_value(host->pdata->gpio_power, |
623 | !host->pdata->power_active_low); |
624 | host->cmdat |= JZ_MMC_CMDAT_INIT; |
625 | clk_enable(host->clk); |
626 | break; |
627 | case MMC_POWER_ON: |
628 | break; |
629 | default: |
630 | if (gpio_is_valid(host->pdata->gpio_power)) |
631 | gpio_set_value(host->pdata->gpio_power, |
632 | host->pdata->power_active_low); |
633 | clk_disable(host->clk); |
634 | break; |
635 | } |
636 | |
637 | switch (ios->bus_width) { |
638 | case MMC_BUS_WIDTH_1: |
639 | host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT; |
640 | break; |
641 | case MMC_BUS_WIDTH_4: |
642 | host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; |
643 | break; |
644 | default: |
645 | break; |
646 | } |
647 | } |
648 | |
649 | static int jz4740_mmc_get_ro(struct mmc_host *mmc) |
650 | { |
651 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
652 | if (!gpio_is_valid(host->pdata->gpio_read_only)) |
653 | return -ENOSYS; |
654 | |
655 | return gpio_get_value(host->pdata->gpio_read_only) ^ |
656 | host->pdata->read_only_active_low; |
657 | } |
658 | |
659 | static int jz4740_mmc_get_cd(struct mmc_host *mmc) |
660 | { |
661 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
662 | if (!gpio_is_valid(host->pdata->gpio_card_detect)) |
663 | return -ENOSYS; |
664 | |
665 | return gpio_get_value(host->pdata->gpio_card_detect) ^ |
666 | host->pdata->card_detect_active_low; |
667 | } |
668 | |
669 | static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid) |
670 | { |
671 | struct jz4740_mmc_host *host = devid; |
672 | |
673 | mmc_detect_change(host->mmc, HZ / 2); |
674 | |
675 | return IRQ_HANDLED; |
676 | } |
677 | |
678 | static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) |
679 | { |
680 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
681 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); |
682 | } |
683 | |
684 | #ifdef CONFIG_CPU_FREQ |
685 | |
686 | static struct jz4740_mmc_host *cpufreq_host; |
687 | |
688 | static int jz4740_mmc_cpufreq_transition(struct notifier_block *nb, |
689 | unsigned long val, void *data) |
690 | { |
691 | /* TODO: We only have to take action when the PLL freq changes: |
692 | the main dividers have no influence on the MSC device clock. */ |
693 | |
694 | if (val == CPUFREQ_PRECHANGE) { |
695 | mmc_claim_host(cpufreq_host->mmc); |
696 | clk_disable(cpufreq_host->clk); |
697 | } else if (val == CPUFREQ_POSTCHANGE) { |
698 | struct mmc_ios *ios = &cpufreq_host->mmc->ios; |
699 | if (ios->clock) |
700 | jz4740_mmc_set_clock_rate(cpufreq_host, ios->clock); |
701 | if (ios->power_mode != MMC_POWER_OFF) |
702 | clk_enable(cpufreq_host->clk); |
703 | mmc_release_host(cpufreq_host->mmc); |
704 | } |
705 | return 0; |
706 | } |
707 | |
708 | static struct notifier_block jz4740_mmc_cpufreq_nb = { |
709 | .notifier_call = jz4740_mmc_cpufreq_transition, |
710 | }; |
711 | |
712 | static inline int jz4740_mmc_cpufreq_register(struct jz4740_mmc_host *host) |
713 | { |
714 | cpufreq_host = host; |
715 | return cpufreq_register_notifier(&jz4740_mmc_cpufreq_nb, |
716 | CPUFREQ_TRANSITION_NOTIFIER); |
717 | } |
718 | |
719 | static inline void jz4740_mmc_cpufreq_unregister(void) |
720 | { |
721 | cpufreq_unregister_notifier(&jz4740_mmc_cpufreq_nb, |
722 | CPUFREQ_TRANSITION_NOTIFIER); |
723 | } |
724 | |
725 | #else |
726 | |
727 | static inline int jz4740_mmc_cpufreq_register(struct jz4740_mmc_host *host) |
728 | { |
729 | return 0; |
730 | } |
731 | |
732 | static inline void jz4740_mmc_cpufreq_unregister(void) |
733 | { |
734 | } |
735 | |
736 | #endif |
737 | |
738 | static const struct mmc_host_ops jz4740_mmc_ops = { |
739 | .request = jz4740_mmc_request, |
740 | .set_ios = jz4740_mmc_set_ios, |
741 | .get_ro = jz4740_mmc_get_ro, |
742 | .get_cd = jz4740_mmc_get_cd, |
743 | .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, |
744 | }; |
745 | |
746 | static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = { |
747 | JZ_GPIO_BULK_PIN(MSC_CMD), |
748 | JZ_GPIO_BULK_PIN(MSC_CLK), |
749 | JZ_GPIO_BULK_PIN(MSC_DATA0), |
750 | JZ_GPIO_BULK_PIN(MSC_DATA1), |
751 | JZ_GPIO_BULK_PIN(MSC_DATA2), |
752 | JZ_GPIO_BULK_PIN(MSC_DATA3), |
753 | }; |
754 | |
755 | static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio, |
756 | const char *name, bool output, int value) |
757 | { |
758 | int ret; |
759 | |
760 | if (!gpio_is_valid(gpio)) |
761 | return 0; |
762 | |
763 | ret = gpio_request(gpio, name); |
764 | if (ret) { |
765 | dev_err(dev, "Failed to request %s gpio: %d\n", name, ret); |
766 | return ret; |
767 | } |
768 | |
769 | if (output) |
770 | gpio_direction_output(gpio, value); |
771 | else |
772 | gpio_direction_input(gpio); |
773 | |
774 | return 0; |
775 | } |
776 | |
777 | static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev) |
778 | { |
779 | int ret; |
780 | struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; |
781 | |
782 | if (!pdata) |
783 | return 0; |
784 | |
785 | ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect, |
786 | "MMC detect change", false, 0); |
787 | if (ret) |
788 | goto err; |
789 | |
790 | ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only, |
791 | "MMC read only", false, 0); |
792 | if (ret) |
793 | goto err_free_gpio_card_detect; |
794 | |
795 | ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power, |
796 | "MMC read only", true, pdata->power_active_low); |
797 | if (ret) |
798 | goto err_free_gpio_read_only; |
799 | |
800 | return 0; |
801 | |
802 | err_free_gpio_read_only: |
803 | if (gpio_is_valid(pdata->gpio_read_only)) |
804 | gpio_free(pdata->gpio_read_only); |
805 | err_free_gpio_card_detect: |
806 | if (gpio_is_valid(pdata->gpio_card_detect)) |
807 | gpio_free(pdata->gpio_card_detect); |
808 | err: |
809 | return ret; |
810 | } |
811 | |
812 | static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev, |
813 | struct jz4740_mmc_host *host) |
814 | { |
815 | struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; |
816 | |
817 | if (!gpio_is_valid(pdata->gpio_card_detect)) |
818 | return 0; |
819 | |
820 | host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect); |
821 | if (host->card_detect_irq < 0) { |
822 | dev_warn(&pdev->dev, "Failed to get card detect irq\n"); |
823 | return 0; |
824 | } |
825 | |
826 | return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq, |
827 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
828 | "MMC card detect", host); |
829 | } |
830 | |
831 | static void jz4740_mmc_free_gpios(struct platform_device *pdev) |
832 | { |
833 | struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; |
834 | |
835 | if (!pdata) |
836 | return; |
837 | |
838 | if (gpio_is_valid(pdata->gpio_power)) |
839 | gpio_free(pdata->gpio_power); |
840 | if (gpio_is_valid(pdata->gpio_read_only)) |
841 | gpio_free(pdata->gpio_read_only); |
842 | if (gpio_is_valid(pdata->gpio_card_detect)) |
843 | gpio_free(pdata->gpio_card_detect); |
844 | } |
845 | |
846 | static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host) |
847 | { |
848 | size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins); |
849 | if (host->pdata && host->pdata->data_1bit) |
850 | num_pins -= 3; |
851 | |
852 | return num_pins; |
853 | } |
854 | |
855 | static int __devinit jz4740_mmc_probe(struct platform_device* pdev) |
856 | { |
857 | int ret; |
858 | struct mmc_host *mmc; |
859 | struct jz4740_mmc_host *host; |
860 | struct jz4740_mmc_platform_data *pdata; |
861 | |
862 | pdata = pdev->dev.platform_data; |
863 | |
864 | mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); |
865 | if (!mmc) { |
866 | dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); |
867 | return -ENOMEM; |
868 | } |
869 | |
870 | host = mmc_priv(mmc); |
871 | host->pdata = pdata; |
872 | |
873 | host->irq = platform_get_irq(pdev, 0); |
874 | if (host->irq < 0) { |
875 | ret = host->irq; |
876 | dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); |
877 | goto err_free_host; |
878 | } |
879 | |
880 | host->clk = clk_get(&pdev->dev, "mmc"); |
881 | if (IS_ERR(host->clk)) { |
882 | ret = PTR_ERR(host->clk); |
883 | dev_err(&pdev->dev, "Failed to get mmc clock\n"); |
884 | goto err_free_host; |
885 | } |
886 | |
887 | ret = jz4740_mmc_cpufreq_register(host); |
888 | if (ret) { |
889 | dev_err(&pdev->dev, |
890 | "Failed to register cpufreq transition notifier\n"); |
891 | goto err_clk_put; |
892 | } |
893 | |
894 | host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
895 | if (!host->mem) { |
896 | ret = -ENOENT; |
897 | dev_err(&pdev->dev, "Failed to get base platform memory\n"); |
898 | goto err_cpufreq_unreg; |
899 | } |
900 | |
901 | host->mem = request_mem_region(host->mem->start, |
902 | resource_size(host->mem), pdev->name); |
903 | if (!host->mem) { |
904 | ret = -EBUSY; |
905 | dev_err(&pdev->dev, "Failed to request base memory region\n"); |
906 | goto err_cpufreq_unreg; |
907 | } |
908 | |
909 | host->base = ioremap_nocache(host->mem->start, resource_size(host->mem)); |
910 | if (!host->base) { |
911 | ret = -EBUSY; |
912 | dev_err(&pdev->dev, "Failed to ioremap base memory\n"); |
913 | goto err_release_mem_region; |
914 | } |
915 | |
916 | ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
917 | if (ret) { |
918 | dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret); |
919 | goto err_iounmap; |
920 | } |
921 | |
922 | ret = jz4740_mmc_request_gpios(pdev); |
923 | if (ret) |
924 | goto err_gpio_bulk_free; |
925 | |
926 | mmc->ops = &jz4740_mmc_ops; |
927 | mmc->f_min = JZ_MMC_CLK_RATE / 128; |
928 | mmc->f_max = JZ_MMC_CLK_RATE; |
929 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
930 | mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA; |
931 | mmc->caps |= MMC_CAP_SDIO_IRQ; |
932 | |
933 | mmc->max_blk_size = (1 << 10) - 1; |
934 | mmc->max_blk_count = (1 << 15) - 1; |
935 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; |
936 | |
937 | mmc->max_segs = 128; |
938 | mmc->max_seg_size = mmc->max_req_size; |
939 | |
940 | host->mmc = mmc; |
941 | host->pdev = pdev; |
942 | spin_lock_init(&host->lock); |
943 | host->irq_mask = 0xffff; |
944 | |
945 | ret = jz4740_mmc_request_cd_irq(pdev, host); |
946 | if (ret) { |
947 | dev_err(&pdev->dev, "Failed to request card detect irq\n"); |
948 | goto err_free_gpios; |
949 | } |
950 | |
951 | ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, |
952 | dev_name(&pdev->dev), host); |
953 | if (ret) { |
954 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
955 | goto err_free_card_detect_irq; |
956 | } |
957 | |
958 | jz4740_mmc_reset(host); |
959 | jz4740_mmc_clock_disable(host); |
960 | setup_timer(&host->timeout_timer, jz4740_mmc_timeout, |
961 | (unsigned long)host); |
962 | /* It is not important when it times out, it just needs to timeout. */ |
963 | set_timer_slack(&host->timeout_timer, HZ); |
964 | |
965 | platform_set_drvdata(pdev, host); |
966 | ret = mmc_add_host(mmc); |
967 | |
968 | if (ret) { |
969 | dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); |
970 | goto err_free_irq; |
971 | } |
972 | dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); |
973 | |
974 | return 0; |
975 | |
976 | err_free_irq: |
977 | free_irq(host->irq, host); |
978 | err_free_card_detect_irq: |
979 | if (host->card_detect_irq >= 0) |
980 | free_irq(host->card_detect_irq, host); |
981 | err_free_gpios: |
982 | jz4740_mmc_free_gpios(pdev); |
983 | err_gpio_bulk_free: |
984 | jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
985 | err_iounmap: |
986 | iounmap(host->base); |
987 | err_release_mem_region: |
988 | release_mem_region(host->mem->start, resource_size(host->mem)); |
989 | err_cpufreq_unreg: |
990 | jz4740_mmc_cpufreq_unregister(); |
991 | err_clk_put: |
992 | clk_put(host->clk); |
993 | err_free_host: |
994 | platform_set_drvdata(pdev, NULL); |
995 | mmc_free_host(mmc); |
996 | |
997 | return ret; |
998 | } |
999 | |
1000 | static int __devexit jz4740_mmc_remove(struct platform_device *pdev) |
1001 | { |
1002 | struct jz4740_mmc_host *host = platform_get_drvdata(pdev); |
1003 | |
1004 | del_timer_sync(&host->timeout_timer); |
1005 | jz4740_mmc_set_irq_enabled(host, 0xff, false); |
1006 | jz4740_mmc_reset(host); |
1007 | |
1008 | mmc_remove_host(host->mmc); |
1009 | |
1010 | free_irq(host->irq, host); |
1011 | if (host->card_detect_irq >= 0) |
1012 | free_irq(host->card_detect_irq, host); |
1013 | |
1014 | jz4740_mmc_free_gpios(pdev); |
1015 | jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
1016 | |
1017 | iounmap(host->base); |
1018 | release_mem_region(host->mem->start, resource_size(host->mem)); |
1019 | |
1020 | jz4740_mmc_cpufreq_unregister(); |
1021 | clk_put(host->clk); |
1022 | |
1023 | platform_set_drvdata(pdev, NULL); |
1024 | mmc_free_host(host->mmc); |
1025 | |
1026 | return 0; |
1027 | } |
1028 | |
1029 | #ifdef CONFIG_PM |
1030 | |
1031 | static int jz4740_mmc_suspend(struct device *dev) |
1032 | { |
1033 | struct jz4740_mmc_host *host = dev_get_drvdata(dev); |
1034 | |
1035 | mmc_suspend_host(host->mmc); |
1036 | |
1037 | jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
1038 | |
1039 | return 0; |
1040 | } |
1041 | |
1042 | static int jz4740_mmc_resume(struct device *dev) |
1043 | { |
1044 | struct jz4740_mmc_host *host = dev_get_drvdata(dev); |
1045 | |
1046 | jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
1047 | |
1048 | mmc_resume_host(host->mmc); |
1049 | |
1050 | return 0; |
1051 | } |
1052 | |
1053 | const struct dev_pm_ops jz4740_mmc_pm_ops = { |
1054 | .suspend = jz4740_mmc_suspend, |
1055 | .resume = jz4740_mmc_resume, |
1056 | .poweroff = jz4740_mmc_suspend, |
1057 | .restore = jz4740_mmc_resume, |
1058 | }; |
1059 | |
1060 | #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) |
1061 | #else |
1062 | #define JZ4740_MMC_PM_OPS NULL |
1063 | #endif |
1064 | |
1065 | static struct platform_driver jz4740_mmc_driver = { |
1066 | .probe = jz4740_mmc_probe, |
1067 | .remove = __devexit_p(jz4740_mmc_remove), |
1068 | .driver = { |
1069 | .name = "jz4740-mmc", |
1070 | .owner = THIS_MODULE, |
1071 | .pm = JZ4740_MMC_PM_OPS, |
1072 | }, |
1073 | }; |
1074 | |
1075 | module_platform_driver(jz4740_mmc_driver); |
1076 | |
1077 | MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); |
1078 | MODULE_LICENSE("GPL"); |
1079 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |
1080 |
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