Root/
Source at commit 997934523b9da03a20ede8fd49c736522ded20be created 12 years 9 months ago. By Maarten ter Huurne, MIPS: JZ4740: USB: Fix packet read/write functions. | |
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1 | /* |
2 | * linux/drivers/usb/gadget/jz4740_udc.c |
3 | * |
4 | * Ingenic JZ4740 on-chip high speed USB device controller |
5 | * |
6 | * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc. |
7 | * Author: <jlwei@ingenic.cn> |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or |
12 | * (at your option) any later version. |
13 | */ |
14 | |
15 | /* |
16 | * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint. |
17 | * |
18 | * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk. |
19 | * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints. |
20 | */ |
21 | |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> |
24 | #include <linux/platform_device.h> |
25 | #include <linux/delay.h> |
26 | #include <linux/ioport.h> |
27 | #include <linux/slab.h> |
28 | #include <linux/errno.h> |
29 | #include <linux/init.h> |
30 | #include <linux/list.h> |
31 | #include <linux/interrupt.h> |
32 | #include <linux/proc_fs.h> |
33 | #include <linux/usb.h> |
34 | #include <linux/usb/gadget.h> |
35 | #include <linux/clk.h> |
36 | |
37 | #include <asm/byteorder.h> |
38 | #include <asm/io.h> |
39 | #include <asm/irq.h> |
40 | #include <asm/system.h> |
41 | #include <asm/mach-jz4740/clock.h> |
42 | |
43 | #include "jz4740_udc.h" |
44 | |
45 | #define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */ |
46 | #define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */ |
47 | #define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */ |
48 | #define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */ |
49 | #define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */ |
50 | #define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */ |
51 | #define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */ |
52 | #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */ |
53 | #define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */ |
54 | #define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */ |
55 | #define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */ |
56 | |
57 | #define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */ |
58 | #define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */ |
59 | #define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */ |
60 | #define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */ |
61 | |
62 | #define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */ |
63 | #define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */ |
64 | #define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */ |
65 | #define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */ |
66 | |
67 | #define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20) |
68 | |
69 | #define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */ |
70 | #define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */ |
71 | |
72 | #define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */ |
73 | #define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */ |
74 | #define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */ |
75 | #define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */ |
76 | #define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */ |
77 | #define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */ |
78 | #define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */ |
79 | |
80 | /* Power register bit masks */ |
81 | #define USB_POWER_SUSPENDM 0x01 |
82 | #define USB_POWER_RESUME 0x04 |
83 | #define USB_POWER_HSMODE 0x10 |
84 | #define USB_POWER_HSENAB 0x20 |
85 | #define USB_POWER_SOFTCONN 0x40 |
86 | |
87 | /* Interrupt register bit masks */ |
88 | #define USB_INTR_SUSPEND 0x01 |
89 | #define USB_INTR_RESUME 0x02 |
90 | #define USB_INTR_RESET 0x04 |
91 | |
92 | #define USB_INTR_EP0 0x0001 |
93 | #define USB_INTR_INEP1 0x0002 |
94 | #define USB_INTR_INEP2 0x0004 |
95 | #define USB_INTR_OUTEP1 0x0002 |
96 | |
97 | /* CSR0 bit masks */ |
98 | #define USB_CSR0_OUTPKTRDY 0x01 |
99 | #define USB_CSR0_INPKTRDY 0x02 |
100 | #define USB_CSR0_SENTSTALL 0x04 |
101 | #define USB_CSR0_DATAEND 0x08 |
102 | #define USB_CSR0_SETUPEND 0x10 |
103 | #define USB_CSR0_SENDSTALL 0x20 |
104 | #define USB_CSR0_SVDOUTPKTRDY 0x40 |
105 | #define USB_CSR0_SVDSETUPEND 0x80 |
106 | |
107 | /* Endpoint CSR register bits */ |
108 | #define USB_INCSRH_AUTOSET 0x80 |
109 | #define USB_INCSRH_ISO 0x40 |
110 | #define USB_INCSRH_MODE 0x20 |
111 | #define USB_INCSRH_DMAREQENAB 0x10 |
112 | #define USB_INCSRH_DMAREQMODE 0x04 |
113 | #define USB_INCSR_CDT 0x40 |
114 | #define USB_INCSR_SENTSTALL 0x20 |
115 | #define USB_INCSR_SENDSTALL 0x10 |
116 | #define USB_INCSR_FF 0x08 |
117 | #define USB_INCSR_UNDERRUN 0x04 |
118 | #define USB_INCSR_FFNOTEMPT 0x02 |
119 | #define USB_INCSR_INPKTRDY 0x01 |
120 | |
121 | #define USB_OUTCSRH_AUTOCLR 0x80 |
122 | #define USB_OUTCSRH_ISO 0x40 |
123 | #define USB_OUTCSRH_DMAREQENAB 0x20 |
124 | #define USB_OUTCSRH_DNYT 0x10 |
125 | #define USB_OUTCSRH_DMAREQMODE 0x08 |
126 | #define USB_OUTCSR_CDT 0x80 |
127 | #define USB_OUTCSR_SENTSTALL 0x40 |
128 | #define USB_OUTCSR_SENDSTALL 0x20 |
129 | #define USB_OUTCSR_FF 0x10 |
130 | #define USB_OUTCSR_DATAERR 0x08 |
131 | #define USB_OUTCSR_OVERRUN 0x04 |
132 | #define USB_OUTCSR_FFFULL 0x02 |
133 | #define USB_OUTCSR_OUTPKTRDY 0x01 |
134 | |
135 | /* DMA control bits */ |
136 | #define USB_CNTL_ENA 0x01 |
137 | #define USB_CNTL_DIR_IN 0x02 |
138 | #define USB_CNTL_MODE_1 0x04 |
139 | #define USB_CNTL_INTR_EN 0x08 |
140 | #define USB_CNTL_EP(n) ((n) << 4) |
141 | #define USB_CNTL_BURST_0 (0 << 9) |
142 | #define USB_CNTL_BURST_4 (1 << 9) |
143 | #define USB_CNTL_BURST_8 (2 << 9) |
144 | #define USB_CNTL_BURST_16 (3 << 9) |
145 | |
146 | |
147 | #ifndef DEBUG |
148 | # define DEBUG(fmt,args...) do {} while(0) |
149 | #endif |
150 | #ifndef DEBUG_EP0 |
151 | # define NO_STATES |
152 | # define DEBUG_EP0(fmt,args...) do {} while(0) |
153 | #endif |
154 | #ifndef DEBUG_SETUP |
155 | # define DEBUG_SETUP(fmt,args...) do {} while(0) |
156 | #endif |
157 | |
158 | static struct jz4740_udc jz4740_udc_controller; |
159 | |
160 | /* |
161 | * Local declarations. |
162 | */ |
163 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep); |
164 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr); |
165 | |
166 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, |
167 | int status); |
168 | static void pio_irq_enable(struct jz4740_ep *ep); |
169 | static void pio_irq_disable(struct jz4740_ep *ep); |
170 | static void stop_activity(struct jz4740_udc *dev, |
171 | struct usb_gadget_driver *driver); |
172 | static void nuke(struct jz4740_ep *ep, int status); |
173 | static void flush(struct jz4740_ep *ep); |
174 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address); |
175 | |
176 | /*-------------------------------------------------------------------------*/ |
177 | |
178 | /* inline functions of register read/write/set/clear */ |
179 | |
180 | static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg) |
181 | { |
182 | return readb(udc->base + reg); |
183 | } |
184 | |
185 | static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg) |
186 | { |
187 | return readw(udc->base + reg); |
188 | } |
189 | |
190 | static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg) |
191 | { |
192 | return readl(udc->base + reg); |
193 | } |
194 | |
195 | static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val) |
196 | { |
197 | writeb(val, udc->base + reg); |
198 | } |
199 | |
200 | static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val) |
201 | { |
202 | writew(val, udc->base + reg); |
203 | } |
204 | |
205 | static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val) |
206 | { |
207 | writel(val, udc->base + reg); |
208 | } |
209 | |
210 | static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
211 | { |
212 | usb_writeb(udc, reg, usb_readb(udc, reg) | mask); |
213 | } |
214 | |
215 | static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
216 | { |
217 | usb_writew(udc, reg, usb_readw(udc, reg) | mask); |
218 | } |
219 | |
220 | static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
221 | { |
222 | usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask); |
223 | } |
224 | |
225 | static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
226 | { |
227 | usb_writew(udc, reg, usb_readw(udc, reg) & ~mask); |
228 | } |
229 | |
230 | /*-------------------------------------------------------------------------*/ |
231 | |
232 | static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index) |
233 | { |
234 | usb_writeb(udc, JZ_REG_UDC_INDEX, index); |
235 | } |
236 | |
237 | static inline void jz_udc_select_ep(struct jz4740_ep *ep) |
238 | { |
239 | jz_udc_set_index(ep->dev, ep_index(ep)); |
240 | } |
241 | |
242 | static inline int write_packet(struct jz4740_ep *ep, |
243 | struct jz4740_request *req, unsigned int count) |
244 | { |
245 | uint8_t *buf; |
246 | unsigned int length; |
247 | void __iomem *fifo = ep->dev->base + ep->fifo; |
248 | |
249 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
250 | |
251 | buf = req->req.buf + req->req.actual; |
252 | |
253 | length = req->req.length - req->req.actual; |
254 | if (length > count) |
255 | length = count; |
256 | req->req.actual += length; |
257 | |
258 | DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo); |
259 | |
260 | writesl(fifo, buf, length >> 2); |
261 | writesb(fifo, &buf[length - (length & 3)], length & 3); |
262 | |
263 | return length; |
264 | } |
265 | |
266 | static int read_packet(struct jz4740_ep *ep, |
267 | struct jz4740_request *req, unsigned int count) |
268 | { |
269 | uint8_t *buf; |
270 | unsigned int length; |
271 | void __iomem *fifo = ep->dev->base + ep->fifo; |
272 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
273 | |
274 | buf = req->req.buf + req->req.actual; |
275 | |
276 | length = req->req.length - req->req.actual; |
277 | if (length > count) |
278 | length = count; |
279 | req->req.actual += length; |
280 | |
281 | DEBUG("Read %d, fifo %x\n", length, ep->fifo); |
282 | |
283 | readsl(fifo, buf, length >> 2); |
284 | readsb(fifo, &buf[length - (length & 3)], length & 3); |
285 | |
286 | return length; |
287 | } |
288 | |
289 | /*-------------------------------------------------------------------------*/ |
290 | |
291 | /* |
292 | * udc_disable - disable USB device controller |
293 | */ |
294 | static void udc_disable(struct jz4740_udc *dev) |
295 | { |
296 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
297 | |
298 | udc_set_address(dev, 0); |
299 | |
300 | /* Disable interrupts */ |
301 | usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
302 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
303 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0); |
304 | |
305 | /* Disable DMA */ |
306 | usb_writel(dev, JZ_REG_UDC_CNTL1, 0); |
307 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
308 | |
309 | /* Disconnect from usb */ |
310 | usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
311 | |
312 | /* Disable the USB PHY */ |
313 | clk_disable(dev->clk); |
314 | |
315 | dev->ep0state = WAIT_FOR_SETUP; |
316 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
317 | |
318 | return; |
319 | } |
320 | |
321 | /* |
322 | * udc_reinit - initialize software state |
323 | */ |
324 | static void udc_reinit(struct jz4740_udc *dev) |
325 | { |
326 | int i; |
327 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
328 | |
329 | /* device/ep0 records init */ |
330 | INIT_LIST_HEAD(&dev->gadget.ep_list); |
331 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); |
332 | dev->ep0state = WAIT_FOR_SETUP; |
333 | |
334 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
335 | struct jz4740_ep *ep = &dev->ep[i]; |
336 | |
337 | if (i != 0) |
338 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); |
339 | |
340 | INIT_LIST_HEAD(&ep->queue); |
341 | ep->desc = 0; |
342 | ep->stopped = 0; |
343 | } |
344 | } |
345 | |
346 | /* until it's enabled, this UDC should be completely invisible |
347 | * to any USB host. |
348 | */ |
349 | static void udc_enable(struct jz4740_udc *dev) |
350 | { |
351 | int i; |
352 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
353 | |
354 | /* UDC state is incorrect - Added by River */ |
355 | if (dev->state != UDC_STATE_ENABLE) { |
356 | return; |
357 | } |
358 | |
359 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
360 | |
361 | /* Flush FIFO for each */ |
362 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
363 | struct jz4740_ep *ep = &dev->ep[i]; |
364 | |
365 | jz_udc_select_ep(ep); |
366 | flush(ep); |
367 | } |
368 | |
369 | /* Set this bit to allow the UDC entering low-power mode when |
370 | * there are no actions on the USB bus. |
371 | * UDC still works during this bit was set. |
372 | */ |
373 | jz4740_clock_udc_enable_auto_suspend(); |
374 | |
375 | /* Enable the USB PHY */ |
376 | clk_enable(dev->clk); |
377 | |
378 | /* Disable interrupts */ |
379 | /* usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
380 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
381 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/ |
382 | |
383 | /* Enable interrupts */ |
384 | usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0); |
385 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET); |
386 | /* Don't enable rest of the interrupts */ |
387 | /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2); |
388 | usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */ |
389 | |
390 | /* Enable SUSPEND */ |
391 | /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */ |
392 | |
393 | /* Enable HS Mode */ |
394 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB); |
395 | |
396 | /* Let host detect UDC: |
397 | * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this |
398 | * transistor on and pull the USBDP pin HIGH. |
399 | */ |
400 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
401 | |
402 | return; |
403 | } |
404 | |
405 | /*-------------------------------------------------------------------------*/ |
406 | |
407 | /* keeping it simple: |
408 | * - one bus driver, initted first; |
409 | * - one function driver, initted second |
410 | */ |
411 | |
412 | /* |
413 | * Register entry point for the peripheral controller driver. |
414 | */ |
415 | |
416 | int usb_gadget_probe_driver(struct usb_gadget_driver *driver, |
417 | int (*bind)(struct usb_gadget *)) |
418 | { |
419 | struct jz4740_udc *dev = &jz4740_udc_controller; |
420 | int retval; |
421 | |
422 | if (!driver || !bind) |
423 | return -EINVAL; |
424 | |
425 | if (!dev) |
426 | return -ENODEV; |
427 | |
428 | if (dev->driver) |
429 | return -EBUSY; |
430 | |
431 | /* hook up the driver */ |
432 | dev->driver = driver; |
433 | dev->gadget.dev.driver = &driver->driver; |
434 | |
435 | retval = bind(&dev->gadget); |
436 | if (retval) { |
437 | DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name, |
438 | driver->driver.name, retval); |
439 | dev->driver = 0; |
440 | return retval; |
441 | } |
442 | |
443 | /* then enable host detection and ep0; and we're ready |
444 | * for set_configuration as well as eventual disconnect. |
445 | */ |
446 | udc_enable(dev); |
447 | |
448 | DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name, |
449 | driver->driver.name); |
450 | |
451 | return 0; |
452 | } |
453 | EXPORT_SYMBOL(usb_gadget_probe_driver); |
454 | |
455 | static void stop_activity(struct jz4740_udc *dev, |
456 | struct usb_gadget_driver *driver) |
457 | { |
458 | int i; |
459 | |
460 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
461 | |
462 | /* don't disconnect drivers more than once */ |
463 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) |
464 | driver = 0; |
465 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
466 | |
467 | /* prevent new request submissions, kill any outstanding requests */ |
468 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
469 | struct jz4740_ep *ep = &dev->ep[i]; |
470 | |
471 | ep->stopped = 1; |
472 | |
473 | jz_udc_select_ep(ep); |
474 | nuke(ep, -ESHUTDOWN); |
475 | } |
476 | |
477 | /* report disconnect; the driver is already quiesced */ |
478 | if (driver) { |
479 | spin_unlock(&dev->lock); |
480 | driver->disconnect(&dev->gadget); |
481 | spin_lock(&dev->lock); |
482 | } |
483 | |
484 | /* re-init driver-visible data structures */ |
485 | udc_reinit(dev); |
486 | } |
487 | |
488 | |
489 | /* |
490 | * Unregister entry point for the peripheral controller driver. |
491 | */ |
492 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
493 | { |
494 | struct jz4740_udc *dev = &jz4740_udc_controller; |
495 | unsigned long flags; |
496 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
497 | |
498 | if (!dev) |
499 | return -ENODEV; |
500 | if (!driver || driver != dev->driver) |
501 | return -EINVAL; |
502 | if (!driver->unbind) |
503 | return -EBUSY; |
504 | |
505 | spin_lock_irqsave(&dev->lock, flags); |
506 | dev->driver = 0; |
507 | stop_activity(dev, driver); |
508 | spin_unlock_irqrestore(&dev->lock, flags); |
509 | |
510 | driver->unbind(&dev->gadget); |
511 | |
512 | udc_disable(dev); |
513 | |
514 | DEBUG("unregistered driver '%s'\n", driver->driver.name); |
515 | |
516 | return 0; |
517 | } |
518 | |
519 | EXPORT_SYMBOL(usb_gadget_unregister_driver); |
520 | |
521 | /*-------------------------------------------------------------------------*/ |
522 | |
523 | /** Write request to FIFO (max write == maxp size) |
524 | * Return: 0 = still running, 1 = completed, negative = errno |
525 | * NOTE: INDEX register must be set for EP |
526 | */ |
527 | static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
528 | { |
529 | struct jz4740_udc *dev = ep->dev; |
530 | uint32_t max, csr; |
531 | |
532 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
533 | max = le16_to_cpu(ep->desc->wMaxPacketSize); |
534 | |
535 | csr = usb_readb(dev, ep->csr); |
536 | |
537 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
538 | unsigned count; |
539 | int is_last, is_short; |
540 | |
541 | count = write_packet(ep, req, max); |
542 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
543 | |
544 | /* last packet is usually short (or a zlp) */ |
545 | if (unlikely(count != max)) |
546 | is_last = is_short = 1; |
547 | else { |
548 | if (likely(req->req.length != req->req.actual) |
549 | || req->req.zero) |
550 | is_last = 0; |
551 | else |
552 | is_last = 1; |
553 | /* interrupt/iso maxpacket may not fill the fifo */ |
554 | is_short = unlikely(max < ep_maxpacket(ep)); |
555 | } |
556 | |
557 | DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__, |
558 | ep->ep.name, count, |
559 | is_last ? "/L" : "", is_short ? "/S" : "", |
560 | req->req.length - req->req.actual, req); |
561 | |
562 | /* requests complete when all IN data is in the FIFO */ |
563 | if (is_last) { |
564 | done(ep, req, 0); |
565 | if (list_empty(&ep->queue)) { |
566 | pio_irq_disable(ep); |
567 | } |
568 | return 1; |
569 | } |
570 | } else { |
571 | DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep)); |
572 | } |
573 | |
574 | return 0; |
575 | } |
576 | |
577 | /** Read to request from FIFO (max read == bytes in fifo) |
578 | * Return: 0 = still running, 1 = completed, negative = errno |
579 | * NOTE: INDEX register must be set for EP |
580 | */ |
581 | static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
582 | { |
583 | struct jz4740_udc *dev = ep->dev; |
584 | uint32_t csr; |
585 | unsigned count, is_short; |
586 | |
587 | /* make sure there's a packet in the FIFO. */ |
588 | csr = usb_readb(dev, ep->csr); |
589 | if (!(csr & USB_OUTCSR_OUTPKTRDY)) { |
590 | DEBUG("%s: Packet NOT ready!\n", __FUNCTION__); |
591 | return -EINVAL; |
592 | } |
593 | |
594 | /* read all bytes from this packet */ |
595 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
596 | |
597 | is_short = (count < ep->ep.maxpacket); |
598 | |
599 | count = read_packet(ep, req, count); |
600 | |
601 | DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n", |
602 | ep->ep.name, csr, count, |
603 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
604 | |
605 | /* Clear OutPktRdy */ |
606 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
607 | |
608 | /* completion */ |
609 | if (is_short || req->req.actual == req->req.length) { |
610 | done(ep, req, 0); |
611 | |
612 | if (list_empty(&ep->queue)) |
613 | pio_irq_disable(ep); |
614 | return 1; |
615 | } |
616 | |
617 | /* finished that packet. the next one may be waiting... */ |
618 | return 0; |
619 | } |
620 | |
621 | /* |
622 | * done - retire a request; caller blocked irqs |
623 | * INDEX register is preserved to keep same |
624 | */ |
625 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status) |
626 | { |
627 | unsigned int stopped = ep->stopped; |
628 | uint32_t index; |
629 | |
630 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
631 | list_del_init(&req->queue); |
632 | |
633 | if (likely(req->req.status == -EINPROGRESS)) |
634 | req->req.status = status; |
635 | else |
636 | status = req->req.status; |
637 | |
638 | if (status && status != -ESHUTDOWN) |
639 | DEBUG("complete %s req %p stat %d len %u/%u\n", |
640 | ep->ep.name, &req->req, status, |
641 | req->req.actual, req->req.length); |
642 | |
643 | /* don't modify queue heads during completion callback */ |
644 | ep->stopped = 1; |
645 | /* Read current index (completion may modify it) */ |
646 | index = usb_readb(ep->dev, JZ_REG_UDC_INDEX); |
647 | spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags); |
648 | |
649 | req->req.complete(&ep->ep, &req->req); |
650 | |
651 | spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags); |
652 | /* Restore index */ |
653 | jz_udc_set_index(ep->dev, index); |
654 | ep->stopped = stopped; |
655 | } |
656 | |
657 | static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep) |
658 | { |
659 | if (ep_is_in(ep)) |
660 | return JZ_REG_UDC_INTRINE; |
661 | else |
662 | return JZ_REG_UDC_INTROUTE; |
663 | } |
664 | |
665 | /** Enable EP interrupt */ |
666 | static void pio_irq_enable(struct jz4740_ep *ep) |
667 | { |
668 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
669 | |
670 | usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep))); |
671 | } |
672 | |
673 | /** Disable EP interrupt */ |
674 | static void pio_irq_disable(struct jz4740_ep *ep) |
675 | { |
676 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
677 | |
678 | usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep))); |
679 | } |
680 | |
681 | /* |
682 | * nuke - dequeue ALL requests |
683 | */ |
684 | static void nuke(struct jz4740_ep *ep, int status) |
685 | { |
686 | struct jz4740_request *req; |
687 | |
688 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
689 | |
690 | /* Flush FIFO */ |
691 | flush(ep); |
692 | |
693 | /* called with irqs blocked */ |
694 | while (!list_empty(&ep->queue)) { |
695 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
696 | done(ep, req, status); |
697 | } |
698 | |
699 | /* Disable IRQ if EP is enabled (has descriptor) */ |
700 | if (ep->desc) |
701 | pio_irq_disable(ep); |
702 | } |
703 | |
704 | /** Flush EP FIFO |
705 | * NOTE: INDEX register must be set before this call |
706 | */ |
707 | static void flush(struct jz4740_ep *ep) |
708 | { |
709 | DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name); |
710 | |
711 | switch (ep->type) { |
712 | case ep_bulk_in: |
713 | case ep_interrupt: |
714 | usb_setb(ep->dev, ep->csr, USB_INCSR_FF); |
715 | break; |
716 | case ep_bulk_out: |
717 | usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF); |
718 | break; |
719 | case ep_control: |
720 | break; |
721 | } |
722 | } |
723 | |
724 | /** |
725 | * jz4740_in_epn - handle IN interrupt |
726 | */ |
727 | static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
728 | { |
729 | uint32_t csr; |
730 | struct jz4740_ep *ep = &dev->ep[ep_idx + 1]; |
731 | struct jz4740_request *req; |
732 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
733 | |
734 | jz_udc_select_ep(ep); |
735 | |
736 | csr = usb_readb(dev, ep->csr); |
737 | DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr); |
738 | |
739 | if (csr & USB_INCSR_SENTSTALL) { |
740 | DEBUG("USB_INCSR_SENTSTALL\n"); |
741 | usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL); |
742 | return; |
743 | } |
744 | |
745 | if (!ep->desc) { |
746 | DEBUG("%s: NO EP DESC\n", __FUNCTION__); |
747 | return; |
748 | } |
749 | |
750 | if (!list_empty(&ep->queue)) { |
751 | req = list_first_entry(&ep->queue, struct jz4740_request, queue); |
752 | write_fifo(ep, req); |
753 | } |
754 | } |
755 | |
756 | /* |
757 | * Bulk OUT (recv) |
758 | */ |
759 | static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
760 | { |
761 | struct jz4740_ep *ep = &dev->ep[ep_idx]; |
762 | struct jz4740_request *req; |
763 | |
764 | DEBUG("%s: %d\n", __FUNCTION__, ep_idx); |
765 | |
766 | jz_udc_select_ep(ep); |
767 | if (ep->desc) { |
768 | uint32_t csr; |
769 | |
770 | while ((csr = usb_readb(dev, ep->csr)) & |
771 | (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) { |
772 | DEBUG("%s: %x\n", __FUNCTION__, csr); |
773 | |
774 | if (csr & USB_OUTCSR_SENTSTALL) { |
775 | DEBUG("%s: stall sent, flush fifo\n", |
776 | __FUNCTION__); |
777 | /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */ |
778 | flush(ep); |
779 | } else if (csr & USB_OUTCSR_OUTPKTRDY) { |
780 | if (list_empty(&ep->queue)) |
781 | req = 0; |
782 | else |
783 | req = |
784 | list_entry(ep->queue.next, |
785 | struct jz4740_request, |
786 | queue); |
787 | |
788 | if (!req) { |
789 | DEBUG("%s: NULL REQ %d\n", |
790 | __FUNCTION__, ep_idx); |
791 | break; |
792 | } else { |
793 | read_fifo(ep, req); |
794 | } |
795 | } |
796 | } |
797 | } else { |
798 | /* Throw packet away.. */ |
799 | DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx); |
800 | flush(ep); |
801 | } |
802 | } |
803 | |
804 | /** Halt specific EP |
805 | * Return 0 if success |
806 | * NOTE: Sets INDEX register to EP ! |
807 | */ |
808 | static int jz4740_set_halt(struct usb_ep *_ep, int value) |
809 | { |
810 | struct jz4740_udc *dev; |
811 | struct jz4740_ep *ep; |
812 | unsigned long flags; |
813 | |
814 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
815 | |
816 | ep = container_of(_ep, struct jz4740_ep, ep); |
817 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
818 | DEBUG("%s, bad ep\n", __FUNCTION__); |
819 | return -EINVAL; |
820 | } |
821 | |
822 | dev = ep->dev; |
823 | |
824 | spin_lock_irqsave(&dev->lock, flags); |
825 | |
826 | jz_udc_select_ep(ep); |
827 | |
828 | DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value); |
829 | |
830 | if (ep_index(ep) == 0) { |
831 | /* EP0 */ |
832 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL); |
833 | } else if (ep_is_in(ep)) { |
834 | uint32_t csr = usb_readb(dev, ep->csr); |
835 | if (value && ((csr & USB_INCSR_FFNOTEMPT) |
836 | || !list_empty(&ep->queue))) { |
837 | /* |
838 | * Attempts to halt IN endpoints will fail (returning -EAGAIN) |
839 | * if any transfer requests are still queued, or if the controller |
840 | * FIFO still holds bytes that the host hasnÂ’t collected. |
841 | */ |
842 | spin_unlock_irqrestore(&dev->lock, flags); |
843 | DEBUG |
844 | ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n", |
845 | (csr & USB_INCSR_FFNOTEMPT), |
846 | !list_empty(&ep->queue)); |
847 | return -EAGAIN; |
848 | } |
849 | flush(ep); |
850 | if (value) { |
851 | usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL); |
852 | } else { |
853 | usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL); |
854 | usb_setb(dev, ep->csr, USB_INCSR_CDT); |
855 | } |
856 | } else { |
857 | |
858 | flush(ep); |
859 | if (value) { |
860 | usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
861 | } else { |
862 | usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
863 | usb_setb(dev, ep->csr, USB_OUTCSR_CDT); |
864 | } |
865 | } |
866 | |
867 | ep->stopped = value; |
868 | |
869 | spin_unlock_irqrestore(&dev->lock, flags); |
870 | |
871 | DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS"); |
872 | |
873 | return 0; |
874 | } |
875 | |
876 | |
877 | static int jz4740_ep_enable(struct usb_ep *_ep, |
878 | const struct usb_endpoint_descriptor *desc) |
879 | { |
880 | struct jz4740_ep *ep; |
881 | struct jz4740_udc *dev; |
882 | unsigned long flags; |
883 | uint32_t max, csrh = 0; |
884 | |
885 | DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name); |
886 | |
887 | if (!_ep || !desc) |
888 | return -EINVAL; |
889 | |
890 | ep = container_of(_ep, struct jz4740_ep, ep); |
891 | if (ep->desc || ep->type == ep_control |
892 | || desc->bDescriptorType != USB_DT_ENDPOINT |
893 | || ep->bEndpointAddress != desc->bEndpointAddress) { |
894 | DEBUG("%s, bad ep or descriptor\n", __FUNCTION__); |
895 | return -EINVAL; |
896 | } |
897 | |
898 | /* xfer types must match, except that interrupt ~= bulk */ |
899 | if (ep->bmAttributes != desc->bmAttributes |
900 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK |
901 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { |
902 | DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); |
903 | return -EINVAL; |
904 | } |
905 | |
906 | dev = ep->dev; |
907 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { |
908 | DEBUG("%s, bogus device state\n", __FUNCTION__); |
909 | return -ESHUTDOWN; |
910 | } |
911 | |
912 | max = le16_to_cpu(desc->wMaxPacketSize); |
913 | |
914 | spin_lock_irqsave(&ep->dev->lock, flags); |
915 | |
916 | /* Configure the endpoint */ |
917 | jz_udc_select_ep(ep); |
918 | if (ep_is_in(ep)) { |
919 | usb_writew(dev, JZ_REG_UDC_INMAXP, max); |
920 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
921 | case USB_ENDPOINT_XFER_BULK: |
922 | case USB_ENDPOINT_XFER_INT: |
923 | csrh &= ~USB_INCSRH_ISO; |
924 | break; |
925 | case USB_ENDPOINT_XFER_ISOC: |
926 | csrh |= USB_INCSRH_ISO; |
927 | break; |
928 | } |
929 | usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh); |
930 | } |
931 | else { |
932 | usb_writew(dev, JZ_REG_UDC_OUTMAXP, max); |
933 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
934 | case USB_ENDPOINT_XFER_BULK: |
935 | csrh &= ~USB_OUTCSRH_ISO; |
936 | break; |
937 | case USB_ENDPOINT_XFER_INT: |
938 | csrh &= ~USB_OUTCSRH_ISO; |
939 | csrh |= USB_OUTCSRH_DNYT; |
940 | break; |
941 | case USB_ENDPOINT_XFER_ISOC: |
942 | csrh |= USB_OUTCSRH_ISO; |
943 | break; |
944 | } |
945 | usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh); |
946 | } |
947 | |
948 | |
949 | ep->stopped = 0; |
950 | ep->desc = desc; |
951 | ep->ep.maxpacket = max; |
952 | |
953 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
954 | |
955 | /* Reset halt state (does flush) */ |
956 | jz4740_set_halt(_ep, 0); |
957 | |
958 | DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name); |
959 | |
960 | return 0; |
961 | } |
962 | |
963 | /** Disable EP |
964 | * NOTE: Sets INDEX register |
965 | */ |
966 | static int jz4740_ep_disable(struct usb_ep *_ep) |
967 | { |
968 | struct jz4740_ep *ep; |
969 | unsigned long flags; |
970 | |
971 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
972 | |
973 | ep = container_of(_ep, struct jz4740_ep, ep); |
974 | if (!_ep || !ep->desc) { |
975 | DEBUG("%s, %s not enabled\n", __FUNCTION__, |
976 | _ep ? ep->ep.name : NULL); |
977 | return -EINVAL; |
978 | } |
979 | |
980 | spin_lock_irqsave(&ep->dev->lock, flags); |
981 | |
982 | jz_udc_select_ep(ep); |
983 | |
984 | /* Nuke all pending requests (does flush) */ |
985 | nuke(ep, -ESHUTDOWN); |
986 | |
987 | /* Disable ep IRQ */ |
988 | pio_irq_disable(ep); |
989 | |
990 | ep->desc = 0; |
991 | ep->stopped = 1; |
992 | |
993 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
994 | |
995 | DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name); |
996 | return 0; |
997 | } |
998 | |
999 | static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
1000 | { |
1001 | struct jz4740_request *req; |
1002 | |
1003 | req = kzalloc(sizeof(*req), gfp_flags); |
1004 | if (!req) |
1005 | return NULL; |
1006 | |
1007 | INIT_LIST_HEAD(&req->queue); |
1008 | |
1009 | return &req->req; |
1010 | } |
1011 | |
1012 | static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req) |
1013 | { |
1014 | struct jz4740_request *req; |
1015 | |
1016 | req = container_of(_req, struct jz4740_request, req); |
1017 | WARN_ON(!list_empty(&req->queue)); |
1018 | |
1019 | kfree(req); |
1020 | } |
1021 | |
1022 | /*--------------------------------------------------------------------*/ |
1023 | |
1024 | /** Queue one request |
1025 | * Kickstart transfer if needed |
1026 | * NOTE: Sets INDEX register |
1027 | */ |
1028 | static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req, |
1029 | gfp_t gfp_flags) |
1030 | { |
1031 | struct jz4740_request *req; |
1032 | struct jz4740_ep *ep; |
1033 | struct jz4740_udc *dev; |
1034 | |
1035 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1036 | |
1037 | req = container_of(_req, struct jz4740_request, req); |
1038 | if (unlikely |
1039 | (!_req || !_req->complete || !_req->buf |
1040 | || !list_empty(&req->queue))) { |
1041 | DEBUG("%s, bad params\n", __FUNCTION__); |
1042 | return -EINVAL; |
1043 | } |
1044 | |
1045 | ep = container_of(_ep, struct jz4740_ep, ep); |
1046 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
1047 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1048 | return -EINVAL; |
1049 | } |
1050 | |
1051 | dev = ep->dev; |
1052 | if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { |
1053 | DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver); |
1054 | return -ESHUTDOWN; |
1055 | } |
1056 | |
1057 | DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length, |
1058 | _req->buf); |
1059 | |
1060 | spin_lock_irqsave(&dev->lock, dev->lock_flags); |
1061 | |
1062 | _req->status = -EINPROGRESS; |
1063 | _req->actual = 0; |
1064 | |
1065 | /* kickstart this i/o queue? */ |
1066 | DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue), |
1067 | ep->stopped); |
1068 | if (list_empty(&ep->queue) && likely(!ep->stopped)) { |
1069 | uint32_t csr; |
1070 | |
1071 | if (unlikely(ep_index(ep) == 0)) { |
1072 | /* EP0 */ |
1073 | list_add_tail(&req->queue, &ep->queue); |
1074 | jz4740_ep0_kick(dev, ep); |
1075 | req = 0; |
1076 | } |
1077 | else if (ep_is_in(ep)) { |
1078 | /* EP1 & EP2 */ |
1079 | jz_udc_select_ep(ep); |
1080 | csr = usb_readb(dev, ep->csr); |
1081 | pio_irq_enable(ep); |
1082 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
1083 | if (write_fifo(ep, req) == 1) |
1084 | req = 0; |
1085 | } |
1086 | } else { |
1087 | /* EP1 */ |
1088 | jz_udc_select_ep(ep); |
1089 | csr = usb_readb(dev, ep->csr); |
1090 | pio_irq_enable(ep); |
1091 | if (csr & USB_OUTCSR_OUTPKTRDY) { |
1092 | if (read_fifo(ep, req) == 1) |
1093 | req = 0; |
1094 | } |
1095 | } |
1096 | } |
1097 | |
1098 | /* pio or dma irq handler advances the queue. */ |
1099 | if (likely(req != 0)) |
1100 | list_add_tail(&req->queue, &ep->queue); |
1101 | |
1102 | spin_unlock_irqrestore(&dev->lock, dev->lock_flags); |
1103 | |
1104 | return 0; |
1105 | } |
1106 | |
1107 | /* dequeue JUST ONE request */ |
1108 | static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
1109 | { |
1110 | struct jz4740_ep *ep; |
1111 | struct jz4740_request *req; |
1112 | unsigned long flags; |
1113 | |
1114 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1115 | |
1116 | ep = container_of(_ep, struct jz4740_ep, ep); |
1117 | if (!_ep || ep->type == ep_control) |
1118 | return -EINVAL; |
1119 | |
1120 | spin_lock_irqsave(&ep->dev->lock, flags); |
1121 | |
1122 | /* make sure it's actually queued on this endpoint */ |
1123 | list_for_each_entry(req, &ep->queue, queue) { |
1124 | if (&req->req == _req) |
1125 | break; |
1126 | } |
1127 | if (&req->req != _req) { |
1128 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1129 | return -EINVAL; |
1130 | } |
1131 | done(ep, req, -ECONNRESET); |
1132 | |
1133 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1134 | return 0; |
1135 | } |
1136 | |
1137 | /** Return bytes in EP FIFO |
1138 | * NOTE: Sets INDEX register to EP |
1139 | */ |
1140 | static int jz4740_fifo_status(struct usb_ep *_ep) |
1141 | { |
1142 | uint32_t csr; |
1143 | int count = 0; |
1144 | struct jz4740_ep *ep; |
1145 | unsigned long flags; |
1146 | |
1147 | ep = container_of(_ep, struct jz4740_ep, ep); |
1148 | if (!_ep) { |
1149 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1150 | return -ENODEV; |
1151 | } |
1152 | |
1153 | DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep)); |
1154 | |
1155 | /* LPD can't report unclaimed bytes from IN fifos */ |
1156 | if (ep_is_in(ep)) |
1157 | return -EOPNOTSUPP; |
1158 | |
1159 | spin_lock_irqsave(&ep->dev->lock, flags); |
1160 | jz_udc_select_ep(ep); |
1161 | |
1162 | csr = usb_readb(ep->dev, ep->csr); |
1163 | if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN || |
1164 | csr & 0x1) { |
1165 | count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1166 | } |
1167 | |
1168 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1169 | |
1170 | return count; |
1171 | } |
1172 | |
1173 | /** Flush EP FIFO |
1174 | * NOTE: Sets INDEX register to EP |
1175 | */ |
1176 | static void jz4740_fifo_flush(struct usb_ep *_ep) |
1177 | { |
1178 | struct jz4740_ep *ep; |
1179 | unsigned long flags; |
1180 | |
1181 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1182 | |
1183 | ep = container_of(_ep, struct jz4740_ep, ep); |
1184 | if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) { |
1185 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1186 | return; |
1187 | } |
1188 | |
1189 | spin_lock_irqsave(&ep->dev->lock, flags); |
1190 | |
1191 | jz_udc_select_ep(ep); |
1192 | flush(ep); |
1193 | |
1194 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1195 | } |
1196 | |
1197 | /****************************************************************/ |
1198 | /* End Point 0 related functions */ |
1199 | /****************************************************************/ |
1200 | |
1201 | /* return: 0 = still running, 1 = completed, negative = errno */ |
1202 | static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1203 | { |
1204 | uint32_t max; |
1205 | unsigned count; |
1206 | int is_last; |
1207 | |
1208 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1209 | max = ep_maxpacket(ep); |
1210 | |
1211 | count = write_packet(ep, req, max); |
1212 | |
1213 | /* last packet is usually short (or a zlp) */ |
1214 | if (unlikely(count != max)) |
1215 | is_last = 1; |
1216 | else { |
1217 | if (likely(req->req.length != req->req.actual) || req->req.zero) |
1218 | is_last = 0; |
1219 | else |
1220 | is_last = 1; |
1221 | } |
1222 | |
1223 | DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__, |
1224 | ep->ep.name, count, |
1225 | is_last ? "/L" : "", req->req.length - req->req.actual, req); |
1226 | |
1227 | /* requests complete when all IN data is in the FIFO */ |
1228 | if (is_last) { |
1229 | done(ep, req, 0); |
1230 | return 1; |
1231 | } |
1232 | |
1233 | return 0; |
1234 | } |
1235 | |
1236 | static inline int jz4740_fifo_read(struct jz4740_ep *ep, |
1237 | unsigned char *cp, int max) |
1238 | { |
1239 | int bytes; |
1240 | int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1241 | |
1242 | if (count > max) |
1243 | count = max; |
1244 | bytes = count; |
1245 | while (count--) |
1246 | *cp++ = usb_readb(ep->dev, ep->fifo); |
1247 | |
1248 | return bytes; |
1249 | } |
1250 | |
1251 | static inline void jz4740_fifo_write(struct jz4740_ep *ep, |
1252 | unsigned char *cp, int count) |
1253 | { |
1254 | DEBUG("fifo_write: %d %d\n", ep_index(ep), count); |
1255 | while (count--) |
1256 | usb_writeb(ep->dev, ep->fifo, *cp++); |
1257 | } |
1258 | |
1259 | static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1260 | { |
1261 | struct jz4740_udc *dev = ep->dev; |
1262 | uint32_t csr; |
1263 | uint8_t *buf; |
1264 | unsigned bufferspace, count, is_short; |
1265 | |
1266 | DEBUG_EP0("%s\n", __FUNCTION__); |
1267 | |
1268 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1269 | if (!(csr & USB_CSR0_OUTPKTRDY)) |
1270 | return 0; |
1271 | |
1272 | buf = req->req.buf + req->req.actual; |
1273 | prefetchw(buf); |
1274 | bufferspace = req->req.length - req->req.actual; |
1275 | |
1276 | /* read all bytes from this packet */ |
1277 | if (likely(csr & USB_CSR0_OUTPKTRDY)) { |
1278 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
1279 | req->req.actual += min(count, bufferspace); |
1280 | } else /* zlp */ |
1281 | count = 0; |
1282 | |
1283 | is_short = (count < ep->ep.maxpacket); |
1284 | DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n", |
1285 | ep->ep.name, csr, count, |
1286 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
1287 | |
1288 | while (likely(count-- != 0)) { |
1289 | uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo); |
1290 | |
1291 | if (unlikely(bufferspace == 0)) { |
1292 | /* this happens when the driver's buffer |
1293 | * is smaller than what the host sent. |
1294 | * discard the extra data. |
1295 | */ |
1296 | if (req->req.status != -EOVERFLOW) |
1297 | DEBUG_EP0("%s overflow %d\n", ep->ep.name, |
1298 | count); |
1299 | req->req.status = -EOVERFLOW; |
1300 | } else { |
1301 | *buf++ = byte; |
1302 | bufferspace--; |
1303 | } |
1304 | } |
1305 | |
1306 | /* completion */ |
1307 | if (is_short || req->req.actual == req->req.length) { |
1308 | done(ep, req, 0); |
1309 | return 1; |
1310 | } |
1311 | |
1312 | /* finished that packet. the next one may be waiting... */ |
1313 | return 0; |
1314 | } |
1315 | |
1316 | /** |
1317 | * udc_set_address - set the USB address for this device |
1318 | * @address: |
1319 | * |
1320 | * Called from control endpoint function after it decodes a set address setup packet. |
1321 | */ |
1322 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address) |
1323 | { |
1324 | DEBUG_EP0("%s: %d\n", __FUNCTION__, address); |
1325 | |
1326 | usb_writeb(dev, JZ_REG_UDC_FADDR, address); |
1327 | } |
1328 | |
1329 | /* |
1330 | * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY) |
1331 | * - if error |
1332 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1333 | * - else |
1334 | * set USB_CSR0_SVDOUTPKTRDY bit |
1335 | if last set USB_CSR0_DATAEND bit |
1336 | */ |
1337 | static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart) |
1338 | { |
1339 | struct jz4740_request *req; |
1340 | struct jz4740_ep *ep = &dev->ep[0]; |
1341 | int ret; |
1342 | |
1343 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1344 | |
1345 | if (list_empty(&ep->queue)) |
1346 | req = 0; |
1347 | else |
1348 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1349 | |
1350 | if (req) { |
1351 | if (req->req.length == 0) { |
1352 | DEBUG_EP0("ZERO LENGTH OUT!\n"); |
1353 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1354 | dev->ep0state = WAIT_FOR_SETUP; |
1355 | return; |
1356 | } else if (kickstart) { |
1357 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY)); |
1358 | return; |
1359 | } |
1360 | ret = read_fifo_ep0(ep, req); |
1361 | if (ret) { |
1362 | /* Done! */ |
1363 | DEBUG_EP0("%s: finished, waiting for status\n", |
1364 | __FUNCTION__); |
1365 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1366 | dev->ep0state = WAIT_FOR_SETUP; |
1367 | } else { |
1368 | /* Not done yet.. */ |
1369 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1370 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1371 | } |
1372 | } else { |
1373 | DEBUG_EP0("NO REQ??!\n"); |
1374 | } |
1375 | } |
1376 | |
1377 | /* |
1378 | * DATA_STATE_XMIT |
1379 | */ |
1380 | static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr) |
1381 | { |
1382 | struct jz4740_request *req; |
1383 | struct jz4740_ep *ep = &dev->ep[0]; |
1384 | int ret, need_zlp = 0; |
1385 | |
1386 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1387 | |
1388 | if (list_empty(&ep->queue)) |
1389 | req = 0; |
1390 | else |
1391 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1392 | |
1393 | if (!req) { |
1394 | DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__); |
1395 | return 0; |
1396 | } |
1397 | |
1398 | if (req->req.length == 0) { |
1399 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1400 | dev->ep0state = WAIT_FOR_SETUP; |
1401 | return 1; |
1402 | } |
1403 | |
1404 | if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) { |
1405 | /* Next write will end with the packet size, */ |
1406 | /* so we need zero-length-packet */ |
1407 | need_zlp = 1; |
1408 | } |
1409 | |
1410 | ret = write_fifo_ep0(ep, req); |
1411 | |
1412 | if (ret == 1 && !need_zlp) { |
1413 | /* Last packet */ |
1414 | DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__); |
1415 | |
1416 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1417 | dev->ep0state = WAIT_FOR_SETUP; |
1418 | } else { |
1419 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1420 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1421 | } |
1422 | |
1423 | if (need_zlp) { |
1424 | DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__); |
1425 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1426 | dev->ep0state = DATA_STATE_NEED_ZLP; |
1427 | } |
1428 | |
1429 | return 1; |
1430 | } |
1431 | |
1432 | static int jz4740_handle_get_status(struct jz4740_udc *dev, |
1433 | struct usb_ctrlrequest *ctrl) |
1434 | { |
1435 | struct jz4740_ep *ep0 = &dev->ep[0]; |
1436 | struct jz4740_ep *qep; |
1437 | int reqtype = (ctrl->bRequestType & USB_RECIP_MASK); |
1438 | uint16_t val = 0; |
1439 | |
1440 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1441 | |
1442 | if (reqtype == USB_RECIP_INTERFACE) { |
1443 | /* This is not supported. |
1444 | * And according to the USB spec, this one does nothing.. |
1445 | * Just return 0 |
1446 | */ |
1447 | DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n"); |
1448 | } else if (reqtype == USB_RECIP_DEVICE) { |
1449 | DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n"); |
1450 | val |= (1 << 0); /* Self powered */ |
1451 | /*val |= (1<<1); *//* Remote wakeup */ |
1452 | } else if (reqtype == USB_RECIP_ENDPOINT) { |
1453 | int ep_num = (ctrl->wIndex & ~USB_DIR_IN); |
1454 | |
1455 | DEBUG_SETUP |
1456 | ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n", |
1457 | ep_num, ctrl->wLength); |
1458 | |
1459 | if (ctrl->wLength > 2 || ep_num > 3) |
1460 | return -EOPNOTSUPP; |
1461 | |
1462 | qep = &dev->ep[ep_num]; |
1463 | if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0) |
1464 | && ep_index(qep) != 0) { |
1465 | return -EOPNOTSUPP; |
1466 | } |
1467 | |
1468 | jz_udc_select_ep(qep); |
1469 | |
1470 | /* Return status on next IN token */ |
1471 | switch (qep->type) { |
1472 | case ep_control: |
1473 | val = |
1474 | (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) == |
1475 | USB_CSR0_SENDSTALL; |
1476 | break; |
1477 | case ep_bulk_in: |
1478 | case ep_interrupt: |
1479 | val = |
1480 | (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) == |
1481 | USB_INCSR_SENDSTALL; |
1482 | break; |
1483 | case ep_bulk_out: |
1484 | val = |
1485 | (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) == |
1486 | USB_OUTCSR_SENDSTALL; |
1487 | break; |
1488 | } |
1489 | |
1490 | /* Back to EP0 index */ |
1491 | jz_udc_set_index(dev, 0); |
1492 | |
1493 | DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num, |
1494 | ctrl->wIndex, val); |
1495 | } else { |
1496 | DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype); |
1497 | return -EOPNOTSUPP; |
1498 | } |
1499 | |
1500 | /* Clear "out packet ready" */ |
1501 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1502 | /* Put status to FIFO */ |
1503 | jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val)); |
1504 | /* Issue "In packet ready" */ |
1505 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1506 | |
1507 | return 0; |
1508 | } |
1509 | |
1510 | /* |
1511 | * WAIT_FOR_SETUP (OUTPKTRDY) |
1512 | * - read data packet from EP0 FIFO |
1513 | * - decode command |
1514 | * - if error |
1515 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1516 | * - else |
1517 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits |
1518 | */ |
1519 | static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr) |
1520 | { |
1521 | struct jz4740_ep *ep = &dev->ep[0]; |
1522 | struct usb_ctrlrequest ctrl; |
1523 | int i; |
1524 | |
1525 | DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr); |
1526 | |
1527 | /* Nuke all previous transfers */ |
1528 | nuke(ep, -EPROTO); |
1529 | |
1530 | /* read control req from fifo (8 bytes) */ |
1531 | jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8); |
1532 | |
1533 | DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n", |
1534 | ctrl.bRequestType, ctrl.bRequest, |
1535 | ctrl.wValue, ctrl.wIndex, ctrl.wLength); |
1536 | |
1537 | /* Set direction of EP0 */ |
1538 | if (likely(ctrl.bRequestType & USB_DIR_IN)) { |
1539 | ep->bEndpointAddress |= USB_DIR_IN; |
1540 | } else { |
1541 | ep->bEndpointAddress &= ~USB_DIR_IN; |
1542 | } |
1543 | |
1544 | /* Handle some SETUP packets ourselves */ |
1545 | switch (ctrl.bRequest) { |
1546 | case USB_REQ_SET_ADDRESS: |
1547 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1548 | break; |
1549 | |
1550 | DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue); |
1551 | udc_set_address(dev, ctrl.wValue); |
1552 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1553 | return; |
1554 | |
1555 | case USB_REQ_SET_CONFIGURATION: |
1556 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1557 | break; |
1558 | |
1559 | DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue); |
1560 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1561 | |
1562 | /* Enable RESUME and SUSPEND interrupts */ |
1563 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND)); |
1564 | break; |
1565 | |
1566 | case USB_REQ_SET_INTERFACE: |
1567 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1568 | break; |
1569 | |
1570 | DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue); |
1571 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1572 | break; |
1573 | |
1574 | case USB_REQ_GET_STATUS: |
1575 | if (jz4740_handle_get_status(dev, &ctrl) == 0) |
1576 | return; |
1577 | |
1578 | case USB_REQ_CLEAR_FEATURE: |
1579 | case USB_REQ_SET_FEATURE: |
1580 | if (ctrl.bRequestType == USB_RECIP_ENDPOINT) { |
1581 | struct jz4740_ep *qep; |
1582 | int ep_num = (ctrl.wIndex & 0x0f); |
1583 | |
1584 | /* Support only HALT feature */ |
1585 | if (ctrl.wValue != 0 || ctrl.wLength != 0 |
1586 | || ep_num > 3 || ep_num < 1) |
1587 | break; |
1588 | |
1589 | qep = &dev->ep[ep_num]; |
1590 | spin_unlock(&dev->lock); |
1591 | if (ctrl.bRequest == USB_REQ_SET_FEATURE) { |
1592 | DEBUG_SETUP("SET_FEATURE (%d)\n", |
1593 | ep_num); |
1594 | jz4740_set_halt(&qep->ep, 1); |
1595 | } else { |
1596 | DEBUG_SETUP("CLR_FEATURE (%d)\n", |
1597 | ep_num); |
1598 | jz4740_set_halt(&qep->ep, 0); |
1599 | } |
1600 | spin_lock(&dev->lock); |
1601 | |
1602 | jz_udc_set_index(dev, 0); |
1603 | |
1604 | /* Reply with a ZLP on next IN token */ |
1605 | usb_setb(dev, JZ_REG_UDC_CSR0, |
1606 | (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1607 | return; |
1608 | } |
1609 | break; |
1610 | |
1611 | default: |
1612 | break; |
1613 | } |
1614 | |
1615 | /* gadget drivers see class/vendor specific requests, |
1616 | * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, |
1617 | * and more. |
1618 | */ |
1619 | if (dev->driver) { |
1620 | /* device-2-host (IN) or no data setup command, process immediately */ |
1621 | spin_unlock(&dev->lock); |
1622 | |
1623 | i = dev->driver->setup(&dev->gadget, &ctrl); |
1624 | spin_lock(&dev->lock); |
1625 | |
1626 | if (unlikely(i < 0)) { |
1627 | /* setup processing failed, force stall */ |
1628 | DEBUG_SETUP |
1629 | (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n", |
1630 | i); |
1631 | jz_udc_set_index(dev, 0); |
1632 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL)); |
1633 | |
1634 | /* ep->stopped = 1; */ |
1635 | dev->ep0state = WAIT_FOR_SETUP; |
1636 | } |
1637 | else { |
1638 | DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength); |
1639 | /* if (!ctrl.wLength) { |
1640 | usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1641 | }*/ |
1642 | } |
1643 | } |
1644 | } |
1645 | |
1646 | /* |
1647 | * DATA_STATE_NEED_ZLP |
1648 | */ |
1649 | static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr) |
1650 | { |
1651 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1652 | |
1653 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1654 | dev->ep0state = WAIT_FOR_SETUP; |
1655 | } |
1656 | |
1657 | /* |
1658 | * handle ep0 interrupt |
1659 | */ |
1660 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr) |
1661 | { |
1662 | struct jz4740_ep *ep = &dev->ep[0]; |
1663 | uint32_t csr; |
1664 | |
1665 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1666 | /* Set index 0 */ |
1667 | jz_udc_set_index(dev, 0); |
1668 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1669 | |
1670 | DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]); |
1671 | |
1672 | /* |
1673 | * if SENT_STALL is set |
1674 | * - clear the SENT_STALL bit |
1675 | */ |
1676 | if (csr & USB_CSR0_SENTSTALL) { |
1677 | DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr); |
1678 | usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL); |
1679 | nuke(ep, -ECONNABORTED); |
1680 | dev->ep0state = WAIT_FOR_SETUP; |
1681 | return; |
1682 | } |
1683 | |
1684 | /* |
1685 | * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear |
1686 | * - fill EP0 FIFO |
1687 | * - if last packet |
1688 | * - set IN_PKT_RDY | DATA_END |
1689 | * - else |
1690 | * set IN_PKT_RDY |
1691 | */ |
1692 | if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) { |
1693 | DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n", |
1694 | __FUNCTION__); |
1695 | |
1696 | switch (dev->ep0state) { |
1697 | case DATA_STATE_XMIT: |
1698 | DEBUG_EP0("continue with DATA_STATE_XMIT\n"); |
1699 | jz4740_ep0_in(dev, csr); |
1700 | return; |
1701 | case DATA_STATE_NEED_ZLP: |
1702 | DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n"); |
1703 | jz4740_ep0_in_zlp(dev, csr); |
1704 | return; |
1705 | default: |
1706 | /* Stall? */ |
1707 | // DEBUG_EP0("Odd state!! state = %s\n", |
1708 | // state_names[dev->ep0state]); |
1709 | dev->ep0state = WAIT_FOR_SETUP; |
1710 | /* nuke(ep, 0); */ |
1711 | /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */ |
1712 | // break; |
1713 | return; |
1714 | } |
1715 | } |
1716 | |
1717 | /* |
1718 | * if SETUPEND is set |
1719 | * - abort the last transfer |
1720 | * - set SERVICED_SETUP_END_BIT |
1721 | */ |
1722 | if (csr & USB_CSR0_SETUPEND) { |
1723 | DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr); |
1724 | |
1725 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND); |
1726 | nuke(ep, 0); |
1727 | dev->ep0state = WAIT_FOR_SETUP; |
1728 | } |
1729 | |
1730 | /* |
1731 | * if USB_CSR0_OUTPKTRDY is set |
1732 | * - read data packet from EP0 FIFO |
1733 | * - decode command |
1734 | * - if error |
1735 | * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits |
1736 | * - else |
1737 | * set SVDOUTPKTRDY | DATAEND bits |
1738 | */ |
1739 | if (csr & USB_CSR0_OUTPKTRDY) { |
1740 | |
1741 | DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__, |
1742 | csr); |
1743 | |
1744 | switch (dev->ep0state) { |
1745 | case WAIT_FOR_SETUP: |
1746 | DEBUG_EP0("WAIT_FOR_SETUP\n"); |
1747 | jz4740_ep0_setup(dev, csr); |
1748 | break; |
1749 | |
1750 | case DATA_STATE_RECV: |
1751 | DEBUG_EP0("DATA_STATE_RECV\n"); |
1752 | jz4740_ep0_out(dev, csr, 0); |
1753 | break; |
1754 | |
1755 | default: |
1756 | /* send stall? */ |
1757 | DEBUG_EP0("strange state!! 2. send stall? state = %d\n", |
1758 | dev->ep0state); |
1759 | break; |
1760 | } |
1761 | } |
1762 | } |
1763 | |
1764 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep) |
1765 | { |
1766 | uint32_t csr; |
1767 | |
1768 | jz_udc_set_index(dev, 0); |
1769 | |
1770 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1771 | |
1772 | /* Clear "out packet ready" */ |
1773 | |
1774 | if (ep_is_in(ep)) { |
1775 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1776 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1777 | dev->ep0state = DATA_STATE_XMIT; |
1778 | jz4740_ep0_in(dev, csr); |
1779 | } else { |
1780 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1781 | dev->ep0state = DATA_STATE_RECV; |
1782 | jz4740_ep0_out(dev, csr, 1); |
1783 | } |
1784 | } |
1785 | |
1786 | /** Handle USB RESET interrupt |
1787 | */ |
1788 | static void jz4740_reset_irq(struct jz4740_udc *dev) |
1789 | { |
1790 | dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ? |
1791 | USB_SPEED_HIGH : USB_SPEED_FULL; |
1792 | |
1793 | DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0, |
1794 | (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" ); |
1795 | } |
1796 | |
1797 | /* |
1798 | * jz4740 usb device interrupt handler. |
1799 | */ |
1800 | static irqreturn_t jz4740_udc_irq(int irq, void *devid) |
1801 | { |
1802 | struct jz4740_udc *jz4740_udc = devid; |
1803 | uint8_t index; |
1804 | |
1805 | uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */ |
1806 | uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN); |
1807 | uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT); |
1808 | uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR); |
1809 | |
1810 | if (!intr_usb && !intr_in && !intr_out && !intr_dma) |
1811 | return IRQ_HANDLED; |
1812 | |
1813 | |
1814 | DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n", |
1815 | intr_out, intr_in, intr_usb); |
1816 | |
1817 | spin_lock(&jz4740_udc->lock); |
1818 | index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX); |
1819 | |
1820 | /* Check for resume from suspend mode */ |
1821 | if ((intr_usb & USB_INTR_RESUME) && |
1822 | (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) { |
1823 | DEBUG("USB resume\n"); |
1824 | jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */ |
1825 | } |
1826 | |
1827 | /* Check for system interrupts */ |
1828 | if (intr_usb & USB_INTR_RESET) { |
1829 | DEBUG("USB reset\n"); |
1830 | jz4740_reset_irq(jz4740_udc); |
1831 | } |
1832 | |
1833 | /* Check for endpoint 0 interrupt */ |
1834 | if (intr_in & USB_INTR_EP0) { |
1835 | DEBUG("USB_INTR_EP0 (control)\n"); |
1836 | jz4740_handle_ep0(jz4740_udc, intr_in); |
1837 | } |
1838 | |
1839 | /* Check for Bulk-IN DMA interrupt */ |
1840 | if (intr_dma & 0x1) { |
1841 | int ep_num; |
1842 | struct jz4740_ep *ep; |
1843 | ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf; |
1844 | ep = &jz4740_udc->ep[ep_num + 1]; |
1845 | jz_udc_select_ep(ep); |
1846 | usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY); |
1847 | /* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/ |
1848 | } |
1849 | |
1850 | /* Check for Bulk-OUT DMA interrupt */ |
1851 | if (intr_dma & 0x2) { |
1852 | int ep_num; |
1853 | ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf; |
1854 | jz4740_out_epn(jz4740_udc, ep_num, intr_out); |
1855 | } |
1856 | |
1857 | /* Check for each configured endpoint interrupt */ |
1858 | if (intr_in & USB_INTR_INEP1) { |
1859 | DEBUG("USB_INTR_INEP1\n"); |
1860 | jz4740_in_epn(jz4740_udc, 1, intr_in); |
1861 | } |
1862 | |
1863 | if (intr_in & USB_INTR_INEP2) { |
1864 | DEBUG("USB_INTR_INEP2\n"); |
1865 | jz4740_in_epn(jz4740_udc, 2, intr_in); |
1866 | } |
1867 | |
1868 | if (intr_out & USB_INTR_OUTEP1) { |
1869 | DEBUG("USB_INTR_OUTEP1\n"); |
1870 | jz4740_out_epn(jz4740_udc, 1, intr_out); |
1871 | } |
1872 | |
1873 | /* Check for suspend mode */ |
1874 | if ((intr_usb & USB_INTR_SUSPEND) && |
1875 | (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) { |
1876 | DEBUG("USB suspend\n"); |
1877 | jz4740_udc->driver->suspend(&jz4740_udc->gadget); |
1878 | /* Host unloaded from us, can do something, such as flushing |
1879 | the NAND block cache etc. */ |
1880 | } |
1881 | |
1882 | jz_udc_set_index(jz4740_udc, index); |
1883 | |
1884 | spin_unlock(&jz4740_udc->lock); |
1885 | |
1886 | return IRQ_HANDLED; |
1887 | } |
1888 | |
1889 | |
1890 | |
1891 | /*-------------------------------------------------------------------------*/ |
1892 | |
1893 | |
1894 | static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget) |
1895 | { |
1896 | return container_of(gadget, struct jz4740_udc, gadget); |
1897 | } |
1898 | |
1899 | static int jz4740_udc_get_frame(struct usb_gadget *_gadget) |
1900 | { |
1901 | DEBUG("%s, %p\n", __FUNCTION__, _gadget); |
1902 | return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME); |
1903 | } |
1904 | |
1905 | static int jz4740_udc_wakeup(struct usb_gadget *_gadget) |
1906 | { |
1907 | /* host may not have enabled remote wakeup */ |
1908 | /*if ((UDCCS0 & UDCCS0_DRWF) == 0) |
1909 | return -EHOSTUNREACH; |
1910 | udc_set_mask_UDCCR(UDCCR_RSM); */ |
1911 | return -ENOTSUPP; |
1912 | } |
1913 | |
1914 | static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on) |
1915 | { |
1916 | struct jz4740_udc *udc = gadget_to_udc(_gadget); |
1917 | unsigned long flags; |
1918 | |
1919 | local_irq_save(flags); |
1920 | |
1921 | if (on) { |
1922 | udc->state = UDC_STATE_ENABLE; |
1923 | udc_enable(udc); |
1924 | } else { |
1925 | udc->state = UDC_STATE_DISABLE; |
1926 | udc_disable(udc); |
1927 | } |
1928 | |
1929 | local_irq_restore(flags); |
1930 | |
1931 | return 0; |
1932 | } |
1933 | |
1934 | |
1935 | static const struct usb_gadget_ops jz4740_udc_ops = { |
1936 | .get_frame = jz4740_udc_get_frame, |
1937 | .wakeup = jz4740_udc_wakeup, |
1938 | .pullup = jz4740_udc_pullup, |
1939 | }; |
1940 | |
1941 | static struct usb_ep_ops jz4740_ep_ops = { |
1942 | .enable = jz4740_ep_enable, |
1943 | .disable = jz4740_ep_disable, |
1944 | |
1945 | .alloc_request = jz4740_alloc_request, |
1946 | .free_request = jz4740_free_request, |
1947 | |
1948 | .queue = jz4740_queue, |
1949 | .dequeue = jz4740_dequeue, |
1950 | |
1951 | .set_halt = jz4740_set_halt, |
1952 | .fifo_status = jz4740_fifo_status, |
1953 | .fifo_flush = jz4740_fifo_flush, |
1954 | }; |
1955 | |
1956 | |
1957 | /*-------------------------------------------------------------------------*/ |
1958 | |
1959 | static struct jz4740_udc jz4740_udc_controller = { |
1960 | .gadget = { |
1961 | .ops = &jz4740_udc_ops, |
1962 | .ep0 = &jz4740_udc_controller.ep[0].ep, |
1963 | .name = "jz4740-udc", |
1964 | .dev = { |
1965 | .init_name = "gadget", |
1966 | }, |
1967 | }, |
1968 | |
1969 | /* control endpoint */ |
1970 | .ep[0] = { |
1971 | .ep = { |
1972 | .name = "ep0", |
1973 | .ops = &jz4740_ep_ops, |
1974 | .maxpacket = EP0_MAXPACKETSIZE, |
1975 | }, |
1976 | .dev = &jz4740_udc_controller, |
1977 | |
1978 | .bEndpointAddress = 0, |
1979 | .bmAttributes = 0, |
1980 | |
1981 | .type = ep_control, |
1982 | .fifo = JZ_REG_UDC_EP_FIFO(0), |
1983 | .csr = JZ_REG_UDC_CSR0, |
1984 | }, |
1985 | |
1986 | /* bulk out endpoint */ |
1987 | .ep[1] = { |
1988 | .ep = { |
1989 | .name = "ep1out-bulk", |
1990 | .ops = &jz4740_ep_ops, |
1991 | .maxpacket = EPBULK_MAXPACKETSIZE, |
1992 | }, |
1993 | .dev = &jz4740_udc_controller, |
1994 | |
1995 | .bEndpointAddress = 1, |
1996 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
1997 | |
1998 | .type = ep_bulk_out, |
1999 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2000 | .csr = JZ_REG_UDC_OUTCSR, |
2001 | }, |
2002 | |
2003 | /* bulk in endpoint */ |
2004 | .ep[2] = { |
2005 | .ep = { |
2006 | .name = "ep1in-bulk", |
2007 | .ops = &jz4740_ep_ops, |
2008 | .maxpacket = EPBULK_MAXPACKETSIZE, |
2009 | }, |
2010 | .dev = &jz4740_udc_controller, |
2011 | |
2012 | .bEndpointAddress = 1 | USB_DIR_IN, |
2013 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2014 | |
2015 | .type = ep_bulk_in, |
2016 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2017 | .csr = JZ_REG_UDC_INCSR, |
2018 | }, |
2019 | |
2020 | /* interrupt in endpoint */ |
2021 | .ep[3] = { |
2022 | .ep = { |
2023 | .name = "ep2in-int", |
2024 | .ops = &jz4740_ep_ops, |
2025 | .maxpacket = EPINTR_MAXPACKETSIZE, |
2026 | }, |
2027 | .dev = &jz4740_udc_controller, |
2028 | |
2029 | .bEndpointAddress = 2 | USB_DIR_IN, |
2030 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2031 | |
2032 | .type = ep_interrupt, |
2033 | .fifo = JZ_REG_UDC_EP_FIFO(2), |
2034 | .csr = JZ_REG_UDC_INCSR, |
2035 | }, |
2036 | }; |
2037 | |
2038 | static int __devinit jz4740_udc_probe(struct platform_device *pdev) |
2039 | { |
2040 | struct jz4740_udc *jz4740_udc = &jz4740_udc_controller; |
2041 | int ret; |
2042 | |
2043 | spin_lock_init(&jz4740_udc->lock); |
2044 | |
2045 | jz4740_udc->dev = &pdev->dev; |
2046 | jz4740_udc->gadget.dev.parent = &pdev->dev; |
2047 | jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask; |
2048 | |
2049 | ret = device_register(&jz4740_udc->gadget.dev); |
2050 | if (ret) |
2051 | return ret; |
2052 | |
2053 | jz4740_udc->clk = clk_get(&pdev->dev, "udc"); |
2054 | if (IS_ERR(jz4740_udc->clk)) { |
2055 | ret = PTR_ERR(jz4740_udc->clk); |
2056 | dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret); |
2057 | goto err_device_unregister; |
2058 | } |
2059 | |
2060 | platform_set_drvdata(pdev, jz4740_udc); |
2061 | |
2062 | jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2063 | |
2064 | if (!jz4740_udc->mem) { |
2065 | ret = -ENOENT; |
2066 | dev_err(&pdev->dev, "Failed to get mmio memory resource\n"); |
2067 | goto err_clk_put; |
2068 | } |
2069 | |
2070 | jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start, |
2071 | resource_size(jz4740_udc->mem), pdev->name); |
2072 | |
2073 | if (!jz4740_udc->mem) { |
2074 | ret = -EBUSY; |
2075 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
2076 | goto err_device_unregister; |
2077 | } |
2078 | |
2079 | jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem)); |
2080 | |
2081 | if (!jz4740_udc->base) { |
2082 | ret = -EBUSY; |
2083 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
2084 | goto err_release_mem_region; |
2085 | } |
2086 | |
2087 | jz4740_udc->irq = platform_get_irq(pdev, 0); |
2088 | ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name, |
2089 | jz4740_udc); |
2090 | if (ret) { |
2091 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
2092 | goto err_iounmap; |
2093 | } |
2094 | |
2095 | udc_disable(jz4740_udc); |
2096 | udc_reinit(jz4740_udc); |
2097 | |
2098 | return 0; |
2099 | |
2100 | err_iounmap: |
2101 | iounmap(jz4740_udc->base); |
2102 | err_release_mem_region: |
2103 | release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem)); |
2104 | err_clk_put: |
2105 | clk_put(jz4740_udc->clk); |
2106 | err_device_unregister: |
2107 | device_unregister(&jz4740_udc->gadget.dev); |
2108 | platform_set_drvdata(pdev, NULL); |
2109 | |
2110 | return ret; |
2111 | } |
2112 | |
2113 | static int __devexit jz4740_udc_remove(struct platform_device *pdev) |
2114 | { |
2115 | struct jz4740_udc *dev = platform_get_drvdata(pdev); |
2116 | |
2117 | if (dev->driver) |
2118 | return -EBUSY; |
2119 | |
2120 | udc_disable(dev); |
2121 | |
2122 | free_irq(dev->irq, dev); |
2123 | iounmap(dev->base); |
2124 | release_mem_region(dev->mem->start, resource_size(dev->mem)); |
2125 | clk_put(dev->clk); |
2126 | |
2127 | platform_set_drvdata(pdev, NULL); |
2128 | device_unregister(&dev->gadget.dev); |
2129 | |
2130 | return 0; |
2131 | } |
2132 | |
2133 | #ifdef CONFIG_PM |
2134 | |
2135 | static int jz4740_udc_suspend(struct device *dev) |
2136 | { |
2137 | struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev); |
2138 | |
2139 | if (jz4740_udc->state == UDC_STATE_ENABLE) |
2140 | udc_disable(jz4740_udc); |
2141 | |
2142 | return 0; |
2143 | } |
2144 | |
2145 | static int jz4740_udc_resume(struct device *dev) |
2146 | { |
2147 | struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev); |
2148 | |
2149 | if (jz4740_udc->state == UDC_STATE_ENABLE) |
2150 | udc_enable(jz4740_udc); |
2151 | |
2152 | return 0; |
2153 | } |
2154 | |
2155 | static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume); |
2156 | #define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops) |
2157 | |
2158 | #else |
2159 | #define JZ4740_UDC_PM_OPS NULL |
2160 | #endif |
2161 | |
2162 | static struct platform_driver udc_driver = { |
2163 | .probe = jz4740_udc_probe, |
2164 | .remove = __devexit_p(jz4740_udc_remove), |
2165 | .driver = { |
2166 | .name = "jz-udc", |
2167 | .owner = THIS_MODULE, |
2168 | .pm = JZ4740_UDC_PM_OPS, |
2169 | }, |
2170 | }; |
2171 | |
2172 | /*-------------------------------------------------------------------------*/ |
2173 | |
2174 | static int __init udc_init (void) |
2175 | { |
2176 | return platform_driver_register(&udc_driver); |
2177 | } |
2178 | module_init(udc_init); |
2179 | |
2180 | static void __exit udc_exit (void) |
2181 | { |
2182 | platform_driver_unregister(&udc_driver); |
2183 | } |
2184 | module_exit(udc_exit); |
2185 | |
2186 | MODULE_DESCRIPTION("JZ4740 USB Device Controller"); |
2187 | MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>"); |
2188 | MODULE_LICENSE("GPL"); |
2189 |
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