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Source at commit 9a83f481a49cf9337a0aaed749c631572dddb950 created 13 years 3 days ago. By Lars-Peter Clausen, stash | |
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1 | /* |
2 | * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 SoC DMA support |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | */ |
15 | |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> |
18 | #include <linux/spinlock.h> |
19 | #include <linux/interrupt.h> |
20 | |
21 | #include <linux/dma-mapping.h> |
22 | |
23 | #include <jz4740/dma.h> |
24 | #include <jz4740/irq.h> |
25 | |
26 | #include <asm/mach-jz47xx/base.h> |
27 | |
28 | #define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20) |
29 | #define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20) |
30 | #define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20) |
31 | #define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20) |
32 | #define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20) |
33 | #define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20) |
34 | #define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20) |
35 | |
36 | #define JZ_REG_DMA_CTRL 0x300 |
37 | #define JZ_REG_DMA_IRQ 0x304 |
38 | #define JZ_REG_DMA_DOORBELL 0x308 |
39 | #define JZ_REG_DMA_DOORBELL_SET 0x30C |
40 | |
41 | #define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31) |
42 | #define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6) |
43 | #define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4) |
44 | #define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3) |
45 | #define JZ_DMA_STATUS_CTRL_HALT BIT(2) |
46 | #define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1) |
47 | #define JZ_DMA_STATUS_CTRL_ENABLE BIT(0) |
48 | |
49 | #define JZ_DMA_CMD_SRC_INC BIT(23) |
50 | #define JZ_DMA_CMD_DST_INC BIT(22) |
51 | #define JZ_DMA_CMD_RDIL_MASK (0xf << 16) |
52 | #define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14) |
53 | #define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12) |
54 | #define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8) |
55 | #define JZ_DMA_CMD_BLOCK_MODE BIT(7) |
56 | #define JZ_DMA_CMD_DESC_VALID BIT(4) |
57 | #define JZ_DMA_CMD_DESC_VALID_MODE BIT(3) |
58 | #define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2) |
59 | #define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1) |
60 | #define JZ_DMA_CMD_LINK_ENABLE BIT(0) |
61 | |
62 | #define JZ_DMA_CMD_FLAGS_OFFSET 22 |
63 | #define JZ_DMA_CMD_RDIL_OFFSET 16 |
64 | #define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14 |
65 | #define JZ_DMA_CMD_DST_WIDTH_OFFSET 12 |
66 | #define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8 |
67 | #define JZ_DMA_CMD_MODE_OFFSET 7 |
68 | |
69 | #define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8) |
70 | #define JZ_DMA_CTRL_HALT BIT(3) |
71 | #define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2) |
72 | #define JZ_DMA_CTRL_ENABLE BIT(0) |
73 | |
74 | |
75 | static void __iomem *jz4740_dma_base; |
76 | static spinlock_t jz4740_dma_lock; |
77 | |
78 | static inline uint32_t jz4740_dma_read(size_t reg) |
79 | { |
80 | return readl(jz4740_dma_base + reg); |
81 | } |
82 | |
83 | static inline void jz4740_dma_write(size_t reg, uint32_t val) |
84 | { |
85 | writel(val, jz4740_dma_base + reg); |
86 | } |
87 | |
88 | static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask) |
89 | { |
90 | uint32_t val2; |
91 | val2 = jz4740_dma_read(reg); |
92 | val2 &= ~mask; |
93 | val2 |= val; |
94 | jz4740_dma_write(reg, val2); |
95 | } |
96 | |
97 | struct jz4740_dma_chan { |
98 | unsigned int id; |
99 | void *dev; |
100 | const char *name; |
101 | |
102 | enum jz4740_dma_flags flags; |
103 | uint32_t transfer_shift; |
104 | |
105 | jz4740_dma_complete_callback_t complete_cb; |
106 | |
107 | unsigned used:1; |
108 | }; |
109 | |
110 | #define JZ4740_DMA_CHANNEL(_id) { .id = _id } |
111 | |
112 | struct jz4740_dma_chan jz4740_dma_channels[] = { |
113 | JZ4740_DMA_CHANNEL(0), |
114 | JZ4740_DMA_CHANNEL(1), |
115 | JZ4740_DMA_CHANNEL(2), |
116 | JZ4740_DMA_CHANNEL(3), |
117 | JZ4740_DMA_CHANNEL(4), |
118 | JZ4740_DMA_CHANNEL(5), |
119 | }; |
120 | |
121 | struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name) |
122 | { |
123 | unsigned int i; |
124 | struct jz4740_dma_chan *dma = NULL; |
125 | |
126 | spin_lock(&jz4740_dma_lock); |
127 | |
128 | for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) { |
129 | if (!jz4740_dma_channels[i].used) { |
130 | dma = &jz4740_dma_channels[i]; |
131 | dma->used = 1; |
132 | break; |
133 | } |
134 | } |
135 | |
136 | spin_unlock(&jz4740_dma_lock); |
137 | |
138 | if (!dma) |
139 | return NULL; |
140 | |
141 | dma->dev = dev; |
142 | dma->name = name; |
143 | |
144 | return dma; |
145 | } |
146 | EXPORT_SYMBOL_GPL(jz4740_dma_request); |
147 | |
148 | void jz4740_dma_configure(struct jz4740_dma_chan *dma, |
149 | const struct jz4740_dma_config *config) |
150 | { |
151 | uint32_t cmd; |
152 | |
153 | switch (config->transfer_size) { |
154 | case JZ4740_DMA_TRANSFER_SIZE_2BYTE: |
155 | dma->transfer_shift = 1; |
156 | break; |
157 | case JZ4740_DMA_TRANSFER_SIZE_4BYTE: |
158 | dma->transfer_shift = 2; |
159 | break; |
160 | case JZ4740_DMA_TRANSFER_SIZE_16BYTE: |
161 | dma->transfer_shift = 4; |
162 | break; |
163 | case JZ4740_DMA_TRANSFER_SIZE_32BYTE: |
164 | dma->transfer_shift = 5; |
165 | break; |
166 | default: |
167 | dma->transfer_shift = 0; |
168 | break; |
169 | } |
170 | |
171 | cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET; |
172 | cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET; |
173 | cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET; |
174 | cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET; |
175 | cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET; |
176 | cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE; |
177 | |
178 | jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd); |
179 | jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0); |
180 | jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type); |
181 | } |
182 | EXPORT_SYMBOL_GPL(jz4740_dma_configure); |
183 | |
184 | void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src) |
185 | { |
186 | jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src); |
187 | } |
188 | EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr); |
189 | |
190 | void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst) |
191 | { |
192 | jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst); |
193 | } |
194 | EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr); |
195 | |
196 | void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count) |
197 | { |
198 | count >>= dma->transfer_shift; |
199 | jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count); |
200 | } |
201 | EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count); |
202 | |
203 | void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma, |
204 | jz4740_dma_complete_callback_t cb) |
205 | { |
206 | dma->complete_cb = cb; |
207 | } |
208 | EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb); |
209 | |
210 | void jz4740_dma_free(struct jz4740_dma_chan *dma) |
211 | { |
212 | dma->dev = NULL; |
213 | dma->complete_cb = NULL; |
214 | dma->used = 0; |
215 | } |
216 | EXPORT_SYMBOL_GPL(jz4740_dma_free); |
217 | |
218 | void jz4740_dma_enable(struct jz4740_dma_chan *dma) |
219 | { |
220 | jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), |
221 | JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE, |
222 | JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC | |
223 | JZ_DMA_STATUS_CTRL_ENABLE); |
224 | |
225 | jz4740_dma_write_mask(JZ_REG_DMA_CTRL, |
226 | JZ_DMA_CTRL_ENABLE, |
227 | JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE); |
228 | } |
229 | EXPORT_SYMBOL_GPL(jz4740_dma_enable); |
230 | |
231 | void jz4740_dma_disable(struct jz4740_dma_chan *dma) |
232 | { |
233 | jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0, |
234 | JZ_DMA_STATUS_CTRL_ENABLE); |
235 | } |
236 | EXPORT_SYMBOL_GPL(jz4740_dma_disable); |
237 | |
238 | uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma) |
239 | { |
240 | uint32_t residue; |
241 | residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id)); |
242 | return residue << dma->transfer_shift; |
243 | } |
244 | EXPORT_SYMBOL_GPL(jz4740_dma_get_residue); |
245 | |
246 | static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma) |
247 | { |
248 | uint32_t status; |
249 | |
250 | status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id)); |
251 | |
252 | jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0, |
253 | JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE); |
254 | |
255 | if (dma->complete_cb) |
256 | dma->complete_cb(dma, 0, dma->dev); |
257 | } |
258 | |
259 | static irqreturn_t jz4740_dma_irq(int irq, void *dev_id) |
260 | { |
261 | uint32_t irq_status; |
262 | unsigned int i; |
263 | |
264 | irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ); |
265 | |
266 | for (i = 0; i < 6; ++i) { |
267 | if (irq_status & (1 << i)) |
268 | jz4740_dma_chan_irq(&jz4740_dma_channels[i]); |
269 | } |
270 | |
271 | return IRQ_HANDLED; |
272 | } |
273 | |
274 | static int jz4740_dma_init(void) |
275 | { |
276 | unsigned int ret; |
277 | |
278 | jz4740_dma_base = ioremap(JZ47XX_DMAC_BASE_ADDR, 0x400); |
279 | |
280 | if (!jz4740_dma_base) |
281 | return -EBUSY; |
282 | |
283 | spin_lock_init(&jz4740_dma_lock); |
284 | |
285 | ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL); |
286 | |
287 | if (ret) |
288 | printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret); |
289 | |
290 | return ret; |
291 | } |
292 |
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Tags:
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