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Source at commit 9a83f481a49cf9337a0aaed749c631572dddb950 created 13 years 3 days ago. By Lars-Peter Clausen, stash | |
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1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 SoC ADC driver |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | * This driver synchronizes access to the JZ4740 ADC core between the |
15 | * JZ4740 battery and hwmon drivers. |
16 | */ |
17 | |
18 | #include <linux/err.h> |
19 | #include <linux/irq.h> |
20 | #include <linux/interrupt.h> |
21 | #include <linux/kernel.h> |
22 | #include <linux/module.h> |
23 | #include <linux/platform_device.h> |
24 | #include <linux/slab.h> |
25 | #include <linux/spinlock.h> |
26 | |
27 | #include <linux/clk.h> |
28 | #include <linux/mfd/core.h> |
29 | |
30 | #include <linux/jz4740-adc.h> |
31 | |
32 | #include <asm/mach-jz47xx/soc.h> |
33 | |
34 | |
35 | #define JZ_REG_ADC_ENABLE 0x00 |
36 | #define JZ_REG_ADC_CFG 0x04 |
37 | #define JZ_REG_ADC_CTRL 0x08 |
38 | #define JZ_REG_ADC_STATUS 0x0c |
39 | #define JZ_REG_ADC_CLKDIV 0x28 |
40 | |
41 | #define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10 |
42 | #define JZ_REG_ADC_BATTERY_BASE 0x1c |
43 | #define JZ_REG_ADC_HWMON_BASE 0x20 |
44 | |
45 | #define JZ_ADC_ENABLE_TOUCH BIT(2) |
46 | #define JZ_ADC_ENABLE_BATTERY BIT(1) |
47 | #define JZ_ADC_ENABLE_ADCIN BIT(0) |
48 | |
49 | enum { |
50 | JZ_ADC_IRQ_ADCIN = 0, |
51 | JZ_ADC_IRQ_BATTERY, |
52 | JZ_ADC_IRQ_TS_DATA_READY, |
53 | JZ_ADC_IRQ_TS_PENUP, |
54 | JZ_ADC_IRQ_TS_PENDOWN, |
55 | }; |
56 | |
57 | struct jz4740_adc { |
58 | struct resource *mem; |
59 | void __iomem *base; |
60 | |
61 | int irq; |
62 | int irq_base; |
63 | |
64 | struct clk *clk; |
65 | atomic_t clk_ref; |
66 | |
67 | spinlock_t lock; |
68 | }; |
69 | |
70 | static inline void jz4740_adc_irq_set_masked(struct jz4740_adc *adc, int irq, |
71 | bool masked) |
72 | { |
73 | unsigned long flags; |
74 | uint8_t val; |
75 | |
76 | irq -= adc->irq_base; |
77 | |
78 | spin_lock_irqsave(&adc->lock, flags); |
79 | |
80 | val = readb(adc->base + JZ_REG_ADC_CTRL); |
81 | if (masked) |
82 | val |= BIT(irq); |
83 | else |
84 | val &= ~BIT(irq); |
85 | writeb(val, adc->base + JZ_REG_ADC_CTRL); |
86 | |
87 | spin_unlock_irqrestore(&adc->lock, flags); |
88 | } |
89 | |
90 | static void jz4740_adc_irq_mask(struct irq_data *data) |
91 | { |
92 | struct jz4740_adc *adc = irq_data_get_irq_chip_data(data); |
93 | jz4740_adc_irq_set_masked(adc, data->irq, true); |
94 | } |
95 | |
96 | static void jz4740_adc_irq_unmask(struct irq_data *data) |
97 | { |
98 | struct jz4740_adc *adc = irq_data_get_irq_chip_data(data); |
99 | jz4740_adc_irq_set_masked(adc, data->irq, false); |
100 | } |
101 | |
102 | static void jz4740_adc_irq_ack(struct irq_data *data) |
103 | { |
104 | struct jz4740_adc *adc = irq_data_get_irq_chip_data(data); |
105 | unsigned int irq = data->irq - adc->irq_base; |
106 | writeb(BIT(irq), adc->base + JZ_REG_ADC_STATUS); |
107 | } |
108 | |
109 | static struct irq_chip jz4740_adc_irq_chip = { |
110 | .name = "jz4740-adc", |
111 | .irq_mask = jz4740_adc_irq_mask, |
112 | .irq_unmask = jz4740_adc_irq_unmask, |
113 | .irq_ack = jz4740_adc_irq_ack, |
114 | }; |
115 | |
116 | static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc) |
117 | { |
118 | struct jz4740_adc *adc = get_irq_desc_data(desc); |
119 | uint8_t status; |
120 | unsigned int i; |
121 | |
122 | status = readb(adc->base + JZ_REG_ADC_STATUS); |
123 | |
124 | for (i = 0; i < 5; ++i) { |
125 | if (status & BIT(i)) |
126 | generic_handle_irq(adc->irq_base + i); |
127 | } |
128 | } |
129 | |
130 | |
131 | /* Refcounting for the ADC clock is done in here instead of in the clock |
132 | * framework, because it is the only clock which is shared between multiple |
133 | * devices and thus is the only clock which needs refcounting */ |
134 | static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) |
135 | { |
136 | if (atomic_inc_return(&adc->clk_ref) == 1) |
137 | clk_enable(adc->clk); |
138 | } |
139 | |
140 | static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc) |
141 | { |
142 | if (atomic_dec_return(&adc->clk_ref) == 0) |
143 | clk_disable(adc->clk); |
144 | } |
145 | |
146 | static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine, |
147 | bool enabled) |
148 | { |
149 | unsigned long flags; |
150 | uint8_t val; |
151 | |
152 | spin_lock_irqsave(&adc->lock, flags); |
153 | |
154 | val = readb(adc->base + JZ_REG_ADC_ENABLE); |
155 | if (enabled) |
156 | val |= BIT(engine); |
157 | else |
158 | val &= ~BIT(engine); |
159 | writeb(val, adc->base + JZ_REG_ADC_ENABLE); |
160 | |
161 | spin_unlock_irqrestore(&adc->lock, flags); |
162 | } |
163 | |
164 | static int jz4740_adc_cell_enable(struct platform_device *pdev) |
165 | { |
166 | struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); |
167 | |
168 | jz4740_adc_clk_enable(adc); |
169 | jz4740_adc_set_enabled(adc, pdev->id, true); |
170 | |
171 | return 0; |
172 | } |
173 | |
174 | static int jz4740_adc_cell_disable(struct platform_device *pdev) |
175 | { |
176 | struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); |
177 | |
178 | jz4740_adc_set_enabled(adc, pdev->id, false); |
179 | jz4740_adc_clk_disable(adc); |
180 | |
181 | return 0; |
182 | } |
183 | |
184 | int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val) |
185 | { |
186 | struct jz4740_adc *adc = dev_get_drvdata(dev); |
187 | unsigned long flags; |
188 | uint32_t cfg; |
189 | |
190 | if (!adc) |
191 | return -ENODEV; |
192 | |
193 | spin_lock_irqsave(&adc->lock, flags); |
194 | |
195 | cfg = readl(adc->base + JZ_REG_ADC_CFG); |
196 | |
197 | cfg &= ~mask; |
198 | cfg |= val; |
199 | |
200 | writel(cfg, adc->base + JZ_REG_ADC_CFG); |
201 | |
202 | spin_unlock_irqrestore(&adc->lock, flags); |
203 | |
204 | return 0; |
205 | } |
206 | EXPORT_SYMBOL_GPL(jz4740_adc_set_config); |
207 | |
208 | static struct resource jz4740_hwmon_resources[] = { |
209 | { |
210 | .start = JZ_ADC_IRQ_ADCIN, |
211 | .flags = IORESOURCE_IRQ, |
212 | }, |
213 | { |
214 | .start = JZ_REG_ADC_HWMON_BASE, |
215 | .end = JZ_REG_ADC_HWMON_BASE + 3, |
216 | .flags = IORESOURCE_MEM, |
217 | }, |
218 | }; |
219 | |
220 | static struct resource jz4740_battery_resources[] = { |
221 | { |
222 | .start = JZ_ADC_IRQ_BATTERY, |
223 | .flags = IORESOURCE_IRQ, |
224 | }, |
225 | { |
226 | .start = JZ_REG_ADC_BATTERY_BASE, |
227 | .end = JZ_REG_ADC_BATTERY_BASE + 3, |
228 | .flags = IORESOURCE_MEM, |
229 | }, |
230 | }; |
231 | |
232 | static struct resource jz4740_ts_resources[] = { |
233 | { |
234 | .start = JZ_ADC_IRQ_TS_DATA_READY, |
235 | .flags = IORESOURCE_IRQ, |
236 | }, |
237 | { |
238 | .start = JZ_ADC_IRQ_TS_PENUP, |
239 | .flags = IORESOURCE_IRQ, |
240 | }, |
241 | { |
242 | .start = JZ_ADC_IRQ_TS_PENDOWN, |
243 | .flags = IORESOURCE_IRQ, |
244 | }, |
245 | { |
246 | .start = JZ_REG_ADC_TOUCHSCREEN_BASE, |
247 | .end = JZ_REG_ADC_TOUCHSCREEN_BASE + 0xb, |
248 | .flags = IORESOURCE_MEM, |
249 | }, |
250 | }; |
251 | |
252 | |
253 | const struct mfd_cell jz4740_adc_cells[] = { |
254 | { |
255 | .id = 0, |
256 | #ifdef CONFIG_MFD_JZ4740_ADC_USE_HWMON |
257 | .name = "jz4740-hwmon", |
258 | #else /* CONFIG_MFD_JZ4740_ADC_USE_KEYS */ |
259 | .name = "jz47xx-adc-keys", |
260 | #endif |
261 | .num_resources = ARRAY_SIZE(jz4740_hwmon_resources), |
262 | .resources = jz4740_hwmon_resources, |
263 | .platform_data = (void *)&jz4740_adc_cells[0], |
264 | .data_size = sizeof(struct mfd_cell), |
265 | |
266 | .enable = jz4740_adc_cell_enable, |
267 | .disable = jz4740_adc_cell_disable, |
268 | }, |
269 | { |
270 | .id = 1, |
271 | .name = "jz4740-battery", |
272 | .num_resources = ARRAY_SIZE(jz4740_battery_resources), |
273 | .resources = jz4740_battery_resources, |
274 | .platform_data = (void *)&jz4740_adc_cells[1], |
275 | .data_size = sizeof(struct mfd_cell), |
276 | |
277 | .enable = jz4740_adc_cell_enable, |
278 | .disable = jz4740_adc_cell_disable, |
279 | }, |
280 | { |
281 | .id = 2, |
282 | .name = "jz4740-ts", |
283 | .num_resources = ARRAY_SIZE(jz4740_ts_resources), |
284 | .resources = jz4740_ts_resources, |
285 | .platform_data = (void *)&jz4740_adc_cells[2], |
286 | .data_size = sizeof(struct mfd_cell), |
287 | |
288 | .enable = jz4740_adc_cell_enable, |
289 | .disable = jz4740_adc_cell_disable, |
290 | }, |
291 | }; |
292 | |
293 | static int __devinit jz4740_adc_probe(struct platform_device *pdev) |
294 | { |
295 | int ret; |
296 | struct jz4740_adc *adc; |
297 | struct resource *mem_base; |
298 | int irq; |
299 | |
300 | adc = kmalloc(sizeof(*adc), GFP_KERNEL); |
301 | if (!adc) { |
302 | dev_err(&pdev->dev, "Failed to allocate driver structure\n"); |
303 | return -ENOMEM; |
304 | } |
305 | |
306 | adc->irq = platform_get_irq(pdev, 0); |
307 | if (adc->irq < 0) { |
308 | ret = adc->irq; |
309 | dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); |
310 | goto err_free; |
311 | } |
312 | |
313 | adc->irq_base = platform_get_irq(pdev, 1); |
314 | if (adc->irq_base < 0) { |
315 | ret = adc->irq_base; |
316 | dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret); |
317 | goto err_free; |
318 | } |
319 | |
320 | mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
321 | if (!mem_base) { |
322 | ret = -ENOENT; |
323 | dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); |
324 | goto err_free; |
325 | } |
326 | |
327 | /* Only request the shared registers for the MFD driver */ |
328 | adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, |
329 | pdev->name); |
330 | if (!adc->mem) { |
331 | ret = -EBUSY; |
332 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
333 | goto err_free; |
334 | } |
335 | |
336 | adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); |
337 | if (!adc->base) { |
338 | ret = -EBUSY; |
339 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
340 | goto err_release_mem_region; |
341 | } |
342 | |
343 | adc->clk = clk_get(&pdev->dev, "adc"); |
344 | if (IS_ERR(adc->clk)) { |
345 | ret = PTR_ERR(adc->clk); |
346 | dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); |
347 | goto err_iounmap; |
348 | } |
349 | |
350 | spin_lock_init(&adc->lock); |
351 | atomic_set(&adc->clk_ref, 0); |
352 | |
353 | platform_set_drvdata(pdev, adc); |
354 | |
355 | for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) { |
356 | set_irq_chip_data(irq, adc); |
357 | set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip, |
358 | handle_level_irq); |
359 | } |
360 | |
361 | set_irq_data(adc->irq, adc); |
362 | set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux); |
363 | |
364 | jz4740_adc_clk_enable(adc); |
365 | writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); |
366 | writeb(0xff, adc->base + JZ_REG_ADC_CTRL); |
367 | |
368 | if (soc_is_jz4760()) { |
369 | unsigned int div; |
370 | div = clk_get_rate(adc->clk) / 100000 - 1; |
371 | printk("clk div: %u\n", div); |
372 | writel(div | (1 << 12) | (1 << 18), adc->base + JZ_REG_ADC_CLKDIV); |
373 | } |
374 | |
375 | ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, |
376 | ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base); |
377 | if (ret < 0) |
378 | goto err_clk_put; |
379 | |
380 | /* In JZ4750, enabling a clock and issuing a request immediately |
381 | * misses an irq. So keep clock running all the time. */ |
382 | |
383 | return 0; |
384 | |
385 | err_clk_put: |
386 | clk_put(adc->clk); |
387 | err_iounmap: |
388 | platform_set_drvdata(pdev, NULL); |
389 | iounmap(adc->base); |
390 | err_release_mem_region: |
391 | release_mem_region(adc->mem->start, resource_size(adc->mem)); |
392 | err_free: |
393 | kfree(adc); |
394 | |
395 | return ret; |
396 | } |
397 | |
398 | static int __devexit jz4740_adc_remove(struct platform_device *pdev) |
399 | { |
400 | struct jz4740_adc *adc = platform_get_drvdata(pdev); |
401 | |
402 | jz4740_adc_clk_disable(adc); |
403 | |
404 | mfd_remove_devices(&pdev->dev); |
405 | |
406 | set_irq_data(adc->irq, NULL); |
407 | set_irq_chained_handler(adc->irq, NULL); |
408 | |
409 | iounmap(adc->base); |
410 | release_mem_region(adc->mem->start, resource_size(adc->mem)); |
411 | |
412 | clk_put(adc->clk); |
413 | |
414 | platform_set_drvdata(pdev, NULL); |
415 | |
416 | kfree(adc); |
417 | |
418 | return 0; |
419 | } |
420 | |
421 | struct platform_driver jz4740_adc_driver = { |
422 | .probe = jz4740_adc_probe, |
423 | .remove = __devexit_p(jz4740_adc_remove), |
424 | .driver = { |
425 | .name = "jz4740-adc", |
426 | .owner = THIS_MODULE, |
427 | }, |
428 | }; |
429 | |
430 | static int __init jz4740_adc_init(void) |
431 | { |
432 | return platform_driver_register(&jz4740_adc_driver); |
433 | } |
434 | module_init(jz4740_adc_init); |
435 | |
436 | static void __exit jz4740_adc_exit(void) |
437 | { |
438 | platform_driver_unregister(&jz4740_adc_driver); |
439 | } |
440 | module_exit(jz4740_adc_exit); |
441 | |
442 | MODULE_DESCRIPTION("JZ4740 SoC ADC driver"); |
443 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |
444 | MODULE_LICENSE("GPL"); |
445 | MODULE_ALIAS("platform:jz4740-adc"); |
446 |
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