Root/drivers/media/video/pxa_camera.c

Source at commit a47f6be45670465d45a3d27f7ff71986bd35d6c4 created 13 years 7 months ago.
By Stefan Herbrechtsmeier, V4L/DVB: pxa_camera: move fifo reset direct before dma start
1/*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/errno.h>
19#include <linux/fs.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/moduleparam.h>
24#include <linux/time.h>
25#include <linux/version.h>
26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/clk.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31
32#include <media/v4l2-common.h>
33#include <media/v4l2-dev.h>
34#include <media/videobuf-dma-sg.h>
35#include <media/soc_camera.h>
36#include <media/soc_mediabus.h>
37
38#include <linux/videodev2.h>
39
40#include <mach/dma.h>
41#include <mach/camera.h>
42
43#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
44#define PXA_CAM_DRV_NAME "pxa27x-camera"
45
46/* Camera Interface */
47#define CICR0 0x0000
48#define CICR1 0x0004
49#define CICR2 0x0008
50#define CICR3 0x000C
51#define CICR4 0x0010
52#define CISR 0x0014
53#define CIFR 0x0018
54#define CITOR 0x001C
55#define CIBR0 0x0028
56#define CIBR1 0x0030
57#define CIBR2 0x0038
58
59#define CICR0_DMAEN (1 << 31) /* DMA request enable */
60#define CICR0_PAR_EN (1 << 30) /* Parity enable */
61#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
62#define CICR0_ENB (1 << 28) /* Camera interface enable */
63#define CICR0_DIS (1 << 27) /* Camera interface disable */
64#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
65#define CICR0_TOM (1 << 9) /* Time-out mask */
66#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
67#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
68#define CICR0_EOLM (1 << 6) /* End-of-line mask */
69#define CICR0_PERRM (1 << 5) /* Parity-error mask */
70#define CICR0_QDM (1 << 4) /* Quick-disable mask */
71#define CICR0_CDM (1 << 3) /* Disable-done mask */
72#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
73#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
74#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
75
76#define CICR1_TBIT (1 << 31) /* Transparency bit */
77#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
78#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
79#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
80#define CICR1_RGB_F (1 << 11) /* RGB format */
81#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
82#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
83#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
84#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
85#define CICR1_DW (0x7 << 0) /* Data width mask */
86
87#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
88                       wait count mask */
89#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
90                       wait count mask */
91#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
92#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
93                       wait count mask */
94#define CICR2_FSW (0x7 << 0) /* Frame stabilization
95                       wait count mask */
96
97#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
98                       wait count mask */
99#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
100                       wait count mask */
101#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
102#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
103                       wait count mask */
104#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
105
106#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
107#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
108#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
109#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
110#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
111#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
112#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
113#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
114
115#define CISR_FTO (1 << 15) /* FIFO time-out */
116#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
117#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
118#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
119#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
120#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
121#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
122#define CISR_EOL (1 << 8) /* End of line */
123#define CISR_PAR_ERR (1 << 7) /* Parity error */
124#define CISR_CQD (1 << 6) /* Camera interface quick disable */
125#define CISR_CDD (1 << 5) /* Camera interface disable done */
126#define CISR_SOF (1 << 4) /* Start of frame */
127#define CISR_EOF (1 << 3) /* End of frame */
128#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
129#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
130#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
131
132#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
133#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
134#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
135#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
136#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
137#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
138#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
139#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
140
141#define CICR0_SIM_MP (0 << 24)
142#define CICR0_SIM_SP (1 << 24)
143#define CICR0_SIM_MS (2 << 24)
144#define CICR0_SIM_EP (3 << 24)
145#define CICR0_SIM_ES (4 << 24)
146
147#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
148#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
149#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
150#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
151#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
152
153#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
154#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
155#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
156#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
157#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
158
159#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
160#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
161#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
162#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
163
164#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
165            CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
166            CICR0_EOFM | CICR0_FOM)
167
168/*
169 * Structures
170 */
171enum pxa_camera_active_dma {
172    DMA_Y = 0x1,
173    DMA_U = 0x2,
174    DMA_V = 0x4,
175};
176
177/* descriptor needed for the PXA DMA engine */
178struct pxa_cam_dma {
179    dma_addr_t sg_dma;
180    struct pxa_dma_desc *sg_cpu;
181    size_t sg_size;
182    int sglen;
183};
184
185/* buffer for one video frame */
186struct pxa_buffer {
187    /* common v4l buffer stuff -- must be first */
188    struct videobuf_buffer vb;
189    enum v4l2_mbus_pixelcode code;
190    /* our descriptor lists for Y, U and V channels */
191    struct pxa_cam_dma dmas[3];
192    int inwork;
193    enum pxa_camera_active_dma active_dma;
194};
195
196struct pxa_camera_dev {
197    struct soc_camera_host soc_host;
198    /*
199     * PXA27x is only supposed to handle one camera on its Quick Capture
200     * interface. If anyone ever builds hardware to enable more than
201     * one camera, they will have to modify this driver too
202     */
203    struct soc_camera_device *icd;
204    struct clk *clk;
205
206    unsigned int irq;
207    void __iomem *base;
208
209    int channels;
210    unsigned int dma_chans[3];
211
212    struct pxacamera_platform_data *pdata;
213    struct resource *res;
214    unsigned long platform_flags;
215    unsigned long ciclk;
216    unsigned long mclk;
217    u32 mclk_divisor;
218
219    struct list_head capture;
220
221    spinlock_t lock;
222
223    struct pxa_buffer *active;
224    struct pxa_dma_desc *sg_tail[3];
225
226    u32 save_cicr[5];
227};
228
229struct pxa_cam {
230    unsigned long flags;
231};
232
233static const char *pxa_cam_driver_description = "PXA_Camera";
234
235static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
236
237/*
238 * Videobuf operations
239 */
240static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
241                  unsigned int *size)
242{
243    struct soc_camera_device *icd = vq->priv_data;
244    int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
245                        icd->current_fmt->host_fmt);
246
247    if (bytes_per_line < 0)
248        return bytes_per_line;
249
250    dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size);
251
252    *size = bytes_per_line * icd->user_height;
253
254    if (0 == *count)
255        *count = 32;
256    while (*size * *count > vid_limit * 1024 * 1024)
257        (*count)--;
258
259    return 0;
260}
261
262static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
263{
264    struct soc_camera_device *icd = vq->priv_data;
265    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
266    struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
267    int i;
268
269    BUG_ON(in_interrupt());
270
271    dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
272        &buf->vb, buf->vb.baddr, buf->vb.bsize);
273
274    /*
275     * This waits until this buffer is out of danger, i.e., until it is no
276     * longer in STATE_QUEUED or STATE_ACTIVE
277     */
278    videobuf_waiton(&buf->vb, 0, 0);
279    videobuf_dma_unmap(vq, dma);
280    videobuf_dma_free(dma);
281
282    for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
283        if (buf->dmas[i].sg_cpu)
284            dma_free_coherent(ici->v4l2_dev.dev,
285                      buf->dmas[i].sg_size,
286                      buf->dmas[i].sg_cpu,
287                      buf->dmas[i].sg_dma);
288        buf->dmas[i].sg_cpu = NULL;
289    }
290
291    buf->vb.state = VIDEOBUF_NEEDS_INIT;
292}
293
294static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
295                   int sg_first_ofs, int size)
296{
297    int i, offset, dma_len, xfer_len;
298    struct scatterlist *sg;
299
300    offset = sg_first_ofs;
301    for_each_sg(sglist, sg, sglen, i) {
302        dma_len = sg_dma_len(sg);
303
304        /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
305        xfer_len = roundup(min(dma_len - offset, size), 8);
306
307        size = max(0, size - xfer_len);
308        offset = 0;
309        if (size == 0)
310            break;
311    }
312
313    BUG_ON(size != 0);
314    return i + 1;
315}
316
317/**
318 * pxa_init_dma_channel - init dma descriptors
319 * @pcdev: pxa camera device
320 * @buf: pxa buffer to find pxa dma channel
321 * @dma: dma video buffer
322 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
323 * @cibr: camera Receive Buffer Register
324 * @size: bytes to transfer
325 * @sg_first: first element of sg_list
326 * @sg_first_ofs: offset in first element of sg_list
327 *
328 * Prepares the pxa dma descriptors to transfer one camera channel.
329 * Beware sg_first and sg_first_ofs are both input and output parameters.
330 *
331 * Returns 0 or -ENOMEM if no coherent memory is available
332 */
333static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
334                struct pxa_buffer *buf,
335                struct videobuf_dmabuf *dma, int channel,
336                int cibr, int size,
337                struct scatterlist **sg_first, int *sg_first_ofs)
338{
339    struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
340    struct device *dev = pcdev->soc_host.v4l2_dev.dev;
341    struct scatterlist *sg;
342    int i, offset, sglen;
343    int dma_len = 0, xfer_len = 0;
344
345    if (pxa_dma->sg_cpu)
346        dma_free_coherent(dev, pxa_dma->sg_size,
347                  pxa_dma->sg_cpu, pxa_dma->sg_dma);
348
349    sglen = calculate_dma_sglen(*sg_first, dma->sglen,
350                    *sg_first_ofs, size);
351
352    pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
353    pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
354                         &pxa_dma->sg_dma, GFP_KERNEL);
355    if (!pxa_dma->sg_cpu)
356        return -ENOMEM;
357
358    pxa_dma->sglen = sglen;
359    offset = *sg_first_ofs;
360
361    dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
362        *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
363
364
365    for_each_sg(*sg_first, sg, sglen, i) {
366        dma_len = sg_dma_len(sg);
367
368        /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
369        xfer_len = roundup(min(dma_len - offset, size), 8);
370
371        size = max(0, size - xfer_len);
372
373        pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
374        pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
375        pxa_dma->sg_cpu[i].dcmd =
376            DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
377#ifdef DEBUG
378        if (!i)
379            pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
380#endif
381        pxa_dma->sg_cpu[i].ddadr =
382            pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
383
384        dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
385             pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
386             sg_dma_address(sg) + offset, xfer_len);
387        offset = 0;
388
389        if (size == 0)
390            break;
391    }
392
393    pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
394    pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
395
396    /*
397     * Handle 1 special case :
398     * - in 3 planes (YUV422P format), we might finish with xfer_len equal
399     * to dma_len (end on PAGE boundary). In this case, the sg element
400     * for next plane should be the next after the last used to store the
401     * last scatter gather RAM page
402     */
403    if (xfer_len >= dma_len) {
404        *sg_first_ofs = xfer_len - dma_len;
405        *sg_first = sg_next(sg);
406    } else {
407        *sg_first_ofs = xfer_len;
408        *sg_first = sg;
409    }
410
411    return 0;
412}
413
414static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
415                    struct pxa_buffer *buf)
416{
417    buf->active_dma = DMA_Y;
418    if (pcdev->channels == 3)
419        buf->active_dma |= DMA_U | DMA_V;
420}
421
422/*
423 * Please check the DMA prepared buffer structure in :
424 * Documentation/video4linux/pxa_camera.txt
425 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
426 * modification while DMA chain is running will work anyway.
427 */
428static int pxa_videobuf_prepare(struct videobuf_queue *vq,
429        struct videobuf_buffer *vb, enum v4l2_field field)
430{
431    struct soc_camera_device *icd = vq->priv_data;
432    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
433    struct pxa_camera_dev *pcdev = ici->priv;
434    struct device *dev = pcdev->soc_host.v4l2_dev.dev;
435    struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
436    int ret;
437    int size_y, size_u = 0, size_v = 0;
438    int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
439                        icd->current_fmt->host_fmt);
440
441    if (bytes_per_line < 0)
442        return bytes_per_line;
443
444    dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
445        vb, vb->baddr, vb->bsize);
446
447    /* Added list head initialization on alloc */
448    WARN_ON(!list_empty(&vb->queue));
449
450#ifdef DEBUG
451    /*
452     * This can be useful if you want to see if we actually fill
453     * the buffer with something
454     */
455    memset((void *)vb->baddr, 0xaa, vb->bsize);
456#endif
457
458    BUG_ON(NULL == icd->current_fmt);
459
460    /*
461     * I think, in buf_prepare you only have to protect global data,
462     * the actual buffer is yours
463     */
464    buf->inwork = 1;
465
466    if (buf->code != icd->current_fmt->code ||
467        vb->width != icd->user_width ||
468        vb->height != icd->user_height ||
469        vb->field != field) {
470        buf->code = icd->current_fmt->code;
471        vb->width = icd->user_width;
472        vb->height = icd->user_height;
473        vb->field = field;
474        vb->state = VIDEOBUF_NEEDS_INIT;
475    }
476
477    vb->size = bytes_per_line * vb->height;
478    if (0 != vb->baddr && vb->bsize < vb->size) {
479        ret = -EINVAL;
480        goto out;
481    }
482
483    if (vb->state == VIDEOBUF_NEEDS_INIT) {
484        int size = vb->size;
485        int next_ofs = 0;
486        struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
487        struct scatterlist *sg;
488
489        ret = videobuf_iolock(vq, vb, NULL);
490        if (ret)
491            goto fail;
492
493        if (pcdev->channels == 3) {
494            size_y = size / 2;
495            size_u = size_v = size / 4;
496        } else {
497            size_y = size;
498        }
499
500        sg = dma->sglist;
501
502        /* init DMA for Y channel */
503        ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
504                       &sg, &next_ofs);
505        if (ret) {
506            dev_err(dev, "DMA initialization for Y/RGB failed\n");
507            goto fail;
508        }
509
510        /* init DMA for U channel */
511        if (size_u)
512            ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
513                           size_u, &sg, &next_ofs);
514        if (ret) {
515            dev_err(dev, "DMA initialization for U failed\n");
516            goto fail_u;
517        }
518
519        /* init DMA for V channel */
520        if (size_v)
521            ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
522                           size_v, &sg, &next_ofs);
523        if (ret) {
524            dev_err(dev, "DMA initialization for V failed\n");
525            goto fail_v;
526        }
527
528        vb->state = VIDEOBUF_PREPARED;
529    }
530
531    buf->inwork = 0;
532    pxa_videobuf_set_actdma(pcdev, buf);
533
534    return 0;
535
536fail_v:
537    dma_free_coherent(dev, buf->dmas[1].sg_size,
538              buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
539fail_u:
540    dma_free_coherent(dev, buf->dmas[0].sg_size,
541              buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
542fail:
543    free_buffer(vq, buf);
544out:
545    buf->inwork = 0;
546    return ret;
547}
548
549/**
550 * pxa_dma_start_channels - start DMA channel for active buffer
551 * @pcdev: pxa camera device
552 *
553 * Initialize DMA channels to the beginning of the active video buffer, and
554 * start these channels.
555 */
556static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
557{
558    int i;
559    struct pxa_buffer *active;
560
561    active = pcdev->active;
562
563    for (i = 0; i < pcdev->channels; i++) {
564        dev_dbg(pcdev->soc_host.v4l2_dev.dev,
565            "%s (channel=%d) ddadr=%08x\n", __func__,
566            i, active->dmas[i].sg_dma);
567        DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
568        DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
569    }
570}
571
572static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
573{
574    int i;
575
576    for (i = 0; i < pcdev->channels; i++) {
577        dev_dbg(pcdev->soc_host.v4l2_dev.dev,
578            "%s (channel=%d)\n", __func__, i);
579        DCSR(pcdev->dma_chans[i]) = 0;
580    }
581}
582
583static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
584                 struct pxa_buffer *buf)
585{
586    int i;
587    struct pxa_dma_desc *buf_last_desc;
588
589    for (i = 0; i < pcdev->channels; i++) {
590        buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
591        buf_last_desc->ddadr = DDADR_STOP;
592
593        if (pcdev->sg_tail[i])
594            /* Link the new buffer to the old tail */
595            pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
596
597        /* Update the channel tail */
598        pcdev->sg_tail[i] = buf_last_desc;
599    }
600}
601
602/**
603 * pxa_camera_start_capture - start video capturing
604 * @pcdev: camera device
605 *
606 * Launch capturing. DMA channels should not be active yet. They should get
607 * activated at the end of frame interrupt, to capture only whole frames, and
608 * never begin the capture of a partial frame.
609 */
610static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
611{
612    unsigned long cicr0;
613
614    dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
615    /* Enable End-Of-Frame Interrupt */
616    cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
617    cicr0 &= ~CICR0_EOFM;
618    __raw_writel(cicr0, pcdev->base + CICR0);
619}
620
621static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
622{
623    unsigned long cicr0;
624
625    pxa_dma_stop_channels(pcdev);
626
627    cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
628    __raw_writel(cicr0, pcdev->base + CICR0);
629
630    pcdev->active = NULL;
631    dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
632}
633
634/* Called under spinlock_irqsave(&pcdev->lock, ...) */
635static void pxa_videobuf_queue(struct videobuf_queue *vq,
636                   struct videobuf_buffer *vb)
637{
638    struct soc_camera_device *icd = vq->priv_data;
639    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
640    struct pxa_camera_dev *pcdev = ici->priv;
641    struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
642
643    dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
644        __func__, vb, vb->baddr, vb->bsize, pcdev->active);
645
646    list_add_tail(&vb->queue, &pcdev->capture);
647
648    vb->state = VIDEOBUF_ACTIVE;
649    pxa_dma_add_tail_buf(pcdev, buf);
650
651    if (!pcdev->active)
652        pxa_camera_start_capture(pcdev);
653}
654
655static void pxa_videobuf_release(struct videobuf_queue *vq,
656                 struct videobuf_buffer *vb)
657{
658    struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
659#ifdef DEBUG
660    struct soc_camera_device *icd = vq->priv_data;
661    struct device *dev = icd->dev.parent;
662
663    dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
664        vb, vb->baddr, vb->bsize);
665
666    switch (vb->state) {
667    case VIDEOBUF_ACTIVE:
668        dev_dbg(dev, "%s (active)\n", __func__);
669        break;
670    case VIDEOBUF_QUEUED:
671        dev_dbg(dev, "%s (queued)\n", __func__);
672        break;
673    case VIDEOBUF_PREPARED:
674        dev_dbg(dev, "%s (prepared)\n", __func__);
675        break;
676    default:
677        dev_dbg(dev, "%s (unknown)\n", __func__);
678        break;
679    }
680#endif
681
682    free_buffer(vq, buf);
683}
684
685static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
686                  struct videobuf_buffer *vb,
687                  struct pxa_buffer *buf)
688{
689    int i;
690
691    /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
692    list_del_init(&vb->queue);
693    vb->state = VIDEOBUF_DONE;
694    do_gettimeofday(&vb->ts);
695    vb->field_count++;
696    wake_up(&vb->done);
697    dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
698        __func__, vb);
699
700    if (list_empty(&pcdev->capture)) {
701        pxa_camera_stop_capture(pcdev);
702        for (i = 0; i < pcdev->channels; i++)
703            pcdev->sg_tail[i] = NULL;
704        return;
705    }
706
707    pcdev->active = list_entry(pcdev->capture.next,
708                   struct pxa_buffer, vb.queue);
709}
710
711/**
712 * pxa_camera_check_link_miss - check missed DMA linking
713 * @pcdev: camera device
714 *
715 * The DMA chaining is done with DMA running. This means a tiny temporal window
716 * remains, where a buffer is queued on the chain, while the chain is already
717 * stopped. This means the tailed buffer would never be transfered by DMA.
718 * This function restarts the capture for this corner case, where :
719 * - DADR() == DADDR_STOP
720 * - a videobuffer is queued on the pcdev->capture list
721 *
722 * Please check the "DMA hot chaining timeslice issue" in
723 * Documentation/video4linux/pxa_camera.txt
724 *
725 * Context: should only be called within the dma irq handler
726 */
727static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
728{
729    int i, is_dma_stopped = 1;
730
731    for (i = 0; i < pcdev->channels; i++)
732        if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
733            is_dma_stopped = 0;
734    dev_dbg(pcdev->soc_host.v4l2_dev.dev,
735        "%s : top queued buffer=%p, dma_stopped=%d\n",
736        __func__, pcdev->active, is_dma_stopped);
737    if (pcdev->active && is_dma_stopped)
738        pxa_camera_start_capture(pcdev);
739}
740
741static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
742                   enum pxa_camera_active_dma act_dma)
743{
744    struct device *dev = pcdev->soc_host.v4l2_dev.dev;
745    struct pxa_buffer *buf;
746    unsigned long flags;
747    u32 status, camera_status, overrun;
748    struct videobuf_buffer *vb;
749
750    spin_lock_irqsave(&pcdev->lock, flags);
751
752    status = DCSR(channel);
753    DCSR(channel) = status;
754
755    camera_status = __raw_readl(pcdev->base + CISR);
756    overrun = CISR_IFO_0;
757    if (pcdev->channels == 3)
758        overrun |= CISR_IFO_1 | CISR_IFO_2;
759
760    if (status & DCSR_BUSERR) {
761        dev_err(dev, "DMA Bus Error IRQ!\n");
762        goto out;
763    }
764
765    if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
766        dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
767            status);
768        goto out;
769    }
770
771    /*
772     * pcdev->active should not be NULL in DMA irq handler.
773     *
774     * But there is one corner case : if capture was stopped due to an
775     * overrun of channel 1, and at that same channel 2 was completed.
776     *
777     * When handling the overrun in DMA irq for channel 1, we'll stop the
778     * capture and restart it (and thus set pcdev->active to NULL). But the
779     * DMA irq handler will already be pending for channel 2. So on entering
780     * the DMA irq handler for channel 2 there will be no active buffer, yet
781     * that is normal.
782     */
783    if (!pcdev->active)
784        goto out;
785
786    vb = &pcdev->active->vb;
787    buf = container_of(vb, struct pxa_buffer, vb);
788    WARN_ON(buf->inwork || list_empty(&vb->queue));
789
790    dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
791        __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
792        status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
793
794    if (status & DCSR_ENDINTR) {
795        /*
796         * It's normal if the last frame creates an overrun, as there
797         * are no more DMA descriptors to fetch from QCI fifos
798         */
799        if (camera_status & overrun &&
800            !list_is_last(pcdev->capture.next, &pcdev->capture)) {
801            dev_dbg(dev, "FIFO overrun! CISR: %x\n",
802                camera_status);
803            pxa_camera_stop_capture(pcdev);
804            pxa_camera_start_capture(pcdev);
805            goto out;
806        }
807        buf->active_dma &= ~act_dma;
808        if (!buf->active_dma) {
809            pxa_camera_wakeup(pcdev, vb, buf);
810            pxa_camera_check_link_miss(pcdev);
811        }
812    }
813
814out:
815    spin_unlock_irqrestore(&pcdev->lock, flags);
816}
817
818static void pxa_camera_dma_irq_y(int channel, void *data)
819{
820    struct pxa_camera_dev *pcdev = data;
821    pxa_camera_dma_irq(channel, pcdev, DMA_Y);
822}
823
824static void pxa_camera_dma_irq_u(int channel, void *data)
825{
826    struct pxa_camera_dev *pcdev = data;
827    pxa_camera_dma_irq(channel, pcdev, DMA_U);
828}
829
830static void pxa_camera_dma_irq_v(int channel, void *data)
831{
832    struct pxa_camera_dev *pcdev = data;
833    pxa_camera_dma_irq(channel, pcdev, DMA_V);
834}
835
836static struct videobuf_queue_ops pxa_videobuf_ops = {
837    .buf_setup = pxa_videobuf_setup,
838    .buf_prepare = pxa_videobuf_prepare,
839    .buf_queue = pxa_videobuf_queue,
840    .buf_release = pxa_videobuf_release,
841};
842
843static void pxa_camera_init_videobuf(struct videobuf_queue *q,
844                  struct soc_camera_device *icd)
845{
846    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
847    struct pxa_camera_dev *pcdev = ici->priv;
848
849    /*
850     * We must pass NULL as dev pointer, then all pci_* dma operations
851     * transform to normal dma_* ones.
852     */
853    videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
854                V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
855                sizeof(struct pxa_buffer), icd);
856}
857
858static u32 mclk_get_divisor(struct platform_device *pdev,
859                struct pxa_camera_dev *pcdev)
860{
861    unsigned long mclk = pcdev->mclk;
862    struct device *dev = &pdev->dev;
863    u32 div;
864    unsigned long lcdclk;
865
866    lcdclk = clk_get_rate(pcdev->clk);
867    pcdev->ciclk = lcdclk;
868
869    /* mclk <= ciclk / 4 (27.4.2) */
870    if (mclk > lcdclk / 4) {
871        mclk = lcdclk / 4;
872        dev_warn(dev, "Limiting master clock to %lu\n", mclk);
873    }
874
875    /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
876    div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
877
878    /* If we're not supplying MCLK, leave it at 0 */
879    if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
880        pcdev->mclk = lcdclk / (2 * (div + 1));
881
882    dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
883        lcdclk, mclk, div);
884
885    return div;
886}
887
888static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
889                     unsigned long pclk)
890{
891    /* We want a timeout > 1 pixel time, not ">=" */
892    u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
893
894    __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
895}
896
897static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
898{
899    u32 cicr4 = 0;
900
901    /* disable all interrupts */
902    __raw_writel(0x3ff, pcdev->base + CICR0);
903
904    if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
905        cicr4 |= CICR4_PCLK_EN;
906    if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
907        cicr4 |= CICR4_MCLK_EN;
908    if (pcdev->platform_flags & PXA_CAMERA_PCP)
909        cicr4 |= CICR4_PCP;
910    if (pcdev->platform_flags & PXA_CAMERA_HSP)
911        cicr4 |= CICR4_HSP;
912    if (pcdev->platform_flags & PXA_CAMERA_VSP)
913        cicr4 |= CICR4_VSP;
914
915    __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
916
917    if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
918        /* Initialise the timeout under the assumption pclk = mclk */
919        recalculate_fifo_timeout(pcdev, pcdev->mclk);
920    else
921        /* "Safe default" - 13MHz */
922        recalculate_fifo_timeout(pcdev, 13000000);
923
924    clk_enable(pcdev->clk);
925}
926
927static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
928{
929    clk_disable(pcdev->clk);
930}
931
932static irqreturn_t pxa_camera_irq(int irq, void *data)
933{
934    struct pxa_camera_dev *pcdev = data;
935    unsigned long status, cifr, cicr0;
936    struct pxa_buffer *buf;
937    struct videobuf_buffer *vb;
938
939    status = __raw_readl(pcdev->base + CISR);
940    dev_dbg(pcdev->soc_host.v4l2_dev.dev,
941        "Camera interrupt status 0x%lx\n", status);
942
943    if (!status)
944        return IRQ_NONE;
945
946    __raw_writel(status, pcdev->base + CISR);
947
948    if (status & CISR_EOF) {
949        /* Reset the FIFOs */
950        cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
951        __raw_writel(cifr, pcdev->base + CIFR);
952
953        pcdev->active = list_first_entry(&pcdev->capture,
954                       struct pxa_buffer, vb.queue);
955        vb = &pcdev->active->vb;
956        buf = container_of(vb, struct pxa_buffer, vb);
957        pxa_videobuf_set_actdma(pcdev, buf);
958
959        pxa_dma_start_channels(pcdev);
960
961        cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
962        __raw_writel(cicr0, pcdev->base + CICR0);
963    }
964
965    return IRQ_HANDLED;
966}
967
968/*
969 * The following two functions absolutely depend on the fact, that
970 * there can be only one camera on PXA quick capture interface
971 * Called with .video_lock held
972 */
973static int pxa_camera_add_device(struct soc_camera_device *icd)
974{
975    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
976    struct pxa_camera_dev *pcdev = ici->priv;
977
978    if (pcdev->icd)
979        return -EBUSY;
980
981    pxa_camera_activate(pcdev);
982
983    pcdev->icd = icd;
984
985    dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n",
986         icd->devnum);
987
988    return 0;
989}
990
991/* Called with .video_lock held */
992static void pxa_camera_remove_device(struct soc_camera_device *icd)
993{
994    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
995    struct pxa_camera_dev *pcdev = ici->priv;
996
997    BUG_ON(icd != pcdev->icd);
998
999    dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n",
1000         icd->devnum);
1001
1002    /* disable capture, disable interrupts */
1003    __raw_writel(0x3ff, pcdev->base + CICR0);
1004
1005    /* Stop DMA engine */
1006    DCSR(pcdev->dma_chans[0]) = 0;
1007    DCSR(pcdev->dma_chans[1]) = 0;
1008    DCSR(pcdev->dma_chans[2]) = 0;
1009
1010    pxa_camera_deactivate(pcdev);
1011
1012    pcdev->icd = NULL;
1013}
1014
1015static int test_platform_param(struct pxa_camera_dev *pcdev,
1016                   unsigned char buswidth, unsigned long *flags)
1017{
1018    /*
1019     * Platform specified synchronization and pixel clock polarities are
1020     * only a recommendation and are only used during probing. The PXA270
1021     * quick capture interface supports both.
1022     */
1023    *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1024          SOCAM_MASTER : SOCAM_SLAVE) |
1025        SOCAM_HSYNC_ACTIVE_HIGH |
1026        SOCAM_HSYNC_ACTIVE_LOW |
1027        SOCAM_VSYNC_ACTIVE_HIGH |
1028        SOCAM_VSYNC_ACTIVE_LOW |
1029        SOCAM_DATA_ACTIVE_HIGH |
1030        SOCAM_PCLK_SAMPLE_RISING |
1031        SOCAM_PCLK_SAMPLE_FALLING;
1032
1033    /* If requested data width is supported by the platform, use it */
1034    switch (buswidth) {
1035    case 10:
1036        if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1037            return -EINVAL;
1038        *flags |= SOCAM_DATAWIDTH_10;
1039        break;
1040    case 9:
1041        if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1042            return -EINVAL;
1043        *flags |= SOCAM_DATAWIDTH_9;
1044        break;
1045    case 8:
1046        if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1047            return -EINVAL;
1048        *flags |= SOCAM_DATAWIDTH_8;
1049        break;
1050    default:
1051        return -EINVAL;
1052    }
1053
1054    return 0;
1055}
1056
1057static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
1058                  unsigned long flags, __u32 pixfmt)
1059{
1060    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1061    struct pxa_camera_dev *pcdev = ici->priv;
1062    struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1063    unsigned long dw, bpp;
1064    u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1065    int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top);
1066
1067    if (ret < 0)
1068        y_skip_top = 0;
1069
1070    /*
1071     * Datawidth is now guaranteed to be equal to one of the three values.
1072     * We fix bit-per-pixel equal to data-width...
1073     */
1074    switch (flags & SOCAM_DATAWIDTH_MASK) {
1075    case SOCAM_DATAWIDTH_10:
1076        dw = 4;
1077        bpp = 0x40;
1078        break;
1079    case SOCAM_DATAWIDTH_9:
1080        dw = 3;
1081        bpp = 0x20;
1082        break;
1083    default:
1084        /*
1085         * Actually it can only be 8 now,
1086         * default is just to silence compiler warnings
1087         */
1088    case SOCAM_DATAWIDTH_8:
1089        dw = 2;
1090        bpp = 0;
1091    }
1092
1093    if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1094        cicr4 |= CICR4_PCLK_EN;
1095    if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1096        cicr4 |= CICR4_MCLK_EN;
1097    if (flags & SOCAM_PCLK_SAMPLE_FALLING)
1098        cicr4 |= CICR4_PCP;
1099    if (flags & SOCAM_HSYNC_ACTIVE_LOW)
1100        cicr4 |= CICR4_HSP;
1101    if (flags & SOCAM_VSYNC_ACTIVE_LOW)
1102        cicr4 |= CICR4_VSP;
1103
1104    cicr0 = __raw_readl(pcdev->base + CICR0);
1105    if (cicr0 & CICR0_ENB)
1106        __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1107
1108    cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1109
1110    switch (pixfmt) {
1111    case V4L2_PIX_FMT_YUV422P:
1112        pcdev->channels = 3;
1113        cicr1 |= CICR1_YCBCR_F;
1114        /*
1115         * Normally, pxa bus wants as input UYVY format. We allow all
1116         * reorderings of the YUV422 format, as no processing is done,
1117         * and the YUV stream is just passed through without any
1118         * transformation. Note that UYVY is the only format that
1119         * should be used if pxa framebuffer Overlay2 is used.
1120         */
1121    case V4L2_PIX_FMT_UYVY:
1122    case V4L2_PIX_FMT_VYUY:
1123    case V4L2_PIX_FMT_YUYV:
1124    case V4L2_PIX_FMT_YVYU:
1125        cicr1 |= CICR1_COLOR_SP_VAL(2);
1126        break;
1127    case V4L2_PIX_FMT_RGB555:
1128        cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1129            CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1130        break;
1131    case V4L2_PIX_FMT_RGB565:
1132        cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1133        break;
1134    }
1135
1136    cicr2 = 0;
1137    cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1138        CICR3_BFW_VAL(min((u32)255, y_skip_top));
1139    cicr4 |= pcdev->mclk_divisor;
1140
1141    __raw_writel(cicr1, pcdev->base + CICR1);
1142    __raw_writel(cicr2, pcdev->base + CICR2);
1143    __raw_writel(cicr3, pcdev->base + CICR3);
1144    __raw_writel(cicr4, pcdev->base + CICR4);
1145
1146    /* CIF interrupts are not used, only DMA */
1147    cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1148        CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1149    cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1150    __raw_writel(cicr0, pcdev->base + CICR0);
1151}
1152
1153static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1154{
1155    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1156    struct pxa_camera_dev *pcdev = ici->priv;
1157    unsigned long bus_flags, camera_flags, common_flags;
1158    const struct soc_mbus_pixelfmt *fmt;
1159    int ret;
1160    struct pxa_cam *cam = icd->host_priv;
1161
1162    fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
1163    if (!fmt)
1164        return -EINVAL;
1165
1166    ret = test_platform_param(pcdev, fmt->bits_per_sample, &bus_flags);
1167    if (ret < 0)
1168        return ret;
1169
1170    camera_flags = icd->ops->query_bus_param(icd);
1171
1172    common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1173    if (!common_flags)
1174        return -EINVAL;
1175
1176    pcdev->channels = 1;
1177
1178    /* Make choises, based on platform preferences */
1179    if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1180        (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1181        if (pcdev->platform_flags & PXA_CAMERA_HSP)
1182            common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1183        else
1184            common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1185    }
1186
1187    if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1188        (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1189        if (pcdev->platform_flags & PXA_CAMERA_VSP)
1190            common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1191        else
1192            common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1193    }
1194
1195    if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1196        (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1197        if (pcdev->platform_flags & PXA_CAMERA_PCP)
1198            common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1199        else
1200            common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1201    }
1202
1203    cam->flags = common_flags;
1204
1205    ret = icd->ops->set_bus_param(icd, common_flags);
1206    if (ret < 0)
1207        return ret;
1208
1209    pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1210
1211    return 0;
1212}
1213
1214static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1215                    unsigned char buswidth)
1216{
1217    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1218    struct pxa_camera_dev *pcdev = ici->priv;
1219    unsigned long bus_flags, camera_flags;
1220    int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1221
1222    if (ret < 0)
1223        return ret;
1224
1225    camera_flags = icd->ops->query_bus_param(icd);
1226
1227    return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1228}
1229
1230static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
1231    {
1232        .fourcc = V4L2_PIX_FMT_YUV422P,
1233        .name = "Planar YUV422 16 bit",
1234        .bits_per_sample = 8,
1235        .packing = SOC_MBUS_PACKING_2X8_PADHI,
1236        .order = SOC_MBUS_ORDER_LE,
1237    },
1238};
1239
1240/* This will be corrected as we get more formats */
1241static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
1242{
1243    return fmt->packing == SOC_MBUS_PACKING_NONE ||
1244        (fmt->bits_per_sample == 8 &&
1245         fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
1246        (fmt->bits_per_sample > 8 &&
1247         fmt->packing == SOC_MBUS_PACKING_EXTEND16);
1248}
1249
1250static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1251                  struct soc_camera_format_xlate *xlate)
1252{
1253    struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1254    struct device *dev = icd->dev.parent;
1255    int formats = 0, ret;
1256    struct pxa_cam *cam;
1257    enum v4l2_mbus_pixelcode code;
1258    const struct soc_mbus_pixelfmt *fmt;
1259
1260    ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1261    if (ret < 0)
1262        /* No more formats */
1263        return 0;
1264
1265    fmt = soc_mbus_get_fmtdesc(code);
1266    if (!fmt) {
1267        dev_err(dev, "Invalid format code #%d: %d\n", idx, code);
1268        return 0;
1269    }
1270
1271    /* This also checks support for the requested bits-per-sample */
1272    ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample);
1273    if (ret < 0)
1274        return 0;
1275
1276    if (!icd->host_priv) {
1277        cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1278        if (!cam)
1279            return -ENOMEM;
1280
1281        icd->host_priv = cam;
1282    } else {
1283        cam = icd->host_priv;
1284    }
1285
1286    switch (code) {
1287    case V4L2_MBUS_FMT_YUYV8_2X8_BE:
1288        formats++;
1289        if (xlate) {
1290            xlate->host_fmt = &pxa_camera_formats[0];
1291            xlate->code = code;
1292            xlate++;
1293            dev_dbg(dev, "Providing format %s using code %d\n",
1294                pxa_camera_formats[0].name, code);
1295        }
1296    case V4L2_MBUS_FMT_YVYU8_2X8_BE:
1297    case V4L2_MBUS_FMT_YUYV8_2X8_LE:
1298    case V4L2_MBUS_FMT_YVYU8_2X8_LE:
1299    case V4L2_MBUS_FMT_RGB565_2X8_LE:
1300    case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
1301        if (xlate)
1302            dev_dbg(dev, "Providing format %s packed\n",
1303                fmt->name);
1304        break;
1305    default:
1306        if (!pxa_camera_packing_supported(fmt))
1307            return 0;
1308        if (xlate)
1309            dev_dbg(dev,
1310                "Providing format %s in pass-through mode\n",
1311                fmt->name);
1312    }
1313
1314    /* Generic pass-through */
1315    formats++;
1316    if (xlate) {
1317        xlate->host_fmt = fmt;
1318        xlate->code = code;
1319        xlate++;
1320    }
1321
1322    return formats;
1323}
1324
1325static void pxa_camera_put_formats(struct soc_camera_device *icd)
1326{
1327    kfree(icd->host_priv);
1328    icd->host_priv = NULL;
1329}
1330
1331static int pxa_camera_check_frame(u32 width, u32 height)
1332{
1333    /* limit to pxa hardware capabilities */
1334    return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1335        (width & 0x01);
1336}
1337
1338static int pxa_camera_set_crop(struct soc_camera_device *icd,
1339                   struct v4l2_crop *a)
1340{
1341    struct v4l2_rect *rect = &a->c;
1342    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1343    struct pxa_camera_dev *pcdev = ici->priv;
1344    struct device *dev = icd->dev.parent;
1345    struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1346    struct soc_camera_sense sense = {
1347        .master_clock = pcdev->mclk,
1348        .pixel_clock_max = pcdev->ciclk / 4,
1349    };
1350    struct v4l2_mbus_framefmt mf;
1351    struct pxa_cam *cam = icd->host_priv;
1352    u32 fourcc = icd->current_fmt->host_fmt->fourcc;
1353    int ret;
1354
1355    /* If PCLK is used to latch data from the sensor, check sense */
1356    if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1357        icd->sense = &sense;
1358
1359    ret = v4l2_subdev_call(sd, video, s_crop, a);
1360
1361    icd->sense = NULL;
1362
1363    if (ret < 0) {
1364        dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1365             rect->width, rect->height, rect->left, rect->top);
1366        return ret;
1367    }
1368
1369    ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1370    if (ret < 0)
1371        return ret;
1372
1373    if (pxa_camera_check_frame(mf.width, mf.height)) {
1374        /*
1375         * Camera cropping produced a frame beyond our capabilities.
1376         * FIXME: just extract a subframe, that we can process.
1377         */
1378        v4l_bound_align_image(&mf.width, 48, 2048, 1,
1379            &mf.height, 32, 2048, 0,
1380            fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1381        ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1382        if (ret < 0)
1383            return ret;
1384
1385        if (pxa_camera_check_frame(mf.width, mf.height)) {
1386            dev_warn(icd->dev.parent,
1387                 "Inconsistent state. Use S_FMT to repair\n");
1388            return -EINVAL;
1389        }
1390    }
1391
1392    if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1393        if (sense.pixel_clock > sense.pixel_clock_max) {
1394            dev_err(dev,
1395                "pixel clock %lu set by the camera too high!",
1396                sense.pixel_clock);
1397            return -EIO;
1398        }
1399        recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1400    }
1401
1402    icd->user_width = mf.width;
1403    icd->user_height = mf.height;
1404
1405    pxa_camera_setup_cicr(icd, cam->flags, fourcc);
1406
1407    return ret;
1408}
1409
1410static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1411                  struct v4l2_format *f)
1412{
1413    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1414    struct pxa_camera_dev *pcdev = ici->priv;
1415    struct device *dev = icd->dev.parent;
1416    struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1417    const struct soc_camera_format_xlate *xlate = NULL;
1418    struct soc_camera_sense sense = {
1419        .master_clock = pcdev->mclk,
1420        .pixel_clock_max = pcdev->ciclk / 4,
1421    };
1422    struct v4l2_pix_format *pix = &f->fmt.pix;
1423    struct v4l2_mbus_framefmt mf;
1424    int ret;
1425
1426    xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1427    if (!xlate) {
1428        dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1429        return -EINVAL;
1430    }
1431
1432    /* If PCLK is used to latch data from the sensor, check sense */
1433    if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1434        /* The caller holds a mutex. */
1435        icd->sense = &sense;
1436
1437    mf.width = pix->width;
1438    mf.height = pix->height;
1439    mf.field = pix->field;
1440    mf.colorspace = pix->colorspace;
1441    mf.code = xlate->code;
1442
1443    ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1444
1445    if (mf.code != xlate->code)
1446        return -EINVAL;
1447
1448    icd->sense = NULL;
1449
1450    if (ret < 0) {
1451        dev_warn(dev, "Failed to configure for format %x\n",
1452             pix->pixelformat);
1453    } else if (pxa_camera_check_frame(mf.width, mf.height)) {
1454        dev_warn(dev,
1455             "Camera driver produced an unsupported frame %dx%d\n",
1456             mf.width, mf.height);
1457        ret = -EINVAL;
1458    } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1459        if (sense.pixel_clock > sense.pixel_clock_max) {
1460            dev_err(dev,
1461                "pixel clock %lu set by the camera too high!",
1462                sense.pixel_clock);
1463            return -EIO;
1464        }
1465        recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1466    }
1467
1468    if (ret < 0)
1469        return ret;
1470
1471    pix->width = mf.width;
1472    pix->height = mf.height;
1473    pix->field = mf.field;
1474    pix->colorspace = mf.colorspace;
1475    icd->current_fmt = xlate;
1476
1477    return ret;
1478}
1479
1480static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1481                  struct v4l2_format *f)
1482{
1483    struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1484    const struct soc_camera_format_xlate *xlate;
1485    struct v4l2_pix_format *pix = &f->fmt.pix;
1486    struct v4l2_mbus_framefmt mf;
1487    __u32 pixfmt = pix->pixelformat;
1488    int ret;
1489
1490    xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1491    if (!xlate) {
1492        dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
1493        return -EINVAL;
1494    }
1495
1496    /*
1497     * Limit to pxa hardware capabilities. YUV422P planar format requires
1498     * images size to be a multiple of 16 bytes. If not, zeros will be
1499     * inserted between Y and U planes, and U and V planes, which violates
1500     * the YUV422P standard.
1501     */
1502    v4l_bound_align_image(&pix->width, 48, 2048, 1,
1503                  &pix->height, 32, 2048, 0,
1504                  pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1505
1506    pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1507                            xlate->host_fmt);
1508    if (pix->bytesperline < 0)
1509        return pix->bytesperline;
1510    pix->sizeimage = pix->height * pix->bytesperline;
1511
1512    /* limit to sensor capabilities */
1513    mf.width = pix->width;
1514    mf.height = pix->height;
1515    mf.field = pix->field;
1516    mf.colorspace = pix->colorspace;
1517    mf.code = xlate->code;
1518
1519    ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1520    if (ret < 0)
1521        return ret;
1522
1523    pix->width = mf.width;
1524    pix->height = mf.height;
1525    pix->colorspace = mf.colorspace;
1526
1527    switch (mf.field) {
1528    case V4L2_FIELD_ANY:
1529    case V4L2_FIELD_NONE:
1530        pix->field = V4L2_FIELD_NONE;
1531        break;
1532    default:
1533        /* TODO: support interlaced at least in pass-through mode */
1534        dev_err(icd->dev.parent, "Field type %d unsupported.\n",
1535            mf.field);
1536        return -EINVAL;
1537    }
1538
1539    return ret;
1540}
1541
1542static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1543                  struct v4l2_requestbuffers *p)
1544{
1545    int i;
1546
1547    /*
1548     * This is for locking debugging only. I removed spinlocks and now I
1549     * check whether .prepare is ever called on a linked buffer, or whether
1550     * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1551     * it hadn't triggered
1552     */
1553    for (i = 0; i < p->count; i++) {
1554        struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1555                              struct pxa_buffer, vb);
1556        buf->inwork = 0;
1557        INIT_LIST_HEAD(&buf->vb.queue);
1558    }
1559
1560    return 0;
1561}
1562
1563static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1564{
1565    struct soc_camera_file *icf = file->private_data;
1566    struct pxa_buffer *buf;
1567
1568    buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1569             vb.stream);
1570
1571    poll_wait(file, &buf->vb.done, pt);
1572
1573    if (buf->vb.state == VIDEOBUF_DONE ||
1574        buf->vb.state == VIDEOBUF_ERROR)
1575        return POLLIN|POLLRDNORM;
1576
1577    return 0;
1578}
1579
1580static int pxa_camera_querycap(struct soc_camera_host *ici,
1581                   struct v4l2_capability *cap)
1582{
1583    /* cap->name is set by the firendly caller:-> */
1584    strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1585    cap->version = PXA_CAM_VERSION_CODE;
1586    cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1587
1588    return 0;
1589}
1590
1591static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1592{
1593    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1594    struct pxa_camera_dev *pcdev = ici->priv;
1595    int i = 0, ret = 0;
1596
1597    pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1598    pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1599    pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1600    pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1601    pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1602
1603    if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1604        ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1605
1606    return ret;
1607}
1608
1609static int pxa_camera_resume(struct soc_camera_device *icd)
1610{
1611    struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1612    struct pxa_camera_dev *pcdev = ici->priv;
1613    int i = 0, ret = 0;
1614
1615    DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1616    DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1617    DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1618
1619    __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1620    __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1621    __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1622    __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1623    __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1624
1625    if ((pcdev->icd) && (pcdev->icd->ops->resume))
1626        ret = pcdev->icd->ops->resume(pcdev->icd);
1627
1628    /* Restart frame capture if active buffer exists */
1629    if (!ret && pcdev->active)
1630        pxa_camera_start_capture(pcdev);
1631
1632    return ret;
1633}
1634
1635static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1636    .owner = THIS_MODULE,
1637    .add = pxa_camera_add_device,
1638    .remove = pxa_camera_remove_device,
1639    .suspend = pxa_camera_suspend,
1640    .resume = pxa_camera_resume,
1641    .set_crop = pxa_camera_set_crop,
1642    .get_formats = pxa_camera_get_formats,
1643    .put_formats = pxa_camera_put_formats,
1644    .set_fmt = pxa_camera_set_fmt,
1645    .try_fmt = pxa_camera_try_fmt,
1646    .init_videobuf = pxa_camera_init_videobuf,
1647    .reqbufs = pxa_camera_reqbufs,
1648    .poll = pxa_camera_poll,
1649    .querycap = pxa_camera_querycap,
1650    .set_bus_param = pxa_camera_set_bus_param,
1651};
1652
1653static int __devinit pxa_camera_probe(struct platform_device *pdev)
1654{
1655    struct pxa_camera_dev *pcdev;
1656    struct resource *res;
1657    void __iomem *base;
1658    int irq;
1659    int err = 0;
1660
1661    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1662    irq = platform_get_irq(pdev, 0);
1663    if (!res || irq < 0) {
1664        err = -ENODEV;
1665        goto exit;
1666    }
1667
1668    pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1669    if (!pcdev) {
1670        dev_err(&pdev->dev, "Could not allocate pcdev\n");
1671        err = -ENOMEM;
1672        goto exit;
1673    }
1674
1675    pcdev->clk = clk_get(&pdev->dev, NULL);
1676    if (IS_ERR(pcdev->clk)) {
1677        err = PTR_ERR(pcdev->clk);
1678        goto exit_kfree;
1679    }
1680
1681    pcdev->res = res;
1682
1683    pcdev->pdata = pdev->dev.platform_data;
1684    pcdev->platform_flags = pcdev->pdata->flags;
1685    if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1686            PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1687        /*
1688         * Platform hasn't set available data widths. This is bad.
1689         * Warn and use a default.
1690         */
1691        dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1692             "data widths, using default 10 bit\n");
1693        pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1694    }
1695    pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1696    if (!pcdev->mclk) {
1697        dev_warn(&pdev->dev,
1698             "mclk == 0! Please, fix your platform data. "
1699             "Using default 20MHz\n");
1700        pcdev->mclk = 20000000;
1701    }
1702
1703    pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1704
1705    INIT_LIST_HEAD(&pcdev->capture);
1706    spin_lock_init(&pcdev->lock);
1707
1708    /*
1709     * Request the regions.
1710     */
1711    if (!request_mem_region(res->start, resource_size(res),
1712                PXA_CAM_DRV_NAME)) {
1713        err = -EBUSY;
1714        goto exit_clk;
1715    }
1716
1717    base = ioremap(res->start, resource_size(res));
1718    if (!base) {
1719        err = -ENOMEM;
1720        goto exit_release;
1721    }
1722    pcdev->irq = irq;
1723    pcdev->base = base;
1724
1725    /* request dma */
1726    err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1727                  pxa_camera_dma_irq_y, pcdev);
1728    if (err < 0) {
1729        dev_err(&pdev->dev, "Can't request DMA for Y\n");
1730        goto exit_iounmap;
1731    }
1732    pcdev->dma_chans[0] = err;
1733    dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1734
1735    err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1736                  pxa_camera_dma_irq_u, pcdev);
1737    if (err < 0) {
1738        dev_err(&pdev->dev, "Can't request DMA for U\n");
1739        goto exit_free_dma_y;
1740    }
1741    pcdev->dma_chans[1] = err;
1742    dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1743
1744    err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1745                  pxa_camera_dma_irq_v, pcdev);
1746    if (err < 0) {
1747        dev_err(&pdev->dev, "Can't request DMA for V\n");
1748        goto exit_free_dma_u;
1749    }
1750    pcdev->dma_chans[2] = err;
1751    dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1752
1753    DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1754    DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1755    DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1756
1757    /* request irq */
1758    err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1759              pcdev);
1760    if (err) {
1761        dev_err(&pdev->dev, "Camera interrupt register failed \n");
1762        goto exit_free_dma;
1763    }
1764
1765    pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1766    pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1767    pcdev->soc_host.priv = pcdev;
1768    pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1769    pcdev->soc_host.nr = pdev->id;
1770
1771    err = soc_camera_host_register(&pcdev->soc_host);
1772    if (err)
1773        goto exit_free_irq;
1774
1775    return 0;
1776
1777exit_free_irq:
1778    free_irq(pcdev->irq, pcdev);
1779exit_free_dma:
1780    pxa_free_dma(pcdev->dma_chans[2]);
1781exit_free_dma_u:
1782    pxa_free_dma(pcdev->dma_chans[1]);
1783exit_free_dma_y:
1784    pxa_free_dma(pcdev->dma_chans[0]);
1785exit_iounmap:
1786    iounmap(base);
1787exit_release:
1788    release_mem_region(res->start, resource_size(res));
1789exit_clk:
1790    clk_put(pcdev->clk);
1791exit_kfree:
1792    kfree(pcdev);
1793exit:
1794    return err;
1795}
1796
1797static int __devexit pxa_camera_remove(struct platform_device *pdev)
1798{
1799    struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1800    struct pxa_camera_dev *pcdev = container_of(soc_host,
1801                    struct pxa_camera_dev, soc_host);
1802    struct resource *res;
1803
1804    clk_put(pcdev->clk);
1805
1806    pxa_free_dma(pcdev->dma_chans[0]);
1807    pxa_free_dma(pcdev->dma_chans[1]);
1808    pxa_free_dma(pcdev->dma_chans[2]);
1809    free_irq(pcdev->irq, pcdev);
1810
1811    soc_camera_host_unregister(soc_host);
1812
1813    iounmap(pcdev->base);
1814
1815    res = pcdev->res;
1816    release_mem_region(res->start, resource_size(res));
1817
1818    kfree(pcdev);
1819
1820    dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1821
1822    return 0;
1823}
1824
1825static struct platform_driver pxa_camera_driver = {
1826    .driver = {
1827        .name = PXA_CAM_DRV_NAME,
1828    },
1829    .probe = pxa_camera_probe,
1830    .remove = __devexit_p(pxa_camera_remove),
1831};
1832
1833
1834static int __init pxa_camera_init(void)
1835{
1836    return platform_driver_register(&pxa_camera_driver);
1837}
1838
1839static void __exit pxa_camera_exit(void)
1840{
1841    platform_driver_unregister(&pxa_camera_driver);
1842}
1843
1844module_init(pxa_camera_init);
1845module_exit(pxa_camera_exit);
1846
1847MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1848MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1849MODULE_LICENSE("GPL");
1850MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
1851

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