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| Source at commit ae56dee43db20497a8cb74a9df70046557705f6e created 11 years 8 months ago. By Paul Cercueil, MIPS: JZ4740: add the 'panel' attribute to /sys | |
|---|---|
| 1 | /* |
| 2 | * linux/drivers/video/jz4740_slcd.h |
| 3 | * -- LCD panel definitions for Ingenic On-Chip SLCD frame buffer device |
| 4 | * |
| 5 | * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. |
| 6 | * Copyright (C) 2010, Maarten ter Huurne <maarten@treewalker.org> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef __JZ4740_SLCD_H__ |
| 15 | #define __JZ4740_SLCD_H__ |
| 16 | |
| 17 | #include <asm/mach-jz4740/base.h> |
| 18 | #include <linux/gpio.h> |
| 19 | #include <linux/mutex.h> |
| 20 | #include <linux/workqueue.h> |
| 21 | |
| 22 | /************************************************************************* |
| 23 | * SLCD (Smart LCD Controller) |
| 24 | *************************************************************************/ |
| 25 | |
| 26 | #define JZ_REG_SLCD_CFG 0xA0 /* SLCD Configure Register */ |
| 27 | #define JZ_REG_SLCD_CTRL 0xA4 /* SLCD Control Register */ |
| 28 | #define JZ_REG_SLCD_STATE 0xA8 /* SLCD Status Register */ |
| 29 | #define JZ_REG_SLCD_DATA 0xAC /* SLCD Data Register */ |
| 30 | #define JZ_REG_SLCD_FIFO 0xB0 /* SLCD FIFO Register */ |
| 31 | |
| 32 | /* SLCD Configure Register */ |
| 33 | #define SLCD_CFG_BURST_BIT 14 |
| 34 | #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) |
| 35 | #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) |
| 36 | #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) |
| 37 | #define SLCD_CFG_DWIDTH_BIT 10 |
| 38 | #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) |
| 39 | #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) |
| 40 | #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) |
| 41 | #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) |
| 42 | #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) |
| 43 | #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) |
| 44 | #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT) |
| 45 | #define SLCD_CFG_CWIDTH_BIT 8 |
| 46 | #define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT) |
| 47 | #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT) |
| 48 | #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT) |
| 49 | #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT) |
| 50 | #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) |
| 51 | #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) |
| 52 | #define SLCD_CFG_RS_CMD_LOW (0 << 3) |
| 53 | #define SLCD_CFG_RS_CMD_HIGH (1 << 3) |
| 54 | #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) |
| 55 | #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) |
| 56 | #define SLCD_CFG_TYPE_PARALLEL (0 << 0) |
| 57 | #define SLCD_CFG_TYPE_SERIAL (1 << 0) |
| 58 | |
| 59 | /* SLCD Control Register */ |
| 60 | #define SLCD_CTRL_DMA_EN (1 << 0) |
| 61 | |
| 62 | /* SLCD Status Register */ |
| 63 | #define SLCD_STATE_BUSY (1 << 0) |
| 64 | |
| 65 | /* SLCD Data Register */ |
| 66 | #define SLCD_DATA_RS_DATA (0 << 31) |
| 67 | #define SLCD_DATA_RS_COMMAND (1 << 31) |
| 68 | |
| 69 | /* SLCD FIFO Register */ |
| 70 | #define SLCD_FIFO_RS_DATA (0 << 31) |
| 71 | #define SLCD_FIFO_RS_COMMAND (1 << 31) |
| 72 | |
| 73 | /*************************************************************************/ |
| 74 | |
| 75 | struct jzfb { |
| 76 | struct fb_info *fb; |
| 77 | struct platform_device *pdev; |
| 78 | void __iomem *base; |
| 79 | struct resource *mem; |
| 80 | struct jz4740_fb_platform_data *pdata; |
| 81 | const struct jz_slcd_panel *panel; |
| 82 | |
| 83 | size_t vidmem_size; |
| 84 | void *vidmem; |
| 85 | dma_addr_t vidmem_phys; |
| 86 | struct jzfb_framedesc *framedesc; |
| 87 | dma_addr_t framedesc_phys; |
| 88 | struct jz4740_dma_chan *dma; |
| 89 | |
| 90 | struct clk *ldclk; |
| 91 | struct clk *lpclk; |
| 92 | |
| 93 | unsigned is_enabled:1; |
| 94 | struct mutex lock; /* Protecting against running enable/disable in paralell */ |
| 95 | |
| 96 | struct delayed_work refresh_work; |
| 97 | |
| 98 | uint32_t pseudo_palette[16]; |
| 99 | #ifdef CONFIG_JZ_SLCD_ILI9338 |
| 100 | unsigned int rgb[3]; |
| 101 | #endif |
| 102 | }; |
| 103 | |
| 104 | struct jz_slcd_panel { |
| 105 | /* request and configure GPIO pins */ |
| 106 | int (*init)(struct jzfb *jzfb); |
| 107 | /* free GPIO pins */ |
| 108 | void (*exit)(struct jzfb *jzfb); |
| 109 | /* activate, reset and initialize */ |
| 110 | void (*enable)(struct jzfb *jzfb); |
| 111 | /* deactivate */ |
| 112 | void (*disable)(struct jzfb *jzfb); |
| 113 | /* panel name */ |
| 114 | const char *name; |
| 115 | }; |
| 116 | |
| 117 | const struct jz_slcd_panel *jz_slcd_panel_from_name(const char *name); |
| 118 | const struct jz_slcd_panel *jz_slcd_panels_probe(struct jzfb *jzfb); |
| 119 | |
| 120 | #endif /*__JZ4740_SLCD_H__*/ |
| 121 | |
Branches:
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javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9
