Root/drivers/video/jz4740_lcd.h

Source at commit b3353d6753f5aabb2359e9039f005e0cae19ef65 created 8 years 6 months ago.
By Paul Cercueil, MIPS: JZ4740: LCD: Fixed LCD_CMD consts and completed LCD_STATE consts
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC LCD framebuffer driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __JZ4740_LCD_H__
17#define __JZ4740_LCD_H__
18
19#include <linux/bitops.h>
20
21#define JZ_REG_LCD_CFG 0x00
22#define JZ_REG_LCD_VSYNC 0x04
23#define JZ_REG_LCD_HSYNC 0x08
24#define JZ_REG_LCD_VAT 0x0C
25#define JZ_REG_LCD_DAH 0x10
26#define JZ_REG_LCD_DAV 0x14
27#define JZ_REG_LCD_PS 0x18
28#define JZ_REG_LCD_CLS 0x1C
29#define JZ_REG_LCD_SPL 0x20
30#define JZ_REG_LCD_REV 0x24
31#define JZ_REG_LCD_CTRL 0x30
32#define JZ_REG_LCD_STATE 0x34
33#define JZ_REG_LCD_IID 0x38
34#define JZ_REG_LCD_DA0 0x40
35#define JZ_REG_LCD_SA0 0x44
36#define JZ_REG_LCD_FID0 0x48
37#define JZ_REG_LCD_CMD0 0x4C
38#define JZ_REG_LCD_DA1 0x50
39#define JZ_REG_LCD_SA1 0x54
40#define JZ_REG_LCD_FID1 0x58
41#define JZ_REG_LCD_CMD1 0x5C
42
43#define JZ_LCD_CFG_SLCD BIT(31)
44#define JZ_LCD_CFG_PS_DISABLE BIT(23)
45#define JZ_LCD_CFG_CLS_DISABLE BIT(22)
46#define JZ_LCD_CFG_SPL_DISABLE BIT(21)
47#define JZ_LCD_CFG_REV_DISABLE BIT(20)
48#define JZ_LCD_CFG_HSYNCM BIT(19)
49#define JZ_LCD_CFG_PCLKM BIT(18)
50#define JZ_LCD_CFG_INV BIT(17)
51#define JZ_LCD_CFG_SYNC_DIR BIT(16)
52#define JZ_LCD_CFG_PS_POLARITY BIT(15)
53#define JZ_LCD_CFG_CLS_POLARITY BIT(14)
54#define JZ_LCD_CFG_SPL_POLARITY BIT(13)
55#define JZ_LCD_CFG_REV_POLARITY BIT(12)
56#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
57#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
58#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
59#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
60#define JZ_LCD_CFG_18_BIT BIT(7)
61#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
62#define JZ_LCD_CFG_MODE_MASK 0xf
63
64#define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
65#define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
66#define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
67#define JZ_LCD_CTRL_RGB555 BIT(27)
68#define JZ_LCD_CTRL_OFUP BIT(26)
69#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
70#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
71#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
72#define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
73#define JZ_LCD_CTRL_EOF_IRQ BIT(13)
74#define JZ_LCD_CTRL_SOF_IRQ BIT(12)
75#define JZ_LCD_CTRL_OFU_IRQ BIT(11)
76#define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
77#define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
78#define JZ_LCD_CTRL_DD_IRQ BIT(8)
79#define JZ_LCD_CTRL_QDD_IRQ BIT(7)
80#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
81#define JZ_LCD_CTRL_LSB_FISRT BIT(5)
82#define JZ_LCD_CTRL_DISABLE BIT(4)
83#define JZ_LCD_CTRL_ENABLE BIT(3)
84#define JZ_LCD_CTRL_BPP_1 0x0
85#define JZ_LCD_CTRL_BPP_2 0x1
86#define JZ_LCD_CTRL_BPP_4 0x2
87#define JZ_LCD_CTRL_BPP_8 0x3
88#define JZ_LCD_CTRL_BPP_15_16 0x4
89#define JZ_LCD_CTRL_BPP_18_24 0x5
90
91#define JZ_LCD_CMD_SOF_IRQ BIT(31)
92#define JZ_LCD_CMD_EOF_IRQ BIT(30)
93#define JZ_LCD_CMD_ENABLE_PAL BIT(28)
94
95#define JZ_LCD_SYNC_MASK 0x3ff
96
97#define JZ_LCD_STATE_QUICK_DISABLED BIT(7)
98#define JZ_LCD_STATE_EOF BIT(5)
99#define JZ_LCD_STATE_SOF BIT(4)
100#define JZ_LCD_STATE_OUT_FIFO_UNDERRUN BIT(3)
101#define JZ_LCD_STATE_FIFO0_UNDERRUN BIT(2)
102#define JZ_LCD_STATE_FIFO1_UNDERRUN BIT(1)
103#define JZ_LCD_STATE_DISABLED BIT(0)
104
105#endif /*__JZ4740_LCD_H__*/
106

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