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Source at commit b56ba8aa6f3aeab23d3d4b1190ed1098463b2a9c created 14 years 1 month ago. By Colin Tuckley, ARM: 5957/1: ARM: RealView SD/MMC Card detection and write-protect using GPIOLIB | |
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1 | /* |
2 | * linux/arch/arm/mach-realview/core.c |
3 | * |
4 | * Copyright (C) 1999 - 2003 ARM Limited |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by |
9 | * the Free Software Foundation; either version 2 of the License, or |
10 | * (at your option) any later version. |
11 | * |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
15 | * GNU General Public License for more details. |
16 | * |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
20 | */ |
21 | #include <linux/init.h> |
22 | #include <linux/platform_device.h> |
23 | #include <linux/dma-mapping.h> |
24 | #include <linux/sysdev.h> |
25 | #include <linux/interrupt.h> |
26 | #include <linux/amba/bus.h> |
27 | #include <linux/amba/clcd.h> |
28 | #include <linux/clocksource.h> |
29 | #include <linux/clockchips.h> |
30 | #include <linux/io.h> |
31 | #include <linux/smsc911x.h> |
32 | #include <linux/ata_platform.h> |
33 | #include <linux/amba/mmci.h> |
34 | #include <linux/gfp.h> |
35 | |
36 | #include <asm/clkdev.h> |
37 | #include <asm/system.h> |
38 | #include <mach/hardware.h> |
39 | #include <asm/irq.h> |
40 | #include <asm/leds.h> |
41 | #include <asm/mach-types.h> |
42 | #include <asm/hardware/arm_timer.h> |
43 | #include <asm/hardware/icst307.h> |
44 | |
45 | #include <asm/mach/arch.h> |
46 | #include <asm/mach/flash.h> |
47 | #include <asm/mach/irq.h> |
48 | #include <asm/mach/map.h> |
49 | |
50 | #include <asm/hardware/gic.h> |
51 | |
52 | #include <mach/platform.h> |
53 | #include <mach/irqs.h> |
54 | |
55 | #include "core.h" |
56 | #include "clock.h" |
57 | |
58 | #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) |
59 | |
60 | /* used by entry-macro.S and platsmp.c */ |
61 | void __iomem *gic_cpu_base_addr; |
62 | |
63 | #ifdef CONFIG_ZONE_DMA |
64 | /* |
65 | * Adjust the zones if there are restrictions for DMA access. |
66 | */ |
67 | void __init realview_adjust_zones(int node, unsigned long *size, |
68 | unsigned long *hole) |
69 | { |
70 | unsigned long dma_size = SZ_256M >> PAGE_SHIFT; |
71 | |
72 | if (!machine_is_realview_pbx() || node || (size[0] <= dma_size)) |
73 | return; |
74 | |
75 | size[ZONE_NORMAL] = size[0] - dma_size; |
76 | size[ZONE_DMA] = dma_size; |
77 | hole[ZONE_NORMAL] = hole[0]; |
78 | hole[ZONE_DMA] = 0; |
79 | } |
80 | #endif |
81 | |
82 | /* |
83 | * This is the RealView sched_clock implementation. This has |
84 | * a resolution of 41.7ns, and a maximum value of about 179s. |
85 | */ |
86 | unsigned long long sched_clock(void) |
87 | { |
88 | unsigned long long v; |
89 | |
90 | v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125; |
91 | do_div(v, 3); |
92 | |
93 | return v; |
94 | } |
95 | |
96 | |
97 | #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) |
98 | |
99 | static int realview_flash_init(void) |
100 | { |
101 | u32 val; |
102 | |
103 | val = __raw_readl(REALVIEW_FLASHCTRL); |
104 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; |
105 | __raw_writel(val, REALVIEW_FLASHCTRL); |
106 | |
107 | return 0; |
108 | } |
109 | |
110 | static void realview_flash_exit(void) |
111 | { |
112 | u32 val; |
113 | |
114 | val = __raw_readl(REALVIEW_FLASHCTRL); |
115 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; |
116 | __raw_writel(val, REALVIEW_FLASHCTRL); |
117 | } |
118 | |
119 | static void realview_flash_set_vpp(int on) |
120 | { |
121 | u32 val; |
122 | |
123 | val = __raw_readl(REALVIEW_FLASHCTRL); |
124 | if (on) |
125 | val |= REALVIEW_FLASHPROG_FLVPPEN; |
126 | else |
127 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; |
128 | __raw_writel(val, REALVIEW_FLASHCTRL); |
129 | } |
130 | |
131 | static struct flash_platform_data realview_flash_data = { |
132 | .map_name = "cfi_probe", |
133 | .width = 4, |
134 | .init = realview_flash_init, |
135 | .exit = realview_flash_exit, |
136 | .set_vpp = realview_flash_set_vpp, |
137 | }; |
138 | |
139 | struct platform_device realview_flash_device = { |
140 | .name = "armflash", |
141 | .id = 0, |
142 | .dev = { |
143 | .platform_data = &realview_flash_data, |
144 | }, |
145 | }; |
146 | |
147 | int realview_flash_register(struct resource *res, u32 num) |
148 | { |
149 | realview_flash_device.resource = res; |
150 | realview_flash_device.num_resources = num; |
151 | return platform_device_register(&realview_flash_device); |
152 | } |
153 | |
154 | static struct smsc911x_platform_config smsc911x_config = { |
155 | .flags = SMSC911X_USE_32BIT, |
156 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, |
157 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, |
158 | .phy_interface = PHY_INTERFACE_MODE_MII, |
159 | }; |
160 | |
161 | static struct platform_device realview_eth_device = { |
162 | .name = "smsc911x", |
163 | .id = 0, |
164 | .num_resources = 2, |
165 | }; |
166 | |
167 | int realview_eth_register(const char *name, struct resource *res) |
168 | { |
169 | if (name) |
170 | realview_eth_device.name = name; |
171 | realview_eth_device.resource = res; |
172 | if (strcmp(realview_eth_device.name, "smsc911x") == 0) |
173 | realview_eth_device.dev.platform_data = &smsc911x_config; |
174 | |
175 | return platform_device_register(&realview_eth_device); |
176 | } |
177 | |
178 | struct platform_device realview_usb_device = { |
179 | .name = "isp1760", |
180 | .num_resources = 2, |
181 | }; |
182 | |
183 | int realview_usb_register(struct resource *res) |
184 | { |
185 | realview_usb_device.resource = res; |
186 | return platform_device_register(&realview_usb_device); |
187 | } |
188 | |
189 | static struct pata_platform_info pata_platform_data = { |
190 | .ioport_shift = 1, |
191 | }; |
192 | |
193 | static struct resource pata_resources[] = { |
194 | [0] = { |
195 | .start = REALVIEW_CF_BASE, |
196 | .end = REALVIEW_CF_BASE + 0xff, |
197 | .flags = IORESOURCE_MEM, |
198 | }, |
199 | [1] = { |
200 | .start = REALVIEW_CF_BASE + 0x100, |
201 | .end = REALVIEW_CF_BASE + SZ_4K - 1, |
202 | .flags = IORESOURCE_MEM, |
203 | }, |
204 | }; |
205 | |
206 | struct platform_device realview_cf_device = { |
207 | .name = "pata_platform", |
208 | .id = -1, |
209 | .num_resources = ARRAY_SIZE(pata_resources), |
210 | .resource = pata_resources, |
211 | .dev = { |
212 | .platform_data = &pata_platform_data, |
213 | }, |
214 | }; |
215 | |
216 | static struct resource realview_i2c_resource = { |
217 | .start = REALVIEW_I2C_BASE, |
218 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, |
219 | .flags = IORESOURCE_MEM, |
220 | }; |
221 | |
222 | struct platform_device realview_i2c_device = { |
223 | .name = "versatile-i2c", |
224 | .id = 0, |
225 | .num_resources = 1, |
226 | .resource = &realview_i2c_resource, |
227 | }; |
228 | |
229 | static struct i2c_board_info realview_i2c_board_info[] = { |
230 | { |
231 | I2C_BOARD_INFO("ds1338", 0xd0 >> 1), |
232 | }, |
233 | }; |
234 | |
235 | static int __init realview_i2c_init(void) |
236 | { |
237 | return i2c_register_board_info(0, realview_i2c_board_info, |
238 | ARRAY_SIZE(realview_i2c_board_info)); |
239 | } |
240 | arch_initcall(realview_i2c_init); |
241 | |
242 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) |
243 | |
244 | /* |
245 | * This is only used if GPIOLIB support is disabled |
246 | */ |
247 | static unsigned int realview_mmc_status(struct device *dev) |
248 | { |
249 | struct amba_device *adev = container_of(dev, struct amba_device, dev); |
250 | u32 mask; |
251 | |
252 | if (adev->res.start == REALVIEW_MMCI0_BASE) |
253 | mask = 1; |
254 | else |
255 | mask = 2; |
256 | |
257 | return !(readl(REALVIEW_SYSMCI) & mask); |
258 | } |
259 | |
260 | struct mmci_platform_data realview_mmc0_plat_data = { |
261 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
262 | .status = realview_mmc_status, |
263 | .gpio_wp = 17, |
264 | .gpio_cd = 16, |
265 | }; |
266 | |
267 | struct mmci_platform_data realview_mmc1_plat_data = { |
268 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
269 | .status = realview_mmc_status, |
270 | .gpio_wp = 19, |
271 | .gpio_cd = 18, |
272 | }; |
273 | |
274 | /* |
275 | * Clock handling |
276 | */ |
277 | static const struct icst307_params realview_oscvco_params = { |
278 | .ref = 24000, |
279 | .vco_max = 200000, |
280 | .vd_min = 4 + 8, |
281 | .vd_max = 511 + 8, |
282 | .rd_min = 1 + 2, |
283 | .rd_max = 127 + 2, |
284 | }; |
285 | |
286 | static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco) |
287 | { |
288 | void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; |
289 | void __iomem *sys_osc; |
290 | u32 val; |
291 | |
292 | if (machine_is_realview_pb1176()) |
293 | sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET; |
294 | else |
295 | sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET; |
296 | |
297 | val = readl(sys_osc) & ~0x7ffff; |
298 | val |= vco.v | (vco.r << 9) | (vco.s << 16); |
299 | |
300 | writel(0xa05f, sys_lock); |
301 | writel(val, sys_osc); |
302 | writel(0, sys_lock); |
303 | } |
304 | |
305 | static struct clk oscvco_clk = { |
306 | .params = &realview_oscvco_params, |
307 | .setvco = realview_oscvco_set, |
308 | }; |
309 | |
310 | /* |
311 | * These are fixed clocks. |
312 | */ |
313 | static struct clk ref24_clk = { |
314 | .rate = 24000000, |
315 | }; |
316 | |
317 | static struct clk_lookup lookups[] = { |
318 | { /* UART0 */ |
319 | .dev_id = "dev:uart0", |
320 | .clk = &ref24_clk, |
321 | }, { /* UART1 */ |
322 | .dev_id = "dev:uart1", |
323 | .clk = &ref24_clk, |
324 | }, { /* UART2 */ |
325 | .dev_id = "dev:uart2", |
326 | .clk = &ref24_clk, |
327 | }, { /* UART3 */ |
328 | .dev_id = "fpga:uart3", |
329 | .clk = &ref24_clk, |
330 | }, { /* KMI0 */ |
331 | .dev_id = "fpga:kmi0", |
332 | .clk = &ref24_clk, |
333 | }, { /* KMI1 */ |
334 | .dev_id = "fpga:kmi1", |
335 | .clk = &ref24_clk, |
336 | }, { /* MMC0 */ |
337 | .dev_id = "fpga:mmc0", |
338 | .clk = &ref24_clk, |
339 | }, { /* EB:CLCD */ |
340 | .dev_id = "dev:clcd", |
341 | .clk = &oscvco_clk, |
342 | }, { /* PB:CLCD */ |
343 | .dev_id = "issp:clcd", |
344 | .clk = &oscvco_clk, |
345 | } |
346 | }; |
347 | |
348 | static int __init clk_init(void) |
349 | { |
350 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
351 | return 0; |
352 | } |
353 | arch_initcall(clk_init); |
354 | |
355 | /* |
356 | * CLCD support. |
357 | */ |
358 | #define SYS_CLCD_NLCDIOON (1 << 2) |
359 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) |
360 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) |
361 | #define SYS_CLCD_ID_MASK (0x1f << 8) |
362 | #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) |
363 | #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) |
364 | #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) |
365 | #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) |
366 | #define SYS_CLCD_ID_VGA (0x1f << 8) |
367 | |
368 | static struct clcd_panel vga = { |
369 | .mode = { |
370 | .name = "VGA", |
371 | .refresh = 60, |
372 | .xres = 640, |
373 | .yres = 480, |
374 | .pixclock = 39721, |
375 | .left_margin = 40, |
376 | .right_margin = 24, |
377 | .upper_margin = 32, |
378 | .lower_margin = 11, |
379 | .hsync_len = 96, |
380 | .vsync_len = 2, |
381 | .sync = 0, |
382 | .vmode = FB_VMODE_NONINTERLACED, |
383 | }, |
384 | .width = -1, |
385 | .height = -1, |
386 | .tim2 = TIM2_BCD | TIM2_IPC, |
387 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
388 | .bpp = 16, |
389 | }; |
390 | |
391 | static struct clcd_panel xvga = { |
392 | .mode = { |
393 | .name = "XVGA", |
394 | .refresh = 60, |
395 | .xres = 1024, |
396 | .yres = 768, |
397 | .pixclock = 15748, |
398 | .left_margin = 152, |
399 | .right_margin = 48, |
400 | .upper_margin = 23, |
401 | .lower_margin = 3, |
402 | .hsync_len = 104, |
403 | .vsync_len = 4, |
404 | .sync = 0, |
405 | .vmode = FB_VMODE_NONINTERLACED, |
406 | }, |
407 | .width = -1, |
408 | .height = -1, |
409 | .tim2 = TIM2_BCD | TIM2_IPC, |
410 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
411 | .bpp = 16, |
412 | }; |
413 | |
414 | static struct clcd_panel sanyo_3_8_in = { |
415 | .mode = { |
416 | .name = "Sanyo QVGA", |
417 | .refresh = 116, |
418 | .xres = 320, |
419 | .yres = 240, |
420 | .pixclock = 100000, |
421 | .left_margin = 6, |
422 | .right_margin = 6, |
423 | .upper_margin = 5, |
424 | .lower_margin = 5, |
425 | .hsync_len = 6, |
426 | .vsync_len = 6, |
427 | .sync = 0, |
428 | .vmode = FB_VMODE_NONINTERLACED, |
429 | }, |
430 | .width = -1, |
431 | .height = -1, |
432 | .tim2 = TIM2_BCD, |
433 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
434 | .bpp = 16, |
435 | }; |
436 | |
437 | static struct clcd_panel sanyo_2_5_in = { |
438 | .mode = { |
439 | .name = "Sanyo QVGA Portrait", |
440 | .refresh = 116, |
441 | .xres = 240, |
442 | .yres = 320, |
443 | .pixclock = 100000, |
444 | .left_margin = 20, |
445 | .right_margin = 10, |
446 | .upper_margin = 2, |
447 | .lower_margin = 2, |
448 | .hsync_len = 10, |
449 | .vsync_len = 2, |
450 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
451 | .vmode = FB_VMODE_NONINTERLACED, |
452 | }, |
453 | .width = -1, |
454 | .height = -1, |
455 | .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, |
456 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
457 | .bpp = 16, |
458 | }; |
459 | |
460 | static struct clcd_panel epson_2_2_in = { |
461 | .mode = { |
462 | .name = "Epson QCIF", |
463 | .refresh = 390, |
464 | .xres = 176, |
465 | .yres = 220, |
466 | .pixclock = 62500, |
467 | .left_margin = 3, |
468 | .right_margin = 2, |
469 | .upper_margin = 1, |
470 | .lower_margin = 0, |
471 | .hsync_len = 3, |
472 | .vsync_len = 2, |
473 | .sync = 0, |
474 | .vmode = FB_VMODE_NONINTERLACED, |
475 | }, |
476 | .width = -1, |
477 | .height = -1, |
478 | .tim2 = TIM2_BCD | TIM2_IPC, |
479 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
480 | .bpp = 16, |
481 | }; |
482 | |
483 | /* |
484 | * Detect which LCD panel is connected, and return the appropriate |
485 | * clcd_panel structure. Note: we do not have any information on |
486 | * the required timings for the 8.4in panel, so we presently assume |
487 | * VGA timings. |
488 | */ |
489 | static struct clcd_panel *realview_clcd_panel(void) |
490 | { |
491 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
492 | struct clcd_panel *vga_panel; |
493 | struct clcd_panel *panel; |
494 | u32 val; |
495 | |
496 | if (machine_is_realview_eb()) |
497 | vga_panel = &vga; |
498 | else |
499 | vga_panel = &xvga; |
500 | |
501 | val = readl(sys_clcd) & SYS_CLCD_ID_MASK; |
502 | if (val == SYS_CLCD_ID_SANYO_3_8) |
503 | panel = &sanyo_3_8_in; |
504 | else if (val == SYS_CLCD_ID_SANYO_2_5) |
505 | panel = &sanyo_2_5_in; |
506 | else if (val == SYS_CLCD_ID_EPSON_2_2) |
507 | panel = &epson_2_2_in; |
508 | else if (val == SYS_CLCD_ID_VGA) |
509 | panel = vga_panel; |
510 | else { |
511 | printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", |
512 | val); |
513 | panel = vga_panel; |
514 | } |
515 | |
516 | return panel; |
517 | } |
518 | |
519 | /* |
520 | * Disable all display connectors on the interface module. |
521 | */ |
522 | static void realview_clcd_disable(struct clcd_fb *fb) |
523 | { |
524 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
525 | u32 val; |
526 | |
527 | val = readl(sys_clcd); |
528 | val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
529 | writel(val, sys_clcd); |
530 | } |
531 | |
532 | /* |
533 | * Enable the relevant connector on the interface module. |
534 | */ |
535 | static void realview_clcd_enable(struct clcd_fb *fb) |
536 | { |
537 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
538 | u32 val; |
539 | |
540 | /* |
541 | * Enable the PSUs |
542 | */ |
543 | val = readl(sys_clcd); |
544 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
545 | writel(val, sys_clcd); |
546 | } |
547 | |
548 | static int realview_clcd_setup(struct clcd_fb *fb) |
549 | { |
550 | unsigned long framesize; |
551 | dma_addr_t dma; |
552 | |
553 | if (machine_is_realview_eb()) |
554 | /* VGA, 16bpp */ |
555 | framesize = 640 * 480 * 2; |
556 | else |
557 | /* XVGA, 16bpp */ |
558 | framesize = 1024 * 768 * 2; |
559 | |
560 | fb->panel = realview_clcd_panel(); |
561 | |
562 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, |
563 | &dma, GFP_KERNEL | GFP_DMA); |
564 | if (!fb->fb.screen_base) { |
565 | printk(KERN_ERR "CLCD: unable to map framebuffer\n"); |
566 | return -ENOMEM; |
567 | } |
568 | |
569 | fb->fb.fix.smem_start = dma; |
570 | fb->fb.fix.smem_len = framesize; |
571 | |
572 | return 0; |
573 | } |
574 | |
575 | static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) |
576 | { |
577 | return dma_mmap_writecombine(&fb->dev->dev, vma, |
578 | fb->fb.screen_base, |
579 | fb->fb.fix.smem_start, |
580 | fb->fb.fix.smem_len); |
581 | } |
582 | |
583 | static void realview_clcd_remove(struct clcd_fb *fb) |
584 | { |
585 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, |
586 | fb->fb.screen_base, fb->fb.fix.smem_start); |
587 | } |
588 | |
589 | struct clcd_board clcd_plat_data = { |
590 | .name = "RealView", |
591 | .check = clcdfb_check, |
592 | .decode = clcdfb_decode, |
593 | .disable = realview_clcd_disable, |
594 | .enable = realview_clcd_enable, |
595 | .setup = realview_clcd_setup, |
596 | .mmap = realview_clcd_mmap, |
597 | .remove = realview_clcd_remove, |
598 | }; |
599 | |
600 | #ifdef CONFIG_LEDS |
601 | #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET) |
602 | |
603 | void realview_leds_event(led_event_t ledevt) |
604 | { |
605 | unsigned long flags; |
606 | u32 val; |
607 | u32 led = 1 << smp_processor_id(); |
608 | |
609 | local_irq_save(flags); |
610 | val = readl(VA_LEDS_BASE); |
611 | |
612 | switch (ledevt) { |
613 | case led_idle_start: |
614 | val = val & ~led; |
615 | break; |
616 | |
617 | case led_idle_end: |
618 | val = val | led; |
619 | break; |
620 | |
621 | case led_timer: |
622 | val = val ^ REALVIEW_SYS_LED7; |
623 | break; |
624 | |
625 | case led_halted: |
626 | val = 0; |
627 | break; |
628 | |
629 | default: |
630 | break; |
631 | } |
632 | |
633 | writel(val, VA_LEDS_BASE); |
634 | local_irq_restore(flags); |
635 | } |
636 | #endif /* CONFIG_LEDS */ |
637 | |
638 | /* |
639 | * Where is the timer (VA)? |
640 | */ |
641 | void __iomem *timer0_va_base; |
642 | void __iomem *timer1_va_base; |
643 | void __iomem *timer2_va_base; |
644 | void __iomem *timer3_va_base; |
645 | |
646 | /* |
647 | * How long is the timer interval? |
648 | */ |
649 | #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) |
650 | #if TIMER_INTERVAL >= 0x100000 |
651 | #define TIMER_RELOAD (TIMER_INTERVAL >> 8) |
652 | #define TIMER_DIVISOR (TIMER_CTRL_DIV256) |
653 | #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) |
654 | #elif TIMER_INTERVAL >= 0x10000 |
655 | #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ |
656 | #define TIMER_DIVISOR (TIMER_CTRL_DIV16) |
657 | #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) |
658 | #else |
659 | #define TIMER_RELOAD (TIMER_INTERVAL) |
660 | #define TIMER_DIVISOR (TIMER_CTRL_DIV1) |
661 | #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) |
662 | #endif |
663 | |
664 | static void timer_set_mode(enum clock_event_mode mode, |
665 | struct clock_event_device *clk) |
666 | { |
667 | unsigned long ctrl; |
668 | |
669 | switch(mode) { |
670 | case CLOCK_EVT_MODE_PERIODIC: |
671 | writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD); |
672 | |
673 | ctrl = TIMER_CTRL_PERIODIC; |
674 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; |
675 | break; |
676 | case CLOCK_EVT_MODE_ONESHOT: |
677 | /* period set, and timer enabled in 'next_event' hook */ |
678 | ctrl = TIMER_CTRL_ONESHOT; |
679 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE; |
680 | break; |
681 | case CLOCK_EVT_MODE_UNUSED: |
682 | case CLOCK_EVT_MODE_SHUTDOWN: |
683 | default: |
684 | ctrl = 0; |
685 | } |
686 | |
687 | writel(ctrl, timer0_va_base + TIMER_CTRL); |
688 | } |
689 | |
690 | static int timer_set_next_event(unsigned long evt, |
691 | struct clock_event_device *unused) |
692 | { |
693 | unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL); |
694 | |
695 | writel(evt, timer0_va_base + TIMER_LOAD); |
696 | writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL); |
697 | |
698 | return 0; |
699 | } |
700 | |
701 | static struct clock_event_device timer0_clockevent = { |
702 | .name = "timer0", |
703 | .shift = 32, |
704 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
705 | .set_mode = timer_set_mode, |
706 | .set_next_event = timer_set_next_event, |
707 | .rating = 300, |
708 | .cpumask = cpu_all_mask, |
709 | }; |
710 | |
711 | static void __init realview_clockevents_init(unsigned int timer_irq) |
712 | { |
713 | timer0_clockevent.irq = timer_irq; |
714 | timer0_clockevent.mult = |
715 | div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); |
716 | timer0_clockevent.max_delta_ns = |
717 | clockevent_delta2ns(0xffffffff, &timer0_clockevent); |
718 | timer0_clockevent.min_delta_ns = |
719 | clockevent_delta2ns(0xf, &timer0_clockevent); |
720 | |
721 | clockevents_register_device(&timer0_clockevent); |
722 | } |
723 | |
724 | /* |
725 | * IRQ handler for the timer |
726 | */ |
727 | static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) |
728 | { |
729 | struct clock_event_device *evt = &timer0_clockevent; |
730 | |
731 | /* clear the interrupt */ |
732 | writel(1, timer0_va_base + TIMER_INTCLR); |
733 | |
734 | evt->event_handler(evt); |
735 | |
736 | return IRQ_HANDLED; |
737 | } |
738 | |
739 | static struct irqaction realview_timer_irq = { |
740 | .name = "RealView Timer Tick", |
741 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
742 | .handler = realview_timer_interrupt, |
743 | }; |
744 | |
745 | static cycle_t realview_get_cycles(struct clocksource *cs) |
746 | { |
747 | return ~readl(timer3_va_base + TIMER_VALUE); |
748 | } |
749 | |
750 | static struct clocksource clocksource_realview = { |
751 | .name = "timer3", |
752 | .rating = 200, |
753 | .read = realview_get_cycles, |
754 | .mask = CLOCKSOURCE_MASK(32), |
755 | .shift = 20, |
756 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
757 | }; |
758 | |
759 | static void __init realview_clocksource_init(void) |
760 | { |
761 | /* setup timer 0 as free-running clocksource */ |
762 | writel(0, timer3_va_base + TIMER_CTRL); |
763 | writel(0xffffffff, timer3_va_base + TIMER_LOAD); |
764 | writel(0xffffffff, timer3_va_base + TIMER_VALUE); |
765 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
766 | timer3_va_base + TIMER_CTRL); |
767 | |
768 | clocksource_realview.mult = |
769 | clocksource_khz2mult(1000, clocksource_realview.shift); |
770 | clocksource_register(&clocksource_realview); |
771 | } |
772 | |
773 | /* |
774 | * Set up the clock source and clock events devices |
775 | */ |
776 | void __init realview_timer_init(unsigned int timer_irq) |
777 | { |
778 | u32 val; |
779 | |
780 | /* |
781 | * set clock frequency: |
782 | * REALVIEW_REFCLK is 32KHz |
783 | * REALVIEW_TIMCLK is 1MHz |
784 | */ |
785 | val = readl(__io_address(REALVIEW_SCTL_BASE)); |
786 | writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) | |
787 | (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | |
788 | (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) | |
789 | (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val, |
790 | __io_address(REALVIEW_SCTL_BASE)); |
791 | |
792 | /* |
793 | * Initialise to a known state (all timers off) |
794 | */ |
795 | writel(0, timer0_va_base + TIMER_CTRL); |
796 | writel(0, timer1_va_base + TIMER_CTRL); |
797 | writel(0, timer2_va_base + TIMER_CTRL); |
798 | writel(0, timer3_va_base + TIMER_CTRL); |
799 | |
800 | /* |
801 | * Make irqs happen for the system timer |
802 | */ |
803 | setup_irq(timer_irq, &realview_timer_irq); |
804 | |
805 | realview_clocksource_init(); |
806 | realview_clockevents_init(timer_irq); |
807 | } |
808 | |
809 | /* |
810 | * Setup the memory banks. |
811 | */ |
812 | void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from, |
813 | struct meminfo *meminfo) |
814 | { |
815 | /* |
816 | * Most RealView platforms have 512MB contiguous RAM at 0x70000000. |
817 | * Half of this is mirrored at 0. |
818 | */ |
819 | #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET |
820 | meminfo->bank[0].start = 0x70000000; |
821 | meminfo->bank[0].size = SZ_512M; |
822 | meminfo->nr_banks = 1; |
823 | #else |
824 | meminfo->bank[0].start = 0; |
825 | meminfo->bank[0].size = SZ_256M; |
826 | meminfo->nr_banks = 1; |
827 | #endif |
828 | } |
829 |
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