Root/drivers/usb/gadget/jz4740_udc.c

Source at commit be977234bfb4a6dca8a39e7c52165e4cd536ad71 created 9 years 1 month ago.
By Lars-Peter Clausen, jz4740: Fix compile error
1/*
2 * linux/drivers/usb/gadget/jz4740_udc.c
3 *
4 * Ingenic JZ4740 on-chip high speed USB device controller
5 *
6 * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15/*
16 * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
17 *
18 * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
19 * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/list.h>
31#include <linux/interrupt.h>
32#include <linux/proc_fs.h>
33#include <linux/usb.h>
34#include <linux/usb/gadget.h>
35#include <linux/clk.h>
36
37#include <asm/byteorder.h>
38#include <asm/io.h>
39#include <asm/irq.h>
40#include <asm/system.h>
41#include <asm/mach-jz4740/clock.h>
42
43#include "jz4740_udc.h"
44
45#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
46#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
47#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
48#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
49#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
50#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
51#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
52#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
53#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
54#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
55#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
56
57#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
58#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
59#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
60#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
61
62#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
63#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
64#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
65#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
66
67#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
68
69#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
70#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
71
72#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
73#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
74#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
75#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
76#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
77#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
78#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
79
80/* Power register bit masks */
81#define USB_POWER_SUSPENDM 0x01
82#define USB_POWER_RESUME 0x04
83#define USB_POWER_HSMODE 0x10
84#define USB_POWER_HSENAB 0x20
85#define USB_POWER_SOFTCONN 0x40
86
87/* Interrupt register bit masks */
88#define USB_INTR_SUSPEND 0x01
89#define USB_INTR_RESUME 0x02
90#define USB_INTR_RESET 0x04
91
92#define USB_INTR_EP0 0x0001
93#define USB_INTR_INEP1 0x0002
94#define USB_INTR_INEP2 0x0004
95#define USB_INTR_OUTEP1 0x0002
96
97/* CSR0 bit masks */
98#define USB_CSR0_OUTPKTRDY 0x01
99#define USB_CSR0_INPKTRDY 0x02
100#define USB_CSR0_SENTSTALL 0x04
101#define USB_CSR0_DATAEND 0x08
102#define USB_CSR0_SETUPEND 0x10
103#define USB_CSR0_SENDSTALL 0x20
104#define USB_CSR0_SVDOUTPKTRDY 0x40
105#define USB_CSR0_SVDSETUPEND 0x80
106
107/* Endpoint CSR register bits */
108#define USB_INCSRH_AUTOSET 0x80
109#define USB_INCSRH_ISO 0x40
110#define USB_INCSRH_MODE 0x20
111#define USB_INCSRH_DMAREQENAB 0x10
112#define USB_INCSRH_DMAREQMODE 0x04
113#define USB_INCSR_CDT 0x40
114#define USB_INCSR_SENTSTALL 0x20
115#define USB_INCSR_SENDSTALL 0x10
116#define USB_INCSR_FF 0x08
117#define USB_INCSR_UNDERRUN 0x04
118#define USB_INCSR_FFNOTEMPT 0x02
119#define USB_INCSR_INPKTRDY 0x01
120
121#define USB_OUTCSRH_AUTOCLR 0x80
122#define USB_OUTCSRH_ISO 0x40
123#define USB_OUTCSRH_DMAREQENAB 0x20
124#define USB_OUTCSRH_DNYT 0x10
125#define USB_OUTCSRH_DMAREQMODE 0x08
126#define USB_OUTCSR_CDT 0x80
127#define USB_OUTCSR_SENTSTALL 0x40
128#define USB_OUTCSR_SENDSTALL 0x20
129#define USB_OUTCSR_FF 0x10
130#define USB_OUTCSR_DATAERR 0x08
131#define USB_OUTCSR_OVERRUN 0x04
132#define USB_OUTCSR_FFFULL 0x02
133#define USB_OUTCSR_OUTPKTRDY 0x01
134
135/* DMA control bits */
136#define USB_CNTL_ENA 0x01
137#define USB_CNTL_DIR_IN 0x02
138#define USB_CNTL_MODE_1 0x04
139#define USB_CNTL_INTR_EN 0x08
140#define USB_CNTL_EP(n) ((n) << 4)
141#define USB_CNTL_BURST_0 (0 << 9)
142#define USB_CNTL_BURST_4 (1 << 9)
143#define USB_CNTL_BURST_8 (2 << 9)
144#define USB_CNTL_BURST_16 (3 << 9)
145
146
147#ifndef DEBUG
148# define DEBUG(fmt,args...) do {} while(0)
149#endif
150#ifndef DEBUG_EP0
151# define NO_STATES
152# define DEBUG_EP0(fmt,args...) do {} while(0)
153#endif
154#ifndef DEBUG_SETUP
155# define DEBUG_SETUP(fmt,args...) do {} while(0)
156#endif
157
158static struct jz4740_udc jz4740_udc_controller;
159
160/*
161 * Local declarations.
162 */
163static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
164static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
165
166static void done(struct jz4740_ep *ep, struct jz4740_request *req,
167         int status);
168static void pio_irq_enable(struct jz4740_ep *ep);
169static void pio_irq_disable(struct jz4740_ep *ep);
170static void stop_activity(struct jz4740_udc *dev,
171              struct usb_gadget_driver *driver);
172static void nuke(struct jz4740_ep *ep, int status);
173static void flush(struct jz4740_ep *ep);
174static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
175
176/*-------------------------------------------------------------------------*/
177
178/* inline functions of register read/write/set/clear */
179
180static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
181{
182    return readb(udc->base + reg);
183}
184
185static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
186{
187    return readw(udc->base + reg);
188}
189
190static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
191{
192    return readl(udc->base + reg);
193}
194
195static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
196{
197    writeb(val, udc->base + reg);
198}
199
200static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
201{
202    writew(val, udc->base + reg);
203}
204
205static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
206{
207    writel(val, udc->base + reg);
208}
209
210static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
211{
212    usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
213}
214
215static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
216{
217    usb_writew(udc, reg, usb_readw(udc, reg) | mask);
218}
219
220static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
221{
222    usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
223}
224
225static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
226{
227    usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
228}
229
230/*-------------------------------------------------------------------------*/
231
232static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
233{
234    usb_writeb(udc, JZ_REG_UDC_INDEX, index);
235}
236
237static inline void jz_udc_select_ep(struct jz4740_ep *ep)
238{
239    jz_udc_set_index(ep->dev, ep_index(ep));
240}
241
242static inline int write_packet(struct jz4740_ep *ep,
243                   struct jz4740_request *req, unsigned int count)
244{
245    uint8_t *buf;
246    unsigned int length;
247    void __iomem *fifo = ep->dev->base + ep->fifo;
248
249    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
250
251    buf = req->req.buf + req->req.actual;
252
253    length = req->req.length - req->req.actual;
254    if (length > count)
255        length = count;
256    req->req.actual += length;
257
258    DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
259
260    memcpy_toio(fifo, buf, length);
261
262    return length;
263}
264
265static int read_packet(struct jz4740_ep *ep,
266                  struct jz4740_request *req, unsigned int count)
267{
268    uint8_t *buf;
269    unsigned int length;
270    void __iomem *fifo = ep->dev->base + ep->fifo;
271    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
272
273    buf = req->req.buf + req->req.actual;
274
275    length = req->req.length - req->req.actual;
276    if (length > count)
277        length = count;
278    req->req.actual += length;
279
280    memcpy_fromio(buf, fifo, length);
281
282    return length;
283}
284
285/*-------------------------------------------------------------------------*/
286
287/*
288 * udc_disable - disable USB device controller
289 */
290static void udc_disable(struct jz4740_udc *dev)
291{
292    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
293
294    udc_set_address(dev, 0);
295
296    /* Disable interrupts */
297    usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
298    usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
299    usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
300
301    /* Disable DMA */
302    usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
303    usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
304
305    /* Disconnect from usb */
306    usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
307
308    /* Disable the USB PHY */
309    clk_disable(dev->clk);
310
311    dev->ep0state = WAIT_FOR_SETUP;
312    dev->gadget.speed = USB_SPEED_UNKNOWN;
313
314    return;
315}
316
317/*
318 * udc_reinit - initialize software state
319 */
320static void udc_reinit(struct jz4740_udc *dev)
321{
322    int i;
323    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
324
325    /* device/ep0 records init */
326    INIT_LIST_HEAD(&dev->gadget.ep_list);
327    INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
328    dev->ep0state = WAIT_FOR_SETUP;
329
330    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
331        struct jz4740_ep *ep = &dev->ep[i];
332
333        if (i != 0)
334            list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
335
336        INIT_LIST_HEAD(&ep->queue);
337        ep->desc = 0;
338        ep->stopped = 0;
339    }
340}
341
342/* until it's enabled, this UDC should be completely invisible
343 * to any USB host.
344 */
345static void udc_enable(struct jz4740_udc *dev)
346{
347    int i;
348    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
349
350    /* UDC state is incorrect - Added by River */
351    if (dev->state != UDC_STATE_ENABLE) {
352        return;
353    }
354
355    dev->gadget.speed = USB_SPEED_UNKNOWN;
356
357    /* Flush FIFO for each */
358    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
359        struct jz4740_ep *ep = &dev->ep[i];
360
361        jz_udc_select_ep(ep);
362        flush(ep);
363    }
364
365    /* Set this bit to allow the UDC entering low-power mode when
366     * there are no actions on the USB bus.
367     * UDC still works during this bit was set.
368     */
369    jz4740_clock_udc_enable_auto_suspend();
370
371    /* Enable the USB PHY */
372    clk_enable(dev->clk);
373
374    /* Disable interrupts */
375/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
376    usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
377    usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
378
379    /* Enable interrupts */
380    usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
381    usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
382    /* Don't enable rest of the interrupts */
383    /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
384       usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
385
386    /* Enable SUSPEND */
387    /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
388
389    /* Enable HS Mode */
390    usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
391
392    /* Let host detect UDC:
393     * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
394     * transistor on and pull the USBDP pin HIGH.
395     */
396    usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
397
398    return;
399}
400
401/*-------------------------------------------------------------------------*/
402
403/* keeping it simple:
404 * - one bus driver, initted first;
405 * - one function driver, initted second
406 */
407
408/*
409 * Register entry point for the peripheral controller driver.
410 */
411
412int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
413        int (*bind)(struct usb_gadget *))
414{
415    struct jz4740_udc *dev = &jz4740_udc_controller;
416    int retval;
417
418    if (!driver || !bind)
419        return -EINVAL;
420
421    if (!dev)
422        return -ENODEV;
423
424    if (dev->driver)
425        return -EBUSY;
426
427    /* hook up the driver */
428    dev->driver = driver;
429    dev->gadget.dev.driver = &driver->driver;
430
431    retval = bind(&dev->gadget);
432    if (retval) {
433        DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
434                    driver->driver.name, retval);
435        dev->driver = 0;
436        return retval;
437    }
438
439    /* then enable host detection and ep0; and we're ready
440     * for set_configuration as well as eventual disconnect.
441     */
442    udc_enable(dev);
443
444    DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
445          driver->driver.name);
446
447    return 0;
448}
449EXPORT_SYMBOL(usb_gadget_probe_driver);
450
451static void stop_activity(struct jz4740_udc *dev,
452              struct usb_gadget_driver *driver)
453{
454    int i;
455
456    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
457
458    /* don't disconnect drivers more than once */
459    if (dev->gadget.speed == USB_SPEED_UNKNOWN)
460        driver = 0;
461    dev->gadget.speed = USB_SPEED_UNKNOWN;
462
463    /* prevent new request submissions, kill any outstanding requests */
464    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
465        struct jz4740_ep *ep = &dev->ep[i];
466
467        ep->stopped = 1;
468
469        jz_udc_select_ep(ep);
470        nuke(ep, -ESHUTDOWN);
471    }
472
473    /* report disconnect; the driver is already quiesced */
474    if (driver) {
475        spin_unlock(&dev->lock);
476        driver->disconnect(&dev->gadget);
477        spin_lock(&dev->lock);
478    }
479
480    /* re-init driver-visible data structures */
481    udc_reinit(dev);
482}
483
484
485/*
486 * Unregister entry point for the peripheral controller driver.
487 */
488int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
489{
490    struct jz4740_udc *dev = &jz4740_udc_controller;
491    unsigned long flags;
492    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
493
494    if (!dev)
495        return -ENODEV;
496    if (!driver || driver != dev->driver)
497        return -EINVAL;
498    if (!driver->unbind)
499        return -EBUSY;
500
501    spin_lock_irqsave(&dev->lock, flags);
502    dev->driver = 0;
503    stop_activity(dev, driver);
504    spin_unlock_irqrestore(&dev->lock, flags);
505
506    driver->unbind(&dev->gadget);
507
508    udc_disable(dev);
509
510    DEBUG("unregistered driver '%s'\n", driver->driver.name);
511
512    return 0;
513}
514
515EXPORT_SYMBOL(usb_gadget_unregister_driver);
516
517/*-------------------------------------------------------------------------*/
518
519/** Write request to FIFO (max write == maxp size)
520 * Return: 0 = still running, 1 = completed, negative = errno
521 * NOTE: INDEX register must be set for EP
522 */
523static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
524{
525    struct jz4740_udc *dev = ep->dev;
526    uint32_t max, csr;
527
528    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
529    max = le16_to_cpu(ep->desc->wMaxPacketSize);
530
531    csr = usb_readb(dev, ep->csr);
532
533    if (!(csr & USB_INCSR_FFNOTEMPT)) {
534        unsigned count;
535        int is_last, is_short;
536
537        count = write_packet(ep, req, max);
538        usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
539
540        /* last packet is usually short (or a zlp) */
541        if (unlikely(count != max))
542            is_last = is_short = 1;
543        else {
544            if (likely(req->req.length != req->req.actual)
545                || req->req.zero)
546                is_last = 0;
547            else
548                is_last = 1;
549            /* interrupt/iso maxpacket may not fill the fifo */
550            is_short = unlikely(max < ep_maxpacket(ep));
551        }
552
553        DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
554              ep->ep.name, count,
555              is_last ? "/L" : "", is_short ? "/S" : "",
556              req->req.length - req->req.actual, req);
557
558        /* requests complete when all IN data is in the FIFO */
559        if (is_last) {
560            done(ep, req, 0);
561            if (list_empty(&ep->queue)) {
562                pio_irq_disable(ep);
563            }
564            return 1;
565        }
566    } else {
567        DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
568    }
569
570    return 0;
571}
572
573/** Read to request from FIFO (max read == bytes in fifo)
574 * Return: 0 = still running, 1 = completed, negative = errno
575 * NOTE: INDEX register must be set for EP
576 */
577static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
578{
579    struct jz4740_udc *dev = ep->dev;
580    uint32_t csr;
581    unsigned count, is_short;
582
583    /* make sure there's a packet in the FIFO. */
584    csr = usb_readb(dev, ep->csr);
585    if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
586        DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
587        return -EINVAL;
588    }
589
590    /* read all bytes from this packet */
591    count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
592
593    is_short = (count < ep->ep.maxpacket);
594
595    count = read_packet(ep, req, count);
596
597    DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
598          ep->ep.name, csr, count,
599          is_short ? "/S" : "", req, req->req.actual, req->req.length);
600
601    /* Clear OutPktRdy */
602    usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
603
604    /* completion */
605    if (is_short || req->req.actual == req->req.length) {
606        done(ep, req, 0);
607
608        if (list_empty(&ep->queue))
609            pio_irq_disable(ep);
610        return 1;
611    }
612
613    /* finished that packet. the next one may be waiting... */
614    return 0;
615}
616
617/*
618 * done - retire a request; caller blocked irqs
619 * INDEX register is preserved to keep same
620 */
621static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
622{
623    unsigned int stopped = ep->stopped;
624    uint32_t index;
625
626    DEBUG("%s, %p\n", __FUNCTION__, ep);
627    list_del_init(&req->queue);
628
629    if (likely(req->req.status == -EINPROGRESS))
630        req->req.status = status;
631    else
632        status = req->req.status;
633
634    if (status && status != -ESHUTDOWN)
635        DEBUG("complete %s req %p stat %d len %u/%u\n",
636              ep->ep.name, &req->req, status,
637              req->req.actual, req->req.length);
638
639    /* don't modify queue heads during completion callback */
640    ep->stopped = 1;
641    /* Read current index (completion may modify it) */
642    index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
643    spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
644
645    req->req.complete(&ep->ep, &req->req);
646
647    spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
648    /* Restore index */
649    jz_udc_set_index(ep->dev, index);
650    ep->stopped = stopped;
651}
652
653static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep)
654{
655    if (ep_is_in(ep))
656        return JZ_REG_UDC_INTRINE;
657    else
658        return JZ_REG_UDC_INTROUTE;
659}
660
661/** Enable EP interrupt */
662static void pio_irq_enable(struct jz4740_ep *ep)
663{
664    DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
665
666    usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
667}
668
669/** Disable EP interrupt */
670static void pio_irq_disable(struct jz4740_ep *ep)
671{
672    DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
673
674    usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
675}
676
677/*
678 * nuke - dequeue ALL requests
679 */
680static void nuke(struct jz4740_ep *ep, int status)
681{
682    struct jz4740_request *req;
683
684    DEBUG("%s, %p\n", __FUNCTION__, ep);
685
686    /* Flush FIFO */
687    flush(ep);
688
689    /* called with irqs blocked */
690    while (!list_empty(&ep->queue)) {
691        req = list_entry(ep->queue.next, struct jz4740_request, queue);
692        done(ep, req, status);
693    }
694
695    /* Disable IRQ if EP is enabled (has descriptor) */
696    if (ep->desc)
697        pio_irq_disable(ep);
698}
699
700/** Flush EP FIFO
701 * NOTE: INDEX register must be set before this call
702 */
703static void flush(struct jz4740_ep *ep)
704{
705    DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
706
707    switch (ep->type) {
708    case ep_bulk_in:
709    case ep_interrupt:
710        usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
711        break;
712    case ep_bulk_out:
713        usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
714        break;
715    case ep_control:
716        break;
717    }
718}
719
720/**
721 * jz4740_in_epn - handle IN interrupt
722 */
723static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
724{
725    uint32_t csr;
726    struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
727    struct jz4740_request *req;
728    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
729
730    jz_udc_select_ep(ep);
731
732    csr = usb_readb(dev, ep->csr);
733    DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
734
735    if (csr & USB_INCSR_SENTSTALL) {
736        DEBUG("USB_INCSR_SENTSTALL\n");
737        usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
738        return;
739    }
740
741    if (!ep->desc) {
742        DEBUG("%s: NO EP DESC\n", __FUNCTION__);
743        return;
744    }
745
746    if (!list_empty(&ep->queue)) {
747        req = list_first_entry(&ep->queue, struct jz4740_request, queue);
748        write_fifo(ep, req);
749    }
750}
751
752/*
753 * Bulk OUT (recv)
754 */
755static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
756{
757    struct jz4740_ep *ep = &dev->ep[ep_idx];
758    struct jz4740_request *req;
759
760    DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
761
762    jz_udc_select_ep(ep);
763    if (ep->desc) {
764        uint32_t csr;
765
766        while ((csr = usb_readb(dev, ep->csr)) &
767               (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
768            DEBUG("%s: %x\n", __FUNCTION__, csr);
769
770            if (csr & USB_OUTCSR_SENTSTALL) {
771                DEBUG("%s: stall sent, flush fifo\n",
772                      __FUNCTION__);
773                /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
774                flush(ep);
775            } else if (csr & USB_OUTCSR_OUTPKTRDY) {
776                if (list_empty(&ep->queue))
777                    req = 0;
778                else
779                    req =
780                        list_entry(ep->queue.next,
781                               struct jz4740_request,
782                               queue);
783
784                if (!req) {
785                    DEBUG("%s: NULL REQ %d\n",
786                          __FUNCTION__, ep_idx);
787                    break;
788                } else {
789                    read_fifo(ep, req);
790                }
791            }
792        }
793    } else {
794        /* Throw packet away.. */
795        DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
796        flush(ep);
797    }
798}
799
800/** Halt specific EP
801 * Return 0 if success
802 * NOTE: Sets INDEX register to EP !
803 */
804static int jz4740_set_halt(struct usb_ep *_ep, int value)
805{
806    struct jz4740_udc *dev;
807    struct jz4740_ep *ep;
808    unsigned long flags;
809
810    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
811
812    ep = container_of(_ep, struct jz4740_ep, ep);
813    if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
814        DEBUG("%s, bad ep\n", __FUNCTION__);
815        return -EINVAL;
816    }
817
818    dev = ep->dev;
819
820    spin_lock_irqsave(&dev->lock, flags);
821
822    jz_udc_select_ep(ep);
823
824    DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
825
826    if (ep_index(ep) == 0) {
827        /* EP0 */
828        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
829    } else if (ep_is_in(ep)) {
830        uint32_t csr = usb_readb(dev, ep->csr);
831        if (value && ((csr & USB_INCSR_FFNOTEMPT)
832                  || !list_empty(&ep->queue))) {
833            /*
834             * Attempts to halt IN endpoints will fail (returning -EAGAIN)
835             * if any transfer requests are still queued, or if the controller
836             * FIFO still holds bytes that the host hasn¬ít collected.
837             */
838            spin_unlock_irqrestore(&dev->lock, flags);
839            DEBUG
840                ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
841                 (csr & USB_INCSR_FFNOTEMPT),
842                 !list_empty(&ep->queue));
843            return -EAGAIN;
844        }
845        flush(ep);
846        if (value) {
847            usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
848        } else {
849            usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
850            usb_setb(dev, ep->csr, USB_INCSR_CDT);
851        }
852    } else {
853
854        flush(ep);
855        if (value) {
856            usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
857        } else {
858            usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
859            usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
860        }
861    }
862
863    ep->stopped = value;
864
865    spin_unlock_irqrestore(&dev->lock, flags);
866
867    DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
868
869    return 0;
870}
871
872
873static int jz4740_ep_enable(struct usb_ep *_ep,
874                const struct usb_endpoint_descriptor *desc)
875{
876    struct jz4740_ep *ep;
877    struct jz4740_udc *dev;
878    unsigned long flags;
879    uint32_t max, csrh = 0;
880
881    DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
882
883    if (!_ep || !desc)
884        return -EINVAL;
885
886    ep = container_of(_ep, struct jz4740_ep, ep);
887    if (ep->desc || ep->type == ep_control
888        || desc->bDescriptorType != USB_DT_ENDPOINT
889        || ep->bEndpointAddress != desc->bEndpointAddress) {
890        DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
891        return -EINVAL;
892    }
893
894    /* xfer types must match, except that interrupt ~= bulk */
895    if (ep->bmAttributes != desc->bmAttributes
896        && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
897        && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
898        DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
899        return -EINVAL;
900    }
901
902    dev = ep->dev;
903    if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
904        DEBUG("%s, bogus device state\n", __FUNCTION__);
905        return -ESHUTDOWN;
906    }
907
908    max = le16_to_cpu(desc->wMaxPacketSize);
909
910    spin_lock_irqsave(&ep->dev->lock, flags);
911
912    /* Configure the endpoint */
913    jz_udc_select_ep(ep);
914    if (ep_is_in(ep)) {
915        usb_writew(dev, JZ_REG_UDC_INMAXP, max);
916        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
917        case USB_ENDPOINT_XFER_BULK:
918        case USB_ENDPOINT_XFER_INT:
919            csrh &= ~USB_INCSRH_ISO;
920            break;
921        case USB_ENDPOINT_XFER_ISOC:
922            csrh |= USB_INCSRH_ISO;
923            break;
924        }
925        usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
926    }
927    else {
928        usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
929        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
930        case USB_ENDPOINT_XFER_BULK:
931             csrh &= ~USB_OUTCSRH_ISO;
932            break;
933        case USB_ENDPOINT_XFER_INT:
934            csrh &= ~USB_OUTCSRH_ISO;
935            csrh |= USB_OUTCSRH_DNYT;
936            break;
937        case USB_ENDPOINT_XFER_ISOC:
938            csrh |= USB_OUTCSRH_ISO;
939            break;
940        }
941        usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
942    }
943
944
945    ep->stopped = 0;
946    ep->desc = desc;
947    ep->ep.maxpacket = max;
948
949    spin_unlock_irqrestore(&ep->dev->lock, flags);
950
951    /* Reset halt state (does flush) */
952    jz4740_set_halt(_ep, 0);
953
954    DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
955
956    return 0;
957}
958
959/** Disable EP
960 * NOTE: Sets INDEX register
961 */
962static int jz4740_ep_disable(struct usb_ep *_ep)
963{
964    struct jz4740_ep *ep;
965    unsigned long flags;
966
967    DEBUG("%s, %p\n", __FUNCTION__, _ep);
968
969    ep = container_of(_ep, struct jz4740_ep, ep);
970    if (!_ep || !ep->desc) {
971        DEBUG("%s, %s not enabled\n", __FUNCTION__,
972              _ep ? ep->ep.name : NULL);
973        return -EINVAL;
974    }
975
976    spin_lock_irqsave(&ep->dev->lock, flags);
977
978    jz_udc_select_ep(ep);
979
980    /* Nuke all pending requests (does flush) */
981    nuke(ep, -ESHUTDOWN);
982
983    /* Disable ep IRQ */
984    pio_irq_disable(ep);
985
986    ep->desc = 0;
987    ep->stopped = 1;
988
989    spin_unlock_irqrestore(&ep->dev->lock, flags);
990
991    DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
992    return 0;
993}
994
995static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
996{
997    struct jz4740_request *req;
998
999    req = kzalloc(sizeof(*req), gfp_flags);
1000    if (!req)
1001        return NULL;
1002
1003    INIT_LIST_HEAD(&req->queue);
1004
1005    return &req->req;
1006}
1007
1008static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1009{
1010    struct jz4740_request *req;
1011
1012    req = container_of(_req, struct jz4740_request, req);
1013    WARN_ON(!list_empty(&req->queue));
1014
1015    kfree(req);
1016}
1017
1018/*--------------------------------------------------------------------*/
1019
1020/** Queue one request
1021 * Kickstart transfer if needed
1022 * NOTE: Sets INDEX register
1023 */
1024static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1025            gfp_t gfp_flags)
1026{
1027    struct jz4740_request *req;
1028    struct jz4740_ep *ep;
1029    struct jz4740_udc *dev;
1030
1031    DEBUG("%s, %p\n", __FUNCTION__, _ep);
1032
1033    req = container_of(_req, struct jz4740_request, req);
1034    if (unlikely
1035        (!_req || !_req->complete || !_req->buf
1036         || !list_empty(&req->queue))) {
1037        DEBUG("%s, bad params\n", __FUNCTION__);
1038        return -EINVAL;
1039    }
1040
1041    ep = container_of(_ep, struct jz4740_ep, ep);
1042    if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1043        DEBUG("%s, bad ep\n", __FUNCTION__);
1044        return -EINVAL;
1045    }
1046
1047    dev = ep->dev;
1048    if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1049        DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1050        return -ESHUTDOWN;
1051    }
1052
1053    DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1054          _req->buf);
1055
1056    spin_lock_irqsave(&dev->lock, dev->lock_flags);
1057
1058    _req->status = -EINPROGRESS;
1059    _req->actual = 0;
1060
1061    /* kickstart this i/o queue? */
1062    DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1063          ep->stopped);
1064    if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1065        uint32_t csr;
1066
1067        if (unlikely(ep_index(ep) == 0)) {
1068            /* EP0 */
1069            list_add_tail(&req->queue, &ep->queue);
1070            jz4740_ep0_kick(dev, ep);
1071            req = 0;
1072        }
1073        else if (ep_is_in(ep)) {
1074            /* EP1 & EP2 */
1075            jz_udc_select_ep(ep);
1076            csr = usb_readb(dev, ep->csr);
1077            pio_irq_enable(ep);
1078            if (!(csr & USB_INCSR_FFNOTEMPT)) {
1079                if (write_fifo(ep, req) == 1)
1080                    req = 0;
1081            }
1082        } else {
1083            /* EP1 */
1084            jz_udc_select_ep(ep);
1085            csr = usb_readb(dev, ep->csr);
1086            pio_irq_enable(ep);
1087            if (csr & USB_OUTCSR_OUTPKTRDY) {
1088                if (read_fifo(ep, req) == 1)
1089                    req = 0;
1090            }
1091        }
1092    }
1093
1094    /* pio or dma irq handler advances the queue. */
1095    if (likely(req != 0))
1096        list_add_tail(&req->queue, &ep->queue);
1097
1098    spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1099
1100    return 0;
1101}
1102
1103/* dequeue JUST ONE request */
1104static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1105{
1106    struct jz4740_ep *ep;
1107    struct jz4740_request *req;
1108    unsigned long flags;
1109
1110    DEBUG("%s, %p\n", __FUNCTION__, _ep);
1111
1112    ep = container_of(_ep, struct jz4740_ep, ep);
1113    if (!_ep || ep->type == ep_control)
1114        return -EINVAL;
1115
1116    spin_lock_irqsave(&ep->dev->lock, flags);
1117
1118    /* make sure it's actually queued on this endpoint */
1119    list_for_each_entry(req, &ep->queue, queue) {
1120        if (&req->req == _req)
1121            break;
1122    }
1123    if (&req->req != _req) {
1124        spin_unlock_irqrestore(&ep->dev->lock, flags);
1125        return -EINVAL;
1126    }
1127    done(ep, req, -ECONNRESET);
1128
1129    spin_unlock_irqrestore(&ep->dev->lock, flags);
1130    return 0;
1131}
1132
1133/** Return bytes in EP FIFO
1134 * NOTE: Sets INDEX register to EP
1135 */
1136static int jz4740_fifo_status(struct usb_ep *_ep)
1137{
1138    uint32_t csr;
1139    int count = 0;
1140    struct jz4740_ep *ep;
1141    unsigned long flags;
1142
1143    ep = container_of(_ep, struct jz4740_ep, ep);
1144    if (!_ep) {
1145        DEBUG("%s, bad ep\n", __FUNCTION__);
1146        return -ENODEV;
1147    }
1148
1149    DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1150
1151    /* LPD can't report unclaimed bytes from IN fifos */
1152    if (ep_is_in(ep))
1153        return -EOPNOTSUPP;
1154
1155    spin_lock_irqsave(&ep->dev->lock, flags);
1156    jz_udc_select_ep(ep);
1157
1158    csr = usb_readb(ep->dev, ep->csr);
1159    if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1160        csr & 0x1) {
1161        count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1162    }
1163
1164    spin_unlock_irqrestore(&ep->dev->lock, flags);
1165
1166    return count;
1167}
1168
1169/** Flush EP FIFO
1170 * NOTE: Sets INDEX register to EP
1171 */
1172static void jz4740_fifo_flush(struct usb_ep *_ep)
1173{
1174    struct jz4740_ep *ep;
1175    unsigned long flags;
1176
1177    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1178
1179    ep = container_of(_ep, struct jz4740_ep, ep);
1180    if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1181        DEBUG("%s, bad ep\n", __FUNCTION__);
1182        return;
1183    }
1184
1185    spin_lock_irqsave(&ep->dev->lock, flags);
1186
1187    jz_udc_select_ep(ep);
1188    flush(ep);
1189
1190    spin_unlock_irqrestore(&ep->dev->lock, flags);
1191}
1192
1193/****************************************************************/
1194/* End Point 0 related functions */
1195/****************************************************************/
1196
1197/* return: 0 = still running, 1 = completed, negative = errno */
1198static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1199{
1200    uint32_t max;
1201    unsigned count;
1202    int is_last;
1203
1204    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1205    max = ep_maxpacket(ep);
1206
1207    count = write_packet(ep, req, max);
1208
1209    /* last packet is usually short (or a zlp) */
1210    if (unlikely(count != max))
1211        is_last = 1;
1212    else {
1213        if (likely(req->req.length != req->req.actual) || req->req.zero)
1214            is_last = 0;
1215        else
1216            is_last = 1;
1217    }
1218
1219    DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1220          ep->ep.name, count,
1221          is_last ? "/L" : "", req->req.length - req->req.actual, req);
1222
1223    /* requests complete when all IN data is in the FIFO */
1224    if (is_last) {
1225        done(ep, req, 0);
1226        return 1;
1227    }
1228
1229    return 0;
1230}
1231
1232static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1233                       unsigned char *cp, int max)
1234{
1235    int bytes;
1236    int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1237
1238    if (count > max)
1239        count = max;
1240    bytes = count;
1241    while (count--)
1242        *cp++ = usb_readb(ep->dev, ep->fifo);
1243
1244    return bytes;
1245}
1246
1247static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1248                     unsigned char *cp, int count)
1249{
1250    DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1251    while (count--)
1252        usb_writeb(ep->dev, ep->fifo, *cp++);
1253}
1254
1255static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1256{
1257    struct jz4740_udc *dev = ep->dev;
1258    uint32_t csr;
1259    uint8_t *buf;
1260    unsigned bufferspace, count, is_short;
1261
1262    DEBUG_EP0("%s\n", __FUNCTION__);
1263
1264    csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1265    if (!(csr & USB_CSR0_OUTPKTRDY))
1266        return 0;
1267
1268    buf = req->req.buf + req->req.actual;
1269    prefetchw(buf);
1270    bufferspace = req->req.length - req->req.actual;
1271
1272    /* read all bytes from this packet */
1273    if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1274        count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1275        req->req.actual += min(count, bufferspace);
1276    } else /* zlp */
1277        count = 0;
1278
1279    is_short = (count < ep->ep.maxpacket);
1280    DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1281          ep->ep.name, csr, count,
1282          is_short ? "/S" : "", req, req->req.actual, req->req.length);
1283
1284    while (likely(count-- != 0)) {
1285        uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1286
1287        if (unlikely(bufferspace == 0)) {
1288            /* this happens when the driver's buffer
1289             * is smaller than what the host sent.
1290             * discard the extra data.
1291             */
1292            if (req->req.status != -EOVERFLOW)
1293                DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1294                      count);
1295            req->req.status = -EOVERFLOW;
1296        } else {
1297            *buf++ = byte;
1298            bufferspace--;
1299        }
1300    }
1301
1302    /* completion */
1303    if (is_short || req->req.actual == req->req.length) {
1304        done(ep, req, 0);
1305        return 1;
1306    }
1307
1308    /* finished that packet. the next one may be waiting... */
1309    return 0;
1310}
1311
1312/**
1313 * udc_set_address - set the USB address for this device
1314 * @address:
1315 *
1316 * Called from control endpoint function after it decodes a set address setup packet.
1317 */
1318static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1319{
1320    DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1321
1322    usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1323}
1324
1325/*
1326 * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1327 * - if error
1328 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1329 * - else
1330 * set USB_CSR0_SVDOUTPKTRDY bit
1331                 if last set USB_CSR0_DATAEND bit
1332 */
1333static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1334{
1335    struct jz4740_request *req;
1336    struct jz4740_ep *ep = &dev->ep[0];
1337    int ret;
1338
1339    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1340
1341    if (list_empty(&ep->queue))
1342        req = 0;
1343    else
1344        req = list_entry(ep->queue.next, struct jz4740_request, queue);
1345
1346    if (req) {
1347        if (req->req.length == 0) {
1348            DEBUG_EP0("ZERO LENGTH OUT!\n");
1349            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1350            dev->ep0state = WAIT_FOR_SETUP;
1351            return;
1352        } else if (kickstart) {
1353            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1354            return;
1355        }
1356        ret = read_fifo_ep0(ep, req);
1357        if (ret) {
1358            /* Done! */
1359            DEBUG_EP0("%s: finished, waiting for status\n",
1360                  __FUNCTION__);
1361            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1362            dev->ep0state = WAIT_FOR_SETUP;
1363        } else {
1364            /* Not done yet.. */
1365            DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1366            usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1367        }
1368    } else {
1369        DEBUG_EP0("NO REQ??!\n");
1370    }
1371}
1372
1373/*
1374 * DATA_STATE_XMIT
1375 */
1376static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1377{
1378    struct jz4740_request *req;
1379    struct jz4740_ep *ep = &dev->ep[0];
1380    int ret, need_zlp = 0;
1381
1382    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1383
1384    if (list_empty(&ep->queue))
1385        req = 0;
1386    else
1387        req = list_entry(ep->queue.next, struct jz4740_request, queue);
1388
1389    if (!req) {
1390        DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1391        return 0;
1392    }
1393
1394    if (req->req.length == 0) {
1395        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1396        dev->ep0state = WAIT_FOR_SETUP;
1397        return 1;
1398    }
1399
1400    if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1401        /* Next write will end with the packet size, */
1402        /* so we need zero-length-packet */
1403        need_zlp = 1;
1404    }
1405
1406    ret = write_fifo_ep0(ep, req);
1407
1408    if (ret == 1 && !need_zlp) {
1409        /* Last packet */
1410        DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1411
1412        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1413        dev->ep0state = WAIT_FOR_SETUP;
1414    } else {
1415        DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1416        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1417    }
1418
1419    if (need_zlp) {
1420        DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1421        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1422        dev->ep0state = DATA_STATE_NEED_ZLP;
1423    }
1424
1425    return 1;
1426}
1427
1428static int jz4740_handle_get_status(struct jz4740_udc *dev,
1429                    struct usb_ctrlrequest *ctrl)
1430{
1431    struct jz4740_ep *ep0 = &dev->ep[0];
1432    struct jz4740_ep *qep;
1433    int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1434    uint16_t val = 0;
1435
1436    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1437
1438    if (reqtype == USB_RECIP_INTERFACE) {
1439        /* This is not supported.
1440         * And according to the USB spec, this one does nothing..
1441         * Just return 0
1442         */
1443        DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1444    } else if (reqtype == USB_RECIP_DEVICE) {
1445        DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1446        val |= (1 << 0); /* Self powered */
1447        /*val |= (1<<1); *//* Remote wakeup */
1448    } else if (reqtype == USB_RECIP_ENDPOINT) {
1449        int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1450
1451        DEBUG_SETUP
1452            ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1453             ep_num, ctrl->wLength);
1454
1455        if (ctrl->wLength > 2 || ep_num > 3)
1456            return -EOPNOTSUPP;
1457
1458        qep = &dev->ep[ep_num];
1459        if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1460            && ep_index(qep) != 0) {
1461            return -EOPNOTSUPP;
1462        }
1463
1464        jz_udc_select_ep(qep);
1465
1466        /* Return status on next IN token */
1467        switch (qep->type) {
1468        case ep_control:
1469            val =
1470                (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1471                USB_CSR0_SENDSTALL;
1472            break;
1473        case ep_bulk_in:
1474        case ep_interrupt:
1475            val =
1476                (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1477                USB_INCSR_SENDSTALL;
1478            break;
1479        case ep_bulk_out:
1480            val =
1481                (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1482                USB_OUTCSR_SENDSTALL;
1483            break;
1484        }
1485
1486        /* Back to EP0 index */
1487        jz_udc_set_index(dev, 0);
1488
1489        DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1490                ctrl->wIndex, val);
1491    } else {
1492        DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1493        return -EOPNOTSUPP;
1494    }
1495
1496    /* Clear "out packet ready" */
1497    usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1498    /* Put status to FIFO */
1499    jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1500    /* Issue "In packet ready" */
1501    usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1502
1503    return 0;
1504}
1505
1506/*
1507 * WAIT_FOR_SETUP (OUTPKTRDY)
1508 * - read data packet from EP0 FIFO
1509 * - decode command
1510 * - if error
1511 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1512 * - else
1513 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1514 */
1515static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1516{
1517    struct jz4740_ep *ep = &dev->ep[0];
1518    struct usb_ctrlrequest ctrl;
1519    int i;
1520
1521    DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1522
1523    /* Nuke all previous transfers */
1524    nuke(ep, -EPROTO);
1525
1526    /* read control req from fifo (8 bytes) */
1527    jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1528
1529    DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1530            ctrl.bRequestType, ctrl.bRequest,
1531            ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1532
1533    /* Set direction of EP0 */
1534    if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1535        ep->bEndpointAddress |= USB_DIR_IN;
1536    } else {
1537        ep->bEndpointAddress &= ~USB_DIR_IN;
1538    }
1539
1540    /* Handle some SETUP packets ourselves */
1541    switch (ctrl.bRequest) {
1542    case USB_REQ_SET_ADDRESS:
1543        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1544            break;
1545
1546        DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1547        udc_set_address(dev, ctrl.wValue);
1548        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1549        return;
1550
1551    case USB_REQ_SET_CONFIGURATION:
1552        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1553            break;
1554
1555        DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1556/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1557
1558        /* Enable RESUME and SUSPEND interrupts */
1559        usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1560        break;
1561
1562    case USB_REQ_SET_INTERFACE:
1563        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1564            break;
1565
1566        DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1567/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1568        break;
1569
1570    case USB_REQ_GET_STATUS:
1571        if (jz4740_handle_get_status(dev, &ctrl) == 0)
1572            return;
1573
1574    case USB_REQ_CLEAR_FEATURE:
1575    case USB_REQ_SET_FEATURE:
1576        if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1577            struct jz4740_ep *qep;
1578            int ep_num = (ctrl.wIndex & 0x0f);
1579
1580            /* Support only HALT feature */
1581            if (ctrl.wValue != 0 || ctrl.wLength != 0
1582                || ep_num > 3 || ep_num < 1)
1583                break;
1584
1585            qep = &dev->ep[ep_num];
1586            spin_unlock(&dev->lock);
1587            if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1588                DEBUG_SETUP("SET_FEATURE (%d)\n",
1589                        ep_num);
1590                jz4740_set_halt(&qep->ep, 1);
1591            } else {
1592                DEBUG_SETUP("CLR_FEATURE (%d)\n",
1593                        ep_num);
1594                jz4740_set_halt(&qep->ep, 0);
1595            }
1596            spin_lock(&dev->lock);
1597
1598            jz_udc_set_index(dev, 0);
1599
1600            /* Reply with a ZLP on next IN token */
1601            usb_setb(dev, JZ_REG_UDC_CSR0,
1602                 (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1603            return;
1604        }
1605        break;
1606
1607    default:
1608        break;
1609    }
1610
1611    /* gadget drivers see class/vendor specific requests,
1612     * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1613     * and more.
1614     */
1615    if (dev->driver) {
1616        /* device-2-host (IN) or no data setup command, process immediately */
1617        spin_unlock(&dev->lock);
1618
1619        i = dev->driver->setup(&dev->gadget, &ctrl);
1620        spin_lock(&dev->lock);
1621
1622        if (unlikely(i < 0)) {
1623            /* setup processing failed, force stall */
1624            DEBUG_SETUP
1625                (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1626                 i);
1627            jz_udc_set_index(dev, 0);
1628            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1629
1630            /* ep->stopped = 1; */
1631            dev->ep0state = WAIT_FOR_SETUP;
1632        }
1633        else {
1634            DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1635/* if (!ctrl.wLength) {
1636                usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1637            }*/
1638        }
1639    }
1640}
1641
1642/*
1643 * DATA_STATE_NEED_ZLP
1644 */
1645static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1646{
1647    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1648
1649    usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1650    dev->ep0state = WAIT_FOR_SETUP;
1651}
1652
1653/*
1654 * handle ep0 interrupt
1655 */
1656static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1657{
1658    struct jz4740_ep *ep = &dev->ep[0];
1659    uint32_t csr;
1660
1661    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1662    /* Set index 0 */
1663    jz_udc_set_index(dev, 0);
1664    csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1665
1666    DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1667
1668    /*
1669     * if SENT_STALL is set
1670     * - clear the SENT_STALL bit
1671     */
1672    if (csr & USB_CSR0_SENTSTALL) {
1673        DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1674        usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1675        nuke(ep, -ECONNABORTED);
1676        dev->ep0state = WAIT_FOR_SETUP;
1677        return;
1678    }
1679
1680    /*
1681     * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1682     * - fill EP0 FIFO
1683     * - if last packet
1684     * - set IN_PKT_RDY | DATA_END
1685     * - else
1686     * set IN_PKT_RDY
1687     */
1688    if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1689        DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1690              __FUNCTION__);
1691
1692        switch (dev->ep0state) {
1693        case DATA_STATE_XMIT:
1694            DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1695            jz4740_ep0_in(dev, csr);
1696            return;
1697        case DATA_STATE_NEED_ZLP:
1698            DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1699            jz4740_ep0_in_zlp(dev, csr);
1700            return;
1701        default:
1702            /* Stall? */
1703// DEBUG_EP0("Odd state!! state = %s\n",
1704// state_names[dev->ep0state]);
1705            dev->ep0state = WAIT_FOR_SETUP;
1706            /* nuke(ep, 0); */
1707            /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1708// break;
1709            return;
1710        }
1711    }
1712
1713    /*
1714     * if SETUPEND is set
1715     * - abort the last transfer
1716     * - set SERVICED_SETUP_END_BIT
1717     */
1718    if (csr & USB_CSR0_SETUPEND) {
1719        DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1720
1721        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1722        nuke(ep, 0);
1723        dev->ep0state = WAIT_FOR_SETUP;
1724    }
1725
1726    /*
1727     * if USB_CSR0_OUTPKTRDY is set
1728     * - read data packet from EP0 FIFO
1729     * - decode command
1730     * - if error
1731     * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1732     * - else
1733     * set SVDOUTPKTRDY | DATAEND bits
1734     */
1735    if (csr & USB_CSR0_OUTPKTRDY) {
1736
1737        DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1738              csr);
1739
1740        switch (dev->ep0state) {
1741        case WAIT_FOR_SETUP:
1742            DEBUG_EP0("WAIT_FOR_SETUP\n");
1743            jz4740_ep0_setup(dev, csr);
1744            break;
1745
1746        case DATA_STATE_RECV:
1747            DEBUG_EP0("DATA_STATE_RECV\n");
1748            jz4740_ep0_out(dev, csr, 0);
1749            break;
1750
1751        default:
1752            /* send stall? */
1753            DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1754                  dev->ep0state);
1755            break;
1756        }
1757    }
1758}
1759
1760static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1761{
1762    uint32_t csr;
1763
1764    jz_udc_set_index(dev, 0);
1765
1766    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1767
1768    /* Clear "out packet ready" */
1769
1770    if (ep_is_in(ep)) {
1771        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1772        csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1773        dev->ep0state = DATA_STATE_XMIT;
1774        jz4740_ep0_in(dev, csr);
1775    } else {
1776        csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1777        dev->ep0state = DATA_STATE_RECV;
1778        jz4740_ep0_out(dev, csr, 1);
1779    }
1780}
1781
1782/** Handle USB RESET interrupt
1783 */
1784static void jz4740_reset_irq(struct jz4740_udc *dev)
1785{
1786    dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1787        USB_SPEED_HIGH : USB_SPEED_FULL;
1788
1789    DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
1790            (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1791}
1792
1793/*
1794 * jz4740 usb device interrupt handler.
1795 */
1796static irqreturn_t jz4740_udc_irq(int irq, void *devid)
1797{
1798    struct jz4740_udc *jz4740_udc = devid;
1799    uint8_t index;
1800
1801    uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1802    uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
1803    uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
1804    uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
1805
1806    if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1807        return IRQ_HANDLED;
1808
1809
1810    DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1811          intr_out, intr_in, intr_usb);
1812
1813    spin_lock(&jz4740_udc->lock);
1814    index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
1815
1816    /* Check for resume from suspend mode */
1817    if ((intr_usb & USB_INTR_RESUME) &&
1818        (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1819        DEBUG("USB resume\n");
1820        jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
1821    }
1822
1823    /* Check for system interrupts */
1824    if (intr_usb & USB_INTR_RESET) {
1825        DEBUG("USB reset\n");
1826        jz4740_reset_irq(jz4740_udc);
1827    }
1828
1829    /* Check for endpoint 0 interrupt */
1830    if (intr_in & USB_INTR_EP0) {
1831        DEBUG("USB_INTR_EP0 (control)\n");
1832        jz4740_handle_ep0(jz4740_udc, intr_in);
1833    }
1834
1835    /* Check for Bulk-IN DMA interrupt */
1836    if (intr_dma & 0x1) {
1837        int ep_num;
1838        struct jz4740_ep *ep;
1839        ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
1840        ep = &jz4740_udc->ep[ep_num + 1];
1841        jz_udc_select_ep(ep);
1842        usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
1843/* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
1844    }
1845
1846    /* Check for Bulk-OUT DMA interrupt */
1847    if (intr_dma & 0x2) {
1848        int ep_num;
1849        ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
1850        jz4740_out_epn(jz4740_udc, ep_num, intr_out);
1851    }
1852
1853    /* Check for each configured endpoint interrupt */
1854    if (intr_in & USB_INTR_INEP1) {
1855        DEBUG("USB_INTR_INEP1\n");
1856        jz4740_in_epn(jz4740_udc, 1, intr_in);
1857    }
1858
1859    if (intr_in & USB_INTR_INEP2) {
1860        DEBUG("USB_INTR_INEP2\n");
1861        jz4740_in_epn(jz4740_udc, 2, intr_in);
1862    }
1863
1864    if (intr_out & USB_INTR_OUTEP1) {
1865        DEBUG("USB_INTR_OUTEP1\n");
1866        jz4740_out_epn(jz4740_udc, 1, intr_out);
1867    }
1868
1869    /* Check for suspend mode */
1870    if ((intr_usb & USB_INTR_SUSPEND) &&
1871        (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
1872        DEBUG("USB suspend\n");
1873        jz4740_udc->driver->suspend(&jz4740_udc->gadget);
1874        /* Host unloaded from us, can do something, such as flushing
1875         the NAND block cache etc. */
1876    }
1877
1878    jz_udc_set_index(jz4740_udc, index);
1879
1880    spin_unlock(&jz4740_udc->lock);
1881
1882    return IRQ_HANDLED;
1883}
1884
1885
1886
1887/*-------------------------------------------------------------------------*/
1888
1889
1890static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
1891{
1892    return container_of(gadget, struct jz4740_udc, gadget);
1893}
1894
1895static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
1896{
1897    DEBUG("%s, %p\n", __FUNCTION__, _gadget);
1898    return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
1899}
1900
1901static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
1902{
1903    /* host may not have enabled remote wakeup */
1904    /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
1905       return -EHOSTUNREACH;
1906       udc_set_mask_UDCCR(UDCCR_RSM); */
1907    return -ENOTSUPP;
1908}
1909
1910static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
1911{
1912    struct jz4740_udc *udc = gadget_to_udc(_gadget);
1913    unsigned long flags;
1914
1915    local_irq_save(flags);
1916
1917    if (on) {
1918        udc->state = UDC_STATE_ENABLE;
1919        udc_enable(udc);
1920    } else {
1921        udc->state = UDC_STATE_DISABLE;
1922        udc_disable(udc);
1923    }
1924
1925    local_irq_restore(flags);
1926
1927    return 0;
1928}
1929
1930
1931static const struct usb_gadget_ops jz4740_udc_ops = {
1932    .get_frame = jz4740_udc_get_frame,
1933    .wakeup = jz4740_udc_wakeup,
1934    .pullup = jz4740_udc_pullup,
1935};
1936
1937static struct usb_ep_ops jz4740_ep_ops = {
1938    .enable = jz4740_ep_enable,
1939    .disable = jz4740_ep_disable,
1940
1941    .alloc_request = jz4740_alloc_request,
1942    .free_request = jz4740_free_request,
1943
1944    .queue = jz4740_queue,
1945    .dequeue = jz4740_dequeue,
1946
1947    .set_halt = jz4740_set_halt,
1948    .fifo_status = jz4740_fifo_status,
1949    .fifo_flush = jz4740_fifo_flush,
1950};
1951
1952
1953/*-------------------------------------------------------------------------*/
1954
1955static struct jz4740_udc jz4740_udc_controller = {
1956    .gadget = {
1957        .ops = &jz4740_udc_ops,
1958        .ep0 = &jz4740_udc_controller.ep[0].ep,
1959        .name = "jz4740-udc",
1960        .dev = {
1961            .init_name = "gadget",
1962        },
1963    },
1964
1965    /* control endpoint */
1966    .ep[0] = {
1967        .ep = {
1968            .name = "ep0",
1969            .ops = &jz4740_ep_ops,
1970            .maxpacket = EP0_MAXPACKETSIZE,
1971        },
1972        .dev = &jz4740_udc_controller,
1973
1974        .bEndpointAddress = 0,
1975        .bmAttributes = 0,
1976
1977        .type = ep_control,
1978        .fifo = JZ_REG_UDC_EP_FIFO(0),
1979        .csr = JZ_REG_UDC_CSR0,
1980    },
1981
1982    /* bulk out endpoint */
1983    .ep[1] = {
1984        .ep = {
1985            .name = "ep1out-bulk",
1986            .ops = &jz4740_ep_ops,
1987            .maxpacket = EPBULK_MAXPACKETSIZE,
1988        },
1989        .dev = &jz4740_udc_controller,
1990
1991        .bEndpointAddress = 1,
1992        .bmAttributes = USB_ENDPOINT_XFER_BULK,
1993
1994        .type = ep_bulk_out,
1995        .fifo = JZ_REG_UDC_EP_FIFO(1),
1996        .csr = JZ_REG_UDC_OUTCSR,
1997    },
1998
1999    /* bulk in endpoint */
2000    .ep[2] = {
2001        .ep = {
2002            .name = "ep1in-bulk",
2003            .ops = &jz4740_ep_ops,
2004            .maxpacket = EPBULK_MAXPACKETSIZE,
2005        },
2006        .dev = &jz4740_udc_controller,
2007
2008        .bEndpointAddress = 1 | USB_DIR_IN,
2009        .bmAttributes = USB_ENDPOINT_XFER_BULK,
2010
2011        .type = ep_bulk_in,
2012        .fifo = JZ_REG_UDC_EP_FIFO(1),
2013        .csr = JZ_REG_UDC_INCSR,
2014    },
2015
2016    /* interrupt in endpoint */
2017    .ep[3] = {
2018        .ep = {
2019            .name = "ep2in-int",
2020            .ops = &jz4740_ep_ops,
2021            .maxpacket = EPINTR_MAXPACKETSIZE,
2022        },
2023        .dev = &jz4740_udc_controller,
2024
2025        .bEndpointAddress = 2 | USB_DIR_IN,
2026        .bmAttributes = USB_ENDPOINT_XFER_INT,
2027
2028        .type = ep_interrupt,
2029        .fifo = JZ_REG_UDC_EP_FIFO(2),
2030        .csr = JZ_REG_UDC_INCSR,
2031    },
2032};
2033
2034static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2035{
2036    struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2037    int ret;
2038
2039    spin_lock_init(&jz4740_udc->lock);
2040
2041    jz4740_udc->dev = &pdev->dev;
2042    jz4740_udc->gadget.dev.parent = &pdev->dev;
2043    jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
2044
2045    ret = device_register(&jz4740_udc->gadget.dev);
2046    if (ret)
2047        return ret;
2048
2049    jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2050    if (IS_ERR(jz4740_udc->clk)) {
2051        ret = PTR_ERR(jz4740_udc->clk);
2052        dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2053        goto err_device_unregister;
2054    }
2055
2056    platform_set_drvdata(pdev, jz4740_udc);
2057
2058    jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2059
2060    if (!jz4740_udc->mem) {
2061        ret = -ENOENT;
2062        dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2063        goto err_clk_put;
2064    }
2065
2066    jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2067    resource_size(jz4740_udc->mem), pdev->name);
2068
2069    if (!jz4740_udc->mem) {
2070        ret = -EBUSY;
2071        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2072        goto err_device_unregister;
2073    }
2074
2075    jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2076
2077    if (!jz4740_udc->base) {
2078        ret = -EBUSY;
2079        dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2080        goto err_release_mem_region;
2081    }
2082
2083    jz4740_udc->irq = platform_get_irq(pdev, 0);
2084    ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2085    jz4740_udc);
2086        if (ret) {
2087                dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2088                goto err_iounmap;
2089    }
2090
2091    udc_disable(jz4740_udc);
2092    udc_reinit(jz4740_udc);
2093
2094    return 0;
2095
2096err_iounmap:
2097    iounmap(jz4740_udc->base);
2098err_release_mem_region:
2099    release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2100err_clk_put:
2101    clk_put(jz4740_udc->clk);
2102err_device_unregister:
2103    device_unregister(&jz4740_udc->gadget.dev);
2104    platform_set_drvdata(pdev, NULL);
2105
2106    return ret;
2107}
2108
2109static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2110{
2111    struct jz4740_udc *dev = platform_get_drvdata(pdev);
2112
2113    if (dev->driver)
2114        return -EBUSY;
2115
2116    udc_disable(dev);
2117
2118    free_irq(dev->irq, dev);
2119    iounmap(dev->base);
2120    release_mem_region(dev->mem->start, resource_size(dev->mem));
2121    clk_put(dev->clk);
2122
2123    platform_set_drvdata(pdev, NULL);
2124    device_unregister(&dev->gadget.dev);
2125
2126    return 0;
2127}
2128
2129#ifdef CONFIG_PM
2130
2131static int jz4740_udc_suspend(struct device *dev)
2132{
2133    struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2134
2135    if (jz4740_udc->state == UDC_STATE_ENABLE)
2136        udc_disable(jz4740_udc);
2137
2138    return 0;
2139}
2140
2141static int jz4740_udc_resume(struct device *dev)
2142{
2143    struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2144
2145    if (jz4740_udc->state == UDC_STATE_ENABLE)
2146        udc_enable(jz4740_udc);
2147
2148    return 0;
2149}
2150
2151static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume);
2152#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2153
2154#else
2155#define JZ4740_UDC_PM_OPS NULL
2156#endif
2157
2158static struct platform_driver udc_driver = {
2159    .probe = jz4740_udc_probe,
2160    .remove = __devexit_p(jz4740_udc_remove),
2161    .driver = {
2162        .name = "jz-udc",
2163        .owner = THIS_MODULE,
2164        .pm = JZ4740_UDC_PM_OPS,
2165    },
2166};
2167
2168/*-------------------------------------------------------------------------*/
2169
2170static int __init udc_init (void)
2171{
2172    return platform_driver_register(&udc_driver);
2173}
2174module_init(udc_init);
2175
2176static void __exit udc_exit (void)
2177{
2178    platform_driver_unregister(&udc_driver);
2179}
2180module_exit(udc_exit);
2181
2182MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2183MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2184MODULE_LICENSE("GPL");
2185

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