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Source at commit be977234bfb4a6dca8a39e7c52165e4cd536ad71 created 12 years 9 months ago. By Lars-Peter Clausen, jz4740: Fix compile error | |
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1 | /* |
2 | * Intel Langwell USB Device Controller driver |
3 | * Copyright (C) 2008-2009, Intel Corporation. |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms and conditions of the GNU General Public License, |
7 | * version 2, as published by the Free Software Foundation. |
8 | * |
9 | * This program is distributed in the hope it will be useful, but WITHOUT |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
12 | * more details. |
13 | * |
14 | * You should have received a copy of the GNU General Public License along with |
15 | * this program; if not, write to the Free Software Foundation, Inc., |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
17 | * |
18 | */ |
19 | |
20 | #include <linux/usb/langwell_udc.h> |
21 | #include <linux/usb/langwell_otg.h> |
22 | |
23 | /*-------------------------------------------------------------------------*/ |
24 | |
25 | /* driver data structures and utilities */ |
26 | |
27 | /* |
28 | * dTD: Device Endpoint Transfer Descriptor |
29 | * describe to the device controller the location and quantity of |
30 | * data to be send/received for given transfer |
31 | */ |
32 | struct langwell_dtd { |
33 | u32 dtd_next; |
34 | /* bits 31:5, next transfer element pointer */ |
35 | #define DTD_NEXT(d) (((d)>>5)&0x7ffffff) |
36 | #define DTD_NEXT_MASK (0x7ffffff << 5) |
37 | /* terminate */ |
38 | #define DTD_TERM BIT(0) |
39 | /* bits 7:0, execution back states */ |
40 | u32 dtd_status:8; |
41 | #define DTD_STATUS(d) (((d)>>0)&0xff) |
42 | #define DTD_STS_ACTIVE BIT(7) /* active */ |
43 | #define DTD_STS_HALTED BIT(6) /* halted */ |
44 | #define DTD_STS_DBE BIT(5) /* data buffer error */ |
45 | #define DTD_STS_TRE BIT(3) /* transaction error */ |
46 | /* bits 9:8 */ |
47 | u32 dtd_res0:2; |
48 | /* bits 11:10, multipier override */ |
49 | u32 dtd_multo:2; |
50 | #define DTD_MULTO (BIT(11) | BIT(10)) |
51 | /* bits 14:12 */ |
52 | u32 dtd_res1:3; |
53 | /* bit 15, interrupt on complete */ |
54 | u32 dtd_ioc:1; |
55 | #define DTD_IOC BIT(15) |
56 | /* bits 30:16, total bytes */ |
57 | u32 dtd_total:15; |
58 | #define DTD_TOTAL(d) (((d)>>16)&0x7fff) |
59 | #define DTD_MAX_TRANSFER_LENGTH 0x4000 |
60 | /* bit 31 */ |
61 | u32 dtd_res2:1; |
62 | /* dTD buffer pointer page 0 to 4 */ |
63 | u32 dtd_buf[5]; |
64 | #define DTD_OFFSET_MASK 0xfff |
65 | /* bits 31:12, buffer pointer */ |
66 | #define DTD_BUFFER(d) (((d)>>12)&0x3ff) |
67 | /* bits 11:0, current offset */ |
68 | #define DTD_C_OFFSET(d) (((d)>>0)&0xfff) |
69 | /* bits 10:0, frame number */ |
70 | #define DTD_FRAME(d) (((d)>>0)&0x7ff) |
71 | |
72 | /* driver-private parts */ |
73 | |
74 | /* dtd dma address */ |
75 | dma_addr_t dtd_dma; |
76 | /* next dtd virtual address */ |
77 | struct langwell_dtd *next_dtd_virt; |
78 | }; |
79 | |
80 | |
81 | /* |
82 | * dQH: Device Endpoint Queue Head |
83 | * describe where all transfers are managed |
84 | * 48-byte data structure, aligned on 64-byte boundary |
85 | * |
86 | * These are associated with dTD structure |
87 | */ |
88 | struct langwell_dqh { |
89 | /* endpoint capabilities and characteristics */ |
90 | u32 dqh_res0:15; /* bits 14:0 */ |
91 | u32 dqh_ios:1; /* bit 15, interrupt on setup */ |
92 | #define DQH_IOS BIT(15) |
93 | u32 dqh_mpl:11; /* bits 26:16, maximum packet length */ |
94 | #define DQH_MPL (0x7ff << 16) |
95 | u32 dqh_res1:2; /* bits 28:27 */ |
96 | u32 dqh_zlt:1; /* bit 29, zero length termination */ |
97 | #define DQH_ZLT BIT(29) |
98 | u32 dqh_mult:2; /* bits 31:30 */ |
99 | #define DQH_MULT (BIT(30) | BIT(31)) |
100 | |
101 | /* current dTD pointer */ |
102 | u32 dqh_current; /* locate the transfer in progress */ |
103 | #define DQH_C_DTD(e) \ |
104 | (((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */ |
105 | |
106 | /* transfer overlay, hardware parts of a struct langwell_dtd */ |
107 | u32 dtd_next; |
108 | u32 dtd_status:8; /* bits 7:0, execution back states */ |
109 | u32 dtd_res0:2; /* bits 9:8 */ |
110 | u32 dtd_multo:2; /* bits 11:10, multipier override */ |
111 | u32 dtd_res1:3; /* bits 14:12 */ |
112 | u32 dtd_ioc:1; /* bit 15, interrupt on complete */ |
113 | u32 dtd_total:15; /* bits 30:16, total bytes */ |
114 | u32 dtd_res2:1; /* bit 31 */ |
115 | u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */ |
116 | |
117 | u32 dqh_res2; |
118 | struct usb_ctrlrequest dqh_setup; /* setup packet buffer */ |
119 | } __attribute__ ((aligned(64))); |
120 | |
121 | |
122 | /* endpoint data structure */ |
123 | struct langwell_ep { |
124 | struct usb_ep ep; |
125 | dma_addr_t dma; |
126 | struct langwell_udc *dev; |
127 | unsigned long irqs; |
128 | struct list_head queue; |
129 | struct langwell_dqh *dqh; |
130 | const struct usb_endpoint_descriptor *desc; |
131 | char name[14]; |
132 | unsigned stopped:1, |
133 | ep_type:2, |
134 | ep_num:8; |
135 | }; |
136 | |
137 | |
138 | /* request data structure */ |
139 | struct langwell_request { |
140 | struct usb_request req; |
141 | struct langwell_dtd *dtd, *head, *tail; |
142 | struct langwell_ep *ep; |
143 | dma_addr_t dtd_dma; |
144 | struct list_head queue; |
145 | unsigned dtd_count; |
146 | unsigned mapped:1; |
147 | }; |
148 | |
149 | |
150 | /* ep0 transfer state */ |
151 | enum ep0_state { |
152 | WAIT_FOR_SETUP, |
153 | DATA_STATE_XMIT, |
154 | DATA_STATE_NEED_ZLP, |
155 | WAIT_FOR_OUT_STATUS, |
156 | DATA_STATE_RECV, |
157 | }; |
158 | |
159 | |
160 | /* device suspend state */ |
161 | enum lpm_state { |
162 | LPM_L0, /* on */ |
163 | LPM_L1, /* LPM L1 sleep */ |
164 | LPM_L2, /* suspend */ |
165 | LPM_L3, /* off */ |
166 | }; |
167 | |
168 | |
169 | /* device data structure */ |
170 | struct langwell_udc { |
171 | /* each pci device provides one gadget, several endpoints */ |
172 | struct usb_gadget gadget; |
173 | spinlock_t lock; /* device lock */ |
174 | struct langwell_ep *ep; |
175 | struct usb_gadget_driver *driver; |
176 | struct otg_transceiver *transceiver; |
177 | u8 dev_addr; |
178 | u32 usb_state; |
179 | u32 resume_state; |
180 | u32 bus_reset; |
181 | enum lpm_state lpm_state; |
182 | enum ep0_state ep0_state; |
183 | u32 ep0_dir; |
184 | u16 dciversion; |
185 | unsigned ep_max; |
186 | unsigned devcap:1, |
187 | enabled:1, |
188 | region:1, |
189 | got_irq:1, |
190 | powered:1, |
191 | remote_wakeup:1, |
192 | rate:1, |
193 | is_reset:1, |
194 | softconnected:1, |
195 | vbus_active:1, |
196 | suspended:1, |
197 | stopped:1, |
198 | lpm:1, /* LPM capability */ |
199 | has_sram:1, /* SRAM caching */ |
200 | got_sram:1; |
201 | |
202 | /* pci state used to access those endpoints */ |
203 | struct pci_dev *pdev; |
204 | |
205 | /* Langwell otg transceiver */ |
206 | struct langwell_otg *lotg; |
207 | |
208 | /* control registers */ |
209 | struct langwell_cap_regs __iomem *cap_regs; |
210 | struct langwell_op_regs __iomem *op_regs; |
211 | |
212 | struct usb_ctrlrequest local_setup_buff; |
213 | struct langwell_dqh *ep_dqh; |
214 | size_t ep_dqh_size; |
215 | dma_addr_t ep_dqh_dma; |
216 | |
217 | /* ep0 status request */ |
218 | struct langwell_request *status_req; |
219 | |
220 | /* dma pool */ |
221 | struct dma_pool *dtd_pool; |
222 | |
223 | /* make sure release() is done */ |
224 | struct completion *done; |
225 | |
226 | /* for private SRAM caching */ |
227 | unsigned int sram_addr; |
228 | unsigned int sram_size; |
229 | |
230 | /* device status data for get_status request */ |
231 | u16 dev_status; |
232 | }; |
233 | |
234 |
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