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Source at commit be977234bfb4a6dca8a39e7c52165e4cd536ad71 created 12 years 9 months ago. By Lars-Peter Clausen, jz4740: Fix compile error | |
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1 | |
2 | #ifndef __MV_UDC_H |
3 | #define __MV_UDC_H |
4 | |
5 | #define VUSBHS_MAX_PORTS 8 |
6 | |
7 | #define DQH_ALIGNMENT 2048 |
8 | #define DTD_ALIGNMENT 64 |
9 | #define DMA_BOUNDARY 4096 |
10 | |
11 | #define EP_DIR_IN 1 |
12 | #define EP_DIR_OUT 0 |
13 | |
14 | #define DMA_ADDR_INVALID (~(dma_addr_t)0) |
15 | |
16 | #define EP0_MAX_PKT_SIZE 64 |
17 | /* ep0 transfer state */ |
18 | #define WAIT_FOR_SETUP 0 |
19 | #define DATA_STATE_XMIT 1 |
20 | #define DATA_STATE_NEED_ZLP 2 |
21 | #define WAIT_FOR_OUT_STATUS 3 |
22 | #define DATA_STATE_RECV 4 |
23 | |
24 | #define CAPLENGTH_MASK (0xff) |
25 | #define DCCPARAMS_DEN_MASK (0x1f) |
26 | |
27 | #define HCSPARAMS_PPC (0x10) |
28 | |
29 | /* Frame Index Register Bit Masks */ |
30 | #define USB_FRINDEX_MASKS 0x3fff |
31 | |
32 | /* Command Register Bit Masks */ |
33 | #define USBCMD_RUN_STOP (0x00000001) |
34 | #define USBCMD_CTRL_RESET (0x00000002) |
35 | #define USBCMD_SETUP_TRIPWIRE_SET (0x00002000) |
36 | #define USBCMD_SETUP_TRIPWIRE_CLEAR (~USBCMD_SETUP_TRIPWIRE_SET) |
37 | |
38 | #define USBCMD_ATDTW_TRIPWIRE_SET (0x00004000) |
39 | #define USBCMD_ATDTW_TRIPWIRE_CLEAR (~USBCMD_ATDTW_TRIPWIRE_SET) |
40 | |
41 | /* bit 15,3,2 are for frame list size */ |
42 | #define USBCMD_FRAME_SIZE_1024 (0x00000000) /* 000 */ |
43 | #define USBCMD_FRAME_SIZE_512 (0x00000004) /* 001 */ |
44 | #define USBCMD_FRAME_SIZE_256 (0x00000008) /* 010 */ |
45 | #define USBCMD_FRAME_SIZE_128 (0x0000000C) /* 011 */ |
46 | #define USBCMD_FRAME_SIZE_64 (0x00008000) /* 100 */ |
47 | #define USBCMD_FRAME_SIZE_32 (0x00008004) /* 101 */ |
48 | #define USBCMD_FRAME_SIZE_16 (0x00008008) /* 110 */ |
49 | #define USBCMD_FRAME_SIZE_8 (0x0000800C) /* 111 */ |
50 | |
51 | #define EPCTRL_TX_ALL_MASK (0xFFFF0000) |
52 | #define EPCTRL_RX_ALL_MASK (0x0000FFFF) |
53 | |
54 | #define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) |
55 | #define EPCTRL_TX_EP_STALL (0x00010000) |
56 | #define EPCTRL_RX_EP_STALL (0x00000001) |
57 | #define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) |
58 | #define EPCTRL_RX_ENABLE (0x00000080) |
59 | #define EPCTRL_TX_ENABLE (0x00800000) |
60 | #define EPCTRL_CONTROL (0x00000000) |
61 | #define EPCTRL_ISOCHRONOUS (0x00040000) |
62 | #define EPCTRL_BULK (0x00080000) |
63 | #define EPCTRL_INT (0x000C0000) |
64 | #define EPCTRL_TX_TYPE (0x000C0000) |
65 | #define EPCTRL_RX_TYPE (0x0000000C) |
66 | #define EPCTRL_DATA_TOGGLE_INHIBIT (0x00000020) |
67 | #define EPCTRL_TX_EP_TYPE_SHIFT (18) |
68 | #define EPCTRL_RX_EP_TYPE_SHIFT (2) |
69 | |
70 | #define EPCOMPLETE_MAX_ENDPOINTS (16) |
71 | |
72 | /* endpoint list address bit masks */ |
73 | #define USB_EP_LIST_ADDRESS_MASK 0xfffff800 |
74 | |
75 | #define PORTSCX_W1C_BITS 0x2a |
76 | #define PORTSCX_PORT_RESET 0x00000100 |
77 | #define PORTSCX_PORT_POWER 0x00001000 |
78 | #define PORTSCX_FORCE_FULL_SPEED_CONNECT 0x01000000 |
79 | #define PORTSCX_PAR_XCVR_SELECT 0xC0000000 |
80 | #define PORTSCX_PORT_FORCE_RESUME 0x00000040 |
81 | #define PORTSCX_PORT_SUSPEND 0x00000080 |
82 | #define PORTSCX_PORT_SPEED_FULL 0x00000000 |
83 | #define PORTSCX_PORT_SPEED_LOW 0x04000000 |
84 | #define PORTSCX_PORT_SPEED_HIGH 0x08000000 |
85 | #define PORTSCX_PORT_SPEED_MASK 0x0C000000 |
86 | |
87 | /* USB MODE Register Bit Masks */ |
88 | #define USBMODE_CTRL_MODE_IDLE 0x00000000 |
89 | #define USBMODE_CTRL_MODE_DEVICE 0x00000002 |
90 | #define USBMODE_CTRL_MODE_HOST 0x00000003 |
91 | #define USBMODE_CTRL_MODE_RSV 0x00000001 |
92 | #define USBMODE_SETUP_LOCK_OFF 0x00000008 |
93 | #define USBMODE_STREAM_DISABLE 0x00000010 |
94 | |
95 | /* USB STS Register Bit Masks */ |
96 | #define USBSTS_INT 0x00000001 |
97 | #define USBSTS_ERR 0x00000002 |
98 | #define USBSTS_PORT_CHANGE 0x00000004 |
99 | #define USBSTS_FRM_LST_ROLL 0x00000008 |
100 | #define USBSTS_SYS_ERR 0x00000010 |
101 | #define USBSTS_IAA 0x00000020 |
102 | #define USBSTS_RESET 0x00000040 |
103 | #define USBSTS_SOF 0x00000080 |
104 | #define USBSTS_SUSPEND 0x00000100 |
105 | #define USBSTS_HC_HALTED 0x00001000 |
106 | #define USBSTS_RCL 0x00002000 |
107 | #define USBSTS_PERIODIC_SCHEDULE 0x00004000 |
108 | #define USBSTS_ASYNC_SCHEDULE 0x00008000 |
109 | |
110 | |
111 | /* Interrupt Enable Register Bit Masks */ |
112 | #define USBINTR_INT_EN (0x00000001) |
113 | #define USBINTR_ERR_INT_EN (0x00000002) |
114 | #define USBINTR_PORT_CHANGE_DETECT_EN (0x00000004) |
115 | |
116 | #define USBINTR_ASYNC_ADV_AAE (0x00000020) |
117 | #define USBINTR_ASYNC_ADV_AAE_ENABLE (0x00000020) |
118 | #define USBINTR_ASYNC_ADV_AAE_DISABLE (0xFFFFFFDF) |
119 | |
120 | #define USBINTR_RESET_EN (0x00000040) |
121 | #define USBINTR_SOF_UFRAME_EN (0x00000080) |
122 | #define USBINTR_DEVICE_SUSPEND (0x00000100) |
123 | |
124 | #define USB_DEVICE_ADDRESS_MASK (0xfe000000) |
125 | #define USB_DEVICE_ADDRESS_BIT_SHIFT (25) |
126 | |
127 | struct mv_cap_regs { |
128 | u32 caplength_hciversion; |
129 | u32 hcsparams; /* HC structural parameters */ |
130 | u32 hccparams; /* HC Capability Parameters*/ |
131 | u32 reserved[5]; |
132 | u32 dciversion; /* DC version number and reserved 16 bits */ |
133 | u32 dccparams; /* DC Capability Parameters */ |
134 | }; |
135 | |
136 | struct mv_op_regs { |
137 | u32 usbcmd; /* Command register */ |
138 | u32 usbsts; /* Status register */ |
139 | u32 usbintr; /* Interrupt enable */ |
140 | u32 frindex; /* Frame index */ |
141 | u32 reserved1[1]; |
142 | u32 deviceaddr; /* Device Address */ |
143 | u32 eplistaddr; /* Endpoint List Address */ |
144 | u32 ttctrl; /* HOST TT status and control */ |
145 | u32 burstsize; /* Programmable Burst Size */ |
146 | u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */ |
147 | u32 reserved[4]; |
148 | u32 epnak; /* Endpoint NAK */ |
149 | u32 epnaken; /* Endpoint NAK Enable */ |
150 | u32 configflag; /* Configured Flag register */ |
151 | u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */ |
152 | u32 otgsc; |
153 | u32 usbmode; /* USB Host/Device mode */ |
154 | u32 epsetupstat; /* Endpoint Setup Status */ |
155 | u32 epprime; /* Endpoint Initialize */ |
156 | u32 epflush; /* Endpoint De-initialize */ |
157 | u32 epstatus; /* Endpoint Status */ |
158 | u32 epcomplete; /* Endpoint Interrupt On Complete */ |
159 | u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */ |
160 | u32 mcr; /* Mux Control */ |
161 | u32 isr; /* Interrupt Status */ |
162 | u32 ier; /* Interrupt Enable */ |
163 | }; |
164 | |
165 | struct mv_udc { |
166 | struct usb_gadget gadget; |
167 | struct usb_gadget_driver *driver; |
168 | spinlock_t lock; |
169 | struct completion *done; |
170 | struct platform_device *dev; |
171 | int irq; |
172 | |
173 | struct mv_cap_regs __iomem *cap_regs; |
174 | struct mv_op_regs __iomem *op_regs; |
175 | unsigned int phy_regs; |
176 | unsigned int max_eps; |
177 | struct mv_dqh *ep_dqh; |
178 | size_t ep_dqh_size; |
179 | dma_addr_t ep_dqh_dma; |
180 | |
181 | struct dma_pool *dtd_pool; |
182 | struct mv_ep *eps; |
183 | |
184 | struct mv_dtd *dtd_head; |
185 | struct mv_dtd *dtd_tail; |
186 | unsigned int dtd_entries; |
187 | |
188 | struct mv_req *status_req; |
189 | struct usb_ctrlrequest local_setup_buff; |
190 | |
191 | unsigned int resume_state; /* USB state to resume */ |
192 | unsigned int usb_state; /* USB current state */ |
193 | unsigned int ep0_state; /* Endpoint zero state */ |
194 | unsigned int ep0_dir; |
195 | |
196 | unsigned int dev_addr; |
197 | |
198 | int errors; |
199 | unsigned softconnect:1, |
200 | vbus_active:1, |
201 | remote_wakeup:1, |
202 | softconnected:1, |
203 | force_fs:1; |
204 | struct clk *clk; |
205 | }; |
206 | |
207 | /* endpoint data structure */ |
208 | struct mv_ep { |
209 | struct usb_ep ep; |
210 | struct mv_udc *udc; |
211 | struct list_head queue; |
212 | struct mv_dqh *dqh; |
213 | const struct usb_endpoint_descriptor *desc; |
214 | u32 direction; |
215 | char name[14]; |
216 | unsigned stopped:1, |
217 | wedge:1, |
218 | ep_type:2, |
219 | ep_num:8; |
220 | }; |
221 | |
222 | /* request data structure */ |
223 | struct mv_req { |
224 | struct usb_request req; |
225 | struct mv_dtd *dtd, *head, *tail; |
226 | struct mv_ep *ep; |
227 | struct list_head queue; |
228 | unsigned dtd_count; |
229 | unsigned mapped:1; |
230 | }; |
231 | |
232 | #define EP_QUEUE_HEAD_MULT_POS 30 |
233 | #define EP_QUEUE_HEAD_ZLT_SEL 0x20000000 |
234 | #define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16 |
235 | #define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff) |
236 | #define EP_QUEUE_HEAD_IOS 0x00008000 |
237 | #define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001 |
238 | #define EP_QUEUE_HEAD_IOC 0x00008000 |
239 | #define EP_QUEUE_HEAD_MULTO 0x00000C00 |
240 | #define EP_QUEUE_HEAD_STATUS_HALT 0x00000040 |
241 | #define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080 |
242 | #define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF |
243 | #define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0 |
244 | #define EP_QUEUE_FRINDEX_MASK 0x000007FF |
245 | #define EP_MAX_LENGTH_TRANSFER 0x4000 |
246 | |
247 | struct mv_dqh { |
248 | /* Bits 16..26 Bit 15 is Interrupt On Setup */ |
249 | u32 max_packet_length; |
250 | u32 curr_dtd_ptr; /* Current dTD Pointer */ |
251 | u32 next_dtd_ptr; /* Next dTD Pointer */ |
252 | /* Total bytes (16..30), IOC (15), INT (8), STS (0-7) */ |
253 | u32 size_ioc_int_sts; |
254 | u32 buff_ptr0; /* Buffer pointer Page 0 (12-31) */ |
255 | u32 buff_ptr1; /* Buffer pointer Page 1 (12-31) */ |
256 | u32 buff_ptr2; /* Buffer pointer Page 2 (12-31) */ |
257 | u32 buff_ptr3; /* Buffer pointer Page 3 (12-31) */ |
258 | u32 buff_ptr4; /* Buffer pointer Page 4 (12-31) */ |
259 | u32 reserved1; |
260 | /* 8 bytes of setup data that follows the Setup PID */ |
261 | u8 setup_buffer[8]; |
262 | u32 reserved2[4]; |
263 | }; |
264 | |
265 | |
266 | #define DTD_NEXT_TERMINATE (0x00000001) |
267 | #define DTD_IOC (0x00008000) |
268 | #define DTD_STATUS_ACTIVE (0x00000080) |
269 | #define DTD_STATUS_HALTED (0x00000040) |
270 | #define DTD_STATUS_DATA_BUFF_ERR (0x00000020) |
271 | #define DTD_STATUS_TRANSACTION_ERR (0x00000008) |
272 | #define DTD_RESERVED_FIELDS (0x00007F00) |
273 | #define DTD_ERROR_MASK (0x68) |
274 | #define DTD_ADDR_MASK (0xFFFFFFE0) |
275 | #define DTD_PACKET_SIZE 0x7FFF0000 |
276 | #define DTD_LENGTH_BIT_POS (16) |
277 | |
278 | struct mv_dtd { |
279 | u32 dtd_next; |
280 | u32 size_ioc_sts; |
281 | u32 buff_ptr0; /* Buffer pointer Page 0 */ |
282 | u32 buff_ptr1; /* Buffer pointer Page 1 */ |
283 | u32 buff_ptr2; /* Buffer pointer Page 2 */ |
284 | u32 buff_ptr3; /* Buffer pointer Page 3 */ |
285 | u32 buff_ptr4; /* Buffer pointer Page 4 */ |
286 | u32 scratch_ptr; |
287 | /* 32 bytes */ |
288 | dma_addr_t td_dma; /* dma address for this td */ |
289 | struct mv_dtd *next_dtd_virt; |
290 | }; |
291 | |
292 | extern int mv_udc_phy_init(unsigned int base); |
293 | |
294 | #endif |
295 |
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