Root/drivers/ieee802154/adf7242.c

1/*
2 * Analog Devices ADF7242 Low-Power IEEE 802.15.4 Transceiver
3 *
4 * Copyright 2009-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/interrupt.h>
12#include <linux/delay.h>
13#include <linux/mutex.h>
14#include <linux/workqueue.h>
15#include <linux/spinlock.h>
16#include <linux/firmware.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/adf7242.h>
19
20#include <net/mac802154.h>
21#include <net/wpan-phy.h>
22
23/*
24 * DEBUG LEVEL
25 * 0 OFF
26 * 1 INFO
27 * 2 INFO + TRACE
28 */
29
30#define ADF_DEBUG 0
31#define DBG(n, args...) do { if (ADF_DEBUG >= (n)) pr_debug(args); } while (0)
32
33#define FIRMWARE "adf7242_firmware.bin"
34#define MAX_POLL_LOOPS 10
35
36/* All Registers */
37
38#define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control configuration bits */
39#define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */
40#define REG_CCA1 0x105 /* RW RSSI threshold for CCA */
41#define REG_CCA2 0x106 /* RW CCA mode configuration */
42#define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */
43#define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */
44#define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word search delay */
45#define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */
46#define REG_DELAYCFG2 0x10B /* RW Mac delay extention */
47#define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */
48#define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */
49#define REG_SYNC_WORD2 0x10E /* RW sync word bits [23:16] of [23:0] */
50#define REG_SYNC_CONFIG 0x10F /* RW sync word configuration */
51#define REG_RC_CFG 0x13E /* RW RX / TX packet configuration */
52#define REG_RC_VAR44 0x13F /* RW RESERVED */
53#define REG_CH_FREQ0 0x300 /* RW Channel Frequency Settings - Low Byte */
54#define REG_CH_FREQ1 0x301 /* RW Channel Frequency Settings - Middle Byte */
55#define REG_CH_FREQ2 0x302 /* RW Channel Frequency Settings - 2 MSBs */
56#define REG_TX_FD 0x304 /* RW TX Frequency Deviation Register */
57#define REG_DM_CFG0 0x305 /* RW RX Discriminator BW Register */
58#define REG_TX_M 0x306 /* RW TX Mode Register */
59#define REG_RX_M 0x307 /* RW RX Mode Register */
60#define REG_RRB 0x30C /* R RSSI Readback Register */
61#define REG_LRB 0x30D /* R Link Quality Readback Register */
62#define REG_DR0 0x30E /* RW bits [15:8] of [15:0] for data rate setting */
63#define REG_DR1 0x30F /* RW bits [7:0] of [15:0] for data rate setting */
64#define REG_PRAMPG 0x313 /* RW RESERVED */
65#define REG_TXPB 0x314 /* RW TX Packet Storage Base Address */
66#define REG_RXPB 0x315 /* RW RX Packet Storage Base Address */
67#define REG_TMR_CFG0 0x316 /* RW Wake up Timer Configuration Register - High Byte */
68#define REG_TMR_CFG1 0x317 /* RW Wake up Timer Configuration Register - Low Byte */
69#define REG_TMR_RLD0 0x318 /* RW Wake up Timer Value Register - High Byte */
70#define REG_TMR_RLD1 0x319 /* RW Wake up Timer Value Register - Low Byte */
71#define REG_TMR_CTRL 0x31A /* RW Wake up Timer Timeout flag */
72#define REG_PD_AUX 0x31E /* RW Battmon enable */
73#define REG_GP_CFG 0x32C /* RW GPIO Configuration */
74#define REG_GP_OUT 0x32D /* RW GPIO Configuration */
75#define REG_GP_IN 0x32E /* R GPIO Configuration */
76#define REG_SYNT 0x335 /* RW bandwidth calibration timers */
77#define REG_CAL_CFG 0x33D /* RW Calibration Settings */
78#define REG_SYNT_CAL 0x371 /* RW Oscillator and Doubler Configuration */
79#define REG_IIRF_CFG 0x389 /* RW BB Filter Decimation Rate */
80#define REG_CDR_CFG 0x38A /* RW CDR kVCO */
81#define REG_DM_CFG1 0x38B /* RW Postdemodulator Filter */
82#define REG_AGCSTAT 0x38E /* R RXBB Ref Osc Calibration Engine Readback */
83#define REG_RXCAL0 0x395 /* RW RX BB filter tuning, LSB */
84#define REG_RXCAL1 0x396 /* RW RX BB filter tuning, MSB */
85#define REG_RXFE_CFG 0x39B /* RW RXBB Ref Osc & RXFE Calibration */
86#define REG_PA_RR 0x3A7 /* RW Set PA ramp rate */
87#define REG_PA_CFG 0x3A8 /* RW PA enable */
88#define REG_EXTPA_CFG 0x3A9 /* RW External PA BIAS DAC */
89#define REG_EXTPA_MSC 0x3AA /* RW PA Bias Mode */
90#define REG_ADC_RBK 0x3AE /* R Readback temp */
91#define REG_AGC_CFG1 0x3B2 /* RW GC Parameters */
92#define REG_AGC_MAX 0x3B4 /* RW Slew rate */
93#define REG_AGC_CFG2 0x3B6 /* RW RSSI Parameters */
94#define REG_AGC_CFG3 0x3B7 /* RW RSSI Parameters */
95#define REG_AGC_CFG4 0x3B8 /* RW RSSI Parameters */
96#define REG_AGC_CFG5 0x3B9 /* RW RSSI & NDEC Parameters */
97#define REG_AGC_CFG6 0x3BA /* RW NDEC Parameters */
98#define REG_OCL_CFG1 0x3C4 /* RW OCL System Parameters */
99#define REG_IRQ1_EN0 0x3C7 /* RW Interrupt Mask set bits [7:0] of [15:0] for IRQ1 */
100#define REG_IRQ1_EN1 0x3C8 /* RW Interrupt Mask set bits [15:8] of [15:0] for IRQ1 */
101#define REG_IRQ2_EN0 0x3C9 /* RW Interrupt Mask set bits [7:0] of [15:0] for IRQ2 */
102#define REG_IRQ2_EN1 0x3CA /* RW Interrupt Mask set bits [15:8] of [15:0] for IRQ2 */
103#define REG_IRQ1_SRC0 0x3CB /* RW Interrupt Source bits [7:0] of [15:0] for IRQ */
104#define REG_IRQ1_SRC1 0x3CC /* RW Interrupt Source bits [15:8] of [15:0] for IRQ */
105#define REG_OCL_BW0 0x3D2 /* RW OCL System Parameters */
106#define REG_OCL_BW1 0x3D3 /* RW OCL System Parameters */
107#define REG_OCL_BW2 0x3D4 /* RW OCL System Parameters */
108#define REG_OCL_BW3 0x3D5 /* RW OCL System Parameters */
109#define REG_OCL_BW4 0x3D6 /* RW OCL System Parameters */
110#define REG_OCL_BWS 0x3D7 /* RW OCL System Parameters */
111#define REG_OCL_CFG13 0x3E0 /* RW OCL System Parameters */
112#define REG_GP_DRV 0x3E3 /* RW I/O pads Configuration and bg trim */
113#define REG_BM_CFG 0x3E6 /* RW Battery Monitor Threshold Voltage setting */
114#define REG_SFD_15_4 0x3F4 /* RW Option to set non standard SFD */
115#define REG_AFC_CFG 0x3F7 /* RW AFC mode and polarity */
116#define REG_AFC_KI_KP 0x3F8 /* RW AFC ki and kp */
117#define REG_AFC_RANGE 0x3F9 /* RW AFC range */
118#define REG_AFC_READ 0x3FA /* RW Readback frequency error */
119
120#define REG_PAN_ID0 0x112
121#define REG_PAN_ID1 0x113
122#define REG_SHORT_ADDR_0 0x114
123#define REG_SHORT_ADDR_1 0x115
124#define REG_IEEE_ADDR_0 0x116
125#define REG_IEEE_ADDR_1 0x117
126#define REG_IEEE_ADDR_2 0x118
127#define REG_IEEE_ADDR_3 0x119
128#define REG_IEEE_ADDR_4 0x11A
129#define REG_IEEE_ADDR_5 0x11B
130#define REG_IEEE_ADDR_6 0x11C
131#define REG_IEEE_ADDR_7 0x11D
132#define REG_FFILT_CFG 0x11E
133#define REG_AUTO_CFG 0x11F
134#define REG_AUTO_TX1 0x120
135#define REG_AUTO_TX2 0x121
136#define REG_AUTO_STATUS 0x122
137
138/* REG_FFILT_CFG */
139#define ACCEPT_BEACON_FRAMES (1 << 0)
140#define ACCEPT_DATA_FRAMES (1 << 1)
141#define ACCEPT_ACK_FRAMES (1 << 2)
142#define ACCEPT_MACCMD_FRAMES (1 << 3)
143#define ACCEPT_RESERVED_FRAMES (1 << 4)
144#define ACCEPT_ALL_ADDRESS (1 << 5)
145
146/* REG_AUTO_CFG */
147#define AUTO_ACK_FRAMEPEND (1 << 0)
148#define IS_PANCOORD (1 << 1)
149#define RX_AUTO_ACK_EN (1 << 3)
150#define CSMA_CA_RX_TURNAROUND (1 << 4)
151
152/* REG_AUTO_TX1 */
153#define MAX_FRAME_RETRIES(x) ((x) & 0xF)
154#define MAX_CCA_RETRIES(x) (((x) & 0x7) << 4)
155
156/* REG_AUTO_TX2 */
157#define CSMA_MAX_BE(x) ((x) & 0xF)
158#define CSMA_MIN_BE(x) (((x) & 0xF) << 4)
159
160#define CMD_SPI_NOP 0xFF /* No operation. Use for dummy writes */
161#define CMD_SPI_PKT_WR 0x10 /* Write telegram to the Packet RAM starting from the TX packet base address pointer tx_packet_base */
162#define CMD_SPI_PKT_RD 0x30 /* Read telegram from the Packet RAM starting from RX packet base address pointer rxpb.rx_packet_base */
163#define CMD_SPI_MEM_WR(x) (0x18 + (x >> 8)) /* Write data to MCR or Packet RAM sequentially */
164#define CMD_SPI_MEM_RD(x) (0x38 + (x >> 8)) /* Read data from MCR or Packet RAM sequentially */
165#define CMD_SPI_MEMR_WR(x) (0x08 + (x >> 8)) /* Write data to MCR or Packet RAM as random block */
166#define CMD_SPI_MEMR_RD(x) (0x28 + (x >> 8)) /* Read data from MCR or Packet RAM as random block */
167#define CMD_SPI_PRAM_WR 0x1E /* Write data sequentially to current PRAM page selected */
168#define CMD_RC_SLEEP 0xB1 /* Invoke transition of radio controller into SLEEP state */
169#define CMD_RC_IDLE 0xB2 /* Invoke transition of radio controller into IDLE state */
170#define CMD_RC_PHY_RDY 0xB3 /* Invoke transition of radio controller into PHY_RDY state */
171#define CMD_RC_RX 0xB4 /* Invoke transition of radio controller into RX state */
172#define CMD_RC_TX 0xB5 /* Invoke transition of radio controller into TX state */
173#define CMD_RC_MEAS 0xB6 /* Invoke transition of radio controller into MEAS state */
174#define CMD_RC_CCA 0xB7 /* Invoke Clear channel assessment */
175#define CMD_RC_CSMACA 0xC1 /* initiates CSMA-CA channel access sequence and frame transmission */
176
177/* STATUS */
178
179#define STAT_SPI_READY (1 << 7)
180#define STAT_IRQ_STATUS (1 << 6)
181#define STAT_RC_READY (1 << 5)
182#define STAT_CCA_RESULT (1 << 4)
183#define RC_STATUS_IDLE 1
184#define RC_STATUS_MEAS 2
185#define RC_STATUS_PHY_RDY 3
186#define RC_STATUS_RX 4
187#define RC_STATUS_TX 5
188#define RC_STATUS_MASK 0xF
189
190/* AUTO_STATUS */
191
192#define SUCCESS 0
193#define SUCCESS_DATPEND 1
194#define FAILURE_CSMACA 2
195#define FAILURE_NOACK 3
196#define AUTO_STATUS_MASK 0x3
197
198#define PRAM_PAGESIZE 256
199
200/* IRQ1 */
201
202#define IRQ_CCA_COMPLETE (1 << 0)
203#define IRQ_SFD_RX (1 << 1)
204#define IRQ_SFD_TX (1 << 2)
205#define IRQ_RX_PKT_RCVD (1 << 3)
206#define IRQ_TX_PKT_SENT (1 << 4)
207#define IRQ_FRAME_VALID (1 << 5)
208#define IRQ_ADDRESS_VALID (1 << 6)
209#define IRQ_CSMA_CA (1 << 7)
210
211#define AUTO_TX_TURNAROUND (1 << 3)
212#define ADDON_EN (1 << 4)
213
214struct adf7242_local {
215       struct spi_device *spi;
216       struct adf7242_platform_data *pdata;
217       struct work_struct irqwork;
218       struct completion tx_complete;
219       struct ieee802154_dev *dev;
220       struct mutex bmux;
221       spinlock_t lock;
222       unsigned irq_disabled:1; /* P: lock */
223       unsigned is_tx:1; /* P: lock */
224       unsigned mode;
225       unsigned tx_irq;
226       int tx_stat;
227       u8 buf[3];
228};
229
230static int adf7242_status(struct adf7242_local *lp, u8 *stat)
231{
232       int status;
233       struct spi_message msg;
234       u8 buf_tx[1], buf_rx[1];
235
236       struct spi_transfer xfer = {
237               .len = 1,
238               .tx_buf = buf_tx,
239               .rx_buf = buf_rx,
240       };
241
242       buf_tx[0] = CMD_SPI_NOP;
243
244       spi_message_init(&msg);
245       spi_message_add_tail(&xfer, &msg);
246
247       mutex_lock(&lp->bmux);
248       status = spi_sync(lp->spi, &msg);
249       mutex_unlock(&lp->bmux);
250
251       *stat = buf_rx[0];
252
253       return status;
254}
255
256static int adf7242_wait_ready(struct adf7242_local *lp)
257{
258       u8 stat;
259       int cnt = 0;
260
261       DBG(2, "%s :Enter\n", __func__);
262
263       do {
264               adf7242_status(lp, &stat);
265               cnt++;
266       } while (!(stat & STAT_RC_READY) && (cnt < MAX_POLL_LOOPS));
267
268       DBG(2, "%s :Exit loops=%d\n", __func__, cnt);
269
270       return 0;
271}
272
273static int adf7242_wait_status(struct adf7242_local *lp, int status)
274{
275       u8 stat;
276       int cnt = 0;
277
278       DBG(2, "%s :Enter\n", __func__);
279
280       do {
281               adf7242_status(lp, &stat);
282               stat &= RC_STATUS_MASK;
283               cnt++;
284       } while ((stat != status) && (cnt < MAX_POLL_LOOPS));
285
286       DBG(2, "%s :Exit loops=%d\n", __func__, cnt);
287
288       return 0;
289}
290
291static int adf7242_write_fbuf(struct adf7242_local *lp, u8 *data, u8 len)
292{
293       u8 *buf = lp->buf;
294       int status;
295       struct spi_message msg;
296       struct spi_transfer xfer_head = {
297               .len = 2,
298               .tx_buf = buf,
299
300       };
301       struct spi_transfer xfer_buf = {
302               .len = len,
303               .tx_buf = data,
304       };
305
306       DBG(2, "%s :Enter\n", __func__);
307       adf7242_wait_ready(lp);
308
309       buf[0] = CMD_SPI_PKT_WR;
310       buf[1] = len + 2;
311
312       spi_message_init(&msg);
313       spi_message_add_tail(&xfer_head, &msg);
314       spi_message_add_tail(&xfer_buf, &msg);
315
316       mutex_lock(&lp->bmux);
317       status = spi_sync(lp->spi, &msg);
318       mutex_unlock(&lp->bmux);
319
320       DBG(2, "%s :Exit\n", __func__);
321       return status;
322}
323
324static int adf7242_read_fbuf(struct adf7242_local *lp,
325                            u8 *data, u8 *len, u8 *lqi)
326{
327       u8 *buf = lp->buf;
328       int status;
329       struct spi_message msg;
330       struct spi_transfer xfer_head = {
331               .len = 3,
332               .tx_buf = buf,
333               .rx_buf = buf,
334
335       };
336       struct spi_transfer xfer_buf = {
337               .len = *len,
338               .rx_buf = data,
339       };
340
341       DBG(2, "%s :Enter\n", __func__);
342       adf7242_wait_ready(lp);
343
344       mutex_lock(&lp->bmux);
345       buf[0] = CMD_SPI_PKT_RD;
346       buf[1] = CMD_SPI_NOP;
347       buf[2] = 0; /* PHR */
348
349       spi_message_init(&msg);
350       spi_message_add_tail(&xfer_head, &msg);
351       spi_message_add_tail(&xfer_buf, &msg);
352
353       status = spi_sync(lp->spi, &msg);
354
355       if (!status) {
356               *lqi = data[buf[2] - 1];
357               *len = buf[2]; /* PHR */
358       }
359
360       mutex_unlock(&lp->bmux);
361       DBG(2, "%s :Exit\n", __func__);
362       return status;
363}
364
365static int adf7242_read_reg(struct adf7242_local *lp,
366                           u16 addr, u8 *data)
367{
368       int status;
369       struct spi_message msg;
370       u8 buf_tx[4], buf_rx[4];
371
372       struct spi_transfer xfer = {
373               .len = 4,
374               .tx_buf = buf_tx,
375               .rx_buf = buf_rx,
376       };
377
378       DBG(2, "%s :Enter\n", __func__);
379       adf7242_wait_ready(lp);
380
381       mutex_lock(&lp->bmux);
382       buf_tx[0] = CMD_SPI_MEM_RD(addr);
383       buf_tx[1] = addr;
384       buf_tx[2] = CMD_SPI_NOP;
385       buf_tx[3] = CMD_SPI_NOP;
386
387       spi_message_init(&msg);
388       spi_message_add_tail(&xfer, &msg);
389
390       status = spi_sync(lp->spi, &msg);
391       if (msg.status)
392               status = msg.status;
393
394       if (!status)
395               *data = buf_rx[3];
396
397       mutex_unlock(&lp->bmux);
398       DBG(2, "%s :Exit\n", __func__);
399
400       return status;
401}
402
403static int adf7242_write_reg(struct adf7242_local *lp,
404                            u16 addr, u8 data)
405{
406       int status;
407       struct spi_message msg;
408       u8 buf_tx[4];
409
410       struct spi_transfer xfer = {
411               .len = 3,
412               .tx_buf = buf_tx,
413       };
414       DBG(2, "%s :Enter\n", __func__);
415       adf7242_wait_ready(lp);
416
417       buf_tx[0] = CMD_SPI_MEM_WR(addr);
418       buf_tx[1] = addr;
419       buf_tx[2] = data;
420
421       spi_message_init(&msg);
422       spi_message_add_tail(&xfer, &msg);
423
424       mutex_lock(&lp->bmux);
425       status = spi_sync(lp->spi, &msg);
426       mutex_unlock(&lp->bmux);
427       DBG(2, "%s :Exit\n", __func__);
428
429       return status;
430}
431
432static int adf7242_cmd(struct adf7242_local *lp, u8 cmd)
433{
434       int status;
435       struct spi_message msg;
436       u8 buf_tx[1];
437
438       struct spi_transfer xfer = {
439               .len = 1,
440               .tx_buf = buf_tx,
441       };
442
443       DBG(2, "%s :Enter CMD=0x%X\n", __func__, cmd);
444       adf7242_wait_ready(lp);
445
446       buf_tx[0] = cmd;
447       spi_message_init(&msg);
448       spi_message_add_tail(&xfer, &msg);
449
450       mutex_lock(&lp->bmux);
451       status = spi_sync(lp->spi, &msg);
452       mutex_unlock(&lp->bmux);
453       DBG(2, "%s :Exit\n", __func__);
454
455       return status;
456}
457
458static int adf7242_upload_firmware(struct adf7242_local *lp,
459                                  u8 *data, u16 len)
460{
461       int status, i, page = 0;
462       struct spi_message msg;
463       struct spi_transfer xfer_buf = {};
464       u8 buf[2];
465
466       struct spi_transfer xfer_head = {
467               .len = 2,
468               .tx_buf = buf,
469       };
470
471       buf[0] = CMD_SPI_PRAM_WR;
472       buf[1] = 0;
473
474       for (i = len; i >= 0 ; i -= PRAM_PAGESIZE) {
475               adf7242_write_reg(lp, REG_PRAMPG, page);
476
477               xfer_buf.len = i >= PRAM_PAGESIZE ? PRAM_PAGESIZE : i,
478               xfer_buf.tx_buf = &data[page * PRAM_PAGESIZE],
479
480               spi_message_init(&msg);
481               spi_message_add_tail(&xfer_head, &msg);
482               spi_message_add_tail(&xfer_buf, &msg);
483
484               mutex_lock(&lp->bmux);
485               status = spi_sync(lp->spi, &msg);
486               mutex_unlock(&lp->bmux);
487               page++;
488       }
489
490       return status;
491}
492
493static int adf7242_ed(struct ieee802154_dev *dev, u8 *level)
494{
495       struct adf7242_local *lp = dev->priv;
496       int ret;
497
498       DBG(2, "%s :Enter\n", __func__);
499#if 0
500       adf7242_cmd(lp, CMD_RC_PHY_RDY);
501       adf7242_cmd(lp, CMD_RC_CCA);
502       adf7242_wait_status(lp, RC_STATUS_PHY_RDY);
503#else
504       udelay(128);
505#endif
506       ret = adf7242_read_reg(lp, REG_RRB, level);
507       adf7242_cmd(lp, CMD_RC_RX);
508       DBG(2, "%s :Exit\n", __func__);
509
510       return ret;
511}
512
513static int adf7242_start(struct ieee802154_dev *dev)
514{
515       struct adf7242_local *lp = dev->priv;
516       int ret;
517
518       DBG(2, "%s :Enter\n", __func__);
519       ret = adf7242_cmd(lp, CMD_RC_RX);
520       DBG(2, "%s :Exit\n", __func__);
521
522       return ret;
523}
524
525static void adf7242_stop(struct ieee802154_dev *dev)
526{
527       struct adf7242_local *lp = dev->priv;
528
529       DBG(2, "%s :Enter\n", __func__);
530       adf7242_cmd(lp, CMD_RC_PHY_RDY);
531       DBG(2, "%s :Exit\n", __func__);
532}
533
534static int adf7242_channel(struct ieee802154_dev *dev, int page, int channel)
535{
536       struct adf7242_local *lp = dev->priv;
537       unsigned long freq;
538
539       DBG(2, "%s :Enter\n", __func__);
540       DBG(1, "%s :Channel=%d\n", __func__, channel);
541
542       might_sleep();
543
544       BUG_ON(page != 0);
545       BUG_ON(channel < 11);
546       BUG_ON(channel > 26);
547
548       freq = (2405 + 5 * (channel - 11)) * 100;
549
550       adf7242_cmd(lp, CMD_RC_PHY_RDY);
551
552       adf7242_write_reg(lp, REG_CH_FREQ0, freq);
553       adf7242_write_reg(lp, REG_CH_FREQ1, freq >> 8);
554       adf7242_write_reg(lp, REG_CH_FREQ2, freq >> 16);
555
556       adf7242_cmd(lp, CMD_RC_RX);
557
558       dev->phy->current_channel = channel;
559       DBG(2, "%s :Exit\n", __func__);
560
561       return 0;
562}
563
564static int adf7242_set_hw_addr_filt(struct ieee802154_dev *dev,
565                                   struct ieee802154_hw_addr_filt *filt,
566                                   unsigned long changed)
567{
568       struct adf7242_local *lp = dev->priv;
569       u8 reg;
570
571       DBG(2, "%s :Enter\n", __func__);
572       DBG(1, "%s :Changed=0x%lX\n", __func__, changed);
573
574       might_sleep();
575
576       if (changed & IEEE802515_IEEEADDR_CHANGED) {
577               adf7242_write_reg(lp, REG_IEEE_ADDR_0, filt->ieee_addr[7]);
578               adf7242_write_reg(lp, REG_IEEE_ADDR_1, filt->ieee_addr[6]);
579               adf7242_write_reg(lp, REG_IEEE_ADDR_2, filt->ieee_addr[5]);
580               adf7242_write_reg(lp, REG_IEEE_ADDR_3, filt->ieee_addr[4]);
581               adf7242_write_reg(lp, REG_IEEE_ADDR_4, filt->ieee_addr[3]);
582               adf7242_write_reg(lp, REG_IEEE_ADDR_5, filt->ieee_addr[2]);
583               adf7242_write_reg(lp, REG_IEEE_ADDR_6, filt->ieee_addr[1]);
584               adf7242_write_reg(lp, REG_IEEE_ADDR_7, filt->ieee_addr[0]);
585       }
586
587       if (changed & IEEE802515_SADDR_CHANGED) {
588               adf7242_write_reg(lp, REG_SHORT_ADDR_0, filt->short_addr);
589               adf7242_write_reg(lp, REG_SHORT_ADDR_1, filt->short_addr >> 8);
590       }
591
592       if (changed & IEEE802515_PANID_CHANGED) {
593               adf7242_write_reg(lp, REG_PAN_ID0, filt->pan_id);
594               adf7242_write_reg(lp, REG_PAN_ID1, filt->pan_id >> 8);
595       }
596
597       if (changed & IEEE802515_PANC_CHANGED) {
598               adf7242_read_reg(lp, REG_AUTO_CFG, &reg);
599               if (filt->pan_coord)
600                       reg |= IS_PANCOORD;
601               else
602                       reg &= ~IS_PANCOORD;
603               adf7242_write_reg(lp, REG_AUTO_CFG, reg);
604       }
605
606       DBG(2, "%s :Exit\n", __func__);
607       return 0;
608}
609
610static int adf7242_xmit(struct ieee802154_dev *dev, struct sk_buff *skb)
611{
612       struct adf7242_local *lp = dev->priv;
613       int ret;
614       unsigned long flags;
615
616       DBG(2, "%s :Enter\n", __func__);
617
618       spin_lock_irqsave(&lp->lock, flags);
619       BUG_ON(lp->is_tx);
620       lp->is_tx = 1;
621       spin_unlock_irqrestore(&lp->lock, flags);
622
623       ret = adf7242_write_fbuf(lp, skb->data, skb->len);
624       if (ret)
625               goto err_rx;
626
627       if (lp->mode & ADF_IEEE802154_AUTO_CSMA_CA) {
628               ret = adf7242_cmd(lp, CMD_RC_PHY_RDY);
629               ret |= adf7242_cmd(lp, CMD_RC_CSMACA);
630       } else {
631               ret = adf7242_cmd(lp, CMD_RC_TX);
632       }
633
634       if (ret)
635               goto err_rx;
636
637       ret = wait_for_completion_interruptible(&lp->tx_complete);
638
639       if (ret < 0)
640               goto err_rx;
641
642       DBG(2, "%s :Exit\n", __func__);
643       return ret;
644
645err_rx:
646       spin_lock_irqsave(&lp->lock, flags);
647       lp->is_tx = 0;
648       spin_unlock_irqrestore(&lp->lock, flags);
649       return ret;
650}
651
652static int adf7242_rx(struct adf7242_local *lp)
653{
654       u8 len = 128;
655       u8 lqi = 0;
656       int ret;
657       struct sk_buff *skb;
658
659       DBG(2, "%s :Enter\n", __func__);
660
661       skb = alloc_skb(len, GFP_KERNEL);
662       if (!skb)
663               return -ENOMEM;
664
665       ret = adf7242_read_fbuf(lp, skb_put(skb, len), &len, &lqi);
666
667       adf7242_cmd(lp, CMD_RC_RX);
668
669       skb_trim(skb, len - 2); /* We do not put RSSI/LQI or CRC into the frame */
670
671       if (len < 2) {
672               kfree_skb(skb);
673               return -EINVAL;
674       }
675
676       ieee802154_rx_irqsafe(lp->dev, skb, lqi);
677
678       DBG(1, "%s: %d %d %x\n", __func__, ret, len, lqi);
679       DBG(2, "%s :Exit\n", __func__);
680
681       return 0;
682}
683
684static struct ieee802154_ops adf7242_ops = {
685       .owner = THIS_MODULE,
686       .xmit = adf7242_xmit,
687       .ed = adf7242_ed,
688       .set_channel = adf7242_channel,
689       .set_hw_addr_filt = adf7242_set_hw_addr_filt,
690       .start = adf7242_start,
691       .stop = adf7242_stop,
692};
693
694static void adf7242_irqwork(struct work_struct *work)
695{
696       struct adf7242_local *lp =
697               container_of(work, struct adf7242_local, irqwork);
698       u8 irq1, auto_stat = 0, stat = 0;
699       int ret;
700       unsigned long flags;
701
702       DBG(2, "%s :Enter\n", __func__);
703
704       ret = adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1);
705
706       DBG(1, "%s IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", __func__, irq1,
707               irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "",
708               irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "",
709               irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "",
710               irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "",
711               irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "",
712               irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "",
713               irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "",
714               irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : "");
715
716       adf7242_status(lp, &stat);
717
718       DBG(1, "%s STATUS = %X:\n%s\n%s%s%s%s%s\n", __func__, stat,
719               stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY",
720               (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "",
721               (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "",
722               (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "",
723               (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "",
724               (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : "");
725
726       adf7242_write_reg(lp, REG_IRQ1_SRC1, irq1);
727
728       if (irq1 & IRQ_RX_PKT_RCVD) {
729
730               /* Wait until ACK is processed */
731               if ((lp->mode & ADF_IEEE802154_HW_AACK) &&
732                       ((stat & RC_STATUS_MASK) != RC_STATUS_PHY_RDY))
733                       adf7242_wait_status(lp, RC_STATUS_PHY_RDY);
734
735               adf7242_rx(lp);
736       }
737
738       if (irq1 & lp->tx_irq) {
739
740               if (lp->mode & ADF_IEEE802154_AUTO_CSMA_CA) {
741                       adf7242_read_reg(lp, REG_AUTO_STATUS, &auto_stat);
742                       auto_stat &= AUTO_STATUS_MASK;
743
744                       DBG(1, "%s AUTO_STATUS = %X:\n%s%s%s%s\n",
745                        __func__, auto_stat,
746                       auto_stat == SUCCESS ? "SUCCESS" : "",
747                       auto_stat == SUCCESS_DATPEND ? "SUCCESS_DATPEND" : "",
748                       auto_stat == FAILURE_CSMACA ? "FAILURE_CSMACA" : "",
749                       auto_stat == FAILURE_NOACK ? "FAILURE_NOACK" : "");
750
751                       /* save CSMA-CA completion status */
752                       lp->tx_stat = auto_stat;
753               }
754               spin_lock_irqsave(&lp->lock, flags);
755               if (lp->is_tx) {
756                       lp->is_tx = 0;
757                       complete(&lp->tx_complete);
758               }
759               spin_unlock_irqrestore(&lp->lock, flags);
760
761               /* in case we just received a frame we are already in PHY_RX */
762
763               if (!(irq1 & IRQ_RX_PKT_RCVD))
764                       adf7242_cmd(lp, CMD_RC_RX);
765       }
766
767       spin_lock_irqsave(&lp->lock, flags);
768       if (lp->irq_disabled) {
769               lp->irq_disabled = 0;
770               enable_irq(lp->spi->irq);
771       }
772       spin_unlock_irqrestore(&lp->lock, flags);
773
774       DBG(2, "%s :Exit\n", __func__);
775}
776
777static irqreturn_t adf7242_isr(int irq, void *data)
778{
779       struct adf7242_local *lp = data;
780
781       DBG(2, "%s :Enter\n", __func__);
782
783       spin_lock(&lp->lock);
784       if (!lp->irq_disabled) {
785               disable_irq_nosync(irq);
786               lp->irq_disabled = 1;
787       }
788       spin_unlock(&lp->lock);
789
790       schedule_work(&lp->irqwork);
791
792       DBG(2, "%s :Exit\n", __func__);
793
794       return IRQ_HANDLED;
795}
796
797
798static int adf7242_hw_init(struct adf7242_local *lp)
799{
800       int ret;
801       const struct firmware *fw;
802
803       DBG(2, "%s :Enter\n", __func__);
804
805       adf7242_cmd(lp, CMD_RC_IDLE);
806
807       if (lp->mode) {
808               /* get ADF7242 addon firmware
809                * build this driver as module
810                * and place under /lib/firmware/adf7242_firmware.bin
811                */
812               ret = request_firmware(&fw, FIRMWARE, &lp->spi->dev);
813               if (ret) {
814                       dev_err(&lp->spi->dev,
815                               "request_firmware() failed with %i\n", ret);
816                       return ret;
817               }
818
819               adf7242_upload_firmware(lp, (u8 *) fw->data, fw->size);
820               release_firmware(fw);
821
822               adf7242_write_reg(lp, REG_FFILT_CFG,
823                       ACCEPT_BEACON_FRAMES |
824                       ACCEPT_DATA_FRAMES |
825                       ACCEPT_ACK_FRAMES |
826                       ACCEPT_MACCMD_FRAMES |
827                       (lp->mode & ADF_IEEE802154_PROMISCUOUS_MODE ?
828                       ACCEPT_ALL_ADDRESS : 0) |
829                       ACCEPT_RESERVED_FRAMES);
830
831               adf7242_write_reg(lp, REG_AUTO_TX1,
832                       MAX_FRAME_RETRIES(lp->pdata->max_frame_retries) |
833                       MAX_CCA_RETRIES(lp->pdata->max_cca_retries));
834
835               adf7242_write_reg(lp, REG_AUTO_TX2,
836                       CSMA_MAX_BE(lp->pdata->max_csma_be) |
837                       CSMA_MIN_BE(lp->pdata->min_csma_be));
838
839               adf7242_write_reg(lp, REG_AUTO_CFG,
840                       (lp->mode & ADF_IEEE802154_HW_AACK ?
841                       RX_AUTO_ACK_EN : 0));
842       }
843
844       adf7242_write_reg(lp, REG_PKT_CFG, lp->mode ? ADDON_EN : 0);
845
846       adf7242_write_reg(lp, REG_EXTPA_MSC, 0xF1);
847       adf7242_write_reg(lp, REG_RXFE_CFG, 0x1D);
848       adf7242_write_reg(lp, REG_IRQ1_EN0, 0);
849
850       adf7242_write_reg(lp, REG_IRQ1_EN1, IRQ_RX_PKT_RCVD | lp->tx_irq);
851
852       adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF);
853       adf7242_write_reg(lp, REG_IRQ1_SRC0, 0xFF);
854
855       adf7242_cmd(lp, CMD_RC_PHY_RDY);
856
857       DBG(2, "%s :Exit\n", __func__);
858
859       return 0;
860}
861
862static int adf7242_suspend(struct spi_device *spi, pm_message_t message)
863{
864       return 0;
865}
866
867static int adf7242_resume(struct spi_device *spi)
868{
869       return 0;
870}
871
872static ssize_t adf7242_show(struct device *dev,
873                           struct device_attribute *devattr,
874                           char *buf)
875{
876       struct adf7242_local *lp = dev_get_drvdata(dev);
877       u8 stat;
878
879       adf7242_status(lp, &stat);
880
881       return sprintf(buf, "STATUS = %X:\n%s\n%s%s%s%s%s\n", stat,
882               stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY",
883               (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "",
884               (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "",
885               (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "",
886               (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "",
887               (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : "");
888
889}
890static DEVICE_ATTR(status, 0664, adf7242_show, NULL);
891
892static struct attribute *adf7242_attributes[] = {
893       &dev_attr_status.attr,
894       NULL
895};
896
897static const struct attribute_group adf7242_attr_group = {
898       .attrs = adf7242_attributes,
899};
900
901static int __devinit adf7242_probe(struct spi_device *spi)
902{
903       struct adf7242_platform_data *pdata = spi->dev.platform_data;
904       struct ieee802154_dev *dev;
905       struct adf7242_local *lp;
906       int ret;
907
908       if (!spi->irq) {
909               dev_err(&spi->dev, "no IRQ specified\n");
910               return -EINVAL;
911       }
912
913       if (!pdata) {
914               dev_err(&spi->dev, "no platform data?\n");
915               return -ENODEV;
916       }
917
918       dev = ieee802154_alloc_device(sizeof(*lp), &adf7242_ops);
919       if (!dev)
920               return -ENOMEM;
921
922       lp = dev->priv;
923       lp->dev = dev;
924       lp->spi = spi;
925       lp->pdata = pdata;
926       lp->mode = pdata->mode;
927
928       dev->priv = lp;
929       dev->parent = &spi->dev;
930       dev->extra_tx_headroom = 0;
931       /* We do support only 2.4 Ghz */
932
933       dev->phy->channels_supported[0] = 0x7FFF800;
934
935       if (!lp->mode) {
936               adf7242_ops.set_hw_addr_filt = NULL;
937               lp->tx_irq = IRQ_TX_PKT_SENT;
938       } else {
939               if ((lp->mode & ADF_IEEE802154_PROMISCUOUS_MODE) &&
940                       (lp->mode & ADF_IEEE802154_HW_AACK))
941                       lp->mode &= ~ADF_IEEE802154_HW_AACK;
942
943               if (lp->mode & ADF_IEEE802154_AUTO_CSMA_CA)
944                       lp->tx_irq = IRQ_CSMA_CA;
945               else
946                       lp->tx_irq = IRQ_TX_PKT_SENT;
947       }
948
949       dev->flags = IEEE802154_HW_OMIT_CKSUM |
950                       (lp->mode & ADF_IEEE802154_HW_AACK ?
951                       IEEE802154_HW_AACK : 0);
952
953       mutex_init(&lp->bmux);
954       INIT_WORK(&lp->irqwork, adf7242_irqwork);
955       spin_lock_init(&lp->lock);
956       init_completion(&lp->tx_complete);
957
958       spi_set_drvdata(spi, lp);
959
960       ret = adf7242_hw_init(lp);
961       if (ret)
962               goto err_hw_init;
963
964       ret = request_irq(spi->irq, adf7242_isr, IRQF_TRIGGER_HIGH,
965                       dev_name(&spi->dev), lp);
966       if (ret)
967               goto err_hw_init;
968
969       ret = ieee802154_register_device(lp->dev);
970       if (ret)
971               goto err_irq;
972
973       dev_set_drvdata(&spi->dev, lp);
974
975       ret = sysfs_create_group(&spi->dev.kobj, &adf7242_attr_group);
976       if (ret)
977               goto out;
978
979       dev_info(&spi->dev, "mac802154 IRQ-%d registered\n", spi->irq);
980
981       return ret;
982
983out:
984       ieee802154_unregister_device(lp->dev);
985err_irq:
986       free_irq(spi->irq, lp);
987       flush_work(&lp->irqwork);
988err_hw_init:
989       spi_set_drvdata(spi, NULL);
990       mutex_destroy(&lp->bmux);
991       ieee802154_free_device(lp->dev);
992       return ret;
993}
994
995static int __devexit adf7242_remove(struct spi_device *spi)
996{
997       struct adf7242_local *lp = spi_get_drvdata(spi);
998
999       ieee802154_unregister_device(lp->dev);
1000       free_irq(spi->irq, lp);
1001       flush_work(&lp->irqwork);
1002       spi_set_drvdata(spi, NULL);
1003       mutex_destroy(&lp->bmux);
1004       ieee802154_free_device(lp->dev);
1005
1006       return 0;
1007}
1008
1009static struct spi_driver adf7242_driver = {
1010       .driver = {
1011               .name = "adf7242",
1012               .owner = THIS_MODULE,
1013       },
1014       .probe = adf7242_probe,
1015       .remove = __devexit_p(adf7242_remove),
1016       .suspend = adf7242_suspend,
1017       .resume = adf7242_resume,
1018};
1019
1020static int __init adf7242_init(void)
1021{
1022       return spi_register_driver(&adf7242_driver);
1023}
1024module_init(adf7242_init);
1025
1026static void __exit adf7242_exit(void)
1027{
1028       spi_unregister_driver(&adf7242_driver);
1029}
1030module_exit(adf7242_exit);
1031
1032MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1033MODULE_DESCRIPTION("ADF7242 Transceiver Driver");
1034MODULE_LICENSE("GPL");
1035

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