Root/drivers/ieee802154/at86rf230.h

1/*
2 * AT86RF230/RF231 register and protocol definitions
3 *
4 * Copyright (C) 2009 Siemens AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Written by:
20 * Dmitry Eremin-Solenikov <dmitry.baryshkov@siemens.com>
21 */
22
23#ifndef ATR86F230_H
24#define ATR86F230_H
25
26#define RG_TRX_STATUS (0x01)
27#define SR_TRX_STATUS 0x01, 0x1f, 0
28#define SR_RESERVED_01_3 0x01, 0x20, 5
29#define SR_CCA_STATUS 0x01, 0x40, 6
30#define SR_CCA_DONE 0x01, 0x80, 7
31#define RG_TRX_STATE (0x02)
32#define SR_TRX_CMD 0x02, 0x1f, 0
33#define SR_TRAC_STATUS 0x02, 0xe0, 5
34#define RG_TRX_CTRL_0 (0x03)
35#define SR_CLKM_CTRL 0x03, 0x07, 0
36#define SR_CLKM_SHA_SEL 0x03, 0x08, 3
37#define SR_PAD_IO_CLKM 0x03, 0x30, 4
38#define SR_PAD_IO 0x03, 0xc0, 6
39#define RG_TRX_CTRL_1 (0x04)
40#define SR_IRQ_POLARITY 0x04, 0x01, 0
41#define SR_IRQ_MASK_MODE 0x04, 0x02, 1
42#define SR_SPI_CMD_MODE 0x04, 0x0c, 2
43#define SR_RX_BL_CTRL 0x04, 0x10, 4
44#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
45#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
46#define SR_PA_EXT_EN 0x04, 0x80, 7
47#define RG_PHY_TX_PWR (0x05)
48#define SR_TX_PWR 0x05, 0x0f, 0
49#define SR_PA_LT 0x05, 0x30, 4
50#define SR_PA_BUF_LT 0x05, 0xc0, 6
51#define RG_PHY_RSSI (0x06)
52#define SR_RSSI 0x06, 0x1f, 0
53#define SR_RND_VALUE 0x06, 0x60, 5
54#define SR_RX_CRC_VALID 0x06, 0x80, 7
55#define RG_PHY_ED_LEVEL (0x07)
56#define SR_ED_LEVEL 0x07, 0xff, 0
57#define RG_PHY_CC_CCA (0x08)
58#define SR_CHANNEL 0x08, 0x1f, 0
59#define SR_CCA_MODE 0x08, 0x60, 5
60#define SR_CCA_REQUEST 0x08, 0x80, 7
61#define RG_CCA_THRES (0x09)
62#define SR_CCA_ED_THRES 0x09, 0x0f, 0
63#define SR_RESERVED_09_1 0x09, 0xf0, 4
64#define RG_RX_CTRL (0x0a)
65#define SR_PDT_THRES 0x0a, 0x0f, 0
66#define SR_RESERVED_0a_1 0x0a, 0xf0, 4
67#define RG_SFD_VALUE (0x0b)
68#define SR_SFD_VALUE 0x0b, 0xff, 0
69#define RG_TRX_CTRL_2 (0x0c)
70#define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
71#define SR_RESERVED_0c_2 0x0c, 0x7c, 2
72#define SR_RX_SAFE_MODE 0x0c, 0x80, 7
73#define RG_ANT_DIV (0x0d)
74#define SR_ANT_CTRL 0x0d, 0x03, 0
75#define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
76#define SR_ANT_DIV_EN 0x0d, 0x08, 3
77#define SR_RESERVED_0d_2 0x0d, 0x70, 4
78#define SR_ANT_SEL 0x0d, 0x80, 7
79#define RG_IRQ_MASK (0x0e)
80#define SR_IRQ_MASK 0x0e, 0xff, 0
81#define RG_IRQ_STATUS (0x0f)
82#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
83#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
84#define SR_IRQ_2_RX_START 0x0f, 0x04, 2
85#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
86#define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
87#define SR_IRQ_5_AMI 0x0f, 0x20, 5
88#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
89#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
90#define RG_VREG_CTRL (0x10)
91#define SR_RESERVED_10_6 0x10, 0x03, 0
92#define SR_DVDD_OK 0x10, 0x04, 2
93#define SR_DVREG_EXT 0x10, 0x08, 3
94#define SR_RESERVED_10_3 0x10, 0x30, 4
95#define SR_AVDD_OK 0x10, 0x40, 6
96#define SR_AVREG_EXT 0x10, 0x80, 7
97#define RG_BATMON (0x11)
98#define SR_BATMON_VTH 0x11, 0x0f, 0
99#define SR_BATMON_HR 0x11, 0x10, 4
100#define SR_BATMON_OK 0x11, 0x20, 5
101#define SR_RESERVED_11_1 0x11, 0xc0, 6
102#define RG_XOSC_CTRL (0x12)
103#define SR_XTAL_TRIM 0x12, 0x0f, 0
104#define SR_XTAL_MODE 0x12, 0xf0, 4
105#define RG_RX_SYN (0x15)
106#define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
107#define SR_RESERVED_15_2 0x15, 0x70, 4
108#define SR_RX_PDT_DIS 0x15, 0x80, 7
109#define RG_XAH_CTRL_1 (0x17)
110#define SR_RESERVED_17_8 0x17, 0x01, 0
111#define SR_AACK_PROM_MODE 0x17, 0x02, 1
112#define SR_AACK_ACK_TIME 0x17, 0x04, 2
113#define SR_RESERVED_17_5 0x17, 0x08, 3
114#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
115#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
116#define SR_RESERVED_17_2 0x17, 0x40, 6
117#define SR_RESERVED_17_1 0x17, 0x80, 7
118#define RG_FTN_CTRL (0x18)
119#define SR_RESERVED_18_2 0x18, 0x7f, 0
120#define SR_FTN_START 0x18, 0x80, 7
121#define RG_PLL_CF (0x1a)
122#define SR_RESERVED_1a_2 0x1a, 0x7f, 0
123#define SR_PLL_CF_START 0x1a, 0x80, 7
124#define RG_PLL_DCU (0x1b)
125#define SR_RESERVED_1b_3 0x1b, 0x3f, 0
126#define SR_RESERVED_1b_2 0x1b, 0x40, 6
127#define SR_PLL_DCU_START 0x1b, 0x80, 7
128#define RG_PART_NUM (0x1c)
129#define SR_PART_NUM 0x1c, 0xff, 0
130#define RG_VERSION_NUM (0x1d)
131#define SR_VERSION_NUM 0x1d, 0xff, 0
132#define RG_MAN_ID_0 (0x1e)
133#define SR_MAN_ID_0 0x1e, 0xff, 0
134#define RG_MAN_ID_1 (0x1f)
135#define SR_MAN_ID_1 0x1f, 0xff, 0
136#define RG_SHORT_ADDR_0 (0x20)
137#define SR_SHORT_ADDR_0 0x20, 0xff, 0
138#define RG_SHORT_ADDR_1 (0x21)
139#define SR_SHORT_ADDR_1 0x21, 0xff, 0
140#define RG_PAN_ID_0 (0x22)
141#define SR_PAN_ID_0 0x22, 0xff, 0
142#define RG_PAN_ID_1 (0x23)
143#define SR_PAN_ID_1 0x23, 0xff, 0
144#define RG_IEEE_ADDR_0 (0x24)
145#define SR_IEEE_ADDR_0 0x24, 0xff, 0
146#define RG_IEEE_ADDR_1 (0x25)
147#define SR_IEEE_ADDR_1 0x25, 0xff, 0
148#define RG_IEEE_ADDR_2 (0x26)
149#define SR_IEEE_ADDR_2 0x26, 0xff, 0
150#define RG_IEEE_ADDR_3 (0x27)
151#define SR_IEEE_ADDR_3 0x27, 0xff, 0
152#define RG_IEEE_ADDR_4 (0x28)
153#define SR_IEEE_ADDR_4 0x28, 0xff, 0
154#define RG_IEEE_ADDR_5 (0x29)
155#define SR_IEEE_ADDR_5 0x29, 0xff, 0
156#define RG_IEEE_ADDR_6 (0x2a)
157#define SR_IEEE_ADDR_6 0x2a, 0xff, 0
158#define RG_IEEE_ADDR_7 (0x2b)
159#define SR_IEEE_ADDR_7 0x2b, 0xff, 0
160#define RG_XAH_CTRL_0 (0x2c)
161#define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
162#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
163#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
164#define RG_CSMA_SEED_0 (0x2d)
165#define SR_CSMA_SEED_0 0x2d, 0xff, 0
166#define RG_CSMA_SEED_1 (0x2e)
167#define SR_CSMA_SEED_1 0x2e, 0x07, 0
168#define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
169#define SR_AACK_DIS_ACK 0x2e, 0x10, 4
170#define SR_AACK_SET_PD 0x2e, 0x20, 5
171#define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
172#define RG_CSMA_BE (0x2f)
173#define SR_MIN_BE 0x2f, 0x0f, 0
174#define SR_MAX_BE 0x2f, 0xf0, 4
175
176#define CMD_REG 0x80
177#define CMD_REG_MASK 0x3f
178#define CMD_WRITE 0x40
179#define CMD_FB 0x20
180
181#define IRQ_BAT_LOW (1 << 7)
182#define IRQ_TRX_UR (1 << 6)
183#define IRQ_AMI (1 << 5)
184#define IRQ_CCA_ED (1 << 4)
185#define IRQ_TRX_END (1 << 3)
186#define IRQ_RX_START (1 << 2)
187#define IRQ_PLL_UNL (1 << 1)
188#define IRQ_PLL_LOCK (1 << 0)
189
190#define STATE_P_ON 0x00 /* BUSY */
191#define STATE_BUSY_RX 0x01
192#define STATE_BUSY_TX 0x02
193#define STATE_FORCE_TRX_OFF 0x03
194#define STATE_FORCE_TX_ON 0x04 /* IDLE */
195/* 0x05 */ /* INVALID_PARAMETER */
196#define STATE_RX_ON 0x06
197/* 0x07 */ /* SUCCESS */
198#define STATE_TRX_OFF 0x08
199#define STATE_TX_ON 0x09
200/* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
201#define STATE_SLEEP 0x0F
202#define STATE_BUSY_RX_AACK 0x11
203#define STATE_BUSY_TX_ARET 0x12
204#define STATE_BUSY_RX_AACK_ON 0x16
205#define STATE_BUSY_TX_ARET_ON 0x19
206#define STATE_RX_ON_NOCLK 0x1C
207#define STATE_RX_AACK_ON_NOCLK 0x1D
208#define STATE_BUSY_RX_AACK_NOCLK 0x1E
209#define STATE_TRANSITION_IN_PROGRESS 0x1F
210
211#endif /* !ATR86F230_H */
212

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