Root/
1 | /* |
2 | * mmc_spi.c - Access SD/MMC cards through SPI master controllers |
3 | * |
4 | * (C) Copyright 2005, Intec Automation, |
5 | * Mike Lavender (mike@steroidmicros) |
6 | * (C) Copyright 2006-2007, David Brownell |
7 | * (C) Copyright 2007, Axis Communications, |
8 | * Hans-Peter Nilsson (hp@axis.com) |
9 | * (C) Copyright 2007, ATRON electronic GmbH, |
10 | * Jan Nikitenko <jan.nikitenko@gmail.com> |
11 | * |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by |
15 | * the Free Software Foundation; either version 2 of the License, or |
16 | * (at your option) any later version. |
17 | * |
18 | * This program is distributed in the hope that it will be useful, |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
21 | * GNU General Public License for more details. |
22 | * |
23 | * You should have received a copy of the GNU General Public License |
24 | * along with this program; if not, write to the Free Software |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
26 | */ |
27 | #include <linux/sched.h> |
28 | #include <linux/delay.h> |
29 | #include <linux/slab.h> |
30 | #include <linux/bio.h> |
31 | #include <linux/dma-mapping.h> |
32 | #include <linux/crc7.h> |
33 | #include <linux/crc-itu-t.h> |
34 | #include <linux/scatterlist.h> |
35 | |
36 | #include <linux/mmc/host.h> |
37 | #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */ |
38 | |
39 | #include <linux/spi/spi.h> |
40 | #include <linux/spi/mmc_spi.h> |
41 | |
42 | #include <asm/unaligned.h> |
43 | |
44 | |
45 | /* NOTES: |
46 | * |
47 | * - For now, we won't try to interoperate with a real mmc/sd/sdio |
48 | * controller, although some of them do have hardware support for |
49 | * SPI protocol. The main reason for such configs would be mmc-ish |
50 | * cards like DataFlash, which don't support that "native" protocol. |
51 | * |
52 | * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to |
53 | * switch between driver stacks, and in any case if "native" mode |
54 | * is available, it will be faster and hence preferable. |
55 | * |
56 | * - MMC depends on a different chipselect management policy than the |
57 | * SPI interface currently supports for shared bus segments: it needs |
58 | * to issue multiple spi_message requests with the chipselect active, |
59 | * using the results of one message to decide the next one to issue. |
60 | * |
61 | * Pending updates to the programming interface, this driver expects |
62 | * that it not share the bus with other drivers (precluding conflicts). |
63 | * |
64 | * - We tell the controller to keep the chipselect active from the |
65 | * beginning of an mmc_host_ops.request until the end. So beware |
66 | * of SPI controller drivers that mis-handle the cs_change flag! |
67 | * |
68 | * However, many cards seem OK with chipselect flapping up/down |
69 | * during that time ... at least on unshared bus segments. |
70 | */ |
71 | |
72 | |
73 | /* |
74 | * Local protocol constants, internal to data block protocols. |
75 | */ |
76 | |
77 | /* Response tokens used to ack each block written: */ |
78 | #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f) |
79 | #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1) |
80 | #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1) |
81 | #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1) |
82 | |
83 | /* Read and write blocks start with these tokens and end with crc; |
84 | * on error, read tokens act like a subset of R2_SPI_* values. |
85 | */ |
86 | #define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */ |
87 | #define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */ |
88 | #define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */ |
89 | |
90 | #define MMC_SPI_BLOCKSIZE 512 |
91 | |
92 | |
93 | /* These fixed timeouts come from the latest SD specs, which say to ignore |
94 | * the CSD values. The R1B value is for card erase (e.g. the "I forgot the |
95 | * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after |
96 | * reads which takes nowhere near that long. Older cards may be able to use |
97 | * shorter timeouts ... but why bother? |
98 | */ |
99 | #define r1b_timeout (HZ * 3) |
100 | |
101 | /* One of the critical speed parameters is the amount of data which may |
102 | * be transfered in one command. If this value is too low, the SD card |
103 | * controller has to do multiple partial block writes (argggh!). With |
104 | * today (2008) SD cards there is little speed gain if we transfer more |
105 | * than 64 KBytes at a time. So use this value until there is any indication |
106 | * that we should do more here. |
107 | */ |
108 | #define MMC_SPI_BLOCKSATONCE 128 |
109 | |
110 | /****************************************************************************/ |
111 | |
112 | /* |
113 | * Local Data Structures |
114 | */ |
115 | |
116 | /* "scratch" is per-{command,block} data exchanged with the card */ |
117 | struct scratch { |
118 | u8 status[29]; |
119 | u8 data_token; |
120 | __be16 crc_val; |
121 | }; |
122 | |
123 | struct mmc_spi_host { |
124 | struct mmc_host *mmc; |
125 | struct spi_device *spi; |
126 | |
127 | unsigned char power_mode; |
128 | u16 powerup_msecs; |
129 | |
130 | struct mmc_spi_platform_data *pdata; |
131 | |
132 | /* for bulk data transfers */ |
133 | struct spi_transfer token, t, crc, early_status; |
134 | struct spi_message m; |
135 | |
136 | /* for status readback */ |
137 | struct spi_transfer status; |
138 | struct spi_message readback; |
139 | |
140 | /* underlying DMA-aware controller, or null */ |
141 | struct device *dma_dev; |
142 | |
143 | /* buffer used for commands and for message "overhead" */ |
144 | struct scratch *data; |
145 | dma_addr_t data_dma; |
146 | |
147 | /* Specs say to write ones most of the time, even when the card |
148 | * has no need to read its input data; and many cards won't care. |
149 | * This is our source of those ones. |
150 | */ |
151 | void *ones; |
152 | dma_addr_t ones_dma; |
153 | }; |
154 | |
155 | |
156 | /****************************************************************************/ |
157 | |
158 | /* |
159 | * MMC-over-SPI protocol glue, used by the MMC stack interface |
160 | */ |
161 | |
162 | static inline int mmc_cs_off(struct mmc_spi_host *host) |
163 | { |
164 | /* chipselect will always be inactive after setup() */ |
165 | return spi_setup(host->spi); |
166 | } |
167 | |
168 | static int |
169 | mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len) |
170 | { |
171 | int status; |
172 | |
173 | if (len > sizeof(*host->data)) { |
174 | WARN_ON(1); |
175 | return -EIO; |
176 | } |
177 | |
178 | host->status.len = len; |
179 | |
180 | if (host->dma_dev) |
181 | dma_sync_single_for_device(host->dma_dev, |
182 | host->data_dma, sizeof(*host->data), |
183 | DMA_FROM_DEVICE); |
184 | |
185 | status = spi_sync_locked(host->spi, &host->readback); |
186 | |
187 | if (host->dma_dev) |
188 | dma_sync_single_for_cpu(host->dma_dev, |
189 | host->data_dma, sizeof(*host->data), |
190 | DMA_FROM_DEVICE); |
191 | |
192 | return status; |
193 | } |
194 | |
195 | static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout, |
196 | unsigned n, u8 byte) |
197 | { |
198 | u8 *cp = host->data->status; |
199 | unsigned long start = jiffies; |
200 | |
201 | while (1) { |
202 | int status; |
203 | unsigned i; |
204 | |
205 | status = mmc_spi_readbytes(host, n); |
206 | if (status < 0) |
207 | return status; |
208 | |
209 | for (i = 0; i < n; i++) { |
210 | if (cp[i] != byte) |
211 | return cp[i]; |
212 | } |
213 | |
214 | if (time_is_before_jiffies(start + timeout)) |
215 | break; |
216 | |
217 | /* If we need long timeouts, we may release the CPU. |
218 | * We use jiffies here because we want to have a relation |
219 | * between elapsed time and the blocking of the scheduler. |
220 | */ |
221 | if (time_is_before_jiffies(start+1)) |
222 | schedule(); |
223 | } |
224 | return -ETIMEDOUT; |
225 | } |
226 | |
227 | static inline int |
228 | mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout) |
229 | { |
230 | return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0); |
231 | } |
232 | |
233 | static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout) |
234 | { |
235 | return mmc_spi_skip(host, timeout, 1, 0xff); |
236 | } |
237 | |
238 | |
239 | /* |
240 | * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol |
241 | * hosts return! The low byte holds R1_SPI bits. The next byte may hold |
242 | * R2_SPI bits ... for SEND_STATUS, or after data read errors. |
243 | * |
244 | * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on |
245 | * newer cards R7 (IF_COND). |
246 | */ |
247 | |
248 | static char *maptype(struct mmc_command *cmd) |
249 | { |
250 | switch (mmc_spi_resp_type(cmd)) { |
251 | case MMC_RSP_SPI_R1: return "R1"; |
252 | case MMC_RSP_SPI_R1B: return "R1B"; |
253 | case MMC_RSP_SPI_R2: return "R2/R5"; |
254 | case MMC_RSP_SPI_R3: return "R3/R4/R7"; |
255 | default: return "?"; |
256 | } |
257 | } |
258 | |
259 | /* return zero, else negative errno after setting cmd->error */ |
260 | static int mmc_spi_response_get(struct mmc_spi_host *host, |
261 | struct mmc_command *cmd, int cs_on) |
262 | { |
263 | u8 *cp = host->data->status; |
264 | u8 *end = cp + host->t.len; |
265 | int value = 0; |
266 | int bitshift; |
267 | u8 leftover = 0; |
268 | unsigned short rotator; |
269 | int i; |
270 | char tag[32]; |
271 | |
272 | snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s", |
273 | cmd->opcode, maptype(cmd)); |
274 | |
275 | /* Except for data block reads, the whole response will already |
276 | * be stored in the scratch buffer. It's somewhere after the |
277 | * command and the first byte we read after it. We ignore that |
278 | * first byte. After STOP_TRANSMISSION command it may include |
279 | * two data bits, but otherwise it's all ones. |
280 | */ |
281 | cp += 8; |
282 | while (cp < end && *cp == 0xff) |
283 | cp++; |
284 | |
285 | /* Data block reads (R1 response types) may need more data... */ |
286 | if (cp == end) { |
287 | cp = host->data->status; |
288 | end = cp+1; |
289 | |
290 | /* Card sends N(CR) (== 1..8) bytes of all-ones then one |
291 | * status byte ... and we already scanned 2 bytes. |
292 | * |
293 | * REVISIT block read paths use nasty byte-at-a-time I/O |
294 | * so it can always DMA directly into the target buffer. |
295 | * It'd probably be better to memcpy() the first chunk and |
296 | * avoid extra i/o calls... |
297 | * |
298 | * Note we check for more than 8 bytes, because in practice, |
299 | * some SD cards are slow... |
300 | */ |
301 | for (i = 2; i < 16; i++) { |
302 | value = mmc_spi_readbytes(host, 1); |
303 | if (value < 0) |
304 | goto done; |
305 | if (*cp != 0xff) |
306 | goto checkstatus; |
307 | } |
308 | value = -ETIMEDOUT; |
309 | goto done; |
310 | } |
311 | |
312 | checkstatus: |
313 | bitshift = 0; |
314 | if (*cp & 0x80) { |
315 | /* Houston, we have an ugly card with a bit-shifted response */ |
316 | rotator = *cp++ << 8; |
317 | /* read the next byte */ |
318 | if (cp == end) { |
319 | value = mmc_spi_readbytes(host, 1); |
320 | if (value < 0) |
321 | goto done; |
322 | cp = host->data->status; |
323 | end = cp+1; |
324 | } |
325 | rotator |= *cp++; |
326 | while (rotator & 0x8000) { |
327 | bitshift++; |
328 | rotator <<= 1; |
329 | } |
330 | cmd->resp[0] = rotator >> 8; |
331 | leftover = rotator; |
332 | } else { |
333 | cmd->resp[0] = *cp++; |
334 | } |
335 | cmd->error = 0; |
336 | |
337 | /* Status byte: the entire seven-bit R1 response. */ |
338 | if (cmd->resp[0] != 0) { |
339 | if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS) |
340 | & cmd->resp[0]) |
341 | value = -EFAULT; /* Bad address */ |
342 | else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0]) |
343 | value = -ENOSYS; /* Function not implemented */ |
344 | else if (R1_SPI_COM_CRC & cmd->resp[0]) |
345 | value = -EILSEQ; /* Illegal byte sequence */ |
346 | else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET) |
347 | & cmd->resp[0]) |
348 | value = -EIO; /* I/O error */ |
349 | /* else R1_SPI_IDLE, "it's resetting" */ |
350 | } |
351 | |
352 | switch (mmc_spi_resp_type(cmd)) { |
353 | |
354 | /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads) |
355 | * and less-common stuff like various erase operations. |
356 | */ |
357 | case MMC_RSP_SPI_R1B: |
358 | /* maybe we read all the busy tokens already */ |
359 | while (cp < end && *cp == 0) |
360 | cp++; |
361 | if (cp == end) |
362 | mmc_spi_wait_unbusy(host, r1b_timeout); |
363 | break; |
364 | |
365 | /* SPI R2 == R1 + second status byte; SEND_STATUS |
366 | * SPI R5 == R1 + data byte; IO_RW_DIRECT |
367 | */ |
368 | case MMC_RSP_SPI_R2: |
369 | /* read the next byte */ |
370 | if (cp == end) { |
371 | value = mmc_spi_readbytes(host, 1); |
372 | if (value < 0) |
373 | goto done; |
374 | cp = host->data->status; |
375 | end = cp+1; |
376 | } |
377 | if (bitshift) { |
378 | rotator = leftover << 8; |
379 | rotator |= *cp << bitshift; |
380 | cmd->resp[0] |= (rotator & 0xFF00); |
381 | } else { |
382 | cmd->resp[0] |= *cp << 8; |
383 | } |
384 | break; |
385 | |
386 | /* SPI R3, R4, or R7 == R1 + 4 bytes */ |
387 | case MMC_RSP_SPI_R3: |
388 | rotator = leftover << 8; |
389 | cmd->resp[1] = 0; |
390 | for (i = 0; i < 4; i++) { |
391 | cmd->resp[1] <<= 8; |
392 | /* read the next byte */ |
393 | if (cp == end) { |
394 | value = mmc_spi_readbytes(host, 1); |
395 | if (value < 0) |
396 | goto done; |
397 | cp = host->data->status; |
398 | end = cp+1; |
399 | } |
400 | if (bitshift) { |
401 | rotator |= *cp++ << bitshift; |
402 | cmd->resp[1] |= (rotator >> 8); |
403 | rotator <<= 8; |
404 | } else { |
405 | cmd->resp[1] |= *cp++; |
406 | } |
407 | } |
408 | break; |
409 | |
410 | /* SPI R1 == just one status byte */ |
411 | case MMC_RSP_SPI_R1: |
412 | break; |
413 | |
414 | default: |
415 | dev_dbg(&host->spi->dev, "bad response type %04x\n", |
416 | mmc_spi_resp_type(cmd)); |
417 | if (value >= 0) |
418 | value = -EINVAL; |
419 | goto done; |
420 | } |
421 | |
422 | if (value < 0) |
423 | dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n", |
424 | tag, cmd->resp[0], cmd->resp[1]); |
425 | |
426 | /* disable chipselect on errors and some success cases */ |
427 | if (value >= 0 && cs_on) |
428 | return value; |
429 | done: |
430 | if (value < 0) |
431 | cmd->error = value; |
432 | mmc_cs_off(host); |
433 | return value; |
434 | } |
435 | |
436 | /* Issue command and read its response. |
437 | * Returns zero on success, negative for error. |
438 | * |
439 | * On error, caller must cope with mmc core retry mechanism. That |
440 | * means immediate low-level resubmit, which affects the bus lock... |
441 | */ |
442 | static int |
443 | mmc_spi_command_send(struct mmc_spi_host *host, |
444 | struct mmc_request *mrq, |
445 | struct mmc_command *cmd, int cs_on) |
446 | { |
447 | struct scratch *data = host->data; |
448 | u8 *cp = data->status; |
449 | u32 arg = cmd->arg; |
450 | int status; |
451 | struct spi_transfer *t; |
452 | |
453 | /* We can handle most commands (except block reads) in one full |
454 | * duplex I/O operation before either starting the next transfer |
455 | * (data block or command) or else deselecting the card. |
456 | * |
457 | * First, write 7 bytes: |
458 | * - an all-ones byte to ensure the card is ready |
459 | * - opcode byte (plus start and transmission bits) |
460 | * - four bytes of big-endian argument |
461 | * - crc7 (plus end bit) ... always computed, it's cheap |
462 | * |
463 | * We init the whole buffer to all-ones, which is what we need |
464 | * to write while we're reading (later) response data. |
465 | */ |
466 | memset(cp++, 0xff, sizeof(data->status)); |
467 | |
468 | *cp++ = 0x40 | cmd->opcode; |
469 | *cp++ = (u8)(arg >> 24); |
470 | *cp++ = (u8)(arg >> 16); |
471 | *cp++ = (u8)(arg >> 8); |
472 | *cp++ = (u8)arg; |
473 | *cp++ = (crc7(0, &data->status[1], 5) << 1) | 0x01; |
474 | |
475 | /* Then, read up to 13 bytes (while writing all-ones): |
476 | * - N(CR) (== 1..8) bytes of all-ones |
477 | * - status byte (for all response types) |
478 | * - the rest of the response, either: |
479 | * + nothing, for R1 or R1B responses |
480 | * + second status byte, for R2 responses |
481 | * + four data bytes, for R3 and R7 responses |
482 | * |
483 | * Finally, read some more bytes ... in the nice cases we know in |
484 | * advance how many, and reading 1 more is always OK: |
485 | * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish |
486 | * - N(RC) (== 1..N) bytes of all-ones, before next command |
487 | * - N(WR) (== 1..N) bytes of all-ones, before data write |
488 | * |
489 | * So in those cases one full duplex I/O of at most 21 bytes will |
490 | * handle the whole command, leaving the card ready to receive a |
491 | * data block or new command. We do that whenever we can, shaving |
492 | * CPU and IRQ costs (especially when using DMA or FIFOs). |
493 | * |
494 | * There are two other cases, where it's not generally practical |
495 | * to rely on a single I/O: |
496 | * |
497 | * - R1B responses need at least N(EC) bytes of all-zeroes. |
498 | * |
499 | * In this case we can *try* to fit it into one I/O, then |
500 | * maybe read more data later. |
501 | * |
502 | * - Data block reads are more troublesome, since a variable |
503 | * number of padding bytes precede the token and data. |
504 | * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID |
505 | * + N(AC) (== 1..many) bytes of all-ones |
506 | * |
507 | * In this case we currently only have minimal speedups here: |
508 | * when N(CR) == 1 we can avoid I/O in response_get(). |
509 | */ |
510 | if (cs_on && (mrq->data->flags & MMC_DATA_READ)) { |
511 | cp += 2; /* min(N(CR)) + status */ |
512 | /* R1 */ |
513 | } else { |
514 | cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */ |
515 | if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */ |
516 | cp++; |
517 | else if (cmd->flags & MMC_RSP_SPI_B4) /* R3/R4/R7 */ |
518 | cp += 4; |
519 | else if (cmd->flags & MMC_RSP_BUSY) /* R1B */ |
520 | cp = data->status + sizeof(data->status); |
521 | /* else: R1 (most commands) */ |
522 | } |
523 | |
524 | dev_dbg(&host->spi->dev, " mmc_spi: CMD%d, resp %s\n", |
525 | cmd->opcode, maptype(cmd)); |
526 | |
527 | /* send command, leaving chipselect active */ |
528 | spi_message_init(&host->m); |
529 | |
530 | t = &host->t; |
531 | memset(t, 0, sizeof(*t)); |
532 | t->tx_buf = t->rx_buf = data->status; |
533 | t->tx_dma = t->rx_dma = host->data_dma; |
534 | t->len = cp - data->status; |
535 | t->cs_change = 1; |
536 | spi_message_add_tail(t, &host->m); |
537 | |
538 | if (host->dma_dev) { |
539 | host->m.is_dma_mapped = 1; |
540 | dma_sync_single_for_device(host->dma_dev, |
541 | host->data_dma, sizeof(*host->data), |
542 | DMA_BIDIRECTIONAL); |
543 | } |
544 | status = spi_sync_locked(host->spi, &host->m); |
545 | |
546 | if (host->dma_dev) |
547 | dma_sync_single_for_cpu(host->dma_dev, |
548 | host->data_dma, sizeof(*host->data), |
549 | DMA_BIDIRECTIONAL); |
550 | if (status < 0) { |
551 | dev_dbg(&host->spi->dev, " ... write returned %d\n", status); |
552 | cmd->error = status; |
553 | return status; |
554 | } |
555 | |
556 | /* after no-data commands and STOP_TRANSMISSION, chipselect off */ |
557 | return mmc_spi_response_get(host, cmd, cs_on); |
558 | } |
559 | |
560 | /* Build data message with up to four separate transfers. For TX, we |
561 | * start by writing the data token. And in most cases, we finish with |
562 | * a status transfer. |
563 | * |
564 | * We always provide TX data for data and CRC. The MMC/SD protocol |
565 | * requires us to write ones; but Linux defaults to writing zeroes; |
566 | * so we explicitly initialize it to all ones on RX paths. |
567 | * |
568 | * We also handle DMA mapping, so the underlying SPI controller does |
569 | * not need to (re)do it for each message. |
570 | */ |
571 | static void |
572 | mmc_spi_setup_data_message( |
573 | struct mmc_spi_host *host, |
574 | int multiple, |
575 | enum dma_data_direction direction) |
576 | { |
577 | struct spi_transfer *t; |
578 | struct scratch *scratch = host->data; |
579 | dma_addr_t dma = host->data_dma; |
580 | |
581 | spi_message_init(&host->m); |
582 | if (dma) |
583 | host->m.is_dma_mapped = 1; |
584 | |
585 | /* for reads, readblock() skips 0xff bytes before finding |
586 | * the token; for writes, this transfer issues that token. |
587 | */ |
588 | if (direction == DMA_TO_DEVICE) { |
589 | t = &host->token; |
590 | memset(t, 0, sizeof(*t)); |
591 | t->len = 1; |
592 | if (multiple) |
593 | scratch->data_token = SPI_TOKEN_MULTI_WRITE; |
594 | else |
595 | scratch->data_token = SPI_TOKEN_SINGLE; |
596 | t->tx_buf = &scratch->data_token; |
597 | if (dma) |
598 | t->tx_dma = dma + offsetof(struct scratch, data_token); |
599 | spi_message_add_tail(t, &host->m); |
600 | } |
601 | |
602 | /* Body of transfer is buffer, then CRC ... |
603 | * either TX-only, or RX with TX-ones. |
604 | */ |
605 | t = &host->t; |
606 | memset(t, 0, sizeof(*t)); |
607 | t->tx_buf = host->ones; |
608 | t->tx_dma = host->ones_dma; |
609 | /* length and actual buffer info are written later */ |
610 | spi_message_add_tail(t, &host->m); |
611 | |
612 | t = &host->crc; |
613 | memset(t, 0, sizeof(*t)); |
614 | t->len = 2; |
615 | if (direction == DMA_TO_DEVICE) { |
616 | /* the actual CRC may get written later */ |
617 | t->tx_buf = &scratch->crc_val; |
618 | if (dma) |
619 | t->tx_dma = dma + offsetof(struct scratch, crc_val); |
620 | } else { |
621 | t->tx_buf = host->ones; |
622 | t->tx_dma = host->ones_dma; |
623 | t->rx_buf = &scratch->crc_val; |
624 | if (dma) |
625 | t->rx_dma = dma + offsetof(struct scratch, crc_val); |
626 | } |
627 | spi_message_add_tail(t, &host->m); |
628 | |
629 | /* |
630 | * A single block read is followed by N(EC) [0+] all-ones bytes |
631 | * before deselect ... don't bother. |
632 | * |
633 | * Multiblock reads are followed by N(AC) [1+] all-ones bytes before |
634 | * the next block is read, or a STOP_TRANSMISSION is issued. We'll |
635 | * collect that single byte, so readblock() doesn't need to. |
636 | * |
637 | * For a write, the one-byte data response follows immediately, then |
638 | * come zero or more busy bytes, then N(WR) [1+] all-ones bytes. |
639 | * Then single block reads may deselect, and multiblock ones issue |
640 | * the next token (next data block, or STOP_TRAN). We can try to |
641 | * minimize I/O ops by using a single read to collect end-of-busy. |
642 | */ |
643 | if (multiple || direction == DMA_TO_DEVICE) { |
644 | t = &host->early_status; |
645 | memset(t, 0, sizeof(*t)); |
646 | t->len = (direction == DMA_TO_DEVICE) |
647 | ? sizeof(scratch->status) |
648 | : 1; |
649 | t->tx_buf = host->ones; |
650 | t->tx_dma = host->ones_dma; |
651 | t->rx_buf = scratch->status; |
652 | if (dma) |
653 | t->rx_dma = dma + offsetof(struct scratch, status); |
654 | t->cs_change = 1; |
655 | spi_message_add_tail(t, &host->m); |
656 | } |
657 | } |
658 | |
659 | /* |
660 | * Write one block: |
661 | * - caller handled preceding N(WR) [1+] all-ones bytes |
662 | * - data block |
663 | * + token |
664 | * + data bytes |
665 | * + crc16 |
666 | * - an all-ones byte ... card writes a data-response byte |
667 | * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy' |
668 | * |
669 | * Return negative errno, else success. |
670 | */ |
671 | static int |
672 | mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t, |
673 | unsigned long timeout) |
674 | { |
675 | struct spi_device *spi = host->spi; |
676 | int status, i; |
677 | struct scratch *scratch = host->data; |
678 | u32 pattern; |
679 | |
680 | if (host->mmc->use_spi_crc) |
681 | scratch->crc_val = cpu_to_be16( |
682 | crc_itu_t(0, t->tx_buf, t->len)); |
683 | if (host->dma_dev) |
684 | dma_sync_single_for_device(host->dma_dev, |
685 | host->data_dma, sizeof(*scratch), |
686 | DMA_BIDIRECTIONAL); |
687 | |
688 | status = spi_sync_locked(spi, &host->m); |
689 | |
690 | if (status != 0) { |
691 | dev_dbg(&spi->dev, "write error (%d)\n", status); |
692 | return status; |
693 | } |
694 | |
695 | if (host->dma_dev) |
696 | dma_sync_single_for_cpu(host->dma_dev, |
697 | host->data_dma, sizeof(*scratch), |
698 | DMA_BIDIRECTIONAL); |
699 | |
700 | /* |
701 | * Get the transmission data-response reply. It must follow |
702 | * immediately after the data block we transferred. This reply |
703 | * doesn't necessarily tell whether the write operation succeeded; |
704 | * it just says if the transmission was ok and whether *earlier* |
705 | * writes succeeded; see the standard. |
706 | * |
707 | * In practice, there are (even modern SDHC-)cards which are late |
708 | * in sending the response, and miss the time frame by a few bits, |
709 | * so we have to cope with this situation and check the response |
710 | * bit-by-bit. Arggh!!! |
711 | */ |
712 | pattern = scratch->status[0] << 24; |
713 | pattern |= scratch->status[1] << 16; |
714 | pattern |= scratch->status[2] << 8; |
715 | pattern |= scratch->status[3]; |
716 | |
717 | /* First 3 bit of pattern are undefined */ |
718 | pattern |= 0xE0000000; |
719 | |
720 | /* left-adjust to leading 0 bit */ |
721 | while (pattern & 0x80000000) |
722 | pattern <<= 1; |
723 | /* right-adjust for pattern matching. Code is in bit 4..0 now. */ |
724 | pattern >>= 27; |
725 | |
726 | switch (pattern) { |
727 | case SPI_RESPONSE_ACCEPTED: |
728 | status = 0; |
729 | break; |
730 | case SPI_RESPONSE_CRC_ERR: |
731 | /* host shall then issue MMC_STOP_TRANSMISSION */ |
732 | status = -EILSEQ; |
733 | break; |
734 | case SPI_RESPONSE_WRITE_ERR: |
735 | /* host shall then issue MMC_STOP_TRANSMISSION, |
736 | * and should MMC_SEND_STATUS to sort it out |
737 | */ |
738 | status = -EIO; |
739 | break; |
740 | default: |
741 | status = -EPROTO; |
742 | break; |
743 | } |
744 | if (status != 0) { |
745 | dev_dbg(&spi->dev, "write error %02x (%d)\n", |
746 | scratch->status[0], status); |
747 | return status; |
748 | } |
749 | |
750 | t->tx_buf += t->len; |
751 | if (host->dma_dev) |
752 | t->tx_dma += t->len; |
753 | |
754 | /* Return when not busy. If we didn't collect that status yet, |
755 | * we'll need some more I/O. |
756 | */ |
757 | for (i = 4; i < sizeof(scratch->status); i++) { |
758 | /* card is non-busy if the most recent bit is 1 */ |
759 | if (scratch->status[i] & 0x01) |
760 | return 0; |
761 | } |
762 | return mmc_spi_wait_unbusy(host, timeout); |
763 | } |
764 | |
765 | /* |
766 | * Read one block: |
767 | * - skip leading all-ones bytes ... either |
768 | * + N(AC) [1..f(clock,CSD)] usually, else |
769 | * + N(CX) [0..8] when reading CSD or CID |
770 | * - data block |
771 | * + token ... if error token, no data or crc |
772 | * + data bytes |
773 | * + crc16 |
774 | * |
775 | * After single block reads, we're done; N(EC) [0+] all-ones bytes follow |
776 | * before dropping chipselect. |
777 | * |
778 | * For multiblock reads, caller either reads the next block or issues a |
779 | * STOP_TRANSMISSION command. |
780 | */ |
781 | static int |
782 | mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t, |
783 | unsigned long timeout) |
784 | { |
785 | struct spi_device *spi = host->spi; |
786 | int status; |
787 | struct scratch *scratch = host->data; |
788 | unsigned int bitshift; |
789 | u8 leftover; |
790 | |
791 | /* At least one SD card sends an all-zeroes byte when N(CX) |
792 | * applies, before the all-ones bytes ... just cope with that. |
793 | */ |
794 | status = mmc_spi_readbytes(host, 1); |
795 | if (status < 0) |
796 | return status; |
797 | status = scratch->status[0]; |
798 | if (status == 0xff || status == 0) |
799 | status = mmc_spi_readtoken(host, timeout); |
800 | |
801 | if (status < 0) { |
802 | dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status); |
803 | return status; |
804 | } |
805 | |
806 | /* The token may be bit-shifted... |
807 | * the first 0-bit precedes the data stream. |
808 | */ |
809 | bitshift = 7; |
810 | while (status & 0x80) { |
811 | status <<= 1; |
812 | bitshift--; |
813 | } |
814 | leftover = status << 1; |
815 | |
816 | if (host->dma_dev) { |
817 | dma_sync_single_for_device(host->dma_dev, |
818 | host->data_dma, sizeof(*scratch), |
819 | DMA_BIDIRECTIONAL); |
820 | dma_sync_single_for_device(host->dma_dev, |
821 | t->rx_dma, t->len, |
822 | DMA_FROM_DEVICE); |
823 | } |
824 | |
825 | status = spi_sync_locked(spi, &host->m); |
826 | |
827 | if (host->dma_dev) { |
828 | dma_sync_single_for_cpu(host->dma_dev, |
829 | host->data_dma, sizeof(*scratch), |
830 | DMA_BIDIRECTIONAL); |
831 | dma_sync_single_for_cpu(host->dma_dev, |
832 | t->rx_dma, t->len, |
833 | DMA_FROM_DEVICE); |
834 | } |
835 | |
836 | if (bitshift) { |
837 | /* Walk through the data and the crc and do |
838 | * all the magic to get byte-aligned data. |
839 | */ |
840 | u8 *cp = t->rx_buf; |
841 | unsigned int len; |
842 | unsigned int bitright = 8 - bitshift; |
843 | u8 temp; |
844 | for (len = t->len; len; len--) { |
845 | temp = *cp; |
846 | *cp++ = leftover | (temp >> bitshift); |
847 | leftover = temp << bitright; |
848 | } |
849 | cp = (u8 *) &scratch->crc_val; |
850 | temp = *cp; |
851 | *cp++ = leftover | (temp >> bitshift); |
852 | leftover = temp << bitright; |
853 | temp = *cp; |
854 | *cp = leftover | (temp >> bitshift); |
855 | } |
856 | |
857 | if (host->mmc->use_spi_crc) { |
858 | u16 crc = crc_itu_t(0, t->rx_buf, t->len); |
859 | |
860 | be16_to_cpus(&scratch->crc_val); |
861 | if (scratch->crc_val != crc) { |
862 | dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, " |
863 | "computed=0x%04x len=%d\n", |
864 | scratch->crc_val, crc, t->len); |
865 | return -EILSEQ; |
866 | } |
867 | } |
868 | |
869 | t->rx_buf += t->len; |
870 | if (host->dma_dev) |
871 | t->rx_dma += t->len; |
872 | |
873 | return 0; |
874 | } |
875 | |
876 | /* |
877 | * An MMC/SD data stage includes one or more blocks, optional CRCs, |
878 | * and inline handshaking. That handhaking makes it unlike most |
879 | * other SPI protocol stacks. |
880 | */ |
881 | static void |
882 | mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd, |
883 | struct mmc_data *data, u32 blk_size) |
884 | { |
885 | struct spi_device *spi = host->spi; |
886 | struct device *dma_dev = host->dma_dev; |
887 | struct spi_transfer *t; |
888 | enum dma_data_direction direction; |
889 | struct scatterlist *sg; |
890 | unsigned n_sg; |
891 | int multiple = (data->blocks > 1); |
892 | u32 clock_rate; |
893 | unsigned long timeout; |
894 | |
895 | if (data->flags & MMC_DATA_READ) |
896 | direction = DMA_FROM_DEVICE; |
897 | else |
898 | direction = DMA_TO_DEVICE; |
899 | mmc_spi_setup_data_message(host, multiple, direction); |
900 | t = &host->t; |
901 | |
902 | if (t->speed_hz) |
903 | clock_rate = t->speed_hz; |
904 | else |
905 | clock_rate = spi->max_speed_hz; |
906 | |
907 | timeout = data->timeout_ns + |
908 | data->timeout_clks * 1000000 / clock_rate; |
909 | timeout = usecs_to_jiffies((unsigned int)(timeout / 1000)) + 1; |
910 | |
911 | /* Handle scatterlist segments one at a time, with synch for |
912 | * each 512-byte block |
913 | */ |
914 | for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) { |
915 | int status = 0; |
916 | dma_addr_t dma_addr = 0; |
917 | void *kmap_addr; |
918 | unsigned length = sg->length; |
919 | enum dma_data_direction dir = direction; |
920 | |
921 | /* set up dma mapping for controller drivers that might |
922 | * use DMA ... though they may fall back to PIO |
923 | */ |
924 | if (dma_dev) { |
925 | /* never invalidate whole *shared* pages ... */ |
926 | if ((sg->offset != 0 || length != PAGE_SIZE) |
927 | && dir == DMA_FROM_DEVICE) |
928 | dir = DMA_BIDIRECTIONAL; |
929 | |
930 | dma_addr = dma_map_page(dma_dev, sg_page(sg), 0, |
931 | PAGE_SIZE, dir); |
932 | if (direction == DMA_TO_DEVICE) |
933 | t->tx_dma = dma_addr + sg->offset; |
934 | else |
935 | t->rx_dma = dma_addr + sg->offset; |
936 | } |
937 | |
938 | /* allow pio too; we don't allow highmem */ |
939 | kmap_addr = kmap(sg_page(sg)); |
940 | if (direction == DMA_TO_DEVICE) |
941 | t->tx_buf = kmap_addr + sg->offset; |
942 | else |
943 | t->rx_buf = kmap_addr + sg->offset; |
944 | |
945 | /* transfer each block, and update request status */ |
946 | while (length) { |
947 | t->len = min(length, blk_size); |
948 | |
949 | dev_dbg(&host->spi->dev, |
950 | " mmc_spi: %s block, %d bytes\n", |
951 | (direction == DMA_TO_DEVICE) |
952 | ? "write" |
953 | : "read", |
954 | t->len); |
955 | |
956 | if (direction == DMA_TO_DEVICE) |
957 | status = mmc_spi_writeblock(host, t, timeout); |
958 | else |
959 | status = mmc_spi_readblock(host, t, timeout); |
960 | if (status < 0) |
961 | break; |
962 | |
963 | data->bytes_xfered += t->len; |
964 | length -= t->len; |
965 | |
966 | if (!multiple) |
967 | break; |
968 | } |
969 | |
970 | /* discard mappings */ |
971 | if (direction == DMA_FROM_DEVICE) |
972 | flush_kernel_dcache_page(sg_page(sg)); |
973 | kunmap(sg_page(sg)); |
974 | if (dma_dev) |
975 | dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir); |
976 | |
977 | if (status < 0) { |
978 | data->error = status; |
979 | dev_dbg(&spi->dev, "%s status %d\n", |
980 | (direction == DMA_TO_DEVICE) |
981 | ? "write" : "read", |
982 | status); |
983 | break; |
984 | } |
985 | } |
986 | |
987 | /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that |
988 | * can be issued before multiblock writes. Unlike its more widely |
989 | * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23), |
990 | * that can affect the STOP_TRAN logic. Complete (and current) |
991 | * MMC specs should sort that out before Linux starts using CMD23. |
992 | */ |
993 | if (direction == DMA_TO_DEVICE && multiple) { |
994 | struct scratch *scratch = host->data; |
995 | int tmp; |
996 | const unsigned statlen = sizeof(scratch->status); |
997 | |
998 | dev_dbg(&spi->dev, " mmc_spi: STOP_TRAN\n"); |
999 | |
1000 | /* Tweak the per-block message we set up earlier by morphing |
1001 | * it to hold single buffer with the token followed by some |
1002 | * all-ones bytes ... skip N(BR) (0..1), scan the rest for |
1003 | * "not busy any longer" status, and leave chip selected. |
1004 | */ |
1005 | INIT_LIST_HEAD(&host->m.transfers); |
1006 | list_add(&host->early_status.transfer_list, |
1007 | &host->m.transfers); |
1008 | |
1009 | memset(scratch->status, 0xff, statlen); |
1010 | scratch->status[0] = SPI_TOKEN_STOP_TRAN; |
1011 | |
1012 | host->early_status.tx_buf = host->early_status.rx_buf; |
1013 | host->early_status.tx_dma = host->early_status.rx_dma; |
1014 | host->early_status.len = statlen; |
1015 | |
1016 | if (host->dma_dev) |
1017 | dma_sync_single_for_device(host->dma_dev, |
1018 | host->data_dma, sizeof(*scratch), |
1019 | DMA_BIDIRECTIONAL); |
1020 | |
1021 | tmp = spi_sync_locked(spi, &host->m); |
1022 | |
1023 | if (host->dma_dev) |
1024 | dma_sync_single_for_cpu(host->dma_dev, |
1025 | host->data_dma, sizeof(*scratch), |
1026 | DMA_BIDIRECTIONAL); |
1027 | |
1028 | if (tmp < 0) { |
1029 | if (!data->error) |
1030 | data->error = tmp; |
1031 | return; |
1032 | } |
1033 | |
1034 | /* Ideally we collected "not busy" status with one I/O, |
1035 | * avoiding wasteful byte-at-a-time scanning... but more |
1036 | * I/O is often needed. |
1037 | */ |
1038 | for (tmp = 2; tmp < statlen; tmp++) { |
1039 | if (scratch->status[tmp] != 0) |
1040 | return; |
1041 | } |
1042 | tmp = mmc_spi_wait_unbusy(host, timeout); |
1043 | if (tmp < 0 && !data->error) |
1044 | data->error = tmp; |
1045 | } |
1046 | } |
1047 | |
1048 | /****************************************************************************/ |
1049 | |
1050 | /* |
1051 | * MMC driver implementation -- the interface to the MMC stack |
1052 | */ |
1053 | |
1054 | static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) |
1055 | { |
1056 | struct mmc_spi_host *host = mmc_priv(mmc); |
1057 | int status = -EINVAL; |
1058 | int crc_retry = 5; |
1059 | struct mmc_command stop; |
1060 | |
1061 | #ifdef DEBUG |
1062 | /* MMC core and layered drivers *MUST* issue SPI-aware commands */ |
1063 | { |
1064 | struct mmc_command *cmd; |
1065 | int invalid = 0; |
1066 | |
1067 | cmd = mrq->cmd; |
1068 | if (!mmc_spi_resp_type(cmd)) { |
1069 | dev_dbg(&host->spi->dev, "bogus command\n"); |
1070 | cmd->error = -EINVAL; |
1071 | invalid = 1; |
1072 | } |
1073 | |
1074 | cmd = mrq->stop; |
1075 | if (cmd && !mmc_spi_resp_type(cmd)) { |
1076 | dev_dbg(&host->spi->dev, "bogus STOP command\n"); |
1077 | cmd->error = -EINVAL; |
1078 | invalid = 1; |
1079 | } |
1080 | |
1081 | if (invalid) { |
1082 | dump_stack(); |
1083 | mmc_request_done(host->mmc, mrq); |
1084 | return; |
1085 | } |
1086 | } |
1087 | #endif |
1088 | |
1089 | /* request exclusive bus access */ |
1090 | spi_bus_lock(host->spi->master); |
1091 | |
1092 | crc_recover: |
1093 | /* issue command; then optionally data and stop */ |
1094 | status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL); |
1095 | if (status == 0 && mrq->data) { |
1096 | mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz); |
1097 | |
1098 | /* |
1099 | * The SPI bus is not always reliable for large data transfers. |
1100 | * If an occasional crc error is reported by the SD device with |
1101 | * data read/write over SPI, it may be recovered by repeating |
1102 | * the last SD command again. The retry count is set to 5 to |
1103 | * ensure the driver passes stress tests. |
1104 | */ |
1105 | if (mrq->data->error == -EILSEQ && crc_retry) { |
1106 | stop.opcode = MMC_STOP_TRANSMISSION; |
1107 | stop.arg = 0; |
1108 | stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; |
1109 | status = mmc_spi_command_send(host, mrq, &stop, 0); |
1110 | crc_retry--; |
1111 | mrq->data->error = 0; |
1112 | goto crc_recover; |
1113 | } |
1114 | |
1115 | if (mrq->stop) |
1116 | status = mmc_spi_command_send(host, mrq, mrq->stop, 0); |
1117 | else |
1118 | mmc_cs_off(host); |
1119 | } |
1120 | |
1121 | /* release the bus */ |
1122 | spi_bus_unlock(host->spi->master); |
1123 | |
1124 | mmc_request_done(host->mmc, mrq); |
1125 | } |
1126 | |
1127 | /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0" |
1128 | * |
1129 | * NOTE that here we can't know that the card has just been powered up; |
1130 | * not all MMC/SD sockets support power switching. |
1131 | * |
1132 | * FIXME when the card is still in SPI mode, e.g. from a previous kernel, |
1133 | * this doesn't seem to do the right thing at all... |
1134 | */ |
1135 | static void mmc_spi_initsequence(struct mmc_spi_host *host) |
1136 | { |
1137 | /* Try to be very sure any previous command has completed; |
1138 | * wait till not-busy, skip debris from any old commands. |
1139 | */ |
1140 | mmc_spi_wait_unbusy(host, r1b_timeout); |
1141 | mmc_spi_readbytes(host, 10); |
1142 | |
1143 | /* |
1144 | * Do a burst with chipselect active-high. We need to do this to |
1145 | * meet the requirement of 74 clock cycles with both chipselect |
1146 | * and CMD (MOSI) high before CMD0 ... after the card has been |
1147 | * powered up to Vdd(min), and so is ready to take commands. |
1148 | * |
1149 | * Some cards are particularly needy of this (e.g. Viking "SD256") |
1150 | * while most others don't seem to care. |
1151 | * |
1152 | * Note that this is one of the places MMC/SD plays games with the |
1153 | * SPI protocol. Another is that when chipselect is released while |
1154 | * the card returns BUSY status, the clock must issue several cycles |
1155 | * with chipselect high before the card will stop driving its output. |
1156 | */ |
1157 | host->spi->mode |= SPI_CS_HIGH; |
1158 | if (spi_setup(host->spi) != 0) { |
1159 | /* Just warn; most cards work without it. */ |
1160 | dev_warn(&host->spi->dev, |
1161 | "can't change chip-select polarity\n"); |
1162 | host->spi->mode &= ~SPI_CS_HIGH; |
1163 | } else { |
1164 | mmc_spi_readbytes(host, 18); |
1165 | |
1166 | host->spi->mode &= ~SPI_CS_HIGH; |
1167 | if (spi_setup(host->spi) != 0) { |
1168 | /* Wot, we can't get the same setup we had before? */ |
1169 | dev_err(&host->spi->dev, |
1170 | "can't restore chip-select polarity\n"); |
1171 | } |
1172 | } |
1173 | } |
1174 | |
1175 | static char *mmc_powerstring(u8 power_mode) |
1176 | { |
1177 | switch (power_mode) { |
1178 | case MMC_POWER_OFF: return "off"; |
1179 | case MMC_POWER_UP: return "up"; |
1180 | case MMC_POWER_ON: return "on"; |
1181 | } |
1182 | return "?"; |
1183 | } |
1184 | |
1185 | static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1186 | { |
1187 | struct mmc_spi_host *host = mmc_priv(mmc); |
1188 | |
1189 | if (host->power_mode != ios->power_mode) { |
1190 | int canpower; |
1191 | |
1192 | canpower = host->pdata && host->pdata->setpower; |
1193 | |
1194 | dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n", |
1195 | mmc_powerstring(ios->power_mode), |
1196 | ios->vdd, |
1197 | canpower ? ", can switch" : ""); |
1198 | |
1199 | /* switch power on/off if possible, accounting for |
1200 | * max 250msec powerup time if needed. |
1201 | */ |
1202 | if (canpower) { |
1203 | switch (ios->power_mode) { |
1204 | case MMC_POWER_OFF: |
1205 | case MMC_POWER_UP: |
1206 | host->pdata->setpower(&host->spi->dev, |
1207 | ios->vdd); |
1208 | if (ios->power_mode == MMC_POWER_UP) |
1209 | msleep(host->powerup_msecs); |
1210 | } |
1211 | } |
1212 | |
1213 | /* See 6.4.1 in the simplified SD card physical spec 2.0 */ |
1214 | if (ios->power_mode == MMC_POWER_ON) |
1215 | mmc_spi_initsequence(host); |
1216 | |
1217 | /* If powering down, ground all card inputs to avoid power |
1218 | * delivery from data lines! On a shared SPI bus, this |
1219 | * will probably be temporary; 6.4.2 of the simplified SD |
1220 | * spec says this must last at least 1msec. |
1221 | * |
1222 | * - Clock low means CPOL 0, e.g. mode 0 |
1223 | * - MOSI low comes from writing zero |
1224 | * - Chipselect is usually active low... |
1225 | */ |
1226 | if (canpower && ios->power_mode == MMC_POWER_OFF) { |
1227 | int mres; |
1228 | u8 nullbyte = 0; |
1229 | |
1230 | host->spi->mode &= ~(SPI_CPOL|SPI_CPHA); |
1231 | mres = spi_setup(host->spi); |
1232 | if (mres < 0) |
1233 | dev_dbg(&host->spi->dev, |
1234 | "switch to SPI mode 0 failed\n"); |
1235 | |
1236 | if (spi_write(host->spi, &nullbyte, 1) < 0) |
1237 | dev_dbg(&host->spi->dev, |
1238 | "put spi signals to low failed\n"); |
1239 | |
1240 | /* |
1241 | * Now clock should be low due to spi mode 0; |
1242 | * MOSI should be low because of written 0x00; |
1243 | * chipselect should be low (it is active low) |
1244 | * power supply is off, so now MMC is off too! |
1245 | * |
1246 | * FIXME no, chipselect can be high since the |
1247 | * device is inactive and SPI_CS_HIGH is clear... |
1248 | */ |
1249 | msleep(10); |
1250 | if (mres == 0) { |
1251 | host->spi->mode |= (SPI_CPOL|SPI_CPHA); |
1252 | mres = spi_setup(host->spi); |
1253 | if (mres < 0) |
1254 | dev_dbg(&host->spi->dev, |
1255 | "switch back to SPI mode 3" |
1256 | " failed\n"); |
1257 | } |
1258 | } |
1259 | |
1260 | host->power_mode = ios->power_mode; |
1261 | } |
1262 | |
1263 | if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) { |
1264 | int status; |
1265 | |
1266 | host->spi->max_speed_hz = ios->clock; |
1267 | status = spi_setup(host->spi); |
1268 | dev_dbg(&host->spi->dev, |
1269 | "mmc_spi: clock to %d Hz, %d\n", |
1270 | host->spi->max_speed_hz, status); |
1271 | } |
1272 | } |
1273 | |
1274 | static int mmc_spi_get_ro(struct mmc_host *mmc) |
1275 | { |
1276 | struct mmc_spi_host *host = mmc_priv(mmc); |
1277 | |
1278 | if (host->pdata && host->pdata->get_ro) |
1279 | return !!host->pdata->get_ro(mmc->parent); |
1280 | /* |
1281 | * Board doesn't support read only detection; let the mmc core |
1282 | * decide what to do. |
1283 | */ |
1284 | return -ENOSYS; |
1285 | } |
1286 | |
1287 | static int mmc_spi_get_cd(struct mmc_host *mmc) |
1288 | { |
1289 | struct mmc_spi_host *host = mmc_priv(mmc); |
1290 | |
1291 | if (host->pdata && host->pdata->get_cd) |
1292 | return !!host->pdata->get_cd(mmc->parent); |
1293 | return -ENOSYS; |
1294 | } |
1295 | |
1296 | static const struct mmc_host_ops mmc_spi_ops = { |
1297 | .request = mmc_spi_request, |
1298 | .set_ios = mmc_spi_set_ios, |
1299 | .get_ro = mmc_spi_get_ro, |
1300 | .get_cd = mmc_spi_get_cd, |
1301 | }; |
1302 | |
1303 | |
1304 | /****************************************************************************/ |
1305 | |
1306 | /* |
1307 | * SPI driver implementation |
1308 | */ |
1309 | |
1310 | static irqreturn_t |
1311 | mmc_spi_detect_irq(int irq, void *mmc) |
1312 | { |
1313 | struct mmc_spi_host *host = mmc_priv(mmc); |
1314 | u16 delay_msec = max(host->pdata->detect_delay, (u16)100); |
1315 | |
1316 | mmc_detect_change(mmc, msecs_to_jiffies(delay_msec)); |
1317 | return IRQ_HANDLED; |
1318 | } |
1319 | |
1320 | static int mmc_spi_probe(struct spi_device *spi) |
1321 | { |
1322 | void *ones; |
1323 | struct mmc_host *mmc; |
1324 | struct mmc_spi_host *host; |
1325 | int status; |
1326 | |
1327 | /* We rely on full duplex transfers, mostly to reduce |
1328 | * per-transfer overheads (by making fewer transfers). |
1329 | */ |
1330 | if (spi->master->flags & SPI_MASTER_HALF_DUPLEX) |
1331 | return -EINVAL; |
1332 | |
1333 | /* MMC and SD specs only seem to care that sampling is on the |
1334 | * rising edge ... meaning SPI modes 0 or 3. So either SPI mode |
1335 | * should be legit. We'll use mode 0 since the steady state is 0, |
1336 | * which is appropriate for hotplugging, unless the platform data |
1337 | * specify mode 3 (if hardware is not compatible to mode 0). |
1338 | */ |
1339 | if (spi->mode != SPI_MODE_3) |
1340 | spi->mode = SPI_MODE_0; |
1341 | spi->bits_per_word = 8; |
1342 | |
1343 | status = spi_setup(spi); |
1344 | if (status < 0) { |
1345 | dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n", |
1346 | spi->mode, spi->max_speed_hz / 1000, |
1347 | status); |
1348 | return status; |
1349 | } |
1350 | |
1351 | /* We need a supply of ones to transmit. This is the only time |
1352 | * the CPU touches these, so cache coherency isn't a concern. |
1353 | * |
1354 | * NOTE if many systems use more than one MMC-over-SPI connector |
1355 | * it'd save some memory to share this. That's evidently rare. |
1356 | */ |
1357 | status = -ENOMEM; |
1358 | ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL); |
1359 | if (!ones) |
1360 | goto nomem; |
1361 | memset(ones, 0xff, MMC_SPI_BLOCKSIZE); |
1362 | |
1363 | mmc = mmc_alloc_host(sizeof(*host), &spi->dev); |
1364 | if (!mmc) |
1365 | goto nomem; |
1366 | |
1367 | mmc->ops = &mmc_spi_ops; |
1368 | mmc->max_blk_size = MMC_SPI_BLOCKSIZE; |
1369 | mmc->max_segs = MMC_SPI_BLOCKSATONCE; |
1370 | mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE; |
1371 | mmc->max_blk_count = MMC_SPI_BLOCKSATONCE; |
1372 | |
1373 | mmc->caps = MMC_CAP_SPI; |
1374 | |
1375 | /* SPI doesn't need the lowspeed device identification thing for |
1376 | * MMC or SD cards, since it never comes up in open drain mode. |
1377 | * That's good; some SPI masters can't handle very low speeds! |
1378 | * |
1379 | * However, low speed SDIO cards need not handle over 400 KHz; |
1380 | * that's the only reason not to use a few MHz for f_min (until |
1381 | * the upper layer reads the target frequency from the CSD). |
1382 | */ |
1383 | mmc->f_min = 400000; |
1384 | mmc->f_max = spi->max_speed_hz; |
1385 | |
1386 | host = mmc_priv(mmc); |
1387 | host->mmc = mmc; |
1388 | host->spi = spi; |
1389 | |
1390 | host->ones = ones; |
1391 | |
1392 | /* Platform data is used to hook up things like card sensing |
1393 | * and power switching gpios. |
1394 | */ |
1395 | host->pdata = mmc_spi_get_pdata(spi); |
1396 | if (host->pdata) |
1397 | mmc->ocr_avail = host->pdata->ocr_mask; |
1398 | if (!mmc->ocr_avail) { |
1399 | dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n"); |
1400 | mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; |
1401 | } |
1402 | if (host->pdata && host->pdata->setpower) { |
1403 | host->powerup_msecs = host->pdata->powerup_msecs; |
1404 | if (!host->powerup_msecs || host->powerup_msecs > 250) |
1405 | host->powerup_msecs = 250; |
1406 | } |
1407 | |
1408 | dev_set_drvdata(&spi->dev, mmc); |
1409 | |
1410 | /* preallocate dma buffers */ |
1411 | host->data = kmalloc(sizeof(*host->data), GFP_KERNEL); |
1412 | if (!host->data) |
1413 | goto fail_nobuf1; |
1414 | |
1415 | if (spi->master->dev.parent->dma_mask) { |
1416 | struct device *dev = spi->master->dev.parent; |
1417 | |
1418 | host->dma_dev = dev; |
1419 | host->ones_dma = dma_map_single(dev, ones, |
1420 | MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE); |
1421 | host->data_dma = dma_map_single(dev, host->data, |
1422 | sizeof(*host->data), DMA_BIDIRECTIONAL); |
1423 | |
1424 | /* REVISIT in theory those map operations can fail... */ |
1425 | |
1426 | dma_sync_single_for_cpu(host->dma_dev, |
1427 | host->data_dma, sizeof(*host->data), |
1428 | DMA_BIDIRECTIONAL); |
1429 | } |
1430 | |
1431 | /* setup message for status/busy readback */ |
1432 | spi_message_init(&host->readback); |
1433 | host->readback.is_dma_mapped = (host->dma_dev != NULL); |
1434 | |
1435 | spi_message_add_tail(&host->status, &host->readback); |
1436 | host->status.tx_buf = host->ones; |
1437 | host->status.tx_dma = host->ones_dma; |
1438 | host->status.rx_buf = &host->data->status; |
1439 | host->status.rx_dma = host->data_dma + offsetof(struct scratch, status); |
1440 | host->status.cs_change = 1; |
1441 | |
1442 | /* register card detect irq */ |
1443 | if (host->pdata && host->pdata->init) { |
1444 | status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc); |
1445 | if (status != 0) |
1446 | goto fail_glue_init; |
1447 | } |
1448 | |
1449 | /* pass platform capabilities, if any */ |
1450 | if (host->pdata) |
1451 | mmc->caps |= host->pdata->caps; |
1452 | |
1453 | status = mmc_add_host(mmc); |
1454 | if (status != 0) |
1455 | goto fail_add_host; |
1456 | |
1457 | dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n", |
1458 | dev_name(&mmc->class_dev), |
1459 | host->dma_dev ? "" : ", no DMA", |
1460 | (host->pdata && host->pdata->get_ro) |
1461 | ? "" : ", no WP", |
1462 | (host->pdata && host->pdata->setpower) |
1463 | ? "" : ", no poweroff", |
1464 | (mmc->caps & MMC_CAP_NEEDS_POLL) |
1465 | ? ", cd polling" : ""); |
1466 | return 0; |
1467 | |
1468 | fail_add_host: |
1469 | mmc_remove_host (mmc); |
1470 | fail_glue_init: |
1471 | if (host->dma_dev) |
1472 | dma_unmap_single(host->dma_dev, host->data_dma, |
1473 | sizeof(*host->data), DMA_BIDIRECTIONAL); |
1474 | kfree(host->data); |
1475 | |
1476 | fail_nobuf1: |
1477 | mmc_free_host(mmc); |
1478 | mmc_spi_put_pdata(spi); |
1479 | dev_set_drvdata(&spi->dev, NULL); |
1480 | |
1481 | nomem: |
1482 | kfree(ones); |
1483 | return status; |
1484 | } |
1485 | |
1486 | |
1487 | static int __devexit mmc_spi_remove(struct spi_device *spi) |
1488 | { |
1489 | struct mmc_host *mmc = dev_get_drvdata(&spi->dev); |
1490 | struct mmc_spi_host *host; |
1491 | |
1492 | if (mmc) { |
1493 | host = mmc_priv(mmc); |
1494 | |
1495 | /* prevent new mmc_detect_change() calls */ |
1496 | if (host->pdata && host->pdata->exit) |
1497 | host->pdata->exit(&spi->dev, mmc); |
1498 | |
1499 | mmc_remove_host(mmc); |
1500 | |
1501 | if (host->dma_dev) { |
1502 | dma_unmap_single(host->dma_dev, host->ones_dma, |
1503 | MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE); |
1504 | dma_unmap_single(host->dma_dev, host->data_dma, |
1505 | sizeof(*host->data), DMA_BIDIRECTIONAL); |
1506 | } |
1507 | |
1508 | kfree(host->data); |
1509 | kfree(host->ones); |
1510 | |
1511 | spi->max_speed_hz = mmc->f_max; |
1512 | mmc_free_host(mmc); |
1513 | mmc_spi_put_pdata(spi); |
1514 | dev_set_drvdata(&spi->dev, NULL); |
1515 | } |
1516 | return 0; |
1517 | } |
1518 | |
1519 | #if defined(CONFIG_OF) |
1520 | static struct of_device_id mmc_spi_of_match_table[] __devinitdata = { |
1521 | { .compatible = "mmc-spi-slot", }, |
1522 | {}, |
1523 | }; |
1524 | #endif |
1525 | |
1526 | static struct spi_driver mmc_spi_driver = { |
1527 | .driver = { |
1528 | .name = "mmc_spi", |
1529 | .bus = &spi_bus_type, |
1530 | .owner = THIS_MODULE, |
1531 | #if defined(CONFIG_OF) |
1532 | .of_match_table = mmc_spi_of_match_table, |
1533 | #endif |
1534 | }, |
1535 | .probe = mmc_spi_probe, |
1536 | .remove = __devexit_p(mmc_spi_remove), |
1537 | }; |
1538 | |
1539 | |
1540 | static int __init mmc_spi_init(void) |
1541 | { |
1542 | return spi_register_driver(&mmc_spi_driver); |
1543 | } |
1544 | module_init(mmc_spi_init); |
1545 | |
1546 | |
1547 | static void __exit mmc_spi_exit(void) |
1548 | { |
1549 | spi_unregister_driver(&mmc_spi_driver); |
1550 | } |
1551 | module_exit(mmc_spi_exit); |
1552 | |
1553 | |
1554 | MODULE_AUTHOR("Mike Lavender, David Brownell, " |
1555 | "Hans-Peter Nilsson, Jan Nikitenko"); |
1556 | MODULE_DESCRIPTION("SPI SD/MMC host driver"); |
1557 | MODULE_LICENSE("GPL"); |
1558 | MODULE_ALIAS("spi:mmc_spi"); |
1559 |
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