Root/drivers/mmc/host/jz4740_mmc.c

Source at commit c9913093c244a42099fd2236c98554b95d75790c created 6 years 2 months ago.
By Alex Smith, mmc: jz4740: don't wait for PRG_DONE after stop command with R1 response
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/mmc/host.h>
17#include <linux/mmc/slot-gpio.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/delay.h>
25#include <linux/scatterlist.h>
26#include <linux/clk.h>
27#include <linux/cpufreq.h>
28
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <asm/mach-jz4740/gpio.h>
32#include <asm/cacheflush.h>
33#include <linux/dma-mapping.h>
34
35#include <asm/mach-jz4740/jz4740_mmc.h>
36
37#define JZ_REG_MMC_STRPCL 0x00
38#define JZ_REG_MMC_STATUS 0x04
39#define JZ_REG_MMC_CLKRT 0x08
40#define JZ_REG_MMC_CMDAT 0x0C
41#define JZ_REG_MMC_RESTO 0x10
42#define JZ_REG_MMC_RDTO 0x14
43#define JZ_REG_MMC_BLKLEN 0x18
44#define JZ_REG_MMC_NOB 0x1C
45#define JZ_REG_MMC_SNOB 0x20
46#define JZ_REG_MMC_IMASK 0x24
47#define JZ_REG_MMC_IREG 0x28
48#define JZ_REG_MMC_CMD 0x2C
49#define JZ_REG_MMC_ARG 0x30
50#define JZ_REG_MMC_RESP_FIFO 0x34
51#define JZ_REG_MMC_RXFIFO 0x38
52#define JZ_REG_MMC_TXFIFO 0x3C
53
54#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
55#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
56#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
57#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
58#define JZ_MMC_STRPCL_RESET BIT(3)
59#define JZ_MMC_STRPCL_START_OP BIT(2)
60#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
61#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
62#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
63
64
65#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
66#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
67#define JZ_MMC_STATUS_PRG_DONE BIT(13)
68#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
69#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
70#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
71#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
72#define JZ_MMC_STATUS_CLK_EN BIT(8)
73#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
74#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
75#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
76#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
77#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
78#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
79#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
80#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
81
82#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
83#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
84
85
86#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
87#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
88#define JZ_MMC_CMDAT_DMA_EN BIT(8)
89#define JZ_MMC_CMDAT_INIT BIT(7)
90#define JZ_MMC_CMDAT_BUSY BIT(6)
91#define JZ_MMC_CMDAT_STREAM BIT(5)
92#define JZ_MMC_CMDAT_WRITE BIT(4)
93#define JZ_MMC_CMDAT_DATA_EN BIT(3)
94#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
95#define JZ_MMC_CMDAT_RSP_R1 1
96#define JZ_MMC_CMDAT_RSP_R2 2
97#define JZ_MMC_CMDAT_RSP_R3 3
98
99#define JZ_MMC_IRQ_SDIO BIT(7)
100#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
101#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
102#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
103#define JZ_MMC_IRQ_PRG_DONE BIT(1)
104#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
105
106
107#define JZ_MMC_CLK_RATE 24000000
108
109enum jz4740_mmc_state {
110    JZ4740_MMC_STATE_READ_RESPONSE,
111    JZ4740_MMC_STATE_TRANSFER_DATA,
112    JZ4740_MMC_STATE_SEND_STOP,
113    JZ4740_MMC_STATE_DONE,
114};
115
116struct jz4740_mmc_host {
117    struct mmc_host *mmc;
118    struct platform_device *pdev;
119    struct jz4740_mmc_platform_data *pdata;
120    struct clk *clk;
121
122    int irq;
123    int card_detect_irq;
124
125    void __iomem *base;
126    struct mmc_request *req;
127    struct mmc_command *cmd;
128
129    unsigned long waiting;
130
131    uint32_t cmdat;
132
133    uint16_t irq_mask;
134
135    spinlock_t lock;
136
137    struct timer_list timeout_timer;
138    struct sg_mapping_iter miter;
139    enum jz4740_mmc_state state;
140};
141
142static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
143    unsigned int irq, bool enabled)
144{
145    unsigned long flags;
146
147    spin_lock_irqsave(&host->lock, flags);
148    if (enabled)
149        host->irq_mask &= ~irq;
150    else
151        host->irq_mask |= irq;
152    spin_unlock_irqrestore(&host->lock, flags);
153
154    writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
155}
156
157static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
158    bool start_transfer)
159{
160    uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
161
162    if (start_transfer)
163        val |= JZ_MMC_STRPCL_START_OP;
164
165    writew(val, host->base + JZ_REG_MMC_STRPCL);
166}
167
168static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
169{
170    uint32_t status;
171    unsigned int timeout = 1000;
172
173    writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
174    do {
175        status = readl(host->base + JZ_REG_MMC_STATUS);
176    } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
177}
178
179static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
180{
181    uint32_t status;
182    unsigned int timeout = 1000;
183
184    writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
185    udelay(10);
186    do {
187        status = readl(host->base + JZ_REG_MMC_STATUS);
188    } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
189}
190
191static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
192{
193    struct mmc_request *req;
194
195    req = host->req;
196    host->req = NULL;
197
198    mmc_request_done(host->mmc, req);
199}
200
201static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
202    unsigned int irq)
203{
204    unsigned int timeout = 0x800;
205    uint16_t status;
206
207    do {
208        status = readw(host->base + JZ_REG_MMC_IREG);
209    } while (!(status & irq) && --timeout);
210
211    if (timeout == 0) {
212        set_bit(0, &host->waiting);
213        mod_timer(&host->timeout_timer, jiffies + 5*HZ);
214        jz4740_mmc_set_irq_enabled(host, irq, true);
215        return true;
216    }
217
218    return false;
219}
220
221static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
222    struct mmc_data *data)
223{
224    int status;
225
226    status = readl(host->base + JZ_REG_MMC_STATUS);
227    if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
228        if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
229            host->req->cmd->error = -ETIMEDOUT;
230            data->error = -ETIMEDOUT;
231        } else {
232            host->req->cmd->error = -EIO;
233            data->error = -EIO;
234        }
235    } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
236        if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
237            host->req->cmd->error = -ETIMEDOUT;
238            data->error = -ETIMEDOUT;
239        } else {
240            host->req->cmd->error = -EIO;
241            data->error = -EIO;
242        }
243    }
244}
245
246static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
247    struct mmc_data *data)
248{
249    struct sg_mapping_iter *miter = &host->miter;
250    void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
251    uint32_t *buf;
252    bool timeout;
253    size_t i, j;
254
255    while (sg_miter_next(miter)) {
256        buf = miter->addr;
257        i = miter->length / 4;
258        j = i / 8;
259        i = i & 0x7;
260        while (j) {
261            timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
262            if (unlikely(timeout))
263                goto poll_timeout;
264
265            writel(buf[0], fifo_addr);
266            writel(buf[1], fifo_addr);
267            writel(buf[2], fifo_addr);
268            writel(buf[3], fifo_addr);
269            writel(buf[4], fifo_addr);
270            writel(buf[5], fifo_addr);
271            writel(buf[6], fifo_addr);
272            writel(buf[7], fifo_addr);
273            buf += 8;
274            --j;
275        }
276        if (unlikely(i)) {
277            timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
278            if (unlikely(timeout))
279                goto poll_timeout;
280
281            while (i) {
282                writel(*buf, fifo_addr);
283                ++buf;
284                --i;
285            }
286        }
287        data->bytes_xfered += miter->length;
288    }
289    sg_miter_stop(miter);
290
291    return false;
292
293poll_timeout:
294    miter->consumed = (void *)buf - miter->addr;
295    data->bytes_xfered += miter->consumed;
296    sg_miter_stop(miter);
297
298    return true;
299}
300
301static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
302                struct mmc_data *data)
303{
304    struct sg_mapping_iter *miter = &host->miter;
305    void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
306    uint32_t *buf;
307    uint32_t d;
308    uint16_t status;
309    size_t i, j;
310    unsigned int timeout;
311
312    while (sg_miter_next(miter)) {
313        buf = miter->addr;
314        i = miter->length;
315        j = i / 32;
316        i = i & 0x1f;
317        while (j) {
318            timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
319            if (unlikely(timeout))
320                goto poll_timeout;
321
322            buf[0] = readl(fifo_addr);
323            buf[1] = readl(fifo_addr);
324            buf[2] = readl(fifo_addr);
325            buf[3] = readl(fifo_addr);
326            buf[4] = readl(fifo_addr);
327            buf[5] = readl(fifo_addr);
328            buf[6] = readl(fifo_addr);
329            buf[7] = readl(fifo_addr);
330
331            buf += 8;
332            --j;
333        }
334
335        if (unlikely(i)) {
336            timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
337            if (unlikely(timeout))
338                goto poll_timeout;
339
340            while (i >= 4) {
341                *buf++ = readl(fifo_addr);
342                i -= 4;
343            }
344            if (unlikely(i > 0)) {
345                d = readl(fifo_addr);
346                memcpy(buf, &d, i);
347            }
348        }
349        data->bytes_xfered += miter->length;
350
351        /* This can go away once MIPS implements
352         * flush_kernel_dcache_page */
353        flush_dcache_page(miter->page);
354    }
355    sg_miter_stop(miter);
356
357    /* For whatever reason there is sometime one word more in the fifo then
358     * requested */
359    timeout = 1000;
360    status = readl(host->base + JZ_REG_MMC_STATUS);
361    while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
362        d = readl(fifo_addr);
363        status = readl(host->base + JZ_REG_MMC_STATUS);
364    }
365
366    return false;
367
368poll_timeout:
369    miter->consumed = (void *)buf - miter->addr;
370    data->bytes_xfered += miter->consumed;
371    sg_miter_stop(miter);
372
373    return true;
374}
375
376static void jz4740_mmc_timeout(unsigned long data)
377{
378    struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
379
380    if (!test_and_clear_bit(0, &host->waiting))
381        return;
382
383    jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
384
385    host->req->cmd->error = -ETIMEDOUT;
386    jz4740_mmc_request_done(host);
387}
388
389static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
390    struct mmc_command *cmd)
391{
392    int i;
393    uint16_t tmp;
394    void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
395
396    if (cmd->flags & MMC_RSP_136) {
397        tmp = readw(fifo_addr);
398        for (i = 0; i < 4; ++i) {
399            cmd->resp[i] = tmp << 24;
400            tmp = readw(fifo_addr);
401            cmd->resp[i] |= tmp << 8;
402            tmp = readw(fifo_addr);
403            cmd->resp[i] |= tmp >> 8;
404        }
405    } else {
406        cmd->resp[0] = readw(fifo_addr) << 24;
407        cmd->resp[0] |= readw(fifo_addr) << 8;
408        cmd->resp[0] |= readw(fifo_addr) & 0xff;
409    }
410}
411
412static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
413    struct mmc_command *cmd)
414{
415    uint32_t cmdat = host->cmdat;
416
417    host->cmdat &= ~JZ_MMC_CMDAT_INIT;
418    jz4740_mmc_clock_disable(host);
419
420    host->cmd = cmd;
421
422    if (cmd->flags & MMC_RSP_BUSY)
423        cmdat |= JZ_MMC_CMDAT_BUSY;
424
425    switch (mmc_resp_type(cmd)) {
426    case MMC_RSP_R1B:
427    case MMC_RSP_R1:
428        cmdat |= JZ_MMC_CMDAT_RSP_R1;
429        break;
430    case MMC_RSP_R2:
431        cmdat |= JZ_MMC_CMDAT_RSP_R2;
432        break;
433    case MMC_RSP_R3:
434        cmdat |= JZ_MMC_CMDAT_RSP_R3;
435        break;
436    default:
437        break;
438    }
439
440    if (cmd->data) {
441        cmdat |= JZ_MMC_CMDAT_DATA_EN;
442        if (cmd->data->flags & MMC_DATA_WRITE)
443            cmdat |= JZ_MMC_CMDAT_WRITE;
444        if (cmd->data->flags & MMC_DATA_STREAM)
445            cmdat |= JZ_MMC_CMDAT_STREAM;
446
447        writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
448        writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
449    }
450
451    writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
452    writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
453    writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
454
455    jz4740_mmc_clock_enable(host, 1);
456}
457
458static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
459{
460    struct mmc_command *cmd = host->req->cmd;
461    struct mmc_data *data = cmd->data;
462    int direction;
463
464    if (data->flags & MMC_DATA_READ)
465        direction = SG_MITER_TO_SG;
466    else
467        direction = SG_MITER_FROM_SG;
468
469    sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
470}
471
472
473static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
474{
475    struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
476    struct mmc_command *cmd = host->req->cmd;
477    struct mmc_request *req = host->req;
478    bool timeout = false;
479
480    if (cmd->error)
481        host->state = JZ4740_MMC_STATE_DONE;
482
483    switch (host->state) {
484    case JZ4740_MMC_STATE_READ_RESPONSE:
485        if (cmd->flags & MMC_RSP_PRESENT)
486            jz4740_mmc_read_response(host, cmd);
487
488        if (!cmd->data)
489            break;
490
491        jz_mmc_prepare_data_transfer(host);
492
493    case JZ4740_MMC_STATE_TRANSFER_DATA:
494        if (cmd->data->flags & MMC_DATA_READ)
495            timeout = jz4740_mmc_read_data(host, cmd->data);
496        else
497            timeout = jz4740_mmc_write_data(host, cmd->data);
498
499        if (unlikely(timeout)) {
500            host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
501            break;
502        }
503
504        jz4740_mmc_transfer_check_state(host, cmd->data);
505
506        timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
507        if (unlikely(timeout)) {
508            host->state = JZ4740_MMC_STATE_SEND_STOP;
509            break;
510        }
511        writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
512
513    case JZ4740_MMC_STATE_SEND_STOP:
514        if (!req->stop)
515            break;
516
517        jz4740_mmc_send_command(host, req->stop);
518
519        if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
520            timeout = jz4740_mmc_poll_irq(host,
521                              JZ_MMC_IRQ_PRG_DONE);
522            if (timeout) {
523                host->state = JZ4740_MMC_STATE_DONE;
524                break;
525            }
526        }
527    case JZ4740_MMC_STATE_DONE:
528        break;
529    }
530
531    if (!timeout)
532        jz4740_mmc_request_done(host);
533
534    return IRQ_HANDLED;
535}
536
537static irqreturn_t jz_mmc_irq(int irq, void *devid)
538{
539    struct jz4740_mmc_host *host = devid;
540    struct mmc_command *cmd = host->cmd;
541    uint16_t irq_reg, status, tmp;
542
543    irq_reg = readw(host->base + JZ_REG_MMC_IREG);
544
545    tmp = irq_reg;
546    irq_reg &= ~host->irq_mask;
547
548    tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
549        JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
550
551    if (tmp != irq_reg)
552        writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
553
554    if (irq_reg & JZ_MMC_IRQ_SDIO) {
555        writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
556        mmc_signal_sdio_irq(host->mmc);
557        irq_reg &= ~JZ_MMC_IRQ_SDIO;
558    }
559
560    if (host->req && cmd && irq_reg) {
561        if (test_and_clear_bit(0, &host->waiting)) {
562            del_timer(&host->timeout_timer);
563
564            status = readl(host->base + JZ_REG_MMC_STATUS);
565
566            if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
567                    cmd->error = -ETIMEDOUT;
568            } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
569                    cmd->error = -EIO;
570            } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
571                    JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
572                    if (cmd->data)
573                            cmd->data->error = -EIO;
574                    cmd->error = -EIO;
575            }
576
577            jz4740_mmc_set_irq_enabled(host, irq_reg, false);
578            writew(irq_reg, host->base + JZ_REG_MMC_IREG);
579
580            return IRQ_WAKE_THREAD;
581        }
582    }
583
584    return IRQ_HANDLED;
585}
586
587static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
588{
589    int div = 0;
590    int real_rate;
591
592    jz4740_mmc_clock_disable(host);
593    clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
594
595    real_rate = clk_get_rate(host->clk);
596
597    while (real_rate > rate && div < 7) {
598        ++div;
599        real_rate >>= 1;
600    }
601
602    writew(div, host->base + JZ_REG_MMC_CLKRT);
603    return real_rate;
604}
605
606static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
607{
608    struct jz4740_mmc_host *host = mmc_priv(mmc);
609
610    host->req = req;
611
612    writew(0xffff, host->base + JZ_REG_MMC_IREG);
613
614    writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
615    jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
616
617    host->state = JZ4740_MMC_STATE_READ_RESPONSE;
618    set_bit(0, &host->waiting);
619    mod_timer(&host->timeout_timer, jiffies + 5*HZ);
620    jz4740_mmc_send_command(host, req->cmd);
621}
622
623static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
624{
625    struct jz4740_mmc_host *host = mmc_priv(mmc);
626    if (ios->clock)
627        jz4740_mmc_set_clock_rate(host, ios->clock);
628
629    switch (ios->power_mode) {
630    case MMC_POWER_UP:
631        jz4740_mmc_reset(host);
632        mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
633        host->cmdat |= JZ_MMC_CMDAT_INIT;
634        clk_prepare_enable(host->clk);
635        break;
636    case MMC_POWER_ON:
637        break;
638    default:
639        mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
640        clk_disable_unprepare(host->clk);
641        break;
642    }
643
644    switch (ios->bus_width) {
645    case MMC_BUS_WIDTH_1:
646        host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
647        break;
648    case MMC_BUS_WIDTH_4:
649        host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
650        break;
651    default:
652        break;
653    }
654}
655
656static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
657{
658    struct jz4740_mmc_host *host = mmc_priv(mmc);
659    jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
660}
661
662#ifdef CONFIG_CPU_FREQ
663
664static struct jz4740_mmc_host *cpufreq_host;
665
666static int jz4740_mmc_cpufreq_transition(struct notifier_block *nb,
667                     unsigned long val, void *data)
668{
669    /* TODO: We only have to take action when the PLL freq changes:
670             the main dividers have no influence on the MSC device clock. */
671
672    if (val == CPUFREQ_PRECHANGE) {
673        mmc_claim_host(cpufreq_host->mmc);
674        clk_disable_unprepare(cpufreq_host->clk);
675    } else if (val == CPUFREQ_POSTCHANGE) {
676        struct mmc_ios *ios = &cpufreq_host->mmc->ios;
677        if (ios->clock)
678            jz4740_mmc_set_clock_rate(cpufreq_host, ios->clock);
679        if (ios->power_mode != MMC_POWER_OFF)
680            clk_prepare_enable(cpufreq_host->clk);
681        mmc_release_host(cpufreq_host->mmc);
682    }
683    return 0;
684}
685
686static struct notifier_block jz4740_mmc_cpufreq_nb = {
687    .notifier_call = jz4740_mmc_cpufreq_transition,
688};
689
690static inline int jz4740_mmc_cpufreq_register(struct jz4740_mmc_host *host)
691{
692    cpufreq_host = host;
693    return cpufreq_register_notifier(&jz4740_mmc_cpufreq_nb,
694                     CPUFREQ_TRANSITION_NOTIFIER);
695}
696
697static inline void jz4740_mmc_cpufreq_unregister(void)
698{
699    cpufreq_unregister_notifier(&jz4740_mmc_cpufreq_nb,
700                    CPUFREQ_TRANSITION_NOTIFIER);
701}
702
703#else
704
705static inline int jz4740_mmc_cpufreq_register(struct jz4740_mmc_host *host)
706{
707    return 0;
708}
709
710static inline void jz4740_mmc_cpufreq_unregister(void)
711{
712}
713
714#endif
715
716static const struct mmc_host_ops jz4740_mmc_ops = {
717    .request = jz4740_mmc_request,
718    .set_ios = jz4740_mmc_set_ios,
719    .get_ro = mmc_gpio_get_ro,
720    .get_cd = mmc_gpio_get_cd,
721    .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
722};
723
724static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
725    JZ_GPIO_BULK_PIN(MSC_CMD),
726    JZ_GPIO_BULK_PIN(MSC_CLK),
727    JZ_GPIO_BULK_PIN(MSC_DATA0),
728    JZ_GPIO_BULK_PIN(MSC_DATA1),
729    JZ_GPIO_BULK_PIN(MSC_DATA2),
730    JZ_GPIO_BULK_PIN(MSC_DATA3),
731};
732
733static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
734    struct platform_device *pdev)
735{
736    struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
737    int ret = 0;
738
739    if (!pdata)
740        return 0;
741
742    if (!pdata->card_detect_active_low)
743        mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
744    if (!pdata->read_only_active_low)
745        mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
746
747    if (gpio_is_valid(pdata->gpio_card_detect)) {
748        ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0);
749        if (ret)
750            return ret;
751    }
752
753    if (gpio_is_valid(pdata->gpio_read_only))
754        ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only);
755
756    return ret;
757}
758
759static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
760{
761    size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
762    if (host->pdata && host->pdata->data_1bit)
763        num_pins -= 3;
764
765    return num_pins;
766}
767
768static int jz4740_mmc_probe(struct platform_device* pdev)
769{
770    int ret;
771    struct mmc_host *mmc;
772    struct jz4740_mmc_host *host;
773    struct jz4740_mmc_platform_data *pdata;
774    struct resource *res;
775
776    pdata = pdev->dev.platform_data;
777
778    mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
779    if (!mmc) {
780        dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
781        return -ENOMEM;
782    }
783
784    host = mmc_priv(mmc);
785    host->pdata = pdata;
786
787    host->irq = platform_get_irq(pdev, 0);
788    if (host->irq < 0) {
789        ret = host->irq;
790        dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
791        goto err_free_host;
792    }
793
794    host->clk = devm_clk_get(&pdev->dev, "mmc");
795    if (IS_ERR(host->clk)) {
796        ret = PTR_ERR(host->clk);
797        dev_err(&pdev->dev, "Failed to get mmc clock\n");
798        goto err_free_host;
799    }
800
801    ret = jz4740_mmc_cpufreq_register(host);
802    if (ret) {
803        dev_err(&pdev->dev,
804            "Failed to register cpufreq transition notifier\n");
805        goto err_free_host;
806    }
807
808    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
809    host->base = devm_ioremap_resource(&pdev->dev, res);
810    if (IS_ERR(host->base)) {
811        ret = PTR_ERR(host->base);
812        dev_err(&pdev->dev, "Failed to ioremap base memory\n");
813        goto err_cpufreq_unreg;
814    }
815
816    ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
817    if (ret) {
818        dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
819        goto err_cpufreq_unreg;
820    }
821
822    if (pdata) {
823        ret = jz4740_mmc_request_gpios(mmc, pdev);
824        if (ret)
825            goto err_gpio_bulk_free;
826    } else {
827        mmc_of_parse(mmc);
828    }
829
830    ret = mmc_regulator_get_supply(mmc);
831    if (ret)
832        goto err_gpio_bulk_free;
833
834    mmc->ops = &jz4740_mmc_ops;
835    mmc->f_min = JZ_MMC_CLK_RATE / 128;
836    mmc->f_max = JZ_MMC_CLK_RATE;
837    mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
838    mmc->caps |= MMC_CAP_SDIO_IRQ;
839
840    mmc->max_blk_size = (1 << 10) - 1;
841    mmc->max_blk_count = (1 << 15) - 1;
842    mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
843
844    mmc->max_segs = 128;
845    mmc->max_seg_size = mmc->max_req_size;
846
847    host->mmc = mmc;
848    host->pdev = pdev;
849    spin_lock_init(&host->lock);
850    host->irq_mask = 0xffff;
851
852    ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
853            dev_name(&pdev->dev), host);
854    if (ret) {
855        dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
856        goto err_gpio_bulk_free;
857    }
858
859    jz4740_mmc_reset(host);
860    jz4740_mmc_clock_disable(host);
861    setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
862            (unsigned long)host);
863    /* It is not important when it times out, it just needs to timeout. */
864    set_timer_slack(&host->timeout_timer, HZ);
865
866    platform_set_drvdata(pdev, host);
867    ret = mmc_add_host(mmc);
868
869    if (ret) {
870        dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
871        goto err_free_irq;
872    }
873    dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
874
875    return 0;
876
877err_free_irq:
878    free_irq(host->irq, host);
879err_gpio_bulk_free:
880    jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
881err_cpufreq_unreg:
882    jz4740_mmc_cpufreq_unregister();
883err_free_host:
884    mmc_free_host(mmc);
885
886    return ret;
887}
888
889static int jz4740_mmc_remove(struct platform_device *pdev)
890{
891    struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
892
893    del_timer_sync(&host->timeout_timer);
894    jz4740_mmc_set_irq_enabled(host, 0xff, false);
895    jz4740_mmc_reset(host);
896
897    mmc_remove_host(host->mmc);
898
899    free_irq(host->irq, host);
900
901    jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
902
903    jz4740_mmc_cpufreq_unregister();
904    mmc_free_host(host->mmc);
905
906    return 0;
907}
908
909#ifdef CONFIG_PM_SLEEP
910
911static int jz4740_mmc_suspend(struct device *dev)
912{
913    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
914
915    jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
916
917    return 0;
918}
919
920static int jz4740_mmc_resume(struct device *dev)
921{
922    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
923
924    jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
925
926    return 0;
927}
928
929static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
930    jz4740_mmc_resume);
931#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
932#else
933#define JZ4740_MMC_PM_OPS NULL
934#endif
935
936static const struct of_device_id jz4740_mmc_of_match[] = {
937    { .compatible = "ingenic,jz4740-msc" },
938    {},
939};
940MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match);
941
942static struct platform_driver jz4740_mmc_driver = {
943    .probe = jz4740_mmc_probe,
944    .remove = jz4740_mmc_remove,
945    .driver = {
946        .name = "jz4740-mmc",
947        .owner = THIS_MODULE,
948        .pm = JZ4740_MMC_PM_OPS,
949        .of_match_table = jz4740_mmc_of_match,
950    },
951};
952
953module_platform_driver(jz4740_mmc_driver);
954
955MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
956MODULE_LICENSE("GPL");
957MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
958

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