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Source at commit d15ef47a9ccd5d6a001af4dfaa2a50f57e514853 created 14 years 3 months ago. By xiangfu, 050-nand.patch | |
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1 | /* |
2 | * drivers/mtd/nand.c |
3 | * |
4 | * Overview: |
5 | * This is the generic MTD driver for NAND flash devices. It should be |
6 | * capable of working with almost all NAND chips currently available. |
7 | * Basic support for AG-AND chips is provided. |
8 | * |
9 | * Additional technical information is available on |
10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
11 | * |
12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
14 | * |
15 | * Credits: |
16 | * David Woodhouse for adding multichip support |
17 | * |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips |
20 | * |
21 | * TODO: |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW |
24 | * if we have HW ecc support. |
25 | * The AG-AND chips have nice features for speed improvement, |
26 | * which are not supported yet. Read / program 4 pages in one go. |
27 | * BBT table is not serialized, has to be fixed |
28 | * |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as |
31 | * published by the Free Software Foundation. |
32 | * |
33 | */ |
34 | |
35 | #include <linux/module.h> |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> |
38 | #include <linux/err.h> |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> |
41 | #include <linux/types.h> |
42 | #include <linux/mtd/mtd.h> |
43 | #include <linux/mtd/nand.h> |
44 | #include <linux/mtd/nand_ecc.h> |
45 | #include <linux/mtd/compatmac.h> |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> |
48 | #include <linux/leds.h> |
49 | #include <asm/io.h> |
50 | |
51 | #ifdef CONFIG_MTD_PARTITIONS |
52 | #include <linux/mtd/partitions.h> |
53 | #endif |
54 | |
55 | /* Define default oob placement schemes for large and small page devices */ |
56 | static struct nand_ecclayout nand_oob_8 = { |
57 | .eccbytes = 3, |
58 | .eccpos = {0, 1, 2}, |
59 | .oobfree = { |
60 | {.offset = 3, |
61 | .length = 2}, |
62 | {.offset = 6, |
63 | .length = 2}} |
64 | }; |
65 | |
66 | static struct nand_ecclayout nand_oob_16 = { |
67 | .eccbytes = 6, |
68 | .eccpos = {0, 1, 2, 3, 6, 7}, |
69 | .oobfree = { |
70 | {.offset = 8, |
71 | . length = 8}} |
72 | }; |
73 | |
74 | static struct nand_ecclayout nand_oob_64 = { |
75 | .eccbytes = 24, |
76 | .eccpos = { |
77 | 40, 41, 42, 43, 44, 45, 46, 47, |
78 | 48, 49, 50, 51, 52, 53, 54, 55, |
79 | 56, 57, 58, 59, 60, 61, 62, 63}, |
80 | .oobfree = { |
81 | {.offset = 2, |
82 | .length = 38}} |
83 | }; |
84 | |
85 | static struct nand_ecclayout nand_oob_128 = { |
86 | .eccbytes = 48, |
87 | .eccpos = { |
88 | 80, 81, 82, 83, 84, 85, 86, 87, |
89 | 88, 89, 90, 91, 92, 93, 94, 95, |
90 | 96, 97, 98, 99, 100, 101, 102, 103, |
91 | 104, 105, 106, 107, 108, 109, 110, 111, |
92 | 112, 113, 114, 115, 116, 117, 118, 119, |
93 | 120, 121, 122, 123, 124, 125, 126, 127}, |
94 | .oobfree = { |
95 | {.offset = 2, |
96 | .length = 78}} |
97 | }; |
98 | |
99 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
100 | int new_state); |
101 | |
102 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
103 | struct mtd_oob_ops *ops); |
104 | |
105 | /* |
106 | * For devices which display every fart in the system on a separate LED. Is |
107 | * compiled away when LED support is disabled. |
108 | */ |
109 | DEFINE_LED_TRIGGER(nand_led_trigger); |
110 | |
111 | /** |
112 | * nand_release_device - [GENERIC] release chip |
113 | * @mtd: MTD device structure |
114 | * |
115 | * Deselect, release chip lock and wake up anyone waiting on the device |
116 | */ |
117 | static void nand_release_device(struct mtd_info *mtd) |
118 | { |
119 | struct nand_chip *chip = mtd->priv; |
120 | |
121 | /* De-select the NAND device */ |
122 | chip->select_chip(mtd, -1); |
123 | |
124 | /* Release the controller and the chip */ |
125 | spin_lock(&chip->controller->lock); |
126 | chip->controller->active = NULL; |
127 | chip->state = FL_READY; |
128 | wake_up(&chip->controller->wq); |
129 | spin_unlock(&chip->controller->lock); |
130 | } |
131 | |
132 | /** |
133 | * nand_read_byte - [DEFAULT] read one byte from the chip |
134 | * @mtd: MTD device structure |
135 | * |
136 | * Default read function for 8bit buswith |
137 | */ |
138 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
139 | { |
140 | struct nand_chip *chip = mtd->priv; |
141 | return readb(chip->IO_ADDR_R); |
142 | } |
143 | |
144 | /** |
145 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip |
146 | * @mtd: MTD device structure |
147 | * |
148 | * Default read function for 16bit buswith with |
149 | * endianess conversion |
150 | */ |
151 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
152 | { |
153 | struct nand_chip *chip = mtd->priv; |
154 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); |
155 | } |
156 | |
157 | /** |
158 | * nand_read_word - [DEFAULT] read one word from the chip |
159 | * @mtd: MTD device structure |
160 | * |
161 | * Default read function for 16bit buswith without |
162 | * endianess conversion |
163 | */ |
164 | static u16 nand_read_word(struct mtd_info *mtd) |
165 | { |
166 | struct nand_chip *chip = mtd->priv; |
167 | return readw(chip->IO_ADDR_R); |
168 | } |
169 | |
170 | /** |
171 | * nand_select_chip - [DEFAULT] control CE line |
172 | * @mtd: MTD device structure |
173 | * @chipnr: chipnumber to select, -1 for deselect |
174 | * |
175 | * Default select function for 1 chip devices. |
176 | */ |
177 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
178 | { |
179 | struct nand_chip *chip = mtd->priv; |
180 | |
181 | switch (chipnr) { |
182 | case -1: |
183 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
184 | break; |
185 | case 0: |
186 | break; |
187 | |
188 | default: |
189 | BUG(); |
190 | } |
191 | } |
192 | |
193 | /** |
194 | * nand_write_buf - [DEFAULT] write buffer to chip |
195 | * @mtd: MTD device structure |
196 | * @buf: data buffer |
197 | * @len: number of bytes to write |
198 | * |
199 | * Default write function for 8bit buswith |
200 | */ |
201 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
202 | { |
203 | int i; |
204 | struct nand_chip *chip = mtd->priv; |
205 | |
206 | for (i = 0; i < len; i++) |
207 | writeb(buf[i], chip->IO_ADDR_W); |
208 | } |
209 | |
210 | /** |
211 | * nand_read_buf - [DEFAULT] read chip data into buffer |
212 | * @mtd: MTD device structure |
213 | * @buf: buffer to store date |
214 | * @len: number of bytes to read |
215 | * |
216 | * Default read function for 8bit buswith |
217 | */ |
218 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
219 | { |
220 | int i; |
221 | struct nand_chip *chip = mtd->priv; |
222 | |
223 | for (i = 0; i < len; i++) |
224 | buf[i] = readb(chip->IO_ADDR_R); |
225 | } |
226 | |
227 | /** |
228 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
229 | * @mtd: MTD device structure |
230 | * @buf: buffer containing the data to compare |
231 | * @len: number of bytes to compare |
232 | * |
233 | * Default verify function for 8bit buswith |
234 | */ |
235 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
236 | { |
237 | int i; |
238 | struct nand_chip *chip = mtd->priv; |
239 | |
240 | for (i = 0; i < len; i++) |
241 | if (buf[i] != readb(chip->IO_ADDR_R)) |
242 | return -EFAULT; |
243 | return 0; |
244 | } |
245 | |
246 | /** |
247 | * nand_write_buf16 - [DEFAULT] write buffer to chip |
248 | * @mtd: MTD device structure |
249 | * @buf: data buffer |
250 | * @len: number of bytes to write |
251 | * |
252 | * Default write function for 16bit buswith |
253 | */ |
254 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
255 | { |
256 | int i; |
257 | struct nand_chip *chip = mtd->priv; |
258 | u16 *p = (u16 *) buf; |
259 | len >>= 1; |
260 | |
261 | for (i = 0; i < len; i++) |
262 | writew(p[i], chip->IO_ADDR_W); |
263 | |
264 | } |
265 | |
266 | /** |
267 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
268 | * @mtd: MTD device structure |
269 | * @buf: buffer to store date |
270 | * @len: number of bytes to read |
271 | * |
272 | * Default read function for 16bit buswith |
273 | */ |
274 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
275 | { |
276 | int i; |
277 | struct nand_chip *chip = mtd->priv; |
278 | u16 *p = (u16 *) buf; |
279 | len >>= 1; |
280 | |
281 | for (i = 0; i < len; i++) |
282 | p[i] = readw(chip->IO_ADDR_R); |
283 | } |
284 | |
285 | /** |
286 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
287 | * @mtd: MTD device structure |
288 | * @buf: buffer containing the data to compare |
289 | * @len: number of bytes to compare |
290 | * |
291 | * Default verify function for 16bit buswith |
292 | */ |
293 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
294 | { |
295 | int i; |
296 | struct nand_chip *chip = mtd->priv; |
297 | u16 *p = (u16 *) buf; |
298 | len >>= 1; |
299 | |
300 | for (i = 0; i < len; i++) |
301 | if (p[i] != readw(chip->IO_ADDR_R)) |
302 | return -EFAULT; |
303 | |
304 | return 0; |
305 | } |
306 | |
307 | /** |
308 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip |
309 | * @mtd: MTD device structure |
310 | * @ofs: offset from device start |
311 | * @getchip: 0, if the chip is already selected |
312 | * |
313 | * Check, if the block is bad. |
314 | */ |
315 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) |
316 | { |
317 | int page, chipnr, res = 0; |
318 | struct nand_chip *chip = mtd->priv; |
319 | u16 bad; |
320 | |
321 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
322 | |
323 | if (getchip) { |
324 | chipnr = (int)(ofs >> chip->chip_shift); |
325 | |
326 | nand_get_device(chip, mtd, FL_READING); |
327 | |
328 | /* Select the NAND device */ |
329 | chip->select_chip(mtd, chipnr); |
330 | } |
331 | |
332 | if (chip->options & NAND_BUSWIDTH_16) { |
333 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, |
334 | page); |
335 | bad = cpu_to_le16(chip->read_word(mtd)); |
336 | if (chip->badblockpos & 0x1) |
337 | bad >>= 8; |
338 | if ((bad & 0xFF) != 0xff) |
339 | res = 1; |
340 | } else { |
341 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); |
342 | if (chip->read_byte(mtd) != 0xff) |
343 | res = 1; |
344 | } |
345 | |
346 | if (getchip) |
347 | nand_release_device(mtd); |
348 | |
349 | return res; |
350 | } |
351 | |
352 | /** |
353 | * nand_default_block_markbad - [DEFAULT] mark a block bad |
354 | * @mtd: MTD device structure |
355 | * @ofs: offset from device start |
356 | * |
357 | * This is the default implementation, which can be overridden by |
358 | * a hardware specific driver. |
359 | */ |
360 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) |
361 | { |
362 | struct nand_chip *chip = mtd->priv; |
363 | uint8_t buf[2] = { 0, 0 }; |
364 | int block, ret; |
365 | |
366 | /* Get block number */ |
367 | block = (int)(ofs >> chip->bbt_erase_shift); |
368 | if (chip->bbt) |
369 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); |
370 | |
371 | /* Do we have a flash based bad block table ? */ |
372 | if (chip->options & NAND_USE_FLASH_BBT) |
373 | ret = nand_update_bbt(mtd, ofs); |
374 | else { |
375 | /* We write two bytes, so we dont have to mess with 16 bit |
376 | * access |
377 | */ |
378 | nand_get_device(chip, mtd, FL_WRITING); |
379 | ofs += mtd->oobsize; |
380 | chip->ops.len = chip->ops.ooblen = 2; |
381 | chip->ops.datbuf = NULL; |
382 | chip->ops.oobbuf = buf; |
383 | chip->ops.ooboffs = chip->badblockpos & ~0x01; |
384 | |
385 | ret = nand_do_write_oob(mtd, ofs, &chip->ops); |
386 | nand_release_device(mtd); |
387 | } |
388 | if (!ret) |
389 | mtd->ecc_stats.badblocks++; |
390 | |
391 | return ret; |
392 | } |
393 | |
394 | /** |
395 | * nand_check_wp - [GENERIC] check if the chip is write protected |
396 | * @mtd: MTD device structure |
397 | * Check, if the device is write protected |
398 | * |
399 | * The function expects, that the device is already selected |
400 | */ |
401 | static int nand_check_wp(struct mtd_info *mtd) |
402 | { |
403 | struct nand_chip *chip = mtd->priv; |
404 | /* Check the WP bit */ |
405 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
406 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; |
407 | } |
408 | |
409 | /** |
410 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad |
411 | * @mtd: MTD device structure |
412 | * @ofs: offset from device start |
413 | * @getchip: 0, if the chip is already selected |
414 | * @allowbbt: 1, if its allowed to access the bbt area |
415 | * |
416 | * Check, if the block is bad. Either by reading the bad block table or |
417 | * calling of the scan function. |
418 | */ |
419 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
420 | int allowbbt) |
421 | { |
422 | struct nand_chip *chip = mtd->priv; |
423 | |
424 | if (!chip->bbt) |
425 | return chip->block_bad(mtd, ofs, getchip); |
426 | |
427 | /* Return info from the table */ |
428 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
429 | } |
430 | |
431 | /* |
432 | * Wait for the ready pin, after a command |
433 | * The timeout is catched later. |
434 | */ |
435 | void nand_wait_ready(struct mtd_info *mtd) |
436 | { |
437 | struct nand_chip *chip = mtd->priv; |
438 | unsigned long timeo = jiffies + 2; |
439 | |
440 | led_trigger_event(nand_led_trigger, LED_FULL); |
441 | /* wait until command is processed or timeout occures */ |
442 | do { |
443 | if (chip->dev_ready(mtd)) |
444 | break; |
445 | touch_softlockup_watchdog(); |
446 | } while (time_before(jiffies, timeo)); |
447 | led_trigger_event(nand_led_trigger, LED_OFF); |
448 | } |
449 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
450 | |
451 | /** |
452 | * nand_command - [DEFAULT] Send command to NAND device |
453 | * @mtd: MTD device structure |
454 | * @command: the command to be sent |
455 | * @column: the column address for this command, -1 if none |
456 | * @page_addr: the page address for this command, -1 if none |
457 | * |
458 | * Send command to NAND device. This function is used for small page |
459 | * devices (256/512 Bytes per page) |
460 | */ |
461 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
462 | int column, int page_addr) |
463 | { |
464 | register struct nand_chip *chip = mtd->priv; |
465 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
466 | |
467 | /* |
468 | * Write out the command to the device. |
469 | */ |
470 | if (command == NAND_CMD_SEQIN) { |
471 | int readcmd; |
472 | |
473 | if (column >= mtd->writesize) { |
474 | /* OOB area */ |
475 | column -= mtd->writesize; |
476 | readcmd = NAND_CMD_READOOB; |
477 | } else if (column < 256) { |
478 | /* First 256 bytes --> READ0 */ |
479 | readcmd = NAND_CMD_READ0; |
480 | } else { |
481 | column -= 256; |
482 | readcmd = NAND_CMD_READ1; |
483 | } |
484 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
485 | ctrl &= ~NAND_CTRL_CHANGE; |
486 | } |
487 | chip->cmd_ctrl(mtd, command, ctrl); |
488 | |
489 | /* |
490 | * Address cycle, when necessary |
491 | */ |
492 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
493 | /* Serially input address */ |
494 | if (column != -1) { |
495 | /* Adjust columns for 16 bit buswidth */ |
496 | if (chip->options & NAND_BUSWIDTH_16) |
497 | column >>= 1; |
498 | chip->cmd_ctrl(mtd, column, ctrl); |
499 | ctrl &= ~NAND_CTRL_CHANGE; |
500 | } |
501 | if (page_addr != -1) { |
502 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
503 | ctrl &= ~NAND_CTRL_CHANGE; |
504 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
505 | /* One more address cycle for devices > 32MiB */ |
506 | if (chip->chipsize > (32 << 20)) |
507 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); |
508 | } |
509 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
510 | |
511 | /* |
512 | * program and erase have their own busy handlers |
513 | * status and sequential in needs no delay |
514 | */ |
515 | switch (command) { |
516 | |
517 | case NAND_CMD_PAGEPROG: |
518 | case NAND_CMD_ERASE1: |
519 | case NAND_CMD_ERASE2: |
520 | case NAND_CMD_SEQIN: |
521 | case NAND_CMD_STATUS: |
522 | return; |
523 | |
524 | case NAND_CMD_RESET: |
525 | if (chip->dev_ready) |
526 | break; |
527 | udelay(chip->chip_delay); |
528 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
529 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
530 | chip->cmd_ctrl(mtd, |
531 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
532 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
533 | return; |
534 | |
535 | /* This applies to read commands */ |
536 | default: |
537 | /* |
538 | * If we don't have access to the busy pin, we apply the given |
539 | * command delay |
540 | */ |
541 | if (!chip->dev_ready) { |
542 | udelay(chip->chip_delay); |
543 | return; |
544 | } |
545 | } |
546 | /* Apply this short delay always to ensure that we do wait tWB in |
547 | * any case on any machine. */ |
548 | ndelay(100); |
549 | |
550 | nand_wait_ready(mtd); |
551 | } |
552 | |
553 | /** |
554 | * nand_command_lp - [DEFAULT] Send command to NAND large page device |
555 | * @mtd: MTD device structure |
556 | * @command: the command to be sent |
557 | * @column: the column address for this command, -1 if none |
558 | * @page_addr: the page address for this command, -1 if none |
559 | * |
560 | * Send command to NAND device. This is the version for the new large page |
561 | * devices We dont have the separate regions as we have in the small page |
562 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. |
563 | */ |
564 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
565 | int column, int page_addr) |
566 | { |
567 | register struct nand_chip *chip = mtd->priv; |
568 | |
569 | /* Emulate NAND_CMD_READOOB */ |
570 | if (command == NAND_CMD_READOOB) { |
571 | column += mtd->writesize; |
572 | command = NAND_CMD_READ0; |
573 | } |
574 | |
575 | /* Command latch cycle */ |
576 | chip->cmd_ctrl(mtd, command & 0xff, |
577 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
578 | |
579 | if (column != -1 || page_addr != -1) { |
580 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
581 | |
582 | /* Serially input address */ |
583 | if (column != -1) { |
584 | /* Adjust columns for 16 bit buswidth */ |
585 | if (chip->options & NAND_BUSWIDTH_16) |
586 | column >>= 1; |
587 | chip->cmd_ctrl(mtd, column, ctrl); |
588 | ctrl &= ~NAND_CTRL_CHANGE; |
589 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
590 | } |
591 | if (page_addr != -1) { |
592 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
593 | chip->cmd_ctrl(mtd, page_addr >> 8, |
594 | NAND_NCE | NAND_ALE); |
595 | /* One more address cycle for devices > 128MiB */ |
596 | if (chip->chipsize > (128 << 20)) |
597 | chip->cmd_ctrl(mtd, page_addr >> 16, |
598 | NAND_NCE | NAND_ALE); |
599 | } |
600 | } |
601 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
602 | |
603 | /* |
604 | * program and erase have their own busy handlers |
605 | * status, sequential in, and deplete1 need no delay |
606 | */ |
607 | switch (command) { |
608 | |
609 | case NAND_CMD_CACHEDPROG: |
610 | case NAND_CMD_PAGEPROG: |
611 | case NAND_CMD_ERASE1: |
612 | case NAND_CMD_ERASE2: |
613 | case NAND_CMD_SEQIN: |
614 | case NAND_CMD_RNDIN: |
615 | case NAND_CMD_STATUS: |
616 | case NAND_CMD_DEPLETE1: |
617 | return; |
618 | |
619 | /* |
620 | * read error status commands require only a short delay |
621 | */ |
622 | case NAND_CMD_STATUS_ERROR: |
623 | case NAND_CMD_STATUS_ERROR0: |
624 | case NAND_CMD_STATUS_ERROR1: |
625 | case NAND_CMD_STATUS_ERROR2: |
626 | case NAND_CMD_STATUS_ERROR3: |
627 | udelay(chip->chip_delay); |
628 | return; |
629 | |
630 | case NAND_CMD_RESET: |
631 | if (chip->dev_ready) |
632 | break; |
633 | udelay(chip->chip_delay); |
634 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
635 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
636 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, |
637 | NAND_NCE | NAND_CTRL_CHANGE); |
638 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
639 | return; |
640 | |
641 | case NAND_CMD_RNDOUT: |
642 | /* No ready / busy check necessary */ |
643 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, |
644 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
645 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, |
646 | NAND_NCE | NAND_CTRL_CHANGE); |
647 | return; |
648 | |
649 | case NAND_CMD_READ0: |
650 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
651 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
652 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, |
653 | NAND_NCE | NAND_CTRL_CHANGE); |
654 | |
655 | /* This applies to read commands */ |
656 | default: |
657 | /* |
658 | * If we don't have access to the busy pin, we apply the given |
659 | * command delay |
660 | */ |
661 | if (!chip->dev_ready) { |
662 | udelay(chip->chip_delay); |
663 | return; |
664 | } |
665 | } |
666 | |
667 | /* Apply this short delay always to ensure that we do wait tWB in |
668 | * any case on any machine. */ |
669 | ndelay(100); |
670 | |
671 | nand_wait_ready(mtd); |
672 | } |
673 | |
674 | /** |
675 | * nand_get_device - [GENERIC] Get chip for selected access |
676 | * @chip: the nand chip descriptor |
677 | * @mtd: MTD device structure |
678 | * @new_state: the state which is requested |
679 | * |
680 | * Get the device and lock it for exclusive access |
681 | */ |
682 | static int |
683 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
684 | { |
685 | spinlock_t *lock = &chip->controller->lock; |
686 | wait_queue_head_t *wq = &chip->controller->wq; |
687 | DECLARE_WAITQUEUE(wait, current); |
688 | retry: |
689 | spin_lock(lock); |
690 | |
691 | /* Hardware controller shared among independend devices */ |
692 | /* Hardware controller shared among independend devices */ |
693 | if (!chip->controller->active) |
694 | chip->controller->active = chip; |
695 | |
696 | if (chip->controller->active == chip && chip->state == FL_READY) { |
697 | chip->state = new_state; |
698 | spin_unlock(lock); |
699 | return 0; |
700 | } |
701 | if (new_state == FL_PM_SUSPENDED) { |
702 | spin_unlock(lock); |
703 | return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; |
704 | } |
705 | set_current_state(TASK_UNINTERRUPTIBLE); |
706 | add_wait_queue(wq, &wait); |
707 | spin_unlock(lock); |
708 | schedule(); |
709 | remove_wait_queue(wq, &wait); |
710 | goto retry; |
711 | } |
712 | |
713 | /** |
714 | * nand_wait - [DEFAULT] wait until the command is done |
715 | * @mtd: MTD device structure |
716 | * @chip: NAND chip structure |
717 | * |
718 | * Wait for command done. This applies to erase and program only |
719 | * Erase can take up to 400ms and program up to 20ms according to |
720 | * general NAND and SmartMedia specs |
721 | */ |
722 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
723 | { |
724 | |
725 | unsigned long timeo = jiffies; |
726 | int status, state = chip->state; |
727 | |
728 | if (state == FL_ERASING) |
729 | timeo += (HZ * 400) / 1000; |
730 | else |
731 | timeo += (HZ * 20) / 1000; |
732 | |
733 | led_trigger_event(nand_led_trigger, LED_FULL); |
734 | |
735 | /* Apply this short delay always to ensure that we do wait tWB in |
736 | * any case on any machine. */ |
737 | ndelay(100); |
738 | |
739 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
740 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); |
741 | else |
742 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
743 | |
744 | while (time_before(jiffies, timeo)) { |
745 | if (chip->dev_ready) { |
746 | if (chip->dev_ready(mtd)) |
747 | break; |
748 | } else { |
749 | if (chip->read_byte(mtd) & NAND_STATUS_READY) |
750 | break; |
751 | } |
752 | cond_resched(); |
753 | } |
754 | led_trigger_event(nand_led_trigger, LED_OFF); |
755 | |
756 | status = (int)chip->read_byte(mtd); |
757 | return status; |
758 | } |
759 | |
760 | /** |
761 | * nand_read_page_raw - [Intern] read raw page data without ecc |
762 | * @mtd: mtd info structure |
763 | * @chip: nand chip info structure |
764 | * @buf: buffer to store read data |
765 | * |
766 | * Not for syndrome calculating ecc controllers, which use a special oob layout |
767 | */ |
768 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
769 | uint8_t *buf) |
770 | { |
771 | chip->read_buf(mtd, buf, mtd->writesize); |
772 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
773 | return 0; |
774 | } |
775 | |
776 | /** |
777 | * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc |
778 | * @mtd: mtd info structure |
779 | * @chip: nand chip info structure |
780 | * @buf: buffer to store read data |
781 | * |
782 | * We need a special oob layout and handling even when OOB isn't used. |
783 | */ |
784 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
785 | uint8_t *buf) |
786 | { |
787 | int eccsize = chip->ecc.size; |
788 | int eccbytes = chip->ecc.bytes; |
789 | uint8_t *oob = chip->oob_poi; |
790 | int steps, size; |
791 | |
792 | for (steps = chip->ecc.steps; steps > 0; steps--) { |
793 | chip->read_buf(mtd, buf, eccsize); |
794 | buf += eccsize; |
795 | |
796 | if (chip->ecc.prepad) { |
797 | chip->read_buf(mtd, oob, chip->ecc.prepad); |
798 | oob += chip->ecc.prepad; |
799 | } |
800 | |
801 | chip->read_buf(mtd, oob, eccbytes); |
802 | oob += eccbytes; |
803 | |
804 | if (chip->ecc.postpad) { |
805 | chip->read_buf(mtd, oob, chip->ecc.postpad); |
806 | oob += chip->ecc.postpad; |
807 | } |
808 | } |
809 | |
810 | size = mtd->oobsize - (oob - chip->oob_poi); |
811 | if (size) |
812 | chip->read_buf(mtd, oob, size); |
813 | |
814 | return 0; |
815 | } |
816 | |
817 | /** |
818 | * nand_read_page_swecc - [REPLACABLE] software ecc based page read function |
819 | * @mtd: mtd info structure |
820 | * @chip: nand chip info structure |
821 | * @buf: buffer to store read data |
822 | */ |
823 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
824 | uint8_t *buf) |
825 | { |
826 | int i, eccsize = chip->ecc.size; |
827 | int eccbytes = chip->ecc.bytes; |
828 | int eccsteps = chip->ecc.steps; |
829 | uint8_t *p = buf; |
830 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
831 | uint8_t *ecc_code = chip->buffers->ecccode; |
832 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
833 | |
834 | chip->ecc.read_page_raw(mtd, chip, buf); |
835 | |
836 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
837 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
838 | |
839 | for (i = 0; i < chip->ecc.total; i++) |
840 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
841 | |
842 | eccsteps = chip->ecc.steps; |
843 | p = buf; |
844 | |
845 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
846 | int stat; |
847 | |
848 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
849 | if (stat < 0) |
850 | mtd->ecc_stats.failed++; |
851 | else |
852 | mtd->ecc_stats.corrected += stat; |
853 | } |
854 | return 0; |
855 | } |
856 | |
857 | /** |
858 | * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function |
859 | * @mtd: mtd info structure |
860 | * @chip: nand chip info structure |
861 | * @data_offs: offset of requested data within the page |
862 | * @readlen: data length |
863 | * @bufpoi: buffer to store read data |
864 | */ |
865 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) |
866 | { |
867 | int start_step, end_step, num_steps; |
868 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
869 | uint8_t *p; |
870 | int data_col_addr, i, gaps = 0; |
871 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; |
872 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; |
873 | |
874 | /* Column address wihin the page aligned to ECC size (256bytes). */ |
875 | start_step = data_offs / chip->ecc.size; |
876 | end_step = (data_offs + readlen - 1) / chip->ecc.size; |
877 | num_steps = end_step - start_step + 1; |
878 | |
879 | /* Data size aligned to ECC ecc.size*/ |
880 | datafrag_len = num_steps * chip->ecc.size; |
881 | eccfrag_len = num_steps * chip->ecc.bytes; |
882 | |
883 | data_col_addr = start_step * chip->ecc.size; |
884 | /* If we read not a page aligned data */ |
885 | if (data_col_addr != 0) |
886 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); |
887 | |
888 | p = bufpoi + data_col_addr; |
889 | chip->read_buf(mtd, p, datafrag_len); |
890 | |
891 | /* Calculate ECC */ |
892 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
893 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); |
894 | |
895 | /* The performance is faster if to position offsets |
896 | according to ecc.pos. Let make sure here that |
897 | there are no gaps in ecc positions */ |
898 | for (i = 0; i < eccfrag_len - 1; i++) { |
899 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != |
900 | eccpos[i + start_step * chip->ecc.bytes + 1]) { |
901 | gaps = 1; |
902 | break; |
903 | } |
904 | } |
905 | if (gaps) { |
906 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); |
907 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
908 | } else { |
909 | /* send the command to read the particular ecc bytes */ |
910 | /* take care about buswidth alignment in read_buf */ |
911 | aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1); |
912 | aligned_len = eccfrag_len; |
913 | if (eccpos[start_step * chip->ecc.bytes] & (busw - 1)) |
914 | aligned_len++; |
915 | if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1)) |
916 | aligned_len++; |
917 | |
918 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1); |
919 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
920 | } |
921 | |
922 | for (i = 0; i < eccfrag_len; i++) |
923 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]]; |
924 | |
925 | p = bufpoi + data_col_addr; |
926 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { |
927 | int stat; |
928 | |
929 | stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); |
930 | if (stat == -1) |
931 | mtd->ecc_stats.failed++; |
932 | else |
933 | mtd->ecc_stats.corrected += stat; |
934 | } |
935 | return 0; |
936 | } |
937 | |
938 | /** |
939 | * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function |
940 | * @mtd: mtd info structure |
941 | * @chip: nand chip info structure |
942 | * @buf: buffer to store read data |
943 | * |
944 | * Not for syndrome calculating ecc controllers which need a special oob layout |
945 | */ |
946 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
947 | uint8_t *buf) |
948 | { |
949 | int i, eccsize = chip->ecc.size; |
950 | int eccbytes = chip->ecc.bytes; |
951 | int eccsteps = chip->ecc.steps; |
952 | uint8_t *p = buf; |
953 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
954 | uint8_t *ecc_code = chip->buffers->ecccode; |
955 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
956 | int stat; |
957 | |
958 | for (i = 0; i < chip->ecc.total; i++) |
959 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
960 | |
961 | |
962 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
963 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
964 | chip->read_buf(mtd, p, eccsize); |
965 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
966 | if (stat < 0) |
967 | mtd->ecc_stats.failed++; |
968 | else |
969 | mtd->ecc_stats.corrected += stat; |
970 | } |
971 | |
972 | return 0; |
973 | } |
974 | |
975 | /** |
976 | * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read |
977 | * @mtd: mtd info structure |
978 | * @chip: nand chip info structure |
979 | * @buf: buffer to store read data |
980 | * |
981 | * The hw generator calculates the error syndrome automatically. Therefor |
982 | * we need a special oob layout and handling. |
983 | */ |
984 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
985 | uint8_t *buf) |
986 | { |
987 | int i, eccsize = chip->ecc.size; |
988 | int eccbytes = chip->ecc.bytes; |
989 | int eccsteps = chip->ecc.steps; |
990 | uint8_t *p = buf; |
991 | uint8_t *oob = chip->oob_poi; |
992 | |
993 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
994 | int stat; |
995 | |
996 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
997 | chip->read_buf(mtd, p, eccsize); |
998 | |
999 | if (chip->ecc.prepad) { |
1000 | chip->read_buf(mtd, oob, chip->ecc.prepad); |
1001 | oob += chip->ecc.prepad; |
1002 | } |
1003 | |
1004 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1005 | chip->read_buf(mtd, oob, eccbytes); |
1006 | stat = chip->ecc.correct(mtd, p, oob, NULL); |
1007 | |
1008 | if (stat < 0) |
1009 | mtd->ecc_stats.failed++; |
1010 | else |
1011 | mtd->ecc_stats.corrected += stat; |
1012 | |
1013 | oob += eccbytes; |
1014 | |
1015 | if (chip->ecc.postpad) { |
1016 | chip->read_buf(mtd, oob, chip->ecc.postpad); |
1017 | oob += chip->ecc.postpad; |
1018 | } |
1019 | } |
1020 | |
1021 | /* Calculate remaining oob bytes */ |
1022 | i = mtd->oobsize - (oob - chip->oob_poi); |
1023 | if (i) |
1024 | chip->read_buf(mtd, oob, i); |
1025 | |
1026 | return 0; |
1027 | } |
1028 | |
1029 | /** |
1030 | * nand_transfer_oob - [Internal] Transfer oob to client buffer |
1031 | * @chip: nand chip structure |
1032 | * @oob: oob destination address |
1033 | * @ops: oob ops structure |
1034 | * @len: size of oob to transfer |
1035 | */ |
1036 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, |
1037 | struct mtd_oob_ops *ops, size_t len) |
1038 | { |
1039 | switch(ops->mode) { |
1040 | |
1041 | case MTD_OOB_PLACE: |
1042 | case MTD_OOB_RAW: |
1043 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1044 | return oob + len; |
1045 | |
1046 | case MTD_OOB_AUTO: { |
1047 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
1048 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1049 | size_t bytes = 0; |
1050 | |
1051 | for(; free->length && len; free++, len -= bytes) { |
1052 | /* Read request not from offset 0 ? */ |
1053 | if (unlikely(roffs)) { |
1054 | if (roffs >= free->length) { |
1055 | roffs -= free->length; |
1056 | continue; |
1057 | } |
1058 | boffs = free->offset + roffs; |
1059 | bytes = min_t(size_t, len, |
1060 | (free->length - roffs)); |
1061 | roffs = 0; |
1062 | } else { |
1063 | bytes = min_t(size_t, len, free->length); |
1064 | boffs = free->offset; |
1065 | } |
1066 | memcpy(oob, chip->oob_poi + boffs, bytes); |
1067 | oob += bytes; |
1068 | } |
1069 | return oob; |
1070 | } |
1071 | default: |
1072 | BUG(); |
1073 | } |
1074 | return NULL; |
1075 | } |
1076 | |
1077 | /** |
1078 | * nand_do_read_ops - [Internal] Read data with ECC |
1079 | * |
1080 | * @mtd: MTD device structure |
1081 | * @from: offset to read from |
1082 | * @ops: oob ops structure |
1083 | * |
1084 | * Internal function. Called with chip held. |
1085 | */ |
1086 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1087 | struct mtd_oob_ops *ops) |
1088 | { |
1089 | int chipnr, page, realpage, col, bytes, aligned; |
1090 | struct nand_chip *chip = mtd->priv; |
1091 | struct mtd_ecc_stats stats; |
1092 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
1093 | int sndcmd = 1; |
1094 | int ret = 0; |
1095 | uint32_t readlen = ops->len; |
1096 | uint32_t oobreadlen = ops->ooblen; |
1097 | uint8_t *bufpoi, *oob, *buf; |
1098 | |
1099 | stats = mtd->ecc_stats; |
1100 | |
1101 | chipnr = (int)(from >> chip->chip_shift); |
1102 | chip->select_chip(mtd, chipnr); |
1103 | |
1104 | realpage = (int)(from >> chip->page_shift); |
1105 | page = realpage & chip->pagemask; |
1106 | |
1107 | col = (int)(from & (mtd->writesize - 1)); |
1108 | |
1109 | buf = ops->datbuf; |
1110 | oob = ops->oobbuf; |
1111 | |
1112 | while(1) { |
1113 | bytes = min(mtd->writesize - col, readlen); |
1114 | aligned = (bytes == mtd->writesize); |
1115 | |
1116 | /* Is the current page in the buffer ? */ |
1117 | if (realpage != chip->pagebuf || oob) { |
1118 | bufpoi = aligned ? buf : chip->buffers->databuf; |
1119 | |
1120 | if (likely(sndcmd)) { |
1121 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x00, page); |
1122 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1123 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1124 | sndcmd = 0; |
1125 | } |
1126 | |
1127 | /* Now read the page into the buffer */ |
1128 | if (unlikely(ops->mode == MTD_OOB_RAW)) |
1129 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi); |
1130 | else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) |
1131 | ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); |
1132 | else |
1133 | ret = chip->ecc.read_page(mtd, chip, bufpoi); |
1134 | if (ret < 0) |
1135 | break; |
1136 | |
1137 | /* Transfer not aligned data */ |
1138 | if (!aligned) { |
1139 | if (!NAND_SUBPAGE_READ(chip) && !oob) |
1140 | chip->pagebuf = realpage; |
1141 | memcpy(buf, chip->buffers->databuf + col, bytes); |
1142 | } |
1143 | |
1144 | buf += bytes; |
1145 | |
1146 | if (unlikely(oob)) { |
1147 | /* Raw mode does data:oob:data:oob */ |
1148 | if (ops->mode != MTD_OOB_RAW) { |
1149 | int toread = min(oobreadlen, |
1150 | chip->ecc.layout->oobavail); |
1151 | if (toread) { |
1152 | oob = nand_transfer_oob(chip, |
1153 | oob, ops, toread); |
1154 | oobreadlen -= toread; |
1155 | } |
1156 | } else |
1157 | buf = nand_transfer_oob(chip, |
1158 | buf, ops, mtd->oobsize); |
1159 | } |
1160 | |
1161 | if (!(chip->options & NAND_NO_READRDY)) { |
1162 | /* |
1163 | * Apply delay or wait for ready/busy pin. Do |
1164 | * this before the AUTOINCR check, so no |
1165 | * problems arise if a chip which does auto |
1166 | * increment is marked as NOAUTOINCR by the |
1167 | * board driver. |
1168 | */ |
1169 | if (!chip->dev_ready) |
1170 | udelay(chip->chip_delay); |
1171 | else |
1172 | nand_wait_ready(mtd); |
1173 | } |
1174 | } else { |
1175 | memcpy(buf, chip->buffers->databuf + col, bytes); |
1176 | buf += bytes; |
1177 | } |
1178 | |
1179 | readlen -= bytes; |
1180 | |
1181 | if (!readlen) |
1182 | break; |
1183 | |
1184 | /* For subsequent reads align to page boundary. */ |
1185 | col = 0; |
1186 | /* Increment page address */ |
1187 | realpage++; |
1188 | |
1189 | page = realpage & chip->pagemask; |
1190 | /* Check, if we cross a chip boundary */ |
1191 | if (!page) { |
1192 | chipnr++; |
1193 | chip->select_chip(mtd, -1); |
1194 | chip->select_chip(mtd, chipnr); |
1195 | } |
1196 | |
1197 | /* Check, if the chip supports auto page increment |
1198 | * or if we have hit a block boundary. |
1199 | */ |
1200 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
1201 | sndcmd = 1; |
1202 | } |
1203 | |
1204 | ops->retlen = ops->len - (size_t) readlen; |
1205 | if (oob) |
1206 | ops->oobretlen = ops->ooblen - oobreadlen; |
1207 | |
1208 | if (ret) |
1209 | return ret; |
1210 | |
1211 | if (mtd->ecc_stats.failed - stats.failed) |
1212 | return -EBADMSG; |
1213 | |
1214 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; |
1215 | } |
1216 | |
1217 | /** |
1218 | * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc |
1219 | * @mtd: MTD device structure |
1220 | * @from: offset to read from |
1221 | * @len: number of bytes to read |
1222 | * @retlen: pointer to variable to store the number of read bytes |
1223 | * @buf: the databuffer to put data |
1224 | * |
1225 | * Get hold of the chip and call nand_do_read |
1226 | */ |
1227 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, |
1228 | size_t *retlen, uint8_t *buf) |
1229 | { |
1230 | struct nand_chip *chip = mtd->priv; |
1231 | int ret; |
1232 | |
1233 | /* Do not allow reads past end of device */ |
1234 | if ((from + len) > mtd->size) |
1235 | return -EINVAL; |
1236 | if (!len) |
1237 | return 0; |
1238 | |
1239 | nand_get_device(chip, mtd, FL_READING); |
1240 | |
1241 | chip->ops.len = len; |
1242 | chip->ops.datbuf = buf; |
1243 | chip->ops.oobbuf = NULL; |
1244 | |
1245 | ret = nand_do_read_ops(mtd, from, &chip->ops); |
1246 | |
1247 | *retlen = chip->ops.retlen; |
1248 | |
1249 | nand_release_device(mtd); |
1250 | |
1251 | return ret; |
1252 | } |
1253 | |
1254 | /** |
1255 | * nand_read_oob_std - [REPLACABLE] the most common OOB data read function |
1256 | * @mtd: mtd info structure |
1257 | * @chip: nand chip info structure |
1258 | * @page: page number to read |
1259 | * @sndcmd: flag whether to issue read command or not |
1260 | */ |
1261 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, |
1262 | int page, int sndcmd) |
1263 | { |
1264 | if (sndcmd) { |
1265 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
1266 | sndcmd = 0; |
1267 | } |
1268 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1269 | return sndcmd; |
1270 | } |
1271 | |
1272 | /** |
1273 | * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC |
1274 | * with syndromes |
1275 | * @mtd: mtd info structure |
1276 | * @chip: nand chip info structure |
1277 | * @page: page number to read |
1278 | * @sndcmd: flag whether to issue read command or not |
1279 | */ |
1280 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
1281 | int page, int sndcmd) |
1282 | { |
1283 | uint8_t *buf = chip->oob_poi; |
1284 | int length = mtd->oobsize; |
1285 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; |
1286 | int eccsize = chip->ecc.size; |
1287 | uint8_t *bufpoi = buf; |
1288 | int i, toread, sndrnd = 0, pos; |
1289 | |
1290 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); |
1291 | for (i = 0; i < chip->ecc.steps; i++) { |
1292 | if (sndrnd) { |
1293 | pos = eccsize + i * (eccsize + chunk); |
1294 | if (mtd->writesize > 512) |
1295 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); |
1296 | else |
1297 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); |
1298 | } else |
1299 | sndrnd = 1; |
1300 | toread = min_t(int, length, chunk); |
1301 | chip->read_buf(mtd, bufpoi, toread); |
1302 | bufpoi += toread; |
1303 | length -= toread; |
1304 | } |
1305 | if (length > 0) |
1306 | chip->read_buf(mtd, bufpoi, length); |
1307 | |
1308 | return 1; |
1309 | } |
1310 | |
1311 | /** |
1312 | * nand_write_oob_std - [REPLACABLE] the most common OOB data write function |
1313 | * @mtd: mtd info structure |
1314 | * @chip: nand chip info structure |
1315 | * @page: page number to write |
1316 | */ |
1317 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, |
1318 | int page) |
1319 | { |
1320 | int status = 0; |
1321 | const uint8_t *buf = chip->oob_poi; |
1322 | int length = mtd->oobsize; |
1323 | |
1324 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); |
1325 | chip->write_buf(mtd, buf, length); |
1326 | /* Send command to program the OOB data */ |
1327 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
1328 | |
1329 | status = chip->waitfunc(mtd, chip); |
1330 | |
1331 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
1332 | } |
1333 | |
1334 | /** |
1335 | * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC |
1336 | * with syndrome - only for large page flash ! |
1337 | * @mtd: mtd info structure |
1338 | * @chip: nand chip info structure |
1339 | * @page: page number to write |
1340 | */ |
1341 | static int nand_write_oob_syndrome(struct mtd_info *mtd, |
1342 | struct nand_chip *chip, int page) |
1343 | { |
1344 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; |
1345 | int eccsize = chip->ecc.size, length = mtd->oobsize; |
1346 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; |
1347 | const uint8_t *bufpoi = chip->oob_poi; |
1348 | |
1349 | /* |
1350 | * data-ecc-data-ecc ... ecc-oob |
1351 | * or |
1352 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob |
1353 | */ |
1354 | if (!chip->ecc.prepad && !chip->ecc.postpad) { |
1355 | pos = steps * (eccsize + chunk); |
1356 | steps = 0; |
1357 | } else |
1358 | pos = eccsize; |
1359 | |
1360 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); |
1361 | for (i = 0; i < steps; i++) { |
1362 | if (sndcmd) { |
1363 | if (mtd->writesize <= 512) { |
1364 | uint32_t fill = 0xFFFFFFFF; |
1365 | |
1366 | len = eccsize; |
1367 | while (len > 0) { |
1368 | int num = min_t(int, len, 4); |
1369 | chip->write_buf(mtd, (uint8_t *)&fill, |
1370 | num); |
1371 | len -= num; |
1372 | } |
1373 | } else { |
1374 | pos = eccsize + i * (eccsize + chunk); |
1375 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); |
1376 | } |
1377 | } else |
1378 | sndcmd = 1; |
1379 | len = min_t(int, length, chunk); |
1380 | chip->write_buf(mtd, bufpoi, len); |
1381 | bufpoi += len; |
1382 | length -= len; |
1383 | } |
1384 | if (length > 0) |
1385 | chip->write_buf(mtd, bufpoi, length); |
1386 | |
1387 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
1388 | status = chip->waitfunc(mtd, chip); |
1389 | |
1390 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
1391 | } |
1392 | |
1393 | /** |
1394 | * nand_do_read_oob - [Intern] NAND read out-of-band |
1395 | * @mtd: MTD device structure |
1396 | * @from: offset to read from |
1397 | * @ops: oob operations description structure |
1398 | * |
1399 | * NAND read out-of-band data from the spare area |
1400 | */ |
1401 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1402 | struct mtd_oob_ops *ops) |
1403 | { |
1404 | int page, realpage, chipnr, sndcmd = 1; |
1405 | struct nand_chip *chip = mtd->priv; |
1406 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
1407 | int readlen = ops->ooblen; |
1408 | int len; |
1409 | uint8_t *buf = ops->oobbuf; |
1410 | |
1411 | DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n", |
1412 | (unsigned long long)from, readlen); |
1413 | |
1414 | if (ops->mode == MTD_OOB_AUTO) |
1415 | len = chip->ecc.layout->oobavail; |
1416 | else |
1417 | len = mtd->oobsize; |
1418 | |
1419 | if (unlikely(ops->ooboffs >= len)) { |
1420 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " |
1421 | "Attempt to start read outside oob\n"); |
1422 | return -EINVAL; |
1423 | } |
1424 | |
1425 | /* Do not allow reads past end of device */ |
1426 | if (unlikely(from >= mtd->size || |
1427 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - |
1428 | (from >> chip->page_shift)) * len)) { |
1429 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " |
1430 | "Attempt read beyond end of device\n"); |
1431 | return -EINVAL; |
1432 | } |
1433 | |
1434 | chipnr = (int)(from >> chip->chip_shift); |
1435 | chip->select_chip(mtd, chipnr); |
1436 | |
1437 | /* Shift to get page */ |
1438 | realpage = (int)(from >> chip->page_shift); |
1439 | page = realpage & chip->pagemask; |
1440 | |
1441 | while(1) { |
1442 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); |
1443 | |
1444 | len = min(len, readlen); |
1445 | buf = nand_transfer_oob(chip, buf, ops, len); |
1446 | |
1447 | if (!(chip->options & NAND_NO_READRDY)) { |
1448 | /* |
1449 | * Apply delay or wait for ready/busy pin. Do this |
1450 | * before the AUTOINCR check, so no problems arise if a |
1451 | * chip which does auto increment is marked as |
1452 | * NOAUTOINCR by the board driver. |
1453 | */ |
1454 | if (!chip->dev_ready) |
1455 | udelay(chip->chip_delay); |
1456 | else |
1457 | nand_wait_ready(mtd); |
1458 | } |
1459 | |
1460 | readlen -= len; |
1461 | if (!readlen) |
1462 | break; |
1463 | |
1464 | /* Increment page address */ |
1465 | realpage++; |
1466 | |
1467 | page = realpage & chip->pagemask; |
1468 | /* Check, if we cross a chip boundary */ |
1469 | if (!page) { |
1470 | chipnr++; |
1471 | chip->select_chip(mtd, -1); |
1472 | chip->select_chip(mtd, chipnr); |
1473 | } |
1474 | |
1475 | /* Check, if the chip supports auto page increment |
1476 | * or if we have hit a block boundary. |
1477 | */ |
1478 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
1479 | sndcmd = 1; |
1480 | } |
1481 | |
1482 | ops->oobretlen = ops->ooblen; |
1483 | return 0; |
1484 | } |
1485 | |
1486 | /** |
1487 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
1488 | * @mtd: MTD device structure |
1489 | * @from: offset to read from |
1490 | * @ops: oob operation description structure |
1491 | * |
1492 | * NAND read data and/or out-of-band data |
1493 | */ |
1494 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1495 | struct mtd_oob_ops *ops) |
1496 | { |
1497 | struct nand_chip *chip = mtd->priv; |
1498 | int ret = -ENOTSUPP; |
1499 | |
1500 | ops->retlen = 0; |
1501 | |
1502 | /* Do not allow reads past end of device */ |
1503 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
1504 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " |
1505 | "Attempt read beyond end of device\n"); |
1506 | return -EINVAL; |
1507 | } |
1508 | |
1509 | nand_get_device(chip, mtd, FL_READING); |
1510 | |
1511 | switch(ops->mode) { |
1512 | case MTD_OOB_PLACE: |
1513 | case MTD_OOB_AUTO: |
1514 | case MTD_OOB_RAW: |
1515 | break; |
1516 | |
1517 | default: |
1518 | goto out; |
1519 | } |
1520 | |
1521 | if (!ops->datbuf) |
1522 | ret = nand_do_read_oob(mtd, from, ops); |
1523 | else |
1524 | ret = nand_do_read_ops(mtd, from, ops); |
1525 | |
1526 | out: |
1527 | nand_release_device(mtd); |
1528 | return ret; |
1529 | } |
1530 | |
1531 | |
1532 | /** |
1533 | * nand_write_page_raw - [Intern] raw page write function |
1534 | * @mtd: mtd info structure |
1535 | * @chip: nand chip info structure |
1536 | * @buf: data buffer |
1537 | * |
1538 | * Not for syndrome calculating ecc controllers, which use a special oob layout |
1539 | */ |
1540 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1541 | const uint8_t *buf) |
1542 | { |
1543 | chip->write_buf(mtd, buf, mtd->writesize); |
1544 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
1545 | } |
1546 | |
1547 | /** |
1548 | * nand_write_page_raw_syndrome - [Intern] raw page write function |
1549 | * @mtd: mtd info structure |
1550 | * @chip: nand chip info structure |
1551 | * @buf: data buffer |
1552 | * |
1553 | * We need a special oob layout and handling even when ECC isn't checked. |
1554 | */ |
1555 | static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
1556 | const uint8_t *buf) |
1557 | { |
1558 | int eccsize = chip->ecc.size; |
1559 | int eccbytes = chip->ecc.bytes; |
1560 | uint8_t *oob = chip->oob_poi; |
1561 | int steps, size; |
1562 | |
1563 | for (steps = chip->ecc.steps; steps > 0; steps--) { |
1564 | chip->write_buf(mtd, buf, eccsize); |
1565 | buf += eccsize; |
1566 | |
1567 | if (chip->ecc.prepad) { |
1568 | chip->write_buf(mtd, oob, chip->ecc.prepad); |
1569 | oob += chip->ecc.prepad; |
1570 | } |
1571 | |
1572 | chip->read_buf(mtd, oob, eccbytes); |
1573 | oob += eccbytes; |
1574 | |
1575 | if (chip->ecc.postpad) { |
1576 | chip->write_buf(mtd, oob, chip->ecc.postpad); |
1577 | oob += chip->ecc.postpad; |
1578 | } |
1579 | } |
1580 | |
1581 | size = mtd->oobsize - (oob - chip->oob_poi); |
1582 | if (size) |
1583 | chip->write_buf(mtd, oob, size); |
1584 | } |
1585 | /** |
1586 | * nand_write_page_swecc - [REPLACABLE] software ecc based page write function |
1587 | * @mtd: mtd info structure |
1588 | * @chip: nand chip info structure |
1589 | * @buf: data buffer |
1590 | */ |
1591 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1592 | const uint8_t *buf) |
1593 | { |
1594 | int i, eccsize = chip->ecc.size; |
1595 | int eccbytes = chip->ecc.bytes; |
1596 | int eccsteps = chip->ecc.steps; |
1597 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1598 | const uint8_t *p = buf; |
1599 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
1600 | |
1601 | /* Software ecc calculation */ |
1602 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
1603 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
1604 | |
1605 | for (i = 0; i < chip->ecc.total; i++) |
1606 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; |
1607 | |
1608 | chip->ecc.write_page_raw(mtd, chip, buf); |
1609 | } |
1610 | |
1611 | /** |
1612 | * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function |
1613 | * @mtd: mtd info structure |
1614 | * @chip: nand chip info structure |
1615 | * @buf: data buffer |
1616 | */ |
1617 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1618 | const uint8_t *buf) |
1619 | { |
1620 | int i, eccsize = chip->ecc.size; |
1621 | int eccbytes = chip->ecc.bytes; |
1622 | int eccsteps = chip->ecc.steps; |
1623 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1624 | const uint8_t *p = buf; |
1625 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
1626 | |
1627 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1628 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
1629 | chip->write_buf(mtd, p, eccsize); |
1630 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
1631 | } |
1632 | |
1633 | for (i = 0; i < chip->ecc.total; i++) |
1634 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; |
1635 | |
1636 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
1637 | } |
1638 | |
1639 | /** |
1640 | * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write |
1641 | * @mtd: mtd info structure |
1642 | * @chip: nand chip info structure |
1643 | * @buf: data buffer |
1644 | * |
1645 | * The hw generator calculates the error syndrome automatically. Therefor |
1646 | * we need a special oob layout and handling. |
1647 | */ |
1648 | static void nand_write_page_syndrome(struct mtd_info *mtd, |
1649 | struct nand_chip *chip, const uint8_t *buf) |
1650 | { |
1651 | int i, eccsize = chip->ecc.size; |
1652 | int eccbytes = chip->ecc.bytes; |
1653 | int eccsteps = chip->ecc.steps; |
1654 | const uint8_t *p = buf; |
1655 | uint8_t *oob = chip->oob_poi; |
1656 | |
1657 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1658 | |
1659 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
1660 | chip->write_buf(mtd, p, eccsize); |
1661 | |
1662 | if (chip->ecc.prepad) { |
1663 | chip->write_buf(mtd, oob, chip->ecc.prepad); |
1664 | oob += chip->ecc.prepad; |
1665 | } |
1666 | |
1667 | chip->ecc.calculate(mtd, p, oob); |
1668 | chip->write_buf(mtd, oob, eccbytes); |
1669 | oob += eccbytes; |
1670 | |
1671 | if (chip->ecc.postpad) { |
1672 | chip->write_buf(mtd, oob, chip->ecc.postpad); |
1673 | oob += chip->ecc.postpad; |
1674 | } |
1675 | } |
1676 | |
1677 | /* Calculate remaining oob bytes */ |
1678 | i = mtd->oobsize - (oob - chip->oob_poi); |
1679 | if (i) |
1680 | chip->write_buf(mtd, oob, i); |
1681 | } |
1682 | |
1683 | /** |
1684 | * nand_write_page - [REPLACEABLE] write one page |
1685 | * @mtd: MTD device structure |
1686 | * @chip: NAND chip descriptor |
1687 | * @buf: the data to write |
1688 | * @page: page number to write |
1689 | * @cached: cached programming |
1690 | * @raw: use _raw version of write_page |
1691 | */ |
1692 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1693 | const uint8_t *buf, int page, int cached, int raw) |
1694 | { |
1695 | int status; |
1696 | |
1697 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); |
1698 | |
1699 | if (unlikely(raw)) |
1700 | chip->ecc.write_page_raw(mtd, chip, buf); |
1701 | else |
1702 | chip->ecc.write_page(mtd, chip, buf); |
1703 | |
1704 | /* |
1705 | * Cached progamming disabled for now, Not sure if its worth the |
1706 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) |
1707 | */ |
1708 | cached = 0; |
1709 | |
1710 | if (!cached || !(chip->options & NAND_CACHEPRG)) { |
1711 | |
1712 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
1713 | status = chip->waitfunc(mtd, chip); |
1714 | /* |
1715 | * See if operation failed and additional status checks are |
1716 | * available |
1717 | */ |
1718 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) |
1719 | status = chip->errstat(mtd, chip, FL_WRITING, status, |
1720 | page); |
1721 | |
1722 | if (status & NAND_STATUS_FAIL) |
1723 | return -EIO; |
1724 | } else { |
1725 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); |
1726 | status = chip->waitfunc(mtd, chip); |
1727 | } |
1728 | |
1729 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE |
1730 | /* Send command to read back the data */ |
1731 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); |
1732 | |
1733 | if (chip->verify_buf(mtd, buf, mtd->writesize)) |
1734 | return -EIO; |
1735 | #endif |
1736 | return 0; |
1737 | } |
1738 | |
1739 | /** |
1740 | * nand_fill_oob - [Internal] Transfer client buffer to oob |
1741 | * @chip: nand chip structure |
1742 | * @oob: oob data buffer |
1743 | * @ops: oob ops structure |
1744 | */ |
1745 | static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, |
1746 | struct mtd_oob_ops *ops) |
1747 | { |
1748 | size_t len = ops->ooblen; |
1749 | |
1750 | switch(ops->mode) { |
1751 | |
1752 | case MTD_OOB_PLACE: |
1753 | case MTD_OOB_RAW: |
1754 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
1755 | return oob + len; |
1756 | |
1757 | case MTD_OOB_AUTO: { |
1758 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
1759 | uint32_t boffs = 0, woffs = ops->ooboffs; |
1760 | size_t bytes = 0; |
1761 | |
1762 | for(; free->length && len; free++, len -= bytes) { |
1763 | /* Write request not from offset 0 ? */ |
1764 | if (unlikely(woffs)) { |
1765 | if (woffs >= free->length) { |
1766 | woffs -= free->length; |
1767 | continue; |
1768 | } |
1769 | boffs = free->offset + woffs; |
1770 | bytes = min_t(size_t, len, |
1771 | (free->length - woffs)); |
1772 | woffs = 0; |
1773 | } else { |
1774 | bytes = min_t(size_t, len, free->length); |
1775 | boffs = free->offset; |
1776 | } |
1777 | memcpy(chip->oob_poi + boffs, oob, bytes); |
1778 | oob += bytes; |
1779 | } |
1780 | return oob; |
1781 | } |
1782 | default: |
1783 | BUG(); |
1784 | } |
1785 | return NULL; |
1786 | } |
1787 | |
1788 | #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0 |
1789 | |
1790 | /** |
1791 | * nand_do_write_ops - [Internal] NAND write with ECC |
1792 | * @mtd: MTD device structure |
1793 | * @to: offset to write to |
1794 | * @ops: oob operations description structure |
1795 | * |
1796 | * NAND write with ECC |
1797 | */ |
1798 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
1799 | struct mtd_oob_ops *ops) |
1800 | { |
1801 | int chipnr, realpage, page, blockmask, column; |
1802 | struct nand_chip *chip = mtd->priv; |
1803 | uint32_t writelen = ops->len; |
1804 | uint8_t *oob = ops->oobbuf; |
1805 | uint8_t *buf = ops->datbuf; |
1806 | int ret, subpage; |
1807 | |
1808 | ops->retlen = 0; |
1809 | if (!writelen) |
1810 | return 0; |
1811 | |
1812 | /* reject writes, which are not page aligned */ |
1813 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
1814 | printk(KERN_NOTICE "nand_write: " |
1815 | "Attempt to write not page aligned data\n"); |
1816 | return -EINVAL; |
1817 | } |
1818 | |
1819 | column = to & (mtd->writesize - 1); |
1820 | subpage = column || (writelen & (mtd->writesize - 1)); |
1821 | |
1822 | if (subpage && oob) |
1823 | return -EINVAL; |
1824 | |
1825 | chipnr = (int)(to >> chip->chip_shift); |
1826 | chip->select_chip(mtd, chipnr); |
1827 | |
1828 | /* Check, if it is write protected */ |
1829 | if (nand_check_wp(mtd)) |
1830 | return -EIO; |
1831 | |
1832 | realpage = (int)(to >> chip->page_shift); |
1833 | page = realpage & chip->pagemask; |
1834 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
1835 | |
1836 | /* Invalidate the page cache, when we write to the cached page */ |
1837 | if (to <= (chip->pagebuf << chip->page_shift) && |
1838 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
1839 | chip->pagebuf = -1; |
1840 | |
1841 | /* If we're not given explicit OOB data, let it be 0xFF */ |
1842 | if (likely(!oob)) |
1843 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
1844 | |
1845 | while(1) { |
1846 | int bytes = mtd->writesize; |
1847 | int cached = writelen > bytes && page != blockmask; |
1848 | uint8_t *wbuf = buf; |
1849 | |
1850 | /* Partial page write ? */ |
1851 | if (unlikely(column || writelen < (mtd->writesize - 1))) { |
1852 | cached = 0; |
1853 | bytes = min_t(int, bytes - column, (int) writelen); |
1854 | chip->pagebuf = -1; |
1855 | memset(chip->buffers->databuf, 0xff, mtd->writesize); |
1856 | memcpy(&chip->buffers->databuf[column], buf, bytes); |
1857 | wbuf = chip->buffers->databuf; |
1858 | } |
1859 | |
1860 | if (unlikely(oob)) |
1861 | oob = nand_fill_oob(chip, oob, ops); |
1862 | |
1863 | ret = chip->write_page(mtd, chip, wbuf, page, cached, |
1864 | (ops->mode == MTD_OOB_RAW)); |
1865 | if (ret) |
1866 | break; |
1867 | |
1868 | writelen -= bytes; |
1869 | if (!writelen) |
1870 | break; |
1871 | |
1872 | column = 0; |
1873 | buf += bytes; |
1874 | realpage++; |
1875 | |
1876 | page = realpage & chip->pagemask; |
1877 | /* Check, if we cross a chip boundary */ |
1878 | if (!page) { |
1879 | chipnr++; |
1880 | chip->select_chip(mtd, -1); |
1881 | chip->select_chip(mtd, chipnr); |
1882 | } |
1883 | } |
1884 | |
1885 | ops->retlen = ops->len - writelen; |
1886 | if (unlikely(oob)) |
1887 | ops->oobretlen = ops->ooblen; |
1888 | return ret; |
1889 | } |
1890 | |
1891 | /** |
1892 | * nand_write - [MTD Interface] NAND write with ECC |
1893 | * @mtd: MTD device structure |
1894 | * @to: offset to write to |
1895 | * @len: number of bytes to write |
1896 | * @retlen: pointer to variable to store the number of written bytes |
1897 | * @buf: the data to write |
1898 | * |
1899 | * NAND write with ECC |
1900 | */ |
1901 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
1902 | size_t *retlen, const uint8_t *buf) |
1903 | { |
1904 | struct nand_chip *chip = mtd->priv; |
1905 | int ret; |
1906 | |
1907 | /* Do not allow reads past end of device */ |
1908 | if ((to + len) > mtd->size) |
1909 | return -EINVAL; |
1910 | if (!len) |
1911 | return 0; |
1912 | |
1913 | nand_get_device(chip, mtd, FL_WRITING); |
1914 | |
1915 | chip->ops.len = len; |
1916 | chip->ops.datbuf = (uint8_t *)buf; |
1917 | chip->ops.oobbuf = NULL; |
1918 | |
1919 | ret = nand_do_write_ops(mtd, to, &chip->ops); |
1920 | |
1921 | *retlen = chip->ops.retlen; |
1922 | |
1923 | nand_release_device(mtd); |
1924 | |
1925 | return ret; |
1926 | } |
1927 | |
1928 | /** |
1929 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
1930 | * @mtd: MTD device structure |
1931 | * @to: offset to write to |
1932 | * @ops: oob operation description structure |
1933 | * |
1934 | * NAND write out-of-band |
1935 | */ |
1936 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
1937 | struct mtd_oob_ops *ops) |
1938 | { |
1939 | int chipnr, page, status, len; |
1940 | struct nand_chip *chip = mtd->priv; |
1941 | |
1942 | DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", |
1943 | (unsigned int)to, (int)ops->ooblen); |
1944 | |
1945 | if (ops->mode == MTD_OOB_AUTO) |
1946 | len = chip->ecc.layout->oobavail; |
1947 | else |
1948 | len = mtd->oobsize; |
1949 | |
1950 | /* Do not allow write past end of page */ |
1951 | if ((ops->ooboffs + ops->ooblen) > len) { |
1952 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
1953 | "Attempt to write past end of page\n"); |
1954 | return -EINVAL; |
1955 | } |
1956 | |
1957 | if (unlikely(ops->ooboffs >= len)) { |
1958 | DEBUG(MTD_DEBUG_LEVEL0, "nand_do_write_oob: " |
1959 | "Attempt to start write outside oob\n"); |
1960 | return -EINVAL; |
1961 | } |
1962 | |
1963 | /* Do not allow reads past end of device */ |
1964 | if (unlikely(to >= mtd->size || |
1965 | ops->ooboffs + ops->ooblen > |
1966 | ((mtd->size >> chip->page_shift) - |
1967 | (to >> chip->page_shift)) * len)) { |
1968 | DEBUG(MTD_DEBUG_LEVEL0, "nand_do_write_oob: " |
1969 | "Attempt write beyond end of device\n"); |
1970 | return -EINVAL; |
1971 | } |
1972 | |
1973 | chipnr = (int)(to >> chip->chip_shift); |
1974 | chip->select_chip(mtd, chipnr); |
1975 | |
1976 | /* Shift to get page */ |
1977 | page = (int)(to >> chip->page_shift); |
1978 | |
1979 | /* |
1980 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one |
1981 | * of my DiskOnChip 2000 test units) will clear the whole data page too |
1982 | * if we don't do this. I have no clue why, but I seem to have 'fixed' |
1983 | * it in the doc2000 driver in August 1999. dwmw2. |
1984 | */ |
1985 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1986 | |
1987 | /* Check, if it is write protected */ |
1988 | if (nand_check_wp(mtd)) |
1989 | return -EROFS; |
1990 | |
1991 | /* Invalidate the page cache, if we write to the cached page */ |
1992 | if (page == chip->pagebuf) |
1993 | chip->pagebuf = -1; |
1994 | |
1995 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
1996 | nand_fill_oob(chip, ops->oobbuf, ops); |
1997 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); |
1998 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
1999 | |
2000 | if (status) |
2001 | return status; |
2002 | |
2003 | ops->oobretlen = ops->ooblen; |
2004 | |
2005 | return 0; |
2006 | } |
2007 | |
2008 | /** |
2009 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band |
2010 | * @mtd: MTD device structure |
2011 | * @to: offset to write to |
2012 | * @ops: oob operation description structure |
2013 | */ |
2014 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, |
2015 | struct mtd_oob_ops *ops) |
2016 | { |
2017 | struct nand_chip *chip = mtd->priv; |
2018 | int ret = -ENOTSUPP; |
2019 | |
2020 | ops->retlen = 0; |
2021 | |
2022 | /* Do not allow writes past end of device */ |
2023 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
2024 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
2025 | "Attempt write beyond end of device\n"); |
2026 | return -EINVAL; |
2027 | } |
2028 | |
2029 | nand_get_device(chip, mtd, FL_WRITING); |
2030 | |
2031 | switch(ops->mode) { |
2032 | case MTD_OOB_PLACE: |
2033 | case MTD_OOB_AUTO: |
2034 | case MTD_OOB_RAW: |
2035 | break; |
2036 | |
2037 | default: |
2038 | goto out; |
2039 | } |
2040 | |
2041 | if (!ops->datbuf) |
2042 | ret = nand_do_write_oob(mtd, to, ops); |
2043 | else |
2044 | ret = nand_do_write_ops(mtd, to, ops); |
2045 | |
2046 | out: |
2047 | nand_release_device(mtd); |
2048 | return ret; |
2049 | } |
2050 | |
2051 | /** |
2052 | * single_erease_cmd - [GENERIC] NAND standard block erase command function |
2053 | * @mtd: MTD device structure |
2054 | * @page: the page address of the block which will be erased |
2055 | * |
2056 | * Standard erase command for NAND chips |
2057 | */ |
2058 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
2059 | { |
2060 | struct nand_chip *chip = mtd->priv; |
2061 | /* Send commands to erase a block */ |
2062 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2063 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); |
2064 | } |
2065 | |
2066 | /** |
2067 | * multi_erease_cmd - [GENERIC] AND specific block erase command function |
2068 | * @mtd: MTD device structure |
2069 | * @page: the page address of the block which will be erased |
2070 | * |
2071 | * AND multi block erase command function |
2072 | * Erase 4 consecutive blocks |
2073 | */ |
2074 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
2075 | { |
2076 | struct nand_chip *chip = mtd->priv; |
2077 | /* Send commands to erase a block */ |
2078 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2079 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2080 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2081 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2082 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); |
2083 | } |
2084 | |
2085 | /** |
2086 | * nand_erase - [MTD Interface] erase block(s) |
2087 | * @mtd: MTD device structure |
2088 | * @instr: erase instruction |
2089 | * |
2090 | * Erase one ore more blocks |
2091 | */ |
2092 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
2093 | { |
2094 | return nand_erase_nand(mtd, instr, 0); |
2095 | } |
2096 | |
2097 | #define BBT_PAGE_MASK 0xffffff3f |
2098 | /** |
2099 | * nand_erase_nand - [Internal] erase block(s) |
2100 | * @mtd: MTD device structure |
2101 | * @instr: erase instruction |
2102 | * @allowbbt: allow erasing the bbt area |
2103 | * |
2104 | * Erase one ore more blocks |
2105 | */ |
2106 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2107 | int allowbbt) |
2108 | { |
2109 | int page, status, pages_per_block, ret, chipnr; |
2110 | struct nand_chip *chip = mtd->priv; |
2111 | loff_t rewrite_bbt[NAND_MAX_CHIPS]={0}; |
2112 | unsigned int bbt_masked_page = 0xffffffff; |
2113 | loff_t len; |
2114 | |
2115 | DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, len = %llu\n", |
2116 | (unsigned long long)instr->addr, (unsigned long long)instr->len); |
2117 | |
2118 | /* Start address must align on block boundary */ |
2119 | if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { |
2120 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); |
2121 | return -EINVAL; |
2122 | } |
2123 | |
2124 | /* Length must align on block boundary */ |
2125 | if (instr->len & ((1 << chip->phys_erase_shift) - 1)) { |
2126 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
2127 | "Length not block aligned\n"); |
2128 | return -EINVAL; |
2129 | } |
2130 | |
2131 | /* Do not allow erase past end of device */ |
2132 | if ((instr->len + instr->addr) > mtd->size) { |
2133 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
2134 | "Erase past end of device\n"); |
2135 | return -EINVAL; |
2136 | } |
2137 | |
2138 | instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; |
2139 | |
2140 | /* Grab the lock and see if the device is available */ |
2141 | nand_get_device(chip, mtd, FL_ERASING); |
2142 | |
2143 | /* Shift to get first page */ |
2144 | page = (int)(instr->addr >> chip->page_shift); |
2145 | chipnr = (int)(instr->addr >> chip->chip_shift); |
2146 | |
2147 | /* Calculate pages in each block */ |
2148 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
2149 | |
2150 | /* Select the NAND device */ |
2151 | chip->select_chip(mtd, chipnr); |
2152 | |
2153 | /* Check, if it is write protected */ |
2154 | if (nand_check_wp(mtd)) { |
2155 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
2156 | "Device is write protected!!!\n"); |
2157 | instr->state = MTD_ERASE_FAILED; |
2158 | goto erase_exit; |
2159 | } |
2160 | |
2161 | /* |
2162 | * If BBT requires refresh, set the BBT page mask to see if the BBT |
2163 | * should be rewritten. Otherwise the mask is set to 0xffffffff which |
2164 | * can not be matched. This is also done when the bbt is actually |
2165 | * erased to avoid recusrsive updates |
2166 | */ |
2167 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) |
2168 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; |
2169 | |
2170 | /* Loop through the pages */ |
2171 | len = instr->len; |
2172 | |
2173 | instr->state = MTD_ERASING; |
2174 | |
2175 | while (len) { |
2176 | /* |
2177 | * heck if we have a bad block, we do not erase bad blocks ! |
2178 | */ |
2179 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2180 | chip->page_shift, 0, allowbbt)) { |
2181 | printk(KERN_WARNING "nand_erase: attempt to erase a " |
2182 | "bad block at page 0x%08x\n", page); |
2183 | instr->state = MTD_ERASE_FAILED; |
2184 | goto erase_exit; |
2185 | } |
2186 | |
2187 | /* |
2188 | * Invalidate the page cache, if we erase the block which |
2189 | * contains the current cached page |
2190 | */ |
2191 | if (page <= chip->pagebuf && chip->pagebuf < |
2192 | (page + pages_per_block)) |
2193 | chip->pagebuf = -1; |
2194 | |
2195 | chip->erase_cmd(mtd, page & chip->pagemask); |
2196 | |
2197 | status = chip->waitfunc(mtd, chip); |
2198 | |
2199 | /* |
2200 | * See if operation failed and additional status checks are |
2201 | * available |
2202 | */ |
2203 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) |
2204 | status = chip->errstat(mtd, chip, FL_ERASING, |
2205 | status, page); |
2206 | |
2207 | /* See if block erase succeeded */ |
2208 | if (status & NAND_STATUS_FAIL) { |
2209 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
2210 | "Failed erase, page 0x%08x\n", page); |
2211 | instr->state = MTD_ERASE_FAILED; |
2212 | instr->fail_addr = |
2213 | ((loff_t)page << chip->page_shift); |
2214 | goto erase_exit; |
2215 | } |
2216 | |
2217 | /* |
2218 | * If BBT requires refresh, set the BBT rewrite flag to the |
2219 | * page being erased |
2220 | */ |
2221 | if (bbt_masked_page != 0xffffffff && |
2222 | (page & BBT_PAGE_MASK) == bbt_masked_page) |
2223 | rewrite_bbt[chipnr] = |
2224 | ((loff_t)page << chip->page_shift); |
2225 | |
2226 | /* Increment page address and decrement length */ |
2227 | len -= (1 << chip->phys_erase_shift); |
2228 | page += pages_per_block; |
2229 | |
2230 | /* Check, if we cross a chip boundary */ |
2231 | if (len && !(page & chip->pagemask)) { |
2232 | chipnr++; |
2233 | chip->select_chip(mtd, -1); |
2234 | chip->select_chip(mtd, chipnr); |
2235 | |
2236 | /* |
2237 | * If BBT requires refresh and BBT-PERCHIP, set the BBT |
2238 | * page mask to see if this BBT should be rewritten |
2239 | */ |
2240 | if (bbt_masked_page != 0xffffffff && |
2241 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) |
2242 | bbt_masked_page = chip->bbt_td->pages[chipnr] & |
2243 | BBT_PAGE_MASK; |
2244 | } |
2245 | } |
2246 | instr->state = MTD_ERASE_DONE; |
2247 | |
2248 | erase_exit: |
2249 | |
2250 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; |
2251 | |
2252 | /* Deselect and wake up anyone waiting on the device */ |
2253 | nand_release_device(mtd); |
2254 | |
2255 | /* Do call back function */ |
2256 | if (!ret) |
2257 | mtd_erase_callback(instr); |
2258 | |
2259 | /* |
2260 | * If BBT requires refresh and erase was successful, rewrite any |
2261 | * selected bad block tables |
2262 | */ |
2263 | if (bbt_masked_page == 0xffffffff || ret) |
2264 | return ret; |
2265 | |
2266 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { |
2267 | if (!rewrite_bbt[chipnr]) |
2268 | continue; |
2269 | /* update the BBT for chip */ |
2270 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " |
2271 | "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr], |
2272 | chip->bbt_td->pages[chipnr]); |
2273 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
2274 | } |
2275 | |
2276 | /* Return more or less happy */ |
2277 | return ret; |
2278 | } |
2279 | |
2280 | /** |
2281 | * nand_sync - [MTD Interface] sync |
2282 | * @mtd: MTD device structure |
2283 | * |
2284 | * Sync is actually a wait for chip ready function |
2285 | */ |
2286 | static void nand_sync(struct mtd_info *mtd) |
2287 | { |
2288 | struct nand_chip *chip = mtd->priv; |
2289 | |
2290 | DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n"); |
2291 | |
2292 | /* Grab the lock and see if the device is available */ |
2293 | nand_get_device(chip, mtd, FL_SYNCING); |
2294 | /* Release it and go back */ |
2295 | nand_release_device(mtd); |
2296 | } |
2297 | |
2298 | /** |
2299 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
2300 | * @mtd: MTD device structure |
2301 | * @offs: offset relative to mtd start |
2302 | */ |
2303 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
2304 | { |
2305 | /* Check for invalid offset */ |
2306 | if (offs > mtd->size) |
2307 | return -EINVAL; |
2308 | |
2309 | return nand_block_checkbad(mtd, offs, 1, 0); |
2310 | } |
2311 | |
2312 | /** |
2313 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
2314 | * @mtd: MTD device structure |
2315 | * @ofs: offset relative to mtd start |
2316 | */ |
2317 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
2318 | { |
2319 | struct nand_chip *chip = mtd->priv; |
2320 | int ret; |
2321 | |
2322 | if ((ret = nand_block_isbad(mtd, ofs))) { |
2323 | /* If it was bad already, return success and do nothing. */ |
2324 | if (ret > 0) |
2325 | return 0; |
2326 | return ret; |
2327 | } |
2328 | |
2329 | return chip->block_markbad(mtd, ofs); |
2330 | } |
2331 | |
2332 | /** |
2333 | * nand_suspend - [MTD Interface] Suspend the NAND flash |
2334 | * @mtd: MTD device structure |
2335 | */ |
2336 | static int nand_suspend(struct mtd_info *mtd) |
2337 | { |
2338 | struct nand_chip *chip = mtd->priv; |
2339 | |
2340 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
2341 | } |
2342 | |
2343 | /** |
2344 | * nand_resume - [MTD Interface] Resume the NAND flash |
2345 | * @mtd: MTD device structure |
2346 | */ |
2347 | static void nand_resume(struct mtd_info *mtd) |
2348 | { |
2349 | struct nand_chip *chip = mtd->priv; |
2350 | |
2351 | if (chip->state == FL_PM_SUSPENDED) |
2352 | nand_release_device(mtd); |
2353 | else |
2354 | printk(KERN_ERR "nand_resume() called for a chip which is not " |
2355 | "in suspended state\n"); |
2356 | } |
2357 | |
2358 | /* |
2359 | * Set default functions |
2360 | */ |
2361 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
2362 | { |
2363 | /* check for proper chip_delay setup, set 20us if not */ |
2364 | if (!chip->chip_delay) |
2365 | chip->chip_delay = 20; |
2366 | |
2367 | /* check, if a user supplied command function given */ |
2368 | if (chip->cmdfunc == NULL) |
2369 | chip->cmdfunc = nand_command; |
2370 | |
2371 | /* check, if a user supplied wait function given */ |
2372 | if (chip->waitfunc == NULL) |
2373 | chip->waitfunc = nand_wait; |
2374 | |
2375 | if (!chip->select_chip) |
2376 | chip->select_chip = nand_select_chip; |
2377 | if (!chip->read_byte) |
2378 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
2379 | if (!chip->read_word) |
2380 | chip->read_word = nand_read_word; |
2381 | if (!chip->block_bad) |
2382 | chip->block_bad = nand_block_bad; |
2383 | if (!chip->block_markbad) |
2384 | chip->block_markbad = nand_default_block_markbad; |
2385 | if (!chip->write_buf) |
2386 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
2387 | if (!chip->read_buf) |
2388 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
2389 | if (!chip->verify_buf) |
2390 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; |
2391 | if (!chip->scan_bbt) |
2392 | chip->scan_bbt = nand_default_bbt; |
2393 | |
2394 | if (!chip->controller) { |
2395 | chip->controller = &chip->hwcontrol; |
2396 | spin_lock_init(&chip->controller->lock); |
2397 | init_waitqueue_head(&chip->controller->wq); |
2398 | } |
2399 | |
2400 | } |
2401 | |
2402 | /* |
2403 | * Get the flash and manufacturer id and lookup if the type is supported |
2404 | */ |
2405 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, |
2406 | struct nand_chip *chip, |
2407 | int busw, int *maf_id) |
2408 | { |
2409 | struct nand_flash_dev *type = NULL; |
2410 | int i, dev_id, maf_idx; |
2411 | int tmp_id, tmp_manf; |
2412 | |
2413 | /* Select the device */ |
2414 | chip->select_chip(mtd, 0); |
2415 | |
2416 | /* |
2417 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) |
2418 | * after power-up |
2419 | */ |
2420 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
2421 | |
2422 | /* Send the command for reading device ID */ |
2423 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
2424 | |
2425 | /* Read manufacturer and device IDs */ |
2426 | *maf_id = chip->read_byte(mtd); |
2427 | dev_id = chip->read_byte(mtd); |
2428 | |
2429 | /* Try again to make sure, as some systems the bus-hold or other |
2430 | * interface concerns can cause random data which looks like a |
2431 | * possibly credible NAND flash to appear. If the two results do |
2432 | * not match, ignore the device completely. |
2433 | */ |
2434 | |
2435 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
2436 | |
2437 | /* Read manufacturer and device IDs */ |
2438 | |
2439 | tmp_manf = chip->read_byte(mtd); |
2440 | tmp_id = chip->read_byte(mtd); |
2441 | |
2442 | if (tmp_manf != *maf_id || tmp_id != dev_id) { |
2443 | printk(KERN_INFO "%s: second ID read did not match " |
2444 | "%02x,%02x against %02x,%02x\n", __func__, |
2445 | *maf_id, dev_id, tmp_manf, tmp_id); |
2446 | return ERR_PTR(-ENODEV); |
2447 | } |
2448 | |
2449 | /* Lookup the flash id */ |
2450 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { |
2451 | if (dev_id == nand_flash_ids[i].id) { |
2452 | type = &nand_flash_ids[i]; |
2453 | break; |
2454 | } |
2455 | } |
2456 | |
2457 | if (!type) |
2458 | return ERR_PTR(-ENODEV); |
2459 | |
2460 | if (!mtd->name) |
2461 | mtd->name = type->name; |
2462 | |
2463 | chip->chipsize = (uint64_t)type->chipsize << 20; |
2464 | |
2465 | /* Newer devices have all the information in additional id bytes */ |
2466 | if (!type->pagesize) { |
2467 | int extid; |
2468 | /* The 3rd id byte holds MLC / multichip data */ |
2469 | chip->cellinfo = chip->read_byte(mtd); |
2470 | /* The 4th id byte is the important one */ |
2471 | extid = chip->read_byte(mtd); |
2472 | /* Calc pagesize */ |
2473 | mtd->writesize = 1024 << (extid & 0x3); |
2474 | extid >>= 2; |
2475 | /* Calc oobsize */ |
2476 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); |
2477 | extid >>= 2; |
2478 | /* Calc blocksize. Blocksize is multiples of 64KiB */ |
2479 | mtd->erasesize = (64 * 1024) << (extid & 0x03); |
2480 | extid >>= 2; |
2481 | /* Get buswidth information */ |
2482 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; |
2483 | |
2484 | } else { |
2485 | /* |
2486 | * Old devices have chip data hardcoded in the device id table |
2487 | */ |
2488 | mtd->erasesize = type->erasesize; |
2489 | mtd->writesize = type->pagesize; |
2490 | mtd->oobsize = mtd->writesize / 32; |
2491 | busw = type->options & NAND_BUSWIDTH_16; |
2492 | } |
2493 | |
2494 | /* Try to identify manufacturer */ |
2495 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
2496 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
2497 | break; |
2498 | } |
2499 | |
2500 | /* |
2501 | * Check, if buswidth is correct. Hardware drivers should set |
2502 | * chip correct ! |
2503 | */ |
2504 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
2505 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2506 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, |
2507 | dev_id, nand_manuf_ids[maf_idx].name, mtd->name); |
2508 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", |
2509 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
2510 | busw ? 16 : 8); |
2511 | return ERR_PTR(-EINVAL); |
2512 | } |
2513 | |
2514 | /* Calculate the address shift from the page size */ |
2515 | chip->page_shift = ffs(mtd->writesize) - 1; |
2516 | /* Convert chipsize to number of pages per chip -1. */ |
2517 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
2518 | |
2519 | chip->bbt_erase_shift = chip->phys_erase_shift = |
2520 | ffs(mtd->erasesize) - 1; |
2521 | if (chip->chipsize & 0xffffffff) |
2522 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; |
2523 | else |
2524 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1; |
2525 | |
2526 | /* Set the bad block position */ |
2527 | chip->badblockpos = mtd->writesize > 512 ? |
2528 | NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; |
2529 | |
2530 | /* Get chip options, preserve non chip based options */ |
2531 | chip->options &= ~NAND_CHIPOPTIONS_MSK; |
2532 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; |
2533 | |
2534 | /* |
2535 | * Set chip as a default. Board drivers can override it, if necessary |
2536 | */ |
2537 | chip->options |= NAND_NO_AUTOINCR; |
2538 | |
2539 | /* Check if chip is a not a samsung device. Do not clear the |
2540 | * options for chips which are not having an extended id. |
2541 | */ |
2542 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) |
2543 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; |
2544 | |
2545 | /* Check for AND chips with 4 page planes */ |
2546 | if (chip->options & NAND_4PAGE_ARRAY) |
2547 | chip->erase_cmd = multi_erase_cmd; |
2548 | else |
2549 | chip->erase_cmd = single_erase_cmd; |
2550 | |
2551 | /* Do not replace user supplied command function ! */ |
2552 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
2553 | chip->cmdfunc = nand_command_lp; |
2554 | |
2555 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2556 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, |
2557 | nand_manuf_ids[maf_idx].name, type->name); |
2558 | |
2559 | return type; |
2560 | } |
2561 | |
2562 | /** |
2563 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
2564 | * @mtd: MTD device structure |
2565 | * @maxchips: Number of chips to scan for |
2566 | * |
2567 | * This is the first phase of the normal nand_scan() function. It |
2568 | * reads the flash ID and sets up MTD fields accordingly. |
2569 | * |
2570 | * The mtd->owner field must be set to the module of the caller. |
2571 | */ |
2572 | int nand_scan_ident(struct mtd_info *mtd, int maxchips) |
2573 | { |
2574 | int i, busw, nand_maf_id; |
2575 | struct nand_chip *chip = mtd->priv; |
2576 | struct nand_flash_dev *type; |
2577 | |
2578 | /* Get buswidth to select the correct functions */ |
2579 | busw = chip->options & NAND_BUSWIDTH_16; |
2580 | /* Set the default functions */ |
2581 | nand_set_defaults(chip, busw); |
2582 | |
2583 | /* Read the flash type */ |
2584 | type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); |
2585 | |
2586 | if (IS_ERR(type)) { |
2587 | printk(KERN_WARNING "No NAND device found!!!\n"); |
2588 | chip->select_chip(mtd, -1); |
2589 | return PTR_ERR(type); |
2590 | } |
2591 | |
2592 | /* Check for a chip array */ |
2593 | for (i = 1; i < maxchips; i++) { |
2594 | chip->select_chip(mtd, i); |
2595 | /* See comment in nand_get_flash_type for reset */ |
2596 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
2597 | /* Send the command for reading device ID */ |
2598 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
2599 | /* Read manufacturer and device IDs */ |
2600 | if (nand_maf_id != chip->read_byte(mtd) || |
2601 | type->id != chip->read_byte(mtd)) |
2602 | break; |
2603 | } |
2604 | if (i > 1) |
2605 | printk(KERN_INFO "%d NAND chips detected\n", i); |
2606 | |
2607 | /* Store the number of chips and calc total size for mtd */ |
2608 | chip->numchips = i; |
2609 | mtd->size = i * chip->chipsize; |
2610 | |
2611 | return 0; |
2612 | } |
2613 | |
2614 | |
2615 | /** |
2616 | * nand_scan_tail - [NAND Interface] Scan for the NAND device |
2617 | * @mtd: MTD device structure |
2618 | * |
2619 | * This is the second phase of the normal nand_scan() function. It |
2620 | * fills out all the uninitialized function pointers with the defaults |
2621 | * and scans for a bad block table if appropriate. |
2622 | */ |
2623 | int nand_scan_tail(struct mtd_info *mtd) |
2624 | { |
2625 | int i; |
2626 | struct nand_chip *chip = mtd->priv; |
2627 | |
2628 | if (!(chip->options & NAND_OWN_BUFFERS)) |
2629 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); |
2630 | if (!chip->buffers) |
2631 | return -ENOMEM; |
2632 | |
2633 | /* Set the internal oob buffer location, just after the page data */ |
2634 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
2635 | |
2636 | /* |
2637 | * If no default placement scheme is given, select an appropriate one |
2638 | */ |
2639 | if (!chip->ecc.layout) { |
2640 | switch (mtd->oobsize) { |
2641 | case 8: |
2642 | chip->ecc.layout = &nand_oob_8; |
2643 | break; |
2644 | case 16: |
2645 | chip->ecc.layout = &nand_oob_16; |
2646 | break; |
2647 | case 64: |
2648 | chip->ecc.layout = &nand_oob_64; |
2649 | break; |
2650 | case 128: |
2651 | chip->ecc.layout = &nand_oob_128; |
2652 | break; |
2653 | default: |
2654 | printk(KERN_WARNING "No oob scheme defined for " |
2655 | "oobsize %d\n", mtd->oobsize); |
2656 | BUG(); |
2657 | } |
2658 | } |
2659 | |
2660 | if (!chip->write_page) |
2661 | chip->write_page = nand_write_page; |
2662 | |
2663 | /* |
2664 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
2665 | * selected and we have 256 byte pagesize fallback to software ECC |
2666 | */ |
2667 | |
2668 | switch (chip->ecc.mode) { |
2669 | case NAND_ECC_HW: |
2670 | /* Use standard hwecc read page function ? */ |
2671 | if (!chip->ecc.read_page) |
2672 | chip->ecc.read_page = nand_read_page_hwecc; |
2673 | if (!chip->ecc.write_page) |
2674 | chip->ecc.write_page = nand_write_page_hwecc; |
2675 | if (!chip->ecc.read_page_raw) |
2676 | chip->ecc.read_page_raw = nand_read_page_raw; |
2677 | if (!chip->ecc.write_page_raw) |
2678 | chip->ecc.write_page_raw = nand_write_page_raw; |
2679 | if (!chip->ecc.read_oob) |
2680 | chip->ecc.read_oob = nand_read_oob_std; |
2681 | if (!chip->ecc.write_oob) |
2682 | chip->ecc.write_oob = nand_write_oob_std; |
2683 | |
2684 | case NAND_ECC_HW_SYNDROME: |
2685 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
2686 | !chip->ecc.hwctl) && |
2687 | (!chip->ecc.read_page || |
2688 | chip->ecc.read_page == nand_read_page_hwecc || |
2689 | !chip->ecc.write_page || |
2690 | chip->ecc.write_page == nand_write_page_hwecc)) { |
2691 | printk(KERN_WARNING "No ECC functions supplied, " |
2692 | "Hardware ECC not possible\n"); |
2693 | BUG(); |
2694 | } |
2695 | /* Use standard syndrome read/write page function ? */ |
2696 | if (!chip->ecc.read_page) |
2697 | chip->ecc.read_page = nand_read_page_syndrome; |
2698 | if (!chip->ecc.write_page) |
2699 | chip->ecc.write_page = nand_write_page_syndrome; |
2700 | if (!chip->ecc.read_page_raw) |
2701 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; |
2702 | if (!chip->ecc.write_page_raw) |
2703 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; |
2704 | if (!chip->ecc.read_oob) |
2705 | chip->ecc.read_oob = nand_read_oob_syndrome; |
2706 | if (!chip->ecc.write_oob) |
2707 | chip->ecc.write_oob = nand_write_oob_syndrome; |
2708 | |
2709 | if (mtd->writesize >= chip->ecc.size) |
2710 | break; |
2711 | printk(KERN_WARNING "%d byte HW ECC not possible on " |
2712 | "%d byte page size, fallback to SW ECC\n", |
2713 | chip->ecc.size, mtd->writesize); |
2714 | chip->ecc.mode = NAND_ECC_SOFT; |
2715 | |
2716 | case NAND_ECC_SOFT: |
2717 | chip->ecc.calculate = nand_calculate_ecc; |
2718 | chip->ecc.correct = nand_correct_data; |
2719 | chip->ecc.read_page = nand_read_page_swecc; |
2720 | chip->ecc.read_subpage = nand_read_subpage; |
2721 | chip->ecc.write_page = nand_write_page_swecc; |
2722 | chip->ecc.read_page_raw = nand_read_page_raw; |
2723 | chip->ecc.write_page_raw = nand_write_page_raw; |
2724 | chip->ecc.read_oob = nand_read_oob_std; |
2725 | chip->ecc.write_oob = nand_write_oob_std; |
2726 | chip->ecc.size = 256; |
2727 | chip->ecc.bytes = 3; |
2728 | break; |
2729 | |
2730 | case NAND_ECC_NONE: |
2731 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
2732 | "This is not recommended !!\n"); |
2733 | chip->ecc.read_page = nand_read_page_raw; |
2734 | chip->ecc.write_page = nand_write_page_raw; |
2735 | chip->ecc.read_oob = nand_read_oob_std; |
2736 | chip->ecc.read_page_raw = nand_read_page_raw; |
2737 | chip->ecc.write_page_raw = nand_write_page_raw; |
2738 | chip->ecc.write_oob = nand_write_oob_std; |
2739 | chip->ecc.size = mtd->writesize; |
2740 | chip->ecc.bytes = 0; |
2741 | break; |
2742 | |
2743 | default: |
2744 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
2745 | chip->ecc.mode); |
2746 | BUG(); |
2747 | } |
2748 | |
2749 | /* |
2750 | * The number of bytes available for a client to place data into |
2751 | * the out of band area |
2752 | */ |
2753 | chip->ecc.layout->oobavail = 0; |
2754 | for (i = 0; chip->ecc.layout->oobfree[i].length |
2755 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) |
2756 | chip->ecc.layout->oobavail += |
2757 | chip->ecc.layout->oobfree[i].length; |
2758 | mtd->oobavail = chip->ecc.layout->oobavail; |
2759 | |
2760 | /* |
2761 | * Set the number of read / write steps for one page depending on ECC |
2762 | * mode |
2763 | */ |
2764 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
2765 | if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { |
2766 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
2767 | BUG(); |
2768 | } |
2769 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
2770 | |
2771 | /* |
2772 | * Allow subpage writes up to ecc.steps. Not possible for MLC |
2773 | * FLASH. |
2774 | */ |
2775 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && |
2776 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { |
2777 | switch(chip->ecc.steps) { |
2778 | case 2: |
2779 | mtd->subpage_sft = 1; |
2780 | break; |
2781 | case 4: |
2782 | case 8: |
2783 | case 16: |
2784 | mtd->subpage_sft = 2; |
2785 | break; |
2786 | } |
2787 | } |
2788 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; |
2789 | |
2790 | /* Initialize state */ |
2791 | chip->state = FL_READY; |
2792 | |
2793 | /* De-select the device */ |
2794 | chip->select_chip(mtd, -1); |
2795 | |
2796 | /* Invalidate the pagebuffer reference */ |
2797 | chip->pagebuf = -1; |
2798 | |
2799 | /* Fill in remaining MTD driver data */ |
2800 | mtd->type = MTD_NANDFLASH; |
2801 | mtd->flags = MTD_CAP_NANDFLASH; |
2802 | mtd->erase = nand_erase; |
2803 | mtd->point = NULL; |
2804 | mtd->unpoint = NULL; |
2805 | mtd->read = nand_read; |
2806 | mtd->write = nand_write; |
2807 | mtd->read_oob = nand_read_oob; |
2808 | mtd->write_oob = nand_write_oob; |
2809 | mtd->sync = nand_sync; |
2810 | mtd->lock = NULL; |
2811 | mtd->unlock = NULL; |
2812 | mtd->suspend = nand_suspend; |
2813 | mtd->resume = nand_resume; |
2814 | mtd->block_isbad = nand_block_isbad; |
2815 | mtd->block_markbad = nand_block_markbad; |
2816 | |
2817 | /* propagate ecc.layout to mtd_info */ |
2818 | mtd->ecclayout = chip->ecc.layout; |
2819 | |
2820 | /* Check, if we should skip the bad block table scan */ |
2821 | if (chip->options & NAND_SKIP_BBTSCAN) |
2822 | return 0; |
2823 | |
2824 | /* Build bad block table */ |
2825 | return chip->scan_bbt(mtd); |
2826 | } |
2827 | |
2828 | /* is_module_text_address() isn't exported, and it's mostly a pointless |
2829 | test if this is a module _anyway_ -- they'd have to try _really_ hard |
2830 | to call us from in-kernel code if the core NAND support is modular. */ |
2831 | #ifdef MODULE |
2832 | #define caller_is_module() (1) |
2833 | #else |
2834 | #define caller_is_module() \ |
2835 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
2836 | #endif |
2837 | |
2838 | /** |
2839 | * nand_scan - [NAND Interface] Scan for the NAND device |
2840 | * @mtd: MTD device structure |
2841 | * @maxchips: Number of chips to scan for |
2842 | * |
2843 | * This fills out all the uninitialized function pointers |
2844 | * with the defaults. |
2845 | * The flash ID is read and the mtd/chip structures are |
2846 | * filled with the appropriate values. |
2847 | * The mtd->owner field must be set to the module of the caller |
2848 | * |
2849 | */ |
2850 | int nand_scan(struct mtd_info *mtd, int maxchips) |
2851 | { |
2852 | int ret; |
2853 | |
2854 | /* Many callers got this wrong, so check for it for a while... */ |
2855 | if (!mtd->owner && caller_is_module()) { |
2856 | printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n"); |
2857 | BUG(); |
2858 | } |
2859 | |
2860 | ret = nand_scan_ident(mtd, maxchips); |
2861 | if (!ret) |
2862 | ret = nand_scan_tail(mtd); |
2863 | return ret; |
2864 | } |
2865 | |
2866 | /** |
2867 | * nand_release - [NAND Interface] Free resources held by the NAND device |
2868 | * @mtd: MTD device structure |
2869 | */ |
2870 | void nand_release(struct mtd_info *mtd) |
2871 | { |
2872 | struct nand_chip *chip = mtd->priv; |
2873 | |
2874 | #ifdef CONFIG_MTD_PARTITIONS |
2875 | /* Deregister partitions */ |
2876 | del_mtd_partitions(mtd); |
2877 | #endif |
2878 | /* Deregister the device */ |
2879 | del_mtd_device(mtd); |
2880 | |
2881 | /* Free bad block table memory */ |
2882 | kfree(chip->bbt); |
2883 | if (!(chip->options & NAND_OWN_BUFFERS)) |
2884 | kfree(chip->buffers); |
2885 | } |
2886 | |
2887 | EXPORT_SYMBOL_GPL(nand_scan); |
2888 | EXPORT_SYMBOL_GPL(nand_scan_ident); |
2889 | EXPORT_SYMBOL_GPL(nand_scan_tail); |
2890 | EXPORT_SYMBOL_GPL(nand_release); |
2891 | |
2892 | static int __init nand_base_init(void) |
2893 | { |
2894 | led_trigger_register_simple("nand-disk", &nand_led_trigger); |
2895 | return 0; |
2896 | } |
2897 | |
2898 | static void __exit nand_base_exit(void) |
2899 | { |
2900 | led_trigger_unregister_simple(nand_led_trigger); |
2901 | } |
2902 | |
2903 | module_init(nand_base_init); |
2904 | module_exit(nand_base_exit); |
2905 | |
2906 | MODULE_LICENSE("GPL"); |
2907 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); |
2908 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |
2909 |
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javiroman/ks7010
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9