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Source at commit da764510a60b020cb0cffb219e18778c7befb29a created 12 years 9 months ago. By Maarten ter Huurne, MIPS: JZ4740: SLCD framebufer driver. | |
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1 | /* |
2 | * linux/drivers/video/jz4740_slcd_panels.c |
3 | * -- LCD panel definitions for Ingenic On-Chip SLCD frame buffer device |
4 | * |
5 | * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. |
6 | * Copyright (C) 2009, Ignacio Garcia Perez <iggarpe@gmail.com> |
7 | * Copyright (C) 2010, Maarten ter Huurne <maarten@treewalker.org> |
8 | * Copyright (C) 2011, ChinaChip |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as |
12 | * published by the Free Software Foundation. |
13 | * |
14 | */ |
15 | |
16 | #include <asm/io.h> |
17 | #include <asm/mach-jz4740/gpio.h> |
18 | #include <asm/mach-jz4740/jz4740_fb.h> |
19 | #include <linux/delay.h> |
20 | #include <linux/gpio.h> |
21 | #include <linux/kernel.h> |
22 | #include <linux/platform_device.h> |
23 | |
24 | #include "jz4740_slcd.h" |
25 | |
26 | /* Send a command without data. */ |
27 | static void send_panel_command(struct jzfb *jzfb, u32 cmd) { |
28 | u16 slcd_cfg = readw(jzfb->base + JZ_REG_SLCD_CFG); |
29 | switch (slcd_cfg & SLCD_CFG_CWIDTH_MASK) { |
30 | case SLCD_CFG_CWIDTH_8BIT: |
31 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
32 | writel(SLCD_DATA_RS_COMMAND | ((cmd&0xff00) >> 8), jzfb->base + JZ_REG_SLCD_DATA); |
33 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
34 | writel(SLCD_DATA_RS_COMMAND | ((cmd&0xff) >> 0), jzfb->base + JZ_REG_SLCD_DATA); |
35 | break; |
36 | case SLCD_CFG_CWIDTH_16BIT: |
37 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
38 | writel(SLCD_DATA_RS_COMMAND | (cmd&0xffff), jzfb->base + JZ_REG_SLCD_DATA); |
39 | break; |
40 | case SLCD_CFG_CWIDTH_18BIT: |
41 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
42 | writel(SLCD_DATA_RS_COMMAND | ((cmd&0xff00) << 2) | ((cmd&0xff) << 1), jzfb->base + JZ_REG_SLCD_DATA); |
43 | break; |
44 | default: |
45 | break; |
46 | } |
47 | } |
48 | |
49 | /* Send data without command. */ |
50 | static void send_panel_data(struct jzfb *jzfb, u32 data) |
51 | { |
52 | u16 slcd_cfg = readw(jzfb->base + JZ_REG_SLCD_CFG); |
53 | switch (slcd_cfg & SLCD_CFG_DWIDTH_MASK) { |
54 | case SLCD_CFG_DWIDTH_18: |
55 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
56 | data = ((data & 0xff) << 1) | ((data & 0xff00) << 2); |
57 | writel(SLCD_DATA_RS_DATA | ((data<<6)&0xfc0000)|((data<<4)&0xfc00) | ((data<<2)&0xfc), jzfb->base + JZ_REG_SLCD_DATA); |
58 | break; |
59 | case SLCD_CFG_DWIDTH_16: |
60 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
61 | writel(SLCD_DATA_RS_DATA | (data&0xffff), jzfb->base + JZ_REG_SLCD_DATA); |
62 | break; |
63 | case SLCD_CFG_DWIDTH_9_x2: |
64 | data = ((data & 0xff) << 1) | ((data & 0xff00) << 2); |
65 | data = ((data << 6) & 0xfc0000) | ((data << 4) & 0xfc00) | ((data << 2) & 0xfc); |
66 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
67 | writel(SLCD_DATA_RS_DATA | data, jzfb->base + JZ_REG_SLCD_DATA); |
68 | break; |
69 | default: |
70 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
71 | writel(SLCD_DATA_RS_DATA | (data&0xffff), jzfb->base + JZ_REG_SLCD_DATA); |
72 | break; |
73 | } |
74 | } |
75 | |
76 | /* Send command and data. */ |
77 | static void set_panel_reg(struct jzfb *jzfb, u32 cmd, u32 data) |
78 | { |
79 | send_panel_command(jzfb, cmd); |
80 | send_panel_data(jzfb, data); |
81 | } |
82 | |
83 | #ifdef CONFIG_JZ_SLCD_ILI9325 |
84 | |
85 | // TODO(MtH): GPIO assignments belong in the board definition, since two |
86 | // boards using the same panel controller could still use different |
87 | // GPIO assignments. |
88 | // TODO(MtH): CS mismatch: B17 (A320) vs C20 (standard). |
89 | #define ILI9325_GPIO_CS_N JZ_GPIO_PORTB(17) /* Chip select */ |
90 | #define ILI9325_GPIO_RESET_N JZ_GPIO_PORTB(18) /* LCD reset */ |
91 | |
92 | static int ili9325_init(struct jzfb *jzfb) |
93 | { |
94 | struct device *dev = &jzfb->pdev->dev; |
95 | int ret; |
96 | |
97 | ret = gpio_request(ILI9325_GPIO_CS_N, dev_name(dev)); |
98 | if (ret) |
99 | goto err_cs; |
100 | gpio_direction_output(ILI9325_GPIO_CS_N, 1); |
101 | |
102 | ret = gpio_request(ILI9325_GPIO_RESET_N, dev_name(dev)); |
103 | if (ret) |
104 | goto err_reset; |
105 | gpio_direction_output(ILI9325_GPIO_RESET_N, 0); |
106 | |
107 | mdelay(100); |
108 | return 0; |
109 | |
110 | err_reset: |
111 | gpio_free(ILI9325_GPIO_CS_N); |
112 | err_cs: |
113 | dev_err(dev, "Could not reserve GPIO pins for ILI9325 panel driver\n"); |
114 | return ret; |
115 | } |
116 | |
117 | static void ili9325_exit(struct jzfb *jzfb) |
118 | { |
119 | gpio_free(ILI9325_GPIO_CS_N); |
120 | gpio_free(ILI9325_GPIO_RESET_N); |
121 | } |
122 | |
123 | static void ili9325_enable(struct jzfb *jzfb) |
124 | { |
125 | /* RESET pulse */ |
126 | gpio_set_value(ILI9325_GPIO_RESET_N, 0); |
127 | mdelay(10); |
128 | gpio_set_value(ILI9325_GPIO_RESET_N, 1); |
129 | mdelay(50); |
130 | |
131 | /* Enable chip select */ |
132 | gpio_set_value(ILI9325_GPIO_CS_N, 0); |
133 | |
134 | /* Black magic */ |
135 | set_panel_reg(jzfb, 0xE3, 0x3008); |
136 | set_panel_reg(jzfb, 0xE7, 0x0012); |
137 | set_panel_reg(jzfb, 0xEF, 0x1231); |
138 | set_panel_reg(jzfb, 0x01, 0x0100); |
139 | set_panel_reg(jzfb, 0x02, 0x0700); |
140 | set_panel_reg(jzfb, 0x03, 0x1098); |
141 | set_panel_reg(jzfb, 0x04, 0x0000); |
142 | set_panel_reg(jzfb, 0x08, 0x0207); |
143 | set_panel_reg(jzfb, 0x09, 0x0000); |
144 | set_panel_reg(jzfb, 0x0A, 0x0000); |
145 | set_panel_reg(jzfb, 0x0C, 0x0000); |
146 | set_panel_reg(jzfb, 0x0D, 0x0000); |
147 | set_panel_reg(jzfb, 0x0F, 0x0000); |
148 | set_panel_reg(jzfb, 0x10, 0x0000); |
149 | set_panel_reg(jzfb, 0x11, 0x0007); |
150 | set_panel_reg(jzfb, 0x12, 0x0000); |
151 | set_panel_reg(jzfb, 0x13, 0x0000); |
152 | mdelay(200); |
153 | set_panel_reg(jzfb, 0x10, 0x1290); |
154 | set_panel_reg(jzfb, 0x11, 0x0227); |
155 | mdelay(50); |
156 | set_panel_reg(jzfb, 0x12, 0x001B); |
157 | mdelay(50); |
158 | set_panel_reg(jzfb, 0x13, 0x0500); |
159 | set_panel_reg(jzfb, 0x29, 0x000C); |
160 | set_panel_reg(jzfb, 0x2B, 0x000D); |
161 | mdelay(50); |
162 | set_panel_reg(jzfb, 0x20, 0x0000); |
163 | set_panel_reg(jzfb, 0x21, 0x0000); |
164 | set_panel_reg(jzfb, 0x30, 0x0000); |
165 | set_panel_reg(jzfb, 0x31, 0x0204); |
166 | set_panel_reg(jzfb, 0x32, 0x0200); |
167 | set_panel_reg(jzfb, 0x35, 0x0007); |
168 | set_panel_reg(jzfb, 0x36, 0x1404); |
169 | set_panel_reg(jzfb, 0x37, 0x0705); |
170 | set_panel_reg(jzfb, 0x38, 0x0305); |
171 | set_panel_reg(jzfb, 0x39, 0x0707); |
172 | set_panel_reg(jzfb, 0x3C, 0x0701); |
173 | set_panel_reg(jzfb, 0x3D, 0x000E); |
174 | set_panel_reg(jzfb, 0x50, 0x0000); |
175 | set_panel_reg(jzfb, 0x51, 0x00EF); |
176 | set_panel_reg(jzfb, 0x52, 0x0000); |
177 | set_panel_reg(jzfb, 0x53, 0x013F); |
178 | set_panel_reg(jzfb, 0x60, 0xA700); |
179 | set_panel_reg(jzfb, 0x61, 0x0001); |
180 | set_panel_reg(jzfb, 0x6A, 0x0000); |
181 | set_panel_reg(jzfb, 0x80, 0x0000); |
182 | set_panel_reg(jzfb, 0x81, 0x0000); |
183 | set_panel_reg(jzfb, 0x82, 0x0000); |
184 | set_panel_reg(jzfb, 0x83, 0x0000); |
185 | set_panel_reg(jzfb, 0x84, 0x0000); |
186 | set_panel_reg(jzfb, 0x85, 0x0000); |
187 | set_panel_reg(jzfb, 0x90, 0x0010); |
188 | set_panel_reg(jzfb, 0x92, 0x0600); |
189 | mdelay(50); |
190 | set_panel_reg(jzfb, 0x07, 0x0133); |
191 | mdelay(50); |
192 | send_panel_command(jzfb, 0x22); |
193 | } |
194 | |
195 | /* TODO(IGP): make sure LCD power consumption is low in these conditions */ |
196 | static void ili9325_disable(struct jzfb *jzfb) |
197 | { |
198 | /* Keep chip select disabled */ |
199 | gpio_set_value(ILI9325_GPIO_CS_N, 1); |
200 | /* Keep RESET active */ |
201 | gpio_set_value(ILI9325_GPIO_RESET_N, 0); |
202 | } |
203 | |
204 | #endif |
205 | |
206 | #ifdef CONFIG_JZ_SLCD_ILI9331 |
207 | |
208 | #define ILI9331_GPIO_CS_N JZ_GPIO_PORTB(17) /* Chip select */ |
209 | #define ILI9331_GPIO_RESET_N JZ_GPIO_PORTB(18) /* LCD reset */ |
210 | |
211 | static int ili9331_init(struct jzfb *jzfb) |
212 | { |
213 | struct device *dev = &jzfb->pdev->dev; |
214 | int ret; |
215 | |
216 | ret = gpio_request(ILI9331_GPIO_CS_N, dev_name(dev)); |
217 | if (ret) |
218 | goto err_cs; |
219 | gpio_direction_output(ILI9331_GPIO_CS_N, 1); |
220 | |
221 | ret = gpio_request(ILI9331_GPIO_RESET_N, dev_name(dev)); |
222 | if (ret) |
223 | goto err_reset; |
224 | gpio_direction_output(ILI9331_GPIO_RESET_N, 0); |
225 | |
226 | mdelay(100); |
227 | return 0; |
228 | |
229 | err_reset: |
230 | gpio_free(ILI9331_GPIO_CS_N); |
231 | err_cs: |
232 | dev_err(dev, "Could not reserve GPIO pins for ILI9331 panel driver\n"); |
233 | return ret; |
234 | } |
235 | |
236 | static void ili9331_exit(struct jzfb *jzfb) |
237 | { |
238 | gpio_free(ILI9331_GPIO_CS_N); |
239 | gpio_free(ILI9331_GPIO_RESET_N); |
240 | } |
241 | |
242 | static void ili9331_enable(struct jzfb *jzfb) |
243 | { |
244 | /* RESET pulse */ |
245 | gpio_set_value(ILI9331_GPIO_RESET_N, 0); |
246 | mdelay(10); |
247 | gpio_set_value(ILI9331_GPIO_RESET_N, 1); |
248 | mdelay(50); |
249 | |
250 | /* Enable chip select */ |
251 | gpio_set_value(ILI9331_GPIO_CS_N, 0); |
252 | |
253 | /* Black magic */ |
254 | set_panel_reg(jzfb, 0xE7, 0x1014); |
255 | set_panel_reg(jzfb, 0x01, 0x0000); |
256 | set_panel_reg(jzfb, 0x02, 0x0200); |
257 | set_panel_reg(jzfb, 0x03, 0x1048); |
258 | set_panel_reg(jzfb, 0x08, 0x0202); |
259 | set_panel_reg(jzfb, 0x09, 0x0000); |
260 | set_panel_reg(jzfb, 0x0A, 0x0000); |
261 | set_panel_reg(jzfb, 0x0C, 0x0000); |
262 | set_panel_reg(jzfb, 0x0D, 0x0000); |
263 | set_panel_reg(jzfb, 0x0F, 0x0000); |
264 | set_panel_reg(jzfb, 0x10, 0x0000); |
265 | set_panel_reg(jzfb, 0x11, 0x0007); |
266 | set_panel_reg(jzfb, 0x12, 0x0000); |
267 | set_panel_reg(jzfb, 0x13, 0x0000); |
268 | mdelay(100); |
269 | set_panel_reg(jzfb, 0x10, 0x1690); |
270 | set_panel_reg(jzfb, 0x11, 0x0224); |
271 | mdelay(50); |
272 | set_panel_reg(jzfb, 0x12, 0x001F); |
273 | mdelay(50); |
274 | set_panel_reg(jzfb, 0x13, 0x0500); |
275 | set_panel_reg(jzfb, 0x29, 0x000C); |
276 | set_panel_reg(jzfb, 0x2B, 0x000D); |
277 | mdelay(50); |
278 | set_panel_reg(jzfb, 0x30, 0x0000); |
279 | set_panel_reg(jzfb, 0x31, 0x0106); |
280 | set_panel_reg(jzfb, 0x32, 0x0000); |
281 | set_panel_reg(jzfb, 0x35, 0x0204); |
282 | set_panel_reg(jzfb, 0x36, 0x160A); |
283 | set_panel_reg(jzfb, 0x37, 0x0707); |
284 | set_panel_reg(jzfb, 0x38, 0x0106); |
285 | set_panel_reg(jzfb, 0x39, 0x0706); |
286 | set_panel_reg(jzfb, 0x3C, 0x0402); |
287 | set_panel_reg(jzfb, 0x3D, 0x0C0F); |
288 | set_panel_reg(jzfb, 0x50, 0x0000); |
289 | set_panel_reg(jzfb, 0x51, 0x00EF); |
290 | set_panel_reg(jzfb, 0x52, 0x0000); |
291 | set_panel_reg(jzfb, 0x53, 0x013F); |
292 | set_panel_reg(jzfb, 0x20, 0x0000); |
293 | set_panel_reg(jzfb, 0x21, 0x0000); |
294 | set_panel_reg(jzfb, 0x60, 0x2700); |
295 | set_panel_reg(jzfb, 0x61, 0x0001); |
296 | set_panel_reg(jzfb, 0x6A, 0x0000); |
297 | set_panel_reg(jzfb, 0x80, 0x0000); |
298 | set_panel_reg(jzfb, 0x81, 0x0000); |
299 | set_panel_reg(jzfb, 0x82, 0x0000); |
300 | set_panel_reg(jzfb, 0x83, 0x0000); |
301 | set_panel_reg(jzfb, 0x84, 0x0000); |
302 | set_panel_reg(jzfb, 0x85, 0x0000); |
303 | set_panel_reg(jzfb, 0x20, 0x00EF); |
304 | set_panel_reg(jzfb, 0x21, 0x0190); |
305 | set_panel_reg(jzfb, 0x90, 0x0010); |
306 | set_panel_reg(jzfb, 0x92, 0x0600); |
307 | set_panel_reg(jzfb, 0x07, 0x0133); |
308 | send_panel_command(jzfb, 0x22); |
309 | } |
310 | |
311 | /* TODO(IGP): make sure LCD power consumption is low in these conditions */ |
312 | static void ili9331_disable(struct jzfb *jzfb) |
313 | { |
314 | /* Keep chip select disabled */ |
315 | gpio_set_value(ILI9331_GPIO_CS_N, 1); |
316 | /* Keep RESET active */ |
317 | gpio_set_value(ILI9331_GPIO_RESET_N, 0); |
318 | } |
319 | |
320 | #endif |
321 | |
322 | #ifdef CONFIG_JZ_SLCD_ILI9338 |
323 | |
324 | #define ILI9338_GPIO_CS_N JZ_GPIO_PORTB(17) /* Chip select */ |
325 | #define ILI9338_GPIO_RESET_N JZ_GPIO_PORTB(18) /* LCD reset */ |
326 | |
327 | static int ili9338_init(struct jzfb *jzfb) |
328 | { |
329 | struct device *dev = &jzfb->pdev->dev; |
330 | int ret; |
331 | |
332 | ret = gpio_request(ILI9338_GPIO_CS_N, dev_name(dev)); |
333 | if (ret) |
334 | goto err_cs; |
335 | gpio_direction_output(ILI9338_GPIO_CS_N, 1); |
336 | |
337 | ret = gpio_request(ILI9338_GPIO_RESET_N, dev_name(dev)); |
338 | if (ret) |
339 | goto err_reset; |
340 | gpio_direction_output(ILI9338_GPIO_RESET_N, 0); |
341 | |
342 | mdelay(100); |
343 | return 0; |
344 | |
345 | err_reset: |
346 | gpio_free(ILI9338_GPIO_CS_N); |
347 | err_cs: |
348 | dev_err(dev, "Could not reserve GPIO pins for ILI9338 panel driver\n"); |
349 | return ret; |
350 | } |
351 | |
352 | static void ili9338_exit(struct jzfb *jzfb) |
353 | { |
354 | gpio_free(ILI9338_GPIO_CS_N); |
355 | gpio_free(ILI9338_GPIO_RESET_N); |
356 | } |
357 | |
358 | static void ili9338_enable(struct jzfb *jzfb) |
359 | { |
360 | /* RESET pulse */ |
361 | gpio_set_value(ILI9338_GPIO_RESET_N, 0); |
362 | mdelay(10); |
363 | gpio_set_value(ILI9338_GPIO_RESET_N, 1); |
364 | mdelay(50); |
365 | |
366 | /* Enable chip select */ |
367 | gpio_set_value(ILI9338_GPIO_CS_N, 0); |
368 | |
369 | /* Black magic */ |
370 | send_panel_command(jzfb, 0x11); |
371 | mdelay(100); |
372 | |
373 | send_panel_command(jzfb, 0xCB); |
374 | send_panel_data(jzfb, 0x01); |
375 | |
376 | send_panel_command(jzfb, 0xC0); |
377 | send_panel_data(jzfb, 0x26); |
378 | send_panel_data(jzfb, 0x01); |
379 | send_panel_command(jzfb, 0xC1); |
380 | send_panel_data(jzfb, 0x10); |
381 | send_panel_command(jzfb, 0xC5); |
382 | send_panel_data(jzfb, 0x10); |
383 | send_panel_data(jzfb, 0x52); |
384 | |
385 | send_panel_command(jzfb, 0x26); |
386 | send_panel_data(jzfb, 0x01); |
387 | send_panel_command(jzfb, 0xE0); |
388 | send_panel_data(jzfb, 0x10); |
389 | send_panel_data(jzfb, 0x10); |
390 | send_panel_data(jzfb, 0x10); |
391 | send_panel_data(jzfb, 0x08); |
392 | send_panel_data(jzfb, 0x0E); |
393 | send_panel_data(jzfb, 0x06); |
394 | send_panel_data(jzfb, 0x42); |
395 | send_panel_data(jzfb, 0x28); |
396 | send_panel_data(jzfb, 0x36); |
397 | send_panel_data(jzfb, 0x03); |
398 | send_panel_data(jzfb, 0x0E); |
399 | send_panel_data(jzfb, 0x04); |
400 | send_panel_data(jzfb, 0x13); |
401 | send_panel_data(jzfb, 0x0E); |
402 | send_panel_data(jzfb, 0x0C); |
403 | send_panel_command(jzfb, 0XE1); |
404 | send_panel_data(jzfb, 0x0C); |
405 | send_panel_data(jzfb, 0x23); |
406 | send_panel_data(jzfb, 0x26); |
407 | send_panel_data(jzfb, 0x04); |
408 | send_panel_data(jzfb, 0x0C); |
409 | send_panel_data(jzfb, 0x04); |
410 | send_panel_data(jzfb, 0x39); |
411 | send_panel_data(jzfb, 0x24); |
412 | send_panel_data(jzfb, 0x4B); |
413 | send_panel_data(jzfb, 0x03); |
414 | send_panel_data(jzfb, 0x0B); |
415 | send_panel_data(jzfb, 0x0B); |
416 | send_panel_data(jzfb, 0x33); |
417 | send_panel_data(jzfb, 0x37); |
418 | send_panel_data(jzfb, 0x0F); |
419 | |
420 | send_panel_command(jzfb, 0x2a); |
421 | send_panel_data(jzfb, 0x00); |
422 | send_panel_data(jzfb, 0x00); |
423 | send_panel_data(jzfb, 0x01); |
424 | send_panel_data(jzfb, 0x3f); |
425 | |
426 | send_panel_command(jzfb, 0x2b); |
427 | send_panel_data(jzfb, 0x00); |
428 | send_panel_data(jzfb, 0x00); |
429 | send_panel_data(jzfb, 0x00); |
430 | send_panel_data(jzfb, 0xef); |
431 | |
432 | send_panel_command(jzfb, 0x36); |
433 | send_panel_data(jzfb, 0xe8); |
434 | |
435 | send_panel_command(jzfb, 0x3A); |
436 | send_panel_data(jzfb, 0x05); |
437 | |
438 | send_panel_command(jzfb, 0x29); |
439 | |
440 | send_panel_command(jzfb, 0x2c); |
441 | } |
442 | |
443 | /* TODO(IGP): make sure LCD power consumption is low in these conditions */ |
444 | static void ili9338_disable(struct jzfb *jzfb) |
445 | { |
446 | /* Keep chip select disabled */ |
447 | gpio_set_value(ILI9338_GPIO_CS_N, 1); |
448 | /* Keep RESET active */ |
449 | gpio_set_value(ILI9338_GPIO_RESET_N, 0); |
450 | } |
451 | |
452 | #endif |
453 | |
454 | #ifdef CONFIG_JZ_SLCD_LGDP4551 |
455 | |
456 | #define LGDP4551_GPIO_CS_N JZ_GPIO_PORTC(18) /* Chip select */ |
457 | #define LGDP4551_GPIO_RESET_N JZ_GPIO_PORTC(21) /* LCD reset */ |
458 | |
459 | /* Set the start address of screen, for example (0, 0) */ |
460 | static void lgdp4551_set_addr(struct jzfb *jzfb, u16 x, u16 y) |
461 | { |
462 | set_panel_reg(jzfb, 0x20, x); |
463 | udelay(1); |
464 | set_panel_reg(jzfb, 0x21, y); |
465 | udelay(1); |
466 | send_panel_command(jzfb, 0x22); |
467 | } |
468 | |
469 | static int lgdp4551_init(struct jzfb *jzfb) |
470 | { |
471 | struct device *dev = &jzfb->pdev->dev; |
472 | int ret; |
473 | |
474 | ret = gpio_request(LGDP4551_GPIO_CS_N, dev_name(dev)); |
475 | if (ret) |
476 | goto err_cs; |
477 | gpio_direction_output(LGDP4551_GPIO_CS_N, 0); |
478 | |
479 | ret = gpio_request(LGDP4551_GPIO_RESET_N, dev_name(dev)); |
480 | if (ret) |
481 | goto err_reset; |
482 | gpio_direction_output(LGDP4551_GPIO_RESET_N, 1); |
483 | |
484 | mdelay(100); |
485 | return 0; |
486 | |
487 | err_reset: |
488 | gpio_free(LGDP4551_GPIO_CS_N); |
489 | err_cs: |
490 | dev_err(dev, "Could not reserve GPIO pins for LGDP4551 panel\n"); |
491 | return ret; |
492 | } |
493 | |
494 | static void lgdp4551_exit(struct jzfb *jzfb) |
495 | { |
496 | gpio_free(LGDP4551_GPIO_CS_N); |
497 | gpio_free(LGDP4551_GPIO_RESET_N); |
498 | } |
499 | |
500 | static void lgdp4551_enable(struct jzfb *jzfb) |
501 | { |
502 | /* RESET# */ |
503 | gpio_set_value(LGDP4551_GPIO_RESET_N, 1); |
504 | mdelay(10); |
505 | gpio_set_value(LGDP4551_GPIO_RESET_N, 0); |
506 | mdelay(10); |
507 | gpio_set_value(LGDP4551_GPIO_RESET_N, 1); |
508 | mdelay(100); |
509 | set_panel_reg(jzfb, 0x0015, 0x0050); |
510 | set_panel_reg(jzfb, 0x0011, 0x0000); |
511 | set_panel_reg(jzfb, 0x0010, 0x3628); |
512 | set_panel_reg(jzfb, 0x0012, 0x0002); |
513 | set_panel_reg(jzfb, 0x0013, 0x0E47); |
514 | udelay(100); |
515 | set_panel_reg(jzfb, 0x0012, 0x0012); |
516 | udelay(100); |
517 | set_panel_reg(jzfb, 0x0010, 0x3620); |
518 | set_panel_reg(jzfb, 0x0013, 0x2E47); |
519 | udelay(50); |
520 | set_panel_reg(jzfb, 0x0030, 0x0000); |
521 | set_panel_reg(jzfb, 0x0031, 0x0502); |
522 | set_panel_reg(jzfb, 0x0032, 0x0307); |
523 | set_panel_reg(jzfb, 0x0033, 0x0304); |
524 | set_panel_reg(jzfb, 0x0034, 0x0004); |
525 | set_panel_reg(jzfb, 0x0035, 0x0401); |
526 | set_panel_reg(jzfb, 0x0036, 0x0707); |
527 | set_panel_reg(jzfb, 0x0037, 0x0303); |
528 | set_panel_reg(jzfb, 0x0038, 0x1E02); |
529 | set_panel_reg(jzfb, 0x0039, 0x1E02); |
530 | set_panel_reg(jzfb, 0x0001, 0x0000); |
531 | set_panel_reg(jzfb, 0x0002, 0x0300); |
532 | if (jzfb->pdata->bpp == 16) |
533 | set_panel_reg(jzfb, 0x0003, 0x10B8); /*8-bit system interface two transfers |
534 | up:0x10B8 down:0x1088 left:0x1090 right:0x10a0*/ |
535 | else if (jzfb->pdata->bpp == 32) |
536 | set_panel_reg(jzfb, 0x0003, 0xD0B8);/*8-bit system interface three transfers,666 |
537 | up:0xD0B8 down:0xD088 left:0xD090 right:0xD0A0*/ |
538 | set_panel_reg(jzfb, 0x0008, 0x0204); |
539 | set_panel_reg(jzfb, 0x000A, 0x0008); |
540 | set_panel_reg(jzfb, 0x0060, 0x3100); |
541 | set_panel_reg(jzfb, 0x0061, 0x0001); |
542 | set_panel_reg(jzfb, 0x0090, 0x0052); |
543 | set_panel_reg(jzfb, 0x0092, 0x000F); |
544 | set_panel_reg(jzfb, 0x0093, 0x0001); |
545 | set_panel_reg(jzfb, 0x009A, 0x0008); |
546 | set_panel_reg(jzfb, 0x00A3, 0x0010); |
547 | set_panel_reg(jzfb, 0x0050, 0x0000); |
548 | set_panel_reg(jzfb, 0x0051, 0x00EF); |
549 | set_panel_reg(jzfb, 0x0052, 0x0000); |
550 | set_panel_reg(jzfb, 0x0053, 0x018F); |
551 | /*===Display_On_Function=== */ |
552 | set_panel_reg(jzfb, 0x0007, 0x0001); |
553 | set_panel_reg(jzfb, 0x0007, 0x0021); |
554 | set_panel_reg(jzfb, 0x0007, 0x0023); |
555 | set_panel_reg(jzfb, 0x0007, 0x0033); |
556 | set_panel_reg(jzfb, 0x0007, 0x0133); |
557 | send_panel_command(jzfb, 0x0022); /* Write Data to GRAM. */ |
558 | udelay(1); |
559 | lgdp4551_set_addr(jzfb, 0, 0); |
560 | mdelay(100); |
561 | } |
562 | |
563 | static void lgdp4551_disable(struct jzfb *jzfb) |
564 | { |
565 | } |
566 | |
567 | #endif |
568 | |
569 | #ifdef CONFIG_JZ_SLCD_SPFD5420A |
570 | |
571 | #define SPFD5420A_GPIO_CS_N JZ_GPIO_PORTC(22) /* Chip select */ |
572 | #define SPFD5420A_GPIO_RESET_N JZ_GPIO_PORTB(18) /* LCD reset */ |
573 | #define SPFD5420A_GPIO_POWER_N JZ_GPIO_PORTD(0) /* Power off */ |
574 | #define SPFD5420A_GPIO_FMARK_N JZ_GPIO_PORTD(1) /* fmark */ |
575 | |
576 | /* Set the start address of screen, for example (0, 0) */ |
577 | static void spfd5420a_set_addr(struct jzfb *jzfb, u32 x, u32 y) |
578 | { |
579 | set_panel_reg(jzfb, 0x200, x); |
580 | udelay(1); |
581 | set_panel_reg(jzfb, 0x201, y); |
582 | udelay(1); |
583 | send_panel_command(jzfb, 0x202); |
584 | } |
585 | |
586 | static int spfd5420a_init(struct jzfb *jzfb) |
587 | { |
588 | struct device *dev = &jzfb->pdev->dev; |
589 | int ret; |
590 | |
591 | ret = gpio_request(SPFD5420A_GPIO_CS_N, dev_name(dev)); |
592 | if (ret) |
593 | goto err_cs; |
594 | gpio_direction_output(SPFD5420A_GPIO_CS_N, 0); |
595 | |
596 | ret = gpio_request(SPFD5420A_GPIO_RESET_N, dev_name(dev)); |
597 | if (ret) |
598 | goto err_reset; |
599 | gpio_direction_output(SPFD5420A_GPIO_RESET_N, 1); |
600 | |
601 | ret = gpio_request(SPFD5420A_GPIO_POWER_N, dev_name(dev)); |
602 | if (ret) |
603 | goto err_power; |
604 | gpio_direction_output(SPFD5420A_GPIO_POWER_N, 0); |
605 | |
606 | mdelay(100); |
607 | return 0; |
608 | |
609 | err_power: |
610 | gpio_free(SPFD5420A_GPIO_RESET_N); |
611 | err_reset: |
612 | gpio_free(SPFD5420A_GPIO_CS_N); |
613 | err_cs: |
614 | dev_err(dev, "Could not reserve GPIO pins for SPFD5420A panel\n"); |
615 | return ret; |
616 | } |
617 | |
618 | static void spfd5420a_exit(struct jzfb *jzfb) |
619 | { |
620 | gpio_free(SPFD5420A_GPIO_CS_N); |
621 | gpio_free(SPFD5420A_GPIO_RESET_N); |
622 | gpio_free(SPFD5420A_GPIO_POWER_N); |
623 | } |
624 | |
625 | static void spfd5420a_init_gamma(struct jzfb *jzfb) |
626 | { |
627 | set_panel_reg(jzfb, 0x0300, 0x0101); |
628 | set_panel_reg(jzfb, 0x0301, 0x0b27); |
629 | set_panel_reg(jzfb, 0x0302, 0x132a); |
630 | set_panel_reg(jzfb, 0x0303, 0x2a13); |
631 | set_panel_reg(jzfb, 0x0304, 0x270b); |
632 | set_panel_reg(jzfb, 0x0305, 0x0101); |
633 | set_panel_reg(jzfb, 0x0306, 0x1205); |
634 | set_panel_reg(jzfb, 0x0307, 0x0512); |
635 | set_panel_reg(jzfb, 0x0308, 0x0005); |
636 | set_panel_reg(jzfb, 0x0309, 0x0003); |
637 | set_panel_reg(jzfb, 0x030a, 0x0f04); |
638 | set_panel_reg(jzfb, 0x030b, 0x0f00); |
639 | set_panel_reg(jzfb, 0x030c, 0x000f); |
640 | set_panel_reg(jzfb, 0x030d, 0x040f); |
641 | set_panel_reg(jzfb, 0x030e, 0x0300); |
642 | set_panel_reg(jzfb, 0x030f, 0x0500); |
643 | /*** secorrect gamma2 ***/ |
644 | set_panel_reg(jzfb, 0x0400, 0x3500); |
645 | set_panel_reg(jzfb, 0x0401, 0x0001); |
646 | set_panel_reg(jzfb, 0x0404, 0x0000); |
647 | set_panel_reg(jzfb, 0x0500, 0x0000); |
648 | set_panel_reg(jzfb, 0x0501, 0x0000); |
649 | set_panel_reg(jzfb, 0x0502, 0x0000); |
650 | set_panel_reg(jzfb, 0x0503, 0x0000); |
651 | set_panel_reg(jzfb, 0x0504, 0x0000); |
652 | set_panel_reg(jzfb, 0x0505, 0x0000); |
653 | set_panel_reg(jzfb, 0x0600, 0x0000); |
654 | set_panel_reg(jzfb, 0x0606, 0x0000); |
655 | set_panel_reg(jzfb, 0x06f0, 0x0000); |
656 | set_panel_reg(jzfb, 0x07f0, 0x5420); |
657 | set_panel_reg(jzfb, 0x07f3, 0x288a); |
658 | set_panel_reg(jzfb, 0x07f4, 0x0022); |
659 | set_panel_reg(jzfb, 0x07f5, 0x0001); |
660 | set_panel_reg(jzfb, 0x07f0, 0x0000); |
661 | } |
662 | |
663 | static void spfd5420a_enable(struct jzfb *jzfb) |
664 | { |
665 | gpio_set_value(SPFD5420A_GPIO_RESET_N, 1); |
666 | mdelay(10); |
667 | gpio_set_value(SPFD5420A_GPIO_RESET_N, 0); |
668 | mdelay(10); |
669 | gpio_set_value(SPFD5420A_GPIO_RESET_N, 1); |
670 | mdelay(100); |
671 | if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_SMART_PARALLEL_18_BIT) { |
672 | set_panel_reg(jzfb, 0x0606, 0x0000); |
673 | udelay(10); |
674 | set_panel_reg(jzfb, 0x0007, 0x0001); |
675 | udelay(10); |
676 | set_panel_reg(jzfb, 0x0110, 0x0001); |
677 | udelay(10); |
678 | set_panel_reg(jzfb, 0x0100, 0x17b0); |
679 | set_panel_reg(jzfb, 0x0101, 0x0147); |
680 | set_panel_reg(jzfb, 0x0102, 0x019d); |
681 | set_panel_reg(jzfb, 0x0103, 0x8600); |
682 | set_panel_reg(jzfb, 0x0281, 0x0010); |
683 | udelay(10); |
684 | set_panel_reg(jzfb, 0x0102, 0x01bd); |
685 | udelay(10); |
686 | /************initial************/ |
687 | set_panel_reg(jzfb, 0x0000, 0x0000); |
688 | set_panel_reg(jzfb, 0x0001, 0x0000); |
689 | set_panel_reg(jzfb, 0x0002, 0x0400); |
690 | set_panel_reg(jzfb, 0x0003, 0x1288); /*up:0x1288 down:0x12B8 left:0x1290 right:0x12A0*/ |
691 | set_panel_reg(jzfb, 0x0006, 0x0000); |
692 | set_panel_reg(jzfb, 0x0008, 0x0503); |
693 | set_panel_reg(jzfb, 0x0009, 0x0001); |
694 | set_panel_reg(jzfb, 0x000b, 0x0010); |
695 | set_panel_reg(jzfb, 0x000c, 0x0000); |
696 | set_panel_reg(jzfb, 0x000f, 0x0000); |
697 | set_panel_reg(jzfb, 0x0007, 0x0001); |
698 | set_panel_reg(jzfb, 0x0010, 0x0010); |
699 | set_panel_reg(jzfb, 0x0011, 0x0202); |
700 | set_panel_reg(jzfb, 0x0012, 0x0300); |
701 | set_panel_reg(jzfb, 0x0020, 0x021e); |
702 | set_panel_reg(jzfb, 0x0021, 0x0202); |
703 | set_panel_reg(jzfb, 0x0022, 0x0100); |
704 | set_panel_reg(jzfb, 0x0090, 0x0000); |
705 | set_panel_reg(jzfb, 0x0092, 0x0000); |
706 | set_panel_reg(jzfb, 0x0100, 0x16b0); |
707 | set_panel_reg(jzfb, 0x0101, 0x0147); |
708 | set_panel_reg(jzfb, 0x0102, 0x01bd); |
709 | set_panel_reg(jzfb, 0x0103, 0x2c00); |
710 | set_panel_reg(jzfb, 0x0107, 0x0000); |
711 | set_panel_reg(jzfb, 0x0110, 0x0001); |
712 | set_panel_reg(jzfb, 0x0210, 0x0000); |
713 | set_panel_reg(jzfb, 0x0211, 0x00ef); |
714 | set_panel_reg(jzfb, 0x0212, 0x0000); |
715 | set_panel_reg(jzfb, 0x0213, 0x018f); |
716 | set_panel_reg(jzfb, 0x0280, 0x0000); |
717 | set_panel_reg(jzfb, 0x0281, 0x0001); |
718 | set_panel_reg(jzfb, 0x0282, 0x0000); |
719 | spfd5420a_init_gamma(jzfb); |
720 | set_panel_reg(jzfb, 0x0007, 0x0173); |
721 | } else { |
722 | set_panel_reg(jzfb, 0x0600, 0x0001); /*soft reset*/ |
723 | mdelay(10); |
724 | set_panel_reg(jzfb, 0x0600, 0x0000); /*soft reset*/ |
725 | mdelay(10); |
726 | set_panel_reg(jzfb, 0x0606, 0x0000); /*i80-i/F Endian Control*/ |
727 | /*===User setting=== */ |
728 | set_panel_reg(jzfb, 0x0001, 0x0000);/* Driver Output Control-----0x0100 SM(bit10) | 0x400*/ |
729 | set_panel_reg(jzfb, 0x0002, 0x0100); /*LCD Driving Wave Control 0x0100 */ |
730 | if (jzfb->pdata->bpp == 16) |
731 | set_panel_reg(jzfb, 0x0003, 0x50A8);/*Entry Mode 0x1030*/ |
732 | else /*bpp = 18*/ |
733 | set_panel_reg(jzfb, 0x0003, 0x1010 | 0xC8); /*Entry Mode 0x1030*/ |
734 | set_panel_reg(jzfb, 0x0006, 0x0000); /*Outline Sharpening Control*/ |
735 | set_panel_reg(jzfb, 0x0008, 0x0808); /*Sets the number of lines for front/back porch period*/ |
736 | set_panel_reg(jzfb, 0x0009, 0x0001); /*Display Control 3 */ |
737 | set_panel_reg(jzfb, 0x000B, 0x0010); /*Low Power Control*/ |
738 | set_panel_reg(jzfb, 0x000C, 0x0000); /*External Display Interface Control 1 0x0001 */ |
739 | set_panel_reg(jzfb, 0x000F, 0x0000); /*External Display Interface Control 2 */ |
740 | set_panel_reg(jzfb, 0x0400, 0xB104); /*Base Image Number of Line---GS(bit15) | 0x8000*/ |
741 | set_panel_reg(jzfb, 0x0401, 0x0001); /*Base Image Display 0x0001*/ |
742 | set_panel_reg(jzfb, 0x0404, 0x0000); /*Base Image Vertical Scroll Control 0x0000*/ |
743 | set_panel_reg(jzfb, 0x0500, 0x0000); /*Partial Image 1: Display Position*/ |
744 | set_panel_reg(jzfb, 0x0501, 0x0000); /*RAM Address (Start Line Address) */ |
745 | set_panel_reg(jzfb, 0x0502, 0x018f); /*RAM Address (End Line Address) */ |
746 | set_panel_reg(jzfb, 0x0503, 0x0000); /*Partial Image 2: Display Position RAM Address*/ |
747 | set_panel_reg(jzfb, 0x0504, 0x0000); /*RAM Address (Start Line Address) */ |
748 | set_panel_reg(jzfb, 0x0505, 0x0000); /*RAM Address (End Line Address)*/ |
749 | /*Panel interface control===*/ |
750 | set_panel_reg(jzfb, 0x0010, 0x0011); /*Division Ratio,Clocks per Line 14 */ |
751 | mdelay(10); |
752 | set_panel_reg(jzfb, 0x0011, 0x0202); /*Division Ratio,Clocks per Line*/ |
753 | set_panel_reg(jzfb, 0x0012, 0x0300); /*Sets low power VCOM drive period. */ |
754 | mdelay(10); |
755 | set_panel_reg(jzfb, 0x0020, 0x021e); /*Panel Interface Control 4 */ |
756 | set_panel_reg(jzfb, 0x0021, 0x0202); /*Panel Interface Control 5 */ |
757 | set_panel_reg(jzfb, 0x0022, 0x0100); /*Panel Interface Control 6*/ |
758 | set_panel_reg(jzfb, 0x0090, 0x0000); /*Frame Marker Control */ |
759 | set_panel_reg(jzfb, 0x0092, 0x0000); /*MDDI Sub-display Control */ |
760 | /*===Gamma setting=== */ |
761 | set_panel_reg(jzfb, 0x0300, 0x0101); /*γ Control*/ |
762 | set_panel_reg(jzfb, 0x0301, 0x0000); /*γ Control*/ |
763 | set_panel_reg(jzfb, 0x0302, 0x0016); /*γ Control*/ |
764 | set_panel_reg(jzfb, 0x0303, 0x2913); /*γ Control*/ |
765 | set_panel_reg(jzfb, 0x0304, 0x260B); /*γ Control*/ |
766 | set_panel_reg(jzfb, 0x0305, 0x0101); /*γ Control*/ |
767 | set_panel_reg(jzfb, 0x0306, 0x1204); /*γ Control*/ |
768 | set_panel_reg(jzfb, 0x0307, 0x0415); /*γ Control*/ |
769 | set_panel_reg(jzfb, 0x0308, 0x0205); /*γ Control*/ |
770 | set_panel_reg(jzfb, 0x0309, 0x0303); /*γ Control*/ |
771 | set_panel_reg(jzfb, 0x030a, 0x0E05); /*γ Control*/ |
772 | set_panel_reg(jzfb, 0x030b, 0x0D01); /*γ Control*/ |
773 | set_panel_reg(jzfb, 0x030c, 0x010D); /*γ Control*/ |
774 | set_panel_reg(jzfb, 0x030d, 0x050E); /*γ Control*/ |
775 | set_panel_reg(jzfb, 0x030e, 0x0303); /*γ Control*/ |
776 | set_panel_reg(jzfb, 0x030f, 0x0502); /*γ Control*/ |
777 | /*===Power on sequence===*/ |
778 | set_panel_reg(jzfb, 0x0007, 0x0001); /*Display Control 1*/ |
779 | set_panel_reg(jzfb, 0x0110, 0x0001); /*Power supply startup enable bit*/ |
780 | set_panel_reg(jzfb, 0x0112, 0x0060); /*Power Control 7*/ |
781 | set_panel_reg(jzfb, 0x0100, 0x16B0); /*Power Control 1 */ |
782 | set_panel_reg(jzfb, 0x0101, 0x0115); /*Power Control 2*/ |
783 | set_panel_reg(jzfb, 0x0102, 0x0119); /*Starts VLOUT3,Sets the VREG1OUT.*/ |
784 | mdelay(50); |
785 | set_panel_reg(jzfb, 0x0103, 0x2E00); /*set the amplitude of VCOM*/ |
786 | mdelay(50); |
787 | set_panel_reg(jzfb, 0x0282, 0x0093); /*VCOMH voltage, alt: 0x008E, 0x0093*/ |
788 | set_panel_reg(jzfb, 0x0281, 0x000A); /*Selects the factor of VREG1OUT to generate VCOMH. */ |
789 | set_panel_reg(jzfb, 0x0102, 0x01BE); /*Starts VLOUT3,Sets the VREG1OUT.*/ |
790 | mdelay(10); |
791 | /*Address */ |
792 | set_panel_reg(jzfb, 0x0210, 0x0000); /*Window Horizontal RAM Address Start*/ |
793 | set_panel_reg(jzfb, 0x0211, 0x00ef); /*Window Horizontal RAM Address End*/ |
794 | set_panel_reg(jzfb, 0x0212, 0x0000); /*Window Vertical RAM Address Start*/ |
795 | set_panel_reg(jzfb, 0x0213, 0x018f); /*Window Vertical RAM Address End */ |
796 | set_panel_reg(jzfb, 0x0200, 0x0000); /*RAM Address Set (Horizontal Address)*/ |
797 | set_panel_reg(jzfb, 0x0201, 0x018f); /*RAM Address Set (Vertical Address)*/ |
798 | /*===Display_On_Function===*/ |
799 | set_panel_reg(jzfb, 0x0007, 0x0021); /*Display Control 1 */ |
800 | mdelay(50); /*40*/ |
801 | set_panel_reg(jzfb, 0x0007, 0x0061); /*Display Control 1 */ |
802 | mdelay(50); /*100*/ |
803 | set_panel_reg(jzfb, 0x0007, 0x0173); /*Display Control 1 */ |
804 | mdelay(50); /*300*/ |
805 | } |
806 | send_panel_command(jzfb, 0x0202); /*Write Data to GRAM */ |
807 | udelay(10); |
808 | spfd5420a_set_addr(jzfb, 0, 0); |
809 | udelay(100); |
810 | } |
811 | |
812 | static void spfd5420a_disable(struct jzfb *jzfb) |
813 | { |
814 | } |
815 | |
816 | #endif |
817 | |
818 | static const struct jz_slcd_panel jz_slcd_panels[] = { |
819 | #ifdef CONFIG_JZ_SLCD_ILI9325 |
820 | { |
821 | ili9325_init, ili9325_exit, |
822 | ili9325_enable, ili9325_disable, |
823 | }, |
824 | #endif |
825 | #ifdef CONFIG_JZ_SLCD_ILI9331 |
826 | { |
827 | ili9331_init, ili9331_exit, |
828 | ili9331_enable, ili9331_disable, |
829 | }, |
830 | #endif |
831 | #ifdef CONFIG_JZ_SLCD_ILI9338 |
832 | { |
833 | ili9338_init, ili9338_exit, |
834 | ili9338_enable, ili9338_disable, |
835 | }, |
836 | #endif |
837 | #ifdef CONFIG_JZ_SLCD_LGDP4551 |
838 | { |
839 | lgdp4551_init, lgdp4551_exit, |
840 | lgdp4551_enable, lgdp4551_disable, |
841 | }, |
842 | #endif |
843 | #ifdef CONFIG_JZ_SLCD_SPFD5420A |
844 | { |
845 | spfd5420a_init, spfd5420a_exit, |
846 | spfd5420a_enable, spfd5420a_disable, |
847 | }, |
848 | #endif |
849 | }; |
850 | |
851 | const struct jz_slcd_panel *jz_slcd_panels_probe(struct jzfb *jzfb) |
852 | { |
853 | switch (ARRAY_SIZE(jz_slcd_panels)) { |
854 | case 0: |
855 | return NULL; |
856 | case 1: |
857 | return &jz_slcd_panels[0]; |
858 | default: |
859 | dev_warn(&jzfb->pdev->dev, |
860 | "SLCD panel selection not implemented yet; " |
861 | "picking first panel\n"); |
862 | return &jz_slcd_panels[0]; |
863 | } |
864 | } |
865 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
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jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9