Root/
Source at commit e84aa5403dc24f85e23d334d9a6b1e47bb418813 created 13 years 5 days ago. By Maarten ter Huurne, MIPS: JZ4740: SLCD: Make blanking and TV-out mutually exclusive. | |
---|---|
1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * Copyright (C) 2010, Maarten ter Huurne <maarten@treewalker.org> |
4 | * JZ4720/JZ4740 SoC LCD framebuffer driver |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms of the GNU General Public License as published by the |
8 | * Free Software Foundation; either version 2 of the License, or (at your |
9 | * option) any later version. |
10 | * |
11 | * You should have received a copy of the GNU General Public License along |
12 | * with this program; if not, write to the Free Software Foundation, Inc., |
13 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
14 | * |
15 | */ |
16 | |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> |
19 | #include <linux/mutex.h> |
20 | #include <linux/platform_device.h> |
21 | |
22 | #include <linux/clk.h> |
23 | #include <linux/delay.h> |
24 | |
25 | #include <linux/console.h> |
26 | #include <linux/fb.h> |
27 | |
28 | #include <linux/dma-mapping.h> |
29 | |
30 | #include <asm/mach-jz4740/dma.h> |
31 | #include <asm/mach-jz4740/gpio.h> |
32 | #include <asm/mach-jz4740/jz4740_fb.h> |
33 | |
34 | #include "jz4740_lcd.h" |
35 | #include "jz4740_slcd.h" |
36 | |
37 | struct jzfb_framedesc { |
38 | uint32_t next; |
39 | uint32_t addr; |
40 | uint32_t id; |
41 | uint32_t cmd; |
42 | } __attribute__((packed)); |
43 | |
44 | static struct fb_fix_screeninfo jzfb_fix __devinitdata = { |
45 | .id = "JZ4740 SLCD FB", |
46 | .type = FB_TYPE_PACKED_PIXELS, |
47 | .visual = FB_VISUAL_TRUECOLOR, |
48 | .xpanstep = 0, |
49 | .ypanstep = 1, |
50 | .ywrapstep = 0, |
51 | .accel = FB_ACCEL_NONE, |
52 | }; |
53 | |
54 | const static struct jz_gpio_bulk_request jz_slcd_ctrl_pins[] = { |
55 | JZ_GPIO_BULK_PIN(LCD_PCLK), |
56 | JZ_GPIO_BULK_PIN(SLCD_RS), |
57 | JZ_GPIO_BULK_PIN(SLCD_CS), |
58 | }; |
59 | |
60 | const static struct jz_gpio_bulk_request jz_slcd_data_pins[] = { |
61 | JZ_GPIO_BULK_PIN(LCD_DATA0), |
62 | JZ_GPIO_BULK_PIN(LCD_DATA1), |
63 | JZ_GPIO_BULK_PIN(LCD_DATA2), |
64 | JZ_GPIO_BULK_PIN(LCD_DATA3), |
65 | JZ_GPIO_BULK_PIN(LCD_DATA4), |
66 | JZ_GPIO_BULK_PIN(LCD_DATA5), |
67 | JZ_GPIO_BULK_PIN(LCD_DATA6), |
68 | JZ_GPIO_BULK_PIN(LCD_DATA7), |
69 | JZ_GPIO_BULK_PIN(LCD_DATA8), |
70 | JZ_GPIO_BULK_PIN(LCD_DATA9), |
71 | JZ_GPIO_BULK_PIN(LCD_DATA10), |
72 | JZ_GPIO_BULK_PIN(LCD_DATA11), |
73 | JZ_GPIO_BULK_PIN(LCD_DATA12), |
74 | JZ_GPIO_BULK_PIN(LCD_DATA13), |
75 | JZ_GPIO_BULK_PIN(LCD_DATA14), |
76 | JZ_GPIO_BULK_PIN(LCD_DATA15), |
77 | JZ_GPIO_BULK_PIN(LCD_DATA16), |
78 | JZ_GPIO_BULK_PIN(LCD_DATA17), |
79 | }; |
80 | |
81 | static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb) |
82 | { |
83 | return ARRAY_SIZE(jz_slcd_ctrl_pins); |
84 | } |
85 | |
86 | static unsigned int jzfb_num_data_pins(struct jzfb *jzfb) |
87 | { |
88 | switch (jzfb->pdata->lcd_type) { |
89 | case JZ_LCD_TYPE_SMART_PARALLEL_8_BIT: |
90 | return 8; |
91 | case JZ_LCD_TYPE_SMART_PARALLEL_16_BIT: |
92 | return 16; |
93 | case JZ_LCD_TYPE_SMART_PARALLEL_18_BIT: |
94 | return 18; |
95 | default: |
96 | return 0; |
97 | } |
98 | } |
99 | |
100 | static void jzfb_free_gpio_pins(struct jzfb *jzfb) |
101 | { |
102 | jz_gpio_bulk_free(jz_slcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
103 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
104 | /* serial */ |
105 | jz_gpio_bulk_free(&jz_slcd_data_pins[15], 1); |
106 | } else { |
107 | /* parallel */ |
108 | jz_gpio_bulk_free(jz_slcd_data_pins, |
109 | jzfb_num_data_pins(jzfb)); |
110 | } |
111 | } |
112 | |
113 | static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, |
114 | unsigned blue, unsigned transp, struct fb_info *fb) |
115 | { |
116 | if (regno >= 16) |
117 | return -EINVAL; |
118 | |
119 | red = (red * ((1 << fb->var.red.length ) - 1)) / ((1 << 16) - 1); |
120 | green = (green * ((1 << fb->var.green.length) - 1)) / ((1 << 16) - 1); |
121 | blue = (blue * ((1 << fb->var.blue.length ) - 1)) / ((1 << 16) - 1); |
122 | |
123 | ((uint32_t *)fb->pseudo_palette)[regno] = |
124 | (red << fb->var.red.offset ) | |
125 | (green << fb->var.green.offset) | |
126 | (blue << fb->var.blue.offset ); |
127 | |
128 | return 0; |
129 | } |
130 | |
131 | static int jzfb_get_controller_bpp(struct jzfb *jzfb) |
132 | { |
133 | switch (jzfb->pdata->bpp) { |
134 | case 18: |
135 | case 24: |
136 | return 32; |
137 | case 15: |
138 | return 16; |
139 | default: |
140 | return jzfb->pdata->bpp; |
141 | } |
142 | } |
143 | |
144 | static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb, struct fb_var_screeninfo *var) |
145 | { |
146 | size_t i; |
147 | struct fb_videomode *mode = jzfb->pdata->modes; |
148 | |
149 | for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) { |
150 | if (mode->xres == var->xres && mode->yres == var->yres) |
151 | return mode; |
152 | } |
153 | |
154 | return NULL; |
155 | } |
156 | |
157 | static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb) |
158 | { |
159 | struct jzfb *jzfb = fb->par; |
160 | struct fb_videomode *mode; |
161 | |
162 | if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) && |
163 | var->bits_per_pixel != jzfb->pdata->bpp) |
164 | return -EINVAL; |
165 | |
166 | mode = jzfb_get_mode(jzfb, var); |
167 | if (mode == NULL) |
168 | return -EINVAL; |
169 | |
170 | fb_videomode_to_var(var, mode); |
171 | |
172 | /* Reserve space for double buffering. */ |
173 | var->yres_virtual = var->yres * 2; |
174 | |
175 | switch (jzfb->pdata->bpp) { |
176 | case 8: |
177 | break; |
178 | case 15: |
179 | var->red.offset = 10; |
180 | var->red.length = 5; |
181 | var->green.offset = 5; |
182 | var->green.length = 5; |
183 | var->blue.offset = 0; |
184 | var->blue.length = 5; |
185 | break; |
186 | case 16: |
187 | var->red.offset = 11; |
188 | var->red.length = 5; |
189 | var->green.offset = 5; |
190 | var->green.length = 6; |
191 | var->blue.offset = 0; |
192 | var->blue.length = 5; |
193 | break; |
194 | case 18: |
195 | var->red.offset = 16; |
196 | var->red.length = 6; |
197 | var->green.offset = 8; |
198 | var->green.length = 6; |
199 | var->blue.offset = 0; |
200 | var->blue.length = 6; |
201 | var->bits_per_pixel = 32; |
202 | break; |
203 | case 32: |
204 | case 24: |
205 | var->transp.offset = 24; |
206 | var->transp.length = 8; |
207 | var->red.offset = 16; |
208 | var->red.length = 8; |
209 | var->green.offset = 8; |
210 | var->green.length = 8; |
211 | var->blue.offset = 0; |
212 | var->blue.length = 8; |
213 | var->bits_per_pixel = 32; |
214 | break; |
215 | default: |
216 | break; |
217 | } |
218 | |
219 | return 0; |
220 | } |
221 | |
222 | static void jzfb_disable_dma(struct jzfb *jzfb) |
223 | { |
224 | jz4740_dma_disable(jzfb->dma); |
225 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
226 | writeb(readb(jzfb->base + JZ_REG_SLCD_CTRL) & ~SLCD_CTRL_DMA_EN, |
227 | jzfb->base + JZ_REG_SLCD_CTRL); |
228 | } |
229 | |
230 | static struct jz4740_dma_config jzfb_slcd_dma_config = { |
231 | .src_width = JZ4740_DMA_WIDTH_32BIT, |
232 | .dst_width = JZ4740_DMA_WIDTH_16BIT, |
233 | .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE, |
234 | .request_type = JZ4740_DMA_TYPE_SLCD, |
235 | .flags = JZ4740_DMA_SRC_AUTOINC, |
236 | .mode = JZ4740_DMA_MODE_BLOCK, |
237 | }; |
238 | |
239 | static void jzfb_upload_frame_dma(struct jzfb *jzfb) |
240 | { |
241 | struct fb_info *fb = jzfb->fb; |
242 | struct fb_videomode *mode = fb->mode; |
243 | __u32 bytes_per_line = fb->fix.line_length; |
244 | |
245 | jz4740_dma_set_src_addr(jzfb->dma, jzfb->vidmem_phys + |
246 | bytes_per_line * fb->var.yoffset); |
247 | jz4740_dma_set_dst_addr(jzfb->dma, |
248 | CPHYSADDR(jzfb->base + JZ_REG_SLCD_FIFO)); |
249 | jz4740_dma_set_transfer_count(jzfb->dma, bytes_per_line * mode->yres); |
250 | |
251 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
252 | writeb(readb(jzfb->base + JZ_REG_SLCD_CTRL) | SLCD_CTRL_DMA_EN, |
253 | jzfb->base + JZ_REG_SLCD_CTRL); |
254 | jz4740_dma_enable(jzfb->dma); |
255 | } |
256 | |
257 | static void jzfb_upload_frame_cpu(struct jzfb *jzfb) |
258 | { |
259 | const int num_pixels = jzfb->fb->mode->xres * jzfb->fb->mode->yres; |
260 | uint16_t *p = jzfb->vidmem; |
261 | int i; |
262 | |
263 | jzfb_disable_dma(jzfb); |
264 | for (i = 0; i < num_pixels; i++) { |
265 | uint16_t rgb = *p++; |
266 | while (readb(jzfb->base + JZ_REG_SLCD_STATE) & SLCD_STATE_BUSY); |
267 | writel(SLCD_DATA_RS_DATA | rgb, jzfb->base + JZ_REG_SLCD_DATA); |
268 | } |
269 | } |
270 | |
271 | static void jzfb_refresh_work(struct work_struct *work) |
272 | { |
273 | struct jzfb *jzfb = container_of(work, struct jzfb, refresh_work.work); |
274 | |
275 | mutex_lock(&jzfb->lock); |
276 | if (jzfb->is_enabled) { |
277 | if (1) { |
278 | jzfb_upload_frame_dma(jzfb); |
279 | /* The DMA complete callback will reschedule. */ |
280 | } else { |
281 | jzfb_upload_frame_cpu(jzfb); |
282 | schedule_delayed_work(&jzfb->refresh_work, HZ / 10); |
283 | } |
284 | } |
285 | mutex_unlock(&jzfb->lock); |
286 | } |
287 | |
288 | static void jzfb_refresh_work_complete( |
289 | struct jz4740_dma_chan *dma, int res, void *dev) |
290 | { |
291 | struct jzfb *jzfb = dev_get_drvdata(dev); |
292 | // TODO: Stick to refresh rate in mode description. |
293 | int interval = HZ / 60; |
294 | |
295 | schedule_delayed_work(&jzfb->refresh_work, interval); |
296 | } |
297 | |
298 | static int jzfb_set_par(struct fb_info *info) |
299 | { |
300 | struct jzfb *jzfb = info->par; |
301 | struct fb_var_screeninfo *var = &info->var; |
302 | struct fb_videomode *mode; |
303 | uint16_t slcd_cfg; |
304 | |
305 | mode = jzfb_get_mode(jzfb, var); |
306 | if (mode == NULL) |
307 | return -EINVAL; |
308 | |
309 | info->mode = mode; |
310 | |
311 | slcd_cfg = SLCD_CFG_BURST_8_WORD; |
312 | /* command size */ |
313 | slcd_cfg |= (jzfb->pdata->lcd_type & 3) << SLCD_CFG_CWIDTH_BIT; |
314 | /* data size */ |
315 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
316 | /* serial */ |
317 | unsigned int num_bits; |
318 | switch (jzfb->pdata->lcd_type) { |
319 | case JZ_LCD_TYPE_SMART_SERIAL_8_BIT: |
320 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x1; |
321 | num_bits = 8; |
322 | break; |
323 | case JZ_LCD_TYPE_SMART_SERIAL_16_BIT: |
324 | slcd_cfg |= SLCD_CFG_DWIDTH_16; |
325 | num_bits = 16; |
326 | break; |
327 | case JZ_LCD_TYPE_SMART_SERIAL_18_BIT: |
328 | slcd_cfg |= SLCD_CFG_DWIDTH_18; |
329 | num_bits = 18; |
330 | break; |
331 | default: |
332 | num_bits = 0; |
333 | break; |
334 | } |
335 | if (num_bits != jzfb->pdata->bpp) { |
336 | dev_err(&jzfb->pdev->dev, |
337 | "Data size (%d) does not match bpp (%d)\n", |
338 | num_bits, jzfb->pdata->bpp); |
339 | } |
340 | slcd_cfg |= SLCD_CFG_TYPE_SERIAL; |
341 | } else { |
342 | /* parallel */ |
343 | switch (jzfb->pdata->bpp) { |
344 | case 8: |
345 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x1; |
346 | break; |
347 | case 15: |
348 | case 16: |
349 | switch (jzfb->pdata->lcd_type) { |
350 | case JZ_LCD_TYPE_SMART_PARALLEL_8_BIT: |
351 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x2; |
352 | break; |
353 | default: |
354 | slcd_cfg |= SLCD_CFG_DWIDTH_16; |
355 | break; |
356 | } |
357 | break; |
358 | case 18: |
359 | switch (jzfb->pdata->lcd_type) { |
360 | case JZ_LCD_TYPE_SMART_PARALLEL_8_BIT: |
361 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x3; |
362 | break; |
363 | case JZ_LCD_TYPE_SMART_PARALLEL_16_BIT: |
364 | slcd_cfg |= SLCD_CFG_DWIDTH_9_x2; |
365 | break; |
366 | case JZ_LCD_TYPE_SMART_PARALLEL_18_BIT: |
367 | slcd_cfg |= SLCD_CFG_DWIDTH_18; |
368 | break; |
369 | default: |
370 | break; |
371 | } |
372 | break; |
373 | case 24: |
374 | slcd_cfg |= SLCD_CFG_DWIDTH_8_x3; |
375 | break; |
376 | default: |
377 | dev_err(&jzfb->pdev->dev, |
378 | "Unsupported value for bpp: %d\n", |
379 | jzfb->pdata->bpp); |
380 | } |
381 | slcd_cfg |= SLCD_CFG_TYPE_PARALLEL; |
382 | } |
383 | if (!jzfb->pdata->chip_select_active_low) |
384 | slcd_cfg |= SLCD_CFG_CS_ACTIVE_HIGH; |
385 | if (!jzfb->pdata->register_select_active_low) |
386 | slcd_cfg |= SLCD_CFG_RS_CMD_HIGH; |
387 | if (!jzfb->pdata->pixclk_falling_edge) |
388 | slcd_cfg |= SLCD_CFG_CLK_ACTIVE_RISING; |
389 | |
390 | #if 0 |
391 | // TODO(MtH): Compute rate from refresh or vice versa. |
392 | if (mode->pixclock) { |
393 | rate = PICOS2KHZ(mode->pixclock) * 1000; |
394 | mode->refresh = rate / vt / ht; |
395 | } else { |
396 | if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) |
397 | rate = mode->refresh * (vt + 2 * mode->xres) * ht; |
398 | else |
399 | rate = mode->refresh * vt * ht; |
400 | |
401 | mode->pixclock = KHZ2PICOS(rate / 1000); |
402 | } |
403 | #endif |
404 | |
405 | mutex_lock(&jzfb->lock); |
406 | if (!jzfb->is_enabled) |
407 | clk_enable(jzfb->ldclk); |
408 | |
409 | // TODO(MtH): We should not change config while DMA might be running. |
410 | writew(slcd_cfg, jzfb->base + JZ_REG_SLCD_CFG); |
411 | |
412 | if (!jzfb->is_enabled) |
413 | clk_disable(jzfb->ldclk); |
414 | mutex_unlock(&jzfb->lock); |
415 | |
416 | // TODO(MtH): Use maximum transfer speed that panel can handle. |
417 | // ILI9325 can do 10 MHz. |
418 | clk_set_rate(jzfb->lpclk, 12000000); |
419 | clk_set_rate(jzfb->ldclk, 42000000); |
420 | |
421 | return 0; |
422 | } |
423 | |
424 | static void jzfb_enable(struct jzfb *jzfb) |
425 | { |
426 | uint32_t ctrl; |
427 | |
428 | clk_enable(jzfb->ldclk); |
429 | |
430 | jz_gpio_bulk_resume(jz_slcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
431 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
432 | /* serial */ |
433 | jz_gpio_bulk_resume(&jz_slcd_data_pins[15], 1); |
434 | } else { |
435 | /* parallel */ |
436 | jz_gpio_bulk_resume(jz_slcd_data_pins, |
437 | jzfb_num_data_pins(jzfb)); |
438 | } |
439 | jzfb_disable_dma(jzfb); |
440 | jzfb->panel->enable(jzfb); |
441 | |
442 | ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); |
443 | ctrl |= JZ_LCD_CTRL_ENABLE; |
444 | ctrl &= ~JZ_LCD_CTRL_DISABLE; |
445 | writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); |
446 | |
447 | schedule_delayed_work(&jzfb->refresh_work, 0); |
448 | } |
449 | |
450 | static void jzfb_disable(struct jzfb *jzfb) |
451 | { |
452 | /* It is safe but wasteful to call refresh_work() while disabled. */ |
453 | cancel_delayed_work(&jzfb->refresh_work); |
454 | |
455 | /* Abort any DMA transfer that might be in progress and allow direct |
456 | writes to the panel. */ |
457 | jzfb_disable_dma(jzfb); |
458 | |
459 | jzfb->panel->disable(jzfb); |
460 | jz_gpio_bulk_suspend(jz_slcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
461 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
462 | /* serial */ |
463 | jz_gpio_bulk_suspend(&jz_slcd_data_pins[15], 1); |
464 | } else { |
465 | /* parallel */ |
466 | jz_gpio_bulk_suspend(jz_slcd_data_pins, |
467 | jzfb_num_data_pins(jzfb)); |
468 | } |
469 | |
470 | clk_disable(jzfb->ldclk); |
471 | } |
472 | |
473 | static int jzfb_blank(int blank_mode, struct fb_info *info) |
474 | { |
475 | struct jzfb* jzfb = info->par; |
476 | int ret = 0; |
477 | int new_enabled = (blank_mode == FB_BLANK_UNBLANK); |
478 | |
479 | mutex_lock(&jzfb->lock); |
480 | if (new_enabled) { |
481 | if (!jzfb->is_enabled) |
482 | jzfb_enable(jzfb); |
483 | } else { |
484 | if (jzfb->is_enabled) { |
485 | /* No sleep in TV-out mode. */ |
486 | if (readl(jzfb->base + JZ_REG_LCD_CFG) & JZ_LCD_CFG_SLCD) |
487 | jzfb_disable(jzfb); |
488 | else |
489 | ret = -EBUSY; |
490 | } |
491 | } |
492 | if (!ret) |
493 | jzfb->is_enabled = new_enabled; |
494 | mutex_unlock(&jzfb->lock); |
495 | |
496 | return ret; |
497 | } |
498 | |
499 | static int jzfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
500 | { |
501 | info->var.yoffset = var->yoffset; |
502 | return 0; |
503 | } |
504 | |
505 | static int jzfb_alloc_devmem(struct jzfb *jzfb) |
506 | { |
507 | int max_framesize = 0; |
508 | struct fb_videomode *mode = jzfb->pdata->modes; |
509 | void *page; |
510 | int i; |
511 | |
512 | for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) { |
513 | if (max_framesize < mode->xres * mode->yres) |
514 | max_framesize = mode->xres * mode->yres; |
515 | } |
516 | |
517 | max_framesize *= jzfb_get_controller_bpp(jzfb) >> 3; |
518 | |
519 | jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev, |
520 | sizeof(*jzfb->framedesc), |
521 | &jzfb->framedesc_phys, GFP_KERNEL); |
522 | |
523 | if (!jzfb->framedesc) |
524 | return -ENOMEM; |
525 | |
526 | /* reserve memory for two frames to allow double buffering */ |
527 | jzfb->vidmem_size = PAGE_ALIGN(max_framesize * 2); |
528 | jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev, |
529 | jzfb->vidmem_size, |
530 | &jzfb->vidmem_phys, GFP_KERNEL); |
531 | |
532 | if (!jzfb->vidmem) |
533 | goto err_free_framedesc; |
534 | |
535 | for (page = jzfb->vidmem; |
536 | page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size); |
537 | page += PAGE_SIZE) { |
538 | SetPageReserved(virt_to_page(page)); |
539 | } |
540 | |
541 | jzfb->framedesc->next = jzfb->framedesc_phys; |
542 | jzfb->framedesc->addr = jzfb->vidmem_phys; |
543 | jzfb->framedesc->id = 0xdeafbead; |
544 | jzfb->framedesc->cmd = 0; |
545 | jzfb->framedesc->cmd |= max_framesize / 4; |
546 | |
547 | return 0; |
548 | |
549 | err_free_framedesc: |
550 | dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), |
551 | jzfb->framedesc, jzfb->framedesc_phys); |
552 | return -ENOMEM; |
553 | } |
554 | |
555 | static void jzfb_free_devmem(struct jzfb *jzfb) |
556 | { |
557 | dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size, |
558 | jzfb->vidmem, jzfb->vidmem_phys); |
559 | dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), |
560 | jzfb->framedesc, jzfb->framedesc_phys); |
561 | } |
562 | |
563 | #include "jz4740_lcd.h" |
564 | |
565 | #define FBIOA320TVOUT 0x46F0 |
566 | #define FB_A320TV_OFF 0 |
567 | #define FB_A320TV_NTSC 1 |
568 | #define FB_A320TV_PAL 2 |
569 | |
570 | static void jzfb_tv_out(struct jzfb *jzfb, unsigned int mode) |
571 | { |
572 | int blank = jzfb->is_enabled ? FB_BLANK_UNBLANK : FB_BLANK_POWERDOWN; |
573 | struct fb_event event = { |
574 | .info = jzfb->fb, |
575 | .data = &blank, |
576 | }; |
577 | |
578 | printk("A320 TV out: %d\n", mode); |
579 | |
580 | if (mode != FB_A320TV_OFF) { |
581 | cancel_delayed_work(&jzfb->refresh_work); |
582 | /* Abort any DMA transfer that might be in progress and |
583 | allow direct writes to the panel. */ |
584 | jzfb_disable_dma(jzfb); |
585 | jzfb->panel->disable(jzfb); |
586 | |
587 | /* set up LCD controller for TV output */ |
588 | |
589 | writel(JZ_LCD_CFG_HSYNC_ACTIVE_LOW | |
590 | JZ_LCD_CFG_VSYNC_ACTIVE_LOW, |
591 | jzfb->base + JZ_REG_LCD_CFG); |
592 | |
593 | /* V-Sync pulse end position */ |
594 | writel(10, jzfb->base + JZ_REG_LCD_VSYNC); |
595 | |
596 | if (mode == FB_A320TV_PAL) { |
597 | /* PAL */ |
598 | /* H-Sync pulse start position */ |
599 | writel(125, jzfb->base + JZ_REG_LCD_HSYNC); |
600 | /* virtual area size */ |
601 | writel(0x036c0112, jzfb->base + JZ_REG_LCD_VAT); |
602 | /* horizontal start/end point */ |
603 | writel(0x02240364, jzfb->base + JZ_REG_LCD_DAH); |
604 | /* vertical start/end point */ |
605 | writel(0x1b010b, jzfb->base + JZ_REG_LCD_DAV); |
606 | } |
607 | else { |
608 | /* NTSC */ |
609 | writel(0x3c, jzfb->base + JZ_REG_LCD_HSYNC); |
610 | writel(0x02e00110, jzfb->base + JZ_REG_LCD_VAT); |
611 | writel(0x019902d9, jzfb->base + JZ_REG_LCD_DAH); |
612 | writel(0x1d010d, jzfb->base + JZ_REG_LCD_DAV); |
613 | } |
614 | writel(0, jzfb->base + JZ_REG_LCD_PS); |
615 | writel(0, jzfb->base + JZ_REG_LCD_CLS); |
616 | writel(0, jzfb->base + JZ_REG_LCD_SPL); |
617 | writel(0, jzfb->base + JZ_REG_LCD_REV); |
618 | /* reset status register */ |
619 | writel(0, jzfb->base + JZ_REG_LCD_STATE); |
620 | |
621 | /* tell LCDC about the frame descriptor address */ |
622 | writel(jzfb->framedesc_phys, jzfb->base + JZ_REG_LCD_DA0); |
623 | |
624 | writel(JZ_LCD_CTRL_BURST_16 | JZ_LCD_CTRL_ENABLE | |
625 | JZ_LCD_CTRL_BPP_15_16, |
626 | jzfb->base + JZ_REG_LCD_CTRL); |
627 | } |
628 | else { |
629 | /* disable LCD controller and re-enable SLCD */ |
630 | writel(JZ_LCD_CFG_SLCD, jzfb->base + JZ_REG_LCD_CFG); |
631 | jzfb->panel->enable(jzfb); |
632 | schedule_delayed_work(&jzfb->refresh_work, 0); |
633 | } |
634 | |
635 | /* reaffirm the current blanking state, to trigger a backlight update */ |
636 | fb_notifier_call_chain(FB_EVENT_BLANK, &event); |
637 | } |
638 | |
639 | static int jzfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) |
640 | { |
641 | struct jzfb *jzfb = info->par; |
642 | switch (cmd) { |
643 | case FBIOA320TVOUT: |
644 | /* No TV-out mode while sleeping. */ |
645 | if (!jzfb->is_enabled) |
646 | return -EBUSY; |
647 | |
648 | jzfb_tv_out(jzfb, arg); |
649 | break; |
650 | default: |
651 | return -EINVAL; |
652 | } |
653 | return 0; |
654 | } |
655 | |
656 | static struct fb_ops jzfb_ops = { |
657 | .owner = THIS_MODULE, |
658 | .fb_check_var = jzfb_check_var, |
659 | .fb_set_par = jzfb_set_par, |
660 | .fb_setcolreg = jzfb_setcolreg, |
661 | .fb_blank = jzfb_blank, |
662 | .fb_pan_display = jzfb_pan_display, |
663 | .fb_fillrect = sys_fillrect, |
664 | .fb_copyarea = sys_copyarea, |
665 | .fb_imageblit = sys_imageblit, |
666 | .fb_ioctl = jzfb_ioctl, |
667 | }; |
668 | |
669 | static int __devinit jzfb_probe(struct platform_device *pdev) |
670 | { |
671 | int ret; |
672 | struct jzfb *jzfb; |
673 | struct fb_info *fb; |
674 | struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data; |
675 | struct resource *mem; |
676 | |
677 | if (!pdata) { |
678 | dev_err(&pdev->dev, "Missing platform data\n"); |
679 | return -ENOENT; |
680 | } |
681 | |
682 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
683 | |
684 | if (!mem) { |
685 | dev_err(&pdev->dev, "Failed to get register memory resource\n"); |
686 | return -ENOENT; |
687 | } |
688 | |
689 | mem = request_mem_region(mem->start, resource_size(mem), pdev->name); |
690 | |
691 | if (!mem) { |
692 | dev_err(&pdev->dev, "Failed to request register memory region\n"); |
693 | return -EBUSY; |
694 | } |
695 | |
696 | fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev); |
697 | |
698 | if (!fb) { |
699 | dev_err(&pdev->dev, "Failed to allocate framebuffer device\n"); |
700 | ret = -ENOMEM; |
701 | goto err_release_mem_region; |
702 | } |
703 | |
704 | fb->fbops = &jzfb_ops; |
705 | fb->flags = FBINFO_DEFAULT; |
706 | |
707 | jzfb = fb->par; |
708 | jzfb->pdev = pdev; |
709 | jzfb->pdata = pdata; |
710 | jzfb->mem = mem; |
711 | |
712 | jzfb->dma = jz4740_dma_request(&pdev->dev, dev_name(&pdev->dev)); |
713 | if (!jzfb->dma) { |
714 | dev_err(&pdev->dev, "Failed to get DMA channel\n"); |
715 | ret = -EBUSY; |
716 | goto err_framebuffer_release; |
717 | } |
718 | jz4740_dma_configure(jzfb->dma, &jzfb_slcd_dma_config); |
719 | jz4740_dma_set_complete_cb(jzfb->dma, &jzfb_refresh_work_complete); |
720 | |
721 | jzfb->ldclk = clk_get(&pdev->dev, "lcd"); |
722 | if (IS_ERR(jzfb->ldclk)) { |
723 | ret = PTR_ERR(jzfb->ldclk); |
724 | dev_err(&pdev->dev, "Failed to get lcd clock: %d\n", ret); |
725 | goto err_free_dma; |
726 | } |
727 | |
728 | jzfb->lpclk = clk_get(&pdev->dev, "lcd_pclk"); |
729 | if (IS_ERR(jzfb->lpclk)) { |
730 | ret = PTR_ERR(jzfb->lpclk); |
731 | dev_err(&pdev->dev, "Failed to get lcd pixel clock: %d\n", ret); |
732 | goto err_put_ldclk; |
733 | } |
734 | |
735 | jzfb->base = ioremap(mem->start, resource_size(mem)); |
736 | |
737 | if (!jzfb->base) { |
738 | dev_err(&pdev->dev, "Failed to ioremap register memory region\n"); |
739 | ret = -EBUSY; |
740 | goto err_put_lpclk; |
741 | } |
742 | |
743 | platform_set_drvdata(pdev, jzfb); |
744 | |
745 | fb_videomode_to_modelist(pdata->modes, pdata->num_modes, |
746 | &fb->modelist); |
747 | fb->mode = pdata->modes; |
748 | |
749 | fb_videomode_to_var(&fb->var, fb->mode); |
750 | fb->var.bits_per_pixel = pdata->bpp; |
751 | jzfb_check_var(&fb->var, fb); |
752 | |
753 | ret = jzfb_alloc_devmem(jzfb); |
754 | if (ret) { |
755 | dev_err(&pdev->dev, "Failed to allocate video memory\n"); |
756 | goto err_iounmap; |
757 | } |
758 | |
759 | fb->fix = jzfb_fix; |
760 | fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8; |
761 | fb->fix.mmio_start = mem->start; |
762 | fb->fix.mmio_len = resource_size(mem); |
763 | fb->fix.smem_start = jzfb->vidmem_phys; |
764 | fb->fix.smem_len = fb->fix.line_length * fb->var.yres_virtual; |
765 | fb->screen_base = jzfb->vidmem; |
766 | fb->pseudo_palette = jzfb->pseudo_palette; |
767 | |
768 | fb_alloc_cmap(&fb->cmap, 256, 0); |
769 | |
770 | mutex_init(&jzfb->lock); |
771 | |
772 | clk_enable(jzfb->ldclk); |
773 | jzfb->is_enabled = 1; |
774 | |
775 | writel(JZ_LCD_CFG_SLCD, jzfb->base + JZ_REG_LCD_CFG); |
776 | writeb(0, jzfb->base + JZ_REG_SLCD_CTRL); |
777 | |
778 | jzfb_set_par(fb); |
779 | |
780 | jz_gpio_bulk_request(jz_slcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
781 | if (jzfb->pdata->lcd_type & (1 << 6)) { |
782 | /* serial */ |
783 | jz_gpio_bulk_request(&jz_slcd_data_pins[15], 1); |
784 | } else { |
785 | /* parallel */ |
786 | jz_gpio_bulk_request(jz_slcd_data_pins, |
787 | jzfb_num_data_pins(jzfb)); |
788 | } |
789 | |
790 | jzfb->panel = jz_slcd_panels_probe(jzfb); |
791 | if (!jzfb->panel) { |
792 | dev_err(&pdev->dev, "Failed to find panel driver\n"); |
793 | ret = -ENOENT; |
794 | goto err_free_devmem; |
795 | } |
796 | jzfb_disable_dma(jzfb); |
797 | jzfb->panel->init(jzfb); |
798 | jzfb->panel->enable(jzfb); |
799 | |
800 | ret = register_framebuffer(fb); |
801 | if (ret) { |
802 | dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret); |
803 | goto err_free_panel; |
804 | } |
805 | |
806 | jzfb->fb = fb; |
807 | |
808 | INIT_DELAYED_WORK(&jzfb->refresh_work, jzfb_refresh_work); |
809 | schedule_delayed_work(&jzfb->refresh_work, 0); |
810 | |
811 | return 0; |
812 | |
813 | err_free_panel: |
814 | jzfb->panel->exit(jzfb); |
815 | err_free_devmem: |
816 | jzfb_free_gpio_pins(jzfb); |
817 | |
818 | fb_dealloc_cmap(&fb->cmap); |
819 | jzfb_free_devmem(jzfb); |
820 | err_iounmap: |
821 | iounmap(jzfb->base); |
822 | err_put_lpclk: |
823 | clk_put(jzfb->lpclk); |
824 | err_put_ldclk: |
825 | clk_put(jzfb->ldclk); |
826 | err_free_dma: |
827 | jz4740_dma_free(jzfb->dma); |
828 | err_framebuffer_release: |
829 | framebuffer_release(fb); |
830 | err_release_mem_region: |
831 | release_mem_region(mem->start, resource_size(mem)); |
832 | return ret; |
833 | } |
834 | |
835 | static int __devexit jzfb_remove(struct platform_device *pdev) |
836 | { |
837 | struct jzfb *jzfb = platform_get_drvdata(pdev); |
838 | |
839 | jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb); |
840 | |
841 | /* Blanking will prevent future refreshes from behind scheduled. |
842 | Now wait for a possible refresh in progress to finish. */ |
843 | cancel_delayed_work_sync(&jzfb->refresh_work); |
844 | |
845 | jzfb->panel->exit(jzfb); |
846 | |
847 | jzfb_free_gpio_pins(jzfb); |
848 | |
849 | jz4740_dma_free(jzfb->dma); |
850 | |
851 | iounmap(jzfb->base); |
852 | release_mem_region(jzfb->mem->start, resource_size(jzfb->mem)); |
853 | |
854 | fb_dealloc_cmap(&jzfb->fb->cmap); |
855 | jzfb_free_devmem(jzfb); |
856 | |
857 | platform_set_drvdata(pdev, NULL); |
858 | |
859 | clk_put(jzfb->lpclk); |
860 | clk_put(jzfb->ldclk); |
861 | |
862 | framebuffer_release(jzfb->fb); |
863 | |
864 | return 0; |
865 | } |
866 | |
867 | #ifdef CONFIG_PM |
868 | |
869 | static int jzfb_suspend(struct device *dev) |
870 | { |
871 | struct jzfb *jzfb = dev_get_drvdata(dev); |
872 | |
873 | console_lock(); |
874 | fb_set_suspend(jzfb->fb, 1); |
875 | console_unlock(); |
876 | |
877 | mutex_lock(&jzfb->lock); |
878 | if (jzfb->is_enabled) |
879 | jzfb_disable(jzfb); |
880 | mutex_unlock(&jzfb->lock); |
881 | |
882 | return 0; |
883 | } |
884 | |
885 | static int jzfb_resume(struct device *dev) |
886 | { |
887 | struct jzfb *jzfb = dev_get_drvdata(dev); |
888 | clk_enable(jzfb->ldclk); |
889 | |
890 | mutex_lock(&jzfb->lock); |
891 | if (jzfb->is_enabled) |
892 | jzfb_enable(jzfb); |
893 | mutex_unlock(&jzfb->lock); |
894 | |
895 | console_lock(); |
896 | fb_set_suspend(jzfb->fb, 0); |
897 | console_unlock(); |
898 | |
899 | return 0; |
900 | } |
901 | |
902 | static const struct dev_pm_ops jzfb_pm_ops = { |
903 | .suspend = jzfb_suspend, |
904 | .resume = jzfb_resume, |
905 | .poweroff = jzfb_suspend, |
906 | .restore = jzfb_resume, |
907 | }; |
908 | |
909 | #define JZFB_PM_OPS (&jzfb_pm_ops) |
910 | |
911 | #else |
912 | #define JZFB_PM_OPS NULL |
913 | #endif |
914 | |
915 | static struct platform_driver jzfb_driver = { |
916 | .probe = jzfb_probe, |
917 | .remove = __devexit_p(jzfb_remove), |
918 | .driver = { |
919 | .name = "jz4740-fb", |
920 | .pm = JZFB_PM_OPS, |
921 | }, |
922 | }; |
923 | |
924 | static int __init jzfb_init(void) |
925 | { |
926 | return platform_driver_register(&jzfb_driver); |
927 | } |
928 | module_init(jzfb_init); |
929 | |
930 | static void __exit jzfb_exit(void) |
931 | { |
932 | platform_driver_unregister(&jzfb_driver); |
933 | } |
934 | module_exit(jzfb_exit); |
935 | |
936 | MODULE_LICENSE("GPL"); |
937 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>, Maarten ter Huurne <maarten@treewalker.org>"); |
938 | MODULE_DESCRIPTION("JZ4740 SoC SLCD framebuffer driver"); |
939 | MODULE_ALIAS("platform:jz4740-fb"); |
940 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9