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Source at commit eb7e867e25b365fc7e5214607b58c3c800bc93f7 created 13 years 11 months ago. By Lars-Peter Clausen, Add jz4740 udc driver | |
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1 | /* |
2 | * linux/drivers/usb/gadget/jz4740_udc.c |
3 | * |
4 | * Ingenic JZ4740 on-chip high speed USB device controller |
5 | * |
6 | * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc. |
7 | * Author: <jlwei@ingenic.cn> |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or |
12 | * (at your option) any later version. |
13 | */ |
14 | |
15 | /* |
16 | * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint. |
17 | * |
18 | * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk. |
19 | * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints. |
20 | */ |
21 | |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> |
24 | #include <linux/platform_device.h> |
25 | #include <linux/delay.h> |
26 | #include <linux/ioport.h> |
27 | #include <linux/slab.h> |
28 | #include <linux/errno.h> |
29 | #include <linux/init.h> |
30 | #include <linux/list.h> |
31 | #include <linux/interrupt.h> |
32 | #include <linux/proc_fs.h> |
33 | #include <linux/usb.h> |
34 | #include <linux/usb/gadget.h> |
35 | #include <linux/clk.h> |
36 | |
37 | #include <asm/byteorder.h> |
38 | #include <asm/io.h> |
39 | #include <asm/irq.h> |
40 | #include <asm/mach-jz4740/clock.h> |
41 | |
42 | #include "jz4740_udc.h" |
43 | |
44 | #define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */ |
45 | #define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */ |
46 | #define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */ |
47 | #define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */ |
48 | #define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */ |
49 | #define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */ |
50 | #define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */ |
51 | #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */ |
52 | #define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */ |
53 | #define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */ |
54 | #define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */ |
55 | |
56 | #define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */ |
57 | #define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */ |
58 | #define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */ |
59 | #define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */ |
60 | |
61 | #define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */ |
62 | #define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */ |
63 | #define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */ |
64 | #define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */ |
65 | |
66 | #define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20) |
67 | |
68 | #define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */ |
69 | #define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */ |
70 | |
71 | #define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */ |
72 | #define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */ |
73 | #define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */ |
74 | #define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */ |
75 | #define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */ |
76 | #define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */ |
77 | #define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */ |
78 | |
79 | /* Power register bit masks */ |
80 | #define USB_POWER_SUSPENDM 0x01 |
81 | #define USB_POWER_RESUME 0x04 |
82 | #define USB_POWER_HSMODE 0x10 |
83 | #define USB_POWER_HSENAB 0x20 |
84 | #define USB_POWER_SOFTCONN 0x40 |
85 | |
86 | /* Interrupt register bit masks */ |
87 | #define USB_INTR_SUSPEND 0x01 |
88 | #define USB_INTR_RESUME 0x02 |
89 | #define USB_INTR_RESET 0x04 |
90 | |
91 | #define USB_INTR_EP0 0x0001 |
92 | #define USB_INTR_INEP1 0x0002 |
93 | #define USB_INTR_INEP2 0x0004 |
94 | #define USB_INTR_OUTEP1 0x0002 |
95 | |
96 | /* CSR0 bit masks */ |
97 | #define USB_CSR0_OUTPKTRDY 0x01 |
98 | #define USB_CSR0_INPKTRDY 0x02 |
99 | #define USB_CSR0_SENTSTALL 0x04 |
100 | #define USB_CSR0_DATAEND 0x08 |
101 | #define USB_CSR0_SETUPEND 0x10 |
102 | #define USB_CSR0_SENDSTALL 0x20 |
103 | #define USB_CSR0_SVDOUTPKTRDY 0x40 |
104 | #define USB_CSR0_SVDSETUPEND 0x80 |
105 | |
106 | /* Endpoint CSR register bits */ |
107 | #define USB_INCSRH_AUTOSET 0x80 |
108 | #define USB_INCSRH_ISO 0x40 |
109 | #define USB_INCSRH_MODE 0x20 |
110 | #define USB_INCSRH_DMAREQENAB 0x10 |
111 | #define USB_INCSRH_DMAREQMODE 0x04 |
112 | #define USB_INCSR_CDT 0x40 |
113 | #define USB_INCSR_SENTSTALL 0x20 |
114 | #define USB_INCSR_SENDSTALL 0x10 |
115 | #define USB_INCSR_FF 0x08 |
116 | #define USB_INCSR_UNDERRUN 0x04 |
117 | #define USB_INCSR_FFNOTEMPT 0x02 |
118 | #define USB_INCSR_INPKTRDY 0x01 |
119 | |
120 | #define USB_OUTCSRH_AUTOCLR 0x80 |
121 | #define USB_OUTCSRH_ISO 0x40 |
122 | #define USB_OUTCSRH_DMAREQENAB 0x20 |
123 | #define USB_OUTCSRH_DNYT 0x10 |
124 | #define USB_OUTCSRH_DMAREQMODE 0x08 |
125 | #define USB_OUTCSR_CDT 0x80 |
126 | #define USB_OUTCSR_SENTSTALL 0x40 |
127 | #define USB_OUTCSR_SENDSTALL 0x20 |
128 | #define USB_OUTCSR_FF 0x10 |
129 | #define USB_OUTCSR_DATAERR 0x08 |
130 | #define USB_OUTCSR_OVERRUN 0x04 |
131 | #define USB_OUTCSR_FFFULL 0x02 |
132 | #define USB_OUTCSR_OUTPKTRDY 0x01 |
133 | |
134 | /* DMA control bits */ |
135 | #define USB_CNTL_ENA 0x01 |
136 | #define USB_CNTL_DIR_IN 0x02 |
137 | #define USB_CNTL_MODE_1 0x04 |
138 | #define USB_CNTL_INTR_EN 0x08 |
139 | #define USB_CNTL_EP(n) ((n) << 4) |
140 | #define USB_CNTL_BURST_0 (0 << 9) |
141 | #define USB_CNTL_BURST_4 (1 << 9) |
142 | #define USB_CNTL_BURST_8 (2 << 9) |
143 | #define USB_CNTL_BURST_16 (3 << 9) |
144 | |
145 | |
146 | #ifndef DEBUG |
147 | # define DEBUG(fmt,args...) do {} while(0) |
148 | #endif |
149 | #ifndef DEBUG_EP0 |
150 | # define NO_STATES |
151 | # define DEBUG_EP0(fmt,args...) do {} while(0) |
152 | #endif |
153 | #ifndef DEBUG_SETUP |
154 | # define DEBUG_SETUP(fmt,args...) do {} while(0) |
155 | #endif |
156 | |
157 | static struct jz4740_udc jz4740_udc_controller; |
158 | |
159 | /* |
160 | * Local declarations. |
161 | */ |
162 | static int jz4740_udc_start(struct usb_gadget_driver *driver, |
163 | int (*bind)(struct usb_gadget *)); |
164 | static int jz4740_udc_stop(struct usb_gadget_driver *driver); |
165 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep); |
166 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr); |
167 | |
168 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, |
169 | int status); |
170 | static void pio_irq_enable(struct jz4740_ep *ep); |
171 | static void pio_irq_disable(struct jz4740_ep *ep); |
172 | static void stop_activity(struct jz4740_udc *dev, |
173 | struct usb_gadget_driver *driver); |
174 | static void nuke(struct jz4740_ep *ep, int status); |
175 | static void flush(struct jz4740_ep *ep); |
176 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address); |
177 | |
178 | /*-------------------------------------------------------------------------*/ |
179 | |
180 | /* inline functions of register read/write/set/clear */ |
181 | |
182 | static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg) |
183 | { |
184 | return readb(udc->base + reg); |
185 | } |
186 | |
187 | static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg) |
188 | { |
189 | return readw(udc->base + reg); |
190 | } |
191 | |
192 | static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg) |
193 | { |
194 | return readl(udc->base + reg); |
195 | } |
196 | |
197 | static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val) |
198 | { |
199 | writeb(val, udc->base + reg); |
200 | } |
201 | |
202 | static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val) |
203 | { |
204 | writew(val, udc->base + reg); |
205 | } |
206 | |
207 | static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val) |
208 | { |
209 | writel(val, udc->base + reg); |
210 | } |
211 | |
212 | static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
213 | { |
214 | usb_writeb(udc, reg, usb_readb(udc, reg) | mask); |
215 | } |
216 | |
217 | static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
218 | { |
219 | usb_writew(udc, reg, usb_readw(udc, reg) | mask); |
220 | } |
221 | |
222 | static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
223 | { |
224 | usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask); |
225 | } |
226 | |
227 | static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
228 | { |
229 | usb_writew(udc, reg, usb_readw(udc, reg) & ~mask); |
230 | } |
231 | |
232 | /*-------------------------------------------------------------------------*/ |
233 | |
234 | static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index) |
235 | { |
236 | usb_writeb(udc, JZ_REG_UDC_INDEX, index); |
237 | } |
238 | |
239 | static inline void jz_udc_select_ep(struct jz4740_ep *ep) |
240 | { |
241 | jz_udc_set_index(ep->dev, ep_index(ep)); |
242 | } |
243 | |
244 | static inline int write_packet(struct jz4740_ep *ep, |
245 | struct jz4740_request *req, unsigned int count) |
246 | { |
247 | uint8_t *buf; |
248 | unsigned int length; |
249 | void __iomem *fifo = ep->dev->base + ep->fifo; |
250 | |
251 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
252 | |
253 | buf = req->req.buf + req->req.actual; |
254 | |
255 | length = req->req.length - req->req.actual; |
256 | if (length > count) |
257 | length = count; |
258 | req->req.actual += length; |
259 | |
260 | DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo); |
261 | |
262 | writesl(fifo, buf, length >> 2); |
263 | writesb(fifo, &buf[length - (length & 3)], length & 3); |
264 | |
265 | return length; |
266 | } |
267 | |
268 | static int read_packet(struct jz4740_ep *ep, |
269 | struct jz4740_request *req, unsigned int count) |
270 | { |
271 | uint8_t *buf; |
272 | unsigned int length; |
273 | void __iomem *fifo = ep->dev->base + ep->fifo; |
274 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
275 | |
276 | buf = req->req.buf + req->req.actual; |
277 | |
278 | length = req->req.length - req->req.actual; |
279 | if (length > count) |
280 | length = count; |
281 | req->req.actual += length; |
282 | |
283 | DEBUG("Read %d, fifo %x\n", length, ep->fifo); |
284 | |
285 | readsl(fifo, buf, length >> 2); |
286 | readsb(fifo, &buf[length - (length & 3)], length & 3); |
287 | |
288 | return length; |
289 | } |
290 | |
291 | /*-------------------------------------------------------------------------*/ |
292 | |
293 | /* |
294 | * udc_disable - disable USB device controller |
295 | */ |
296 | static void udc_disable(struct jz4740_udc *dev) |
297 | { |
298 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
299 | |
300 | udc_set_address(dev, 0); |
301 | |
302 | /* Disable interrupts */ |
303 | usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
304 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
305 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0); |
306 | |
307 | /* Disable DMA */ |
308 | usb_writel(dev, JZ_REG_UDC_CNTL1, 0); |
309 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
310 | |
311 | /* Disconnect from usb */ |
312 | usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
313 | |
314 | /* Disable the USB PHY */ |
315 | clk_disable(dev->clk); |
316 | |
317 | dev->ep0state = WAIT_FOR_SETUP; |
318 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
319 | |
320 | return; |
321 | } |
322 | |
323 | /* |
324 | * udc_reinit - initialize software state |
325 | */ |
326 | static void udc_reinit(struct jz4740_udc *dev) |
327 | { |
328 | int i; |
329 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
330 | |
331 | /* device/ep0 records init */ |
332 | INIT_LIST_HEAD(&dev->gadget.ep_list); |
333 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); |
334 | dev->ep0state = WAIT_FOR_SETUP; |
335 | |
336 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
337 | struct jz4740_ep *ep = &dev->ep[i]; |
338 | |
339 | if (i != 0) |
340 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); |
341 | |
342 | INIT_LIST_HEAD(&ep->queue); |
343 | ep->desc = 0; |
344 | ep->stopped = 0; |
345 | } |
346 | } |
347 | |
348 | /* until it's enabled, this UDC should be completely invisible |
349 | * to any USB host. |
350 | */ |
351 | static void udc_enable(struct jz4740_udc *dev) |
352 | { |
353 | int i; |
354 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
355 | |
356 | /* UDC state is incorrect - Added by River */ |
357 | if (dev->state != UDC_STATE_ENABLE) { |
358 | return; |
359 | } |
360 | |
361 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
362 | |
363 | /* Flush FIFO for each */ |
364 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
365 | struct jz4740_ep *ep = &dev->ep[i]; |
366 | |
367 | jz_udc_select_ep(ep); |
368 | flush(ep); |
369 | } |
370 | |
371 | /* Set this bit to allow the UDC entering low-power mode when |
372 | * there are no actions on the USB bus. |
373 | * UDC still works during this bit was set. |
374 | */ |
375 | jz4740_clock_udc_enable_auto_suspend(); |
376 | |
377 | /* Enable the USB PHY */ |
378 | clk_enable(dev->clk); |
379 | |
380 | /* Disable interrupts */ |
381 | /* usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
382 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
383 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/ |
384 | |
385 | /* Enable interrupts */ |
386 | usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0); |
387 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET); |
388 | /* Don't enable rest of the interrupts */ |
389 | /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2); |
390 | usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */ |
391 | |
392 | /* Enable SUSPEND */ |
393 | /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */ |
394 | |
395 | /* Enable HS Mode */ |
396 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB); |
397 | |
398 | /* Let host detect UDC: |
399 | * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this |
400 | * transistor on and pull the USBDP pin HIGH. |
401 | */ |
402 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
403 | |
404 | return; |
405 | } |
406 | |
407 | /*-------------------------------------------------------------------------*/ |
408 | |
409 | /* keeping it simple: |
410 | * - one bus driver, initted first; |
411 | * - one function driver, initted second |
412 | */ |
413 | |
414 | /* |
415 | * Register entry point for the peripheral controller driver. |
416 | */ |
417 | |
418 | static int jz4740_udc_start(struct usb_gadget_driver *driver, |
419 | int (*bind)(struct usb_gadget *)) |
420 | { |
421 | struct jz4740_udc *dev = &jz4740_udc_controller; |
422 | int retval; |
423 | |
424 | if (!driver || !bind) |
425 | return -EINVAL; |
426 | |
427 | if (!dev) |
428 | return -ENODEV; |
429 | |
430 | if (dev->driver) |
431 | return -EBUSY; |
432 | |
433 | /* hook up the driver */ |
434 | dev->driver = driver; |
435 | dev->gadget.dev.driver = &driver->driver; |
436 | |
437 | retval = bind(&dev->gadget); |
438 | if (retval) { |
439 | DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name, |
440 | driver->driver.name, retval); |
441 | dev->driver = 0; |
442 | return retval; |
443 | } |
444 | |
445 | /* then enable host detection and ep0; and we're ready |
446 | * for set_configuration as well as eventual disconnect. |
447 | */ |
448 | udc_enable(dev); |
449 | |
450 | DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name, |
451 | driver->driver.name); |
452 | |
453 | return 0; |
454 | } |
455 | |
456 | static void stop_activity(struct jz4740_udc *dev, |
457 | struct usb_gadget_driver *driver) |
458 | { |
459 | int i; |
460 | |
461 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
462 | |
463 | /* don't disconnect drivers more than once */ |
464 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) |
465 | driver = 0; |
466 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
467 | |
468 | /* prevent new request submissions, kill any outstanding requests */ |
469 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
470 | struct jz4740_ep *ep = &dev->ep[i]; |
471 | |
472 | ep->stopped = 1; |
473 | |
474 | jz_udc_select_ep(ep); |
475 | nuke(ep, -ESHUTDOWN); |
476 | } |
477 | |
478 | /* report disconnect; the driver is already quiesced */ |
479 | if (driver) { |
480 | spin_unlock(&dev->lock); |
481 | driver->disconnect(&dev->gadget); |
482 | spin_lock(&dev->lock); |
483 | } |
484 | |
485 | /* re-init driver-visible data structures */ |
486 | udc_reinit(dev); |
487 | } |
488 | |
489 | |
490 | /* |
491 | * Unregister entry point for the peripheral controller driver. |
492 | */ |
493 | static int jz4740_udc_stop(struct usb_gadget_driver *driver) |
494 | { |
495 | struct jz4740_udc *dev = &jz4740_udc_controller; |
496 | unsigned long flags; |
497 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
498 | |
499 | if (!dev) |
500 | return -ENODEV; |
501 | if (!driver || driver != dev->driver) |
502 | return -EINVAL; |
503 | if (!driver->unbind) |
504 | return -EBUSY; |
505 | |
506 | spin_lock_irqsave(&dev->lock, flags); |
507 | dev->driver = 0; |
508 | stop_activity(dev, driver); |
509 | spin_unlock_irqrestore(&dev->lock, flags); |
510 | |
511 | driver->unbind(&dev->gadget); |
512 | |
513 | udc_disable(dev); |
514 | |
515 | DEBUG("unregistered driver '%s'\n", driver->driver.name); |
516 | |
517 | return 0; |
518 | } |
519 | |
520 | /*-------------------------------------------------------------------------*/ |
521 | |
522 | /** Write request to FIFO (max write == maxp size) |
523 | * Return: 0 = still running, 1 = completed, negative = errno |
524 | * NOTE: INDEX register must be set for EP |
525 | */ |
526 | static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
527 | { |
528 | struct jz4740_udc *dev = ep->dev; |
529 | uint32_t max, csr; |
530 | |
531 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
532 | max = le16_to_cpu(ep->desc->wMaxPacketSize); |
533 | |
534 | csr = usb_readb(dev, ep->csr); |
535 | |
536 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
537 | unsigned count; |
538 | int is_last, is_short; |
539 | |
540 | count = write_packet(ep, req, max); |
541 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
542 | |
543 | /* last packet is usually short (or a zlp) */ |
544 | if (unlikely(count != max)) |
545 | is_last = is_short = 1; |
546 | else { |
547 | if (likely(req->req.length != req->req.actual) |
548 | || req->req.zero) |
549 | is_last = 0; |
550 | else |
551 | is_last = 1; |
552 | /* interrupt/iso maxpacket may not fill the fifo */ |
553 | is_short = unlikely(max < ep_maxpacket(ep)); |
554 | } |
555 | |
556 | DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__, |
557 | ep->ep.name, count, |
558 | is_last ? "/L" : "", is_short ? "/S" : "", |
559 | req->req.length - req->req.actual, req); |
560 | |
561 | /* requests complete when all IN data is in the FIFO */ |
562 | if (is_last) { |
563 | done(ep, req, 0); |
564 | if (list_empty(&ep->queue)) { |
565 | pio_irq_disable(ep); |
566 | } |
567 | return 1; |
568 | } |
569 | } else { |
570 | DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep)); |
571 | } |
572 | |
573 | return 0; |
574 | } |
575 | |
576 | /** Read to request from FIFO (max read == bytes in fifo) |
577 | * Return: 0 = still running, 1 = completed, negative = errno |
578 | * NOTE: INDEX register must be set for EP |
579 | */ |
580 | static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
581 | { |
582 | struct jz4740_udc *dev = ep->dev; |
583 | uint32_t csr; |
584 | unsigned count, is_short; |
585 | |
586 | /* make sure there's a packet in the FIFO. */ |
587 | csr = usb_readb(dev, ep->csr); |
588 | if (!(csr & USB_OUTCSR_OUTPKTRDY)) { |
589 | DEBUG("%s: Packet NOT ready!\n", __FUNCTION__); |
590 | return -EINVAL; |
591 | } |
592 | |
593 | /* read all bytes from this packet */ |
594 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
595 | |
596 | is_short = (count < ep->ep.maxpacket); |
597 | |
598 | count = read_packet(ep, req, count); |
599 | |
600 | DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n", |
601 | ep->ep.name, csr, count, |
602 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
603 | |
604 | /* Clear OutPktRdy */ |
605 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
606 | |
607 | /* completion */ |
608 | if (is_short || req->req.actual == req->req.length) { |
609 | done(ep, req, 0); |
610 | |
611 | if (list_empty(&ep->queue)) |
612 | pio_irq_disable(ep); |
613 | return 1; |
614 | } |
615 | |
616 | /* finished that packet. the next one may be waiting... */ |
617 | return 0; |
618 | } |
619 | |
620 | /* |
621 | * done - retire a request; caller blocked irqs |
622 | * INDEX register is preserved to keep same |
623 | */ |
624 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status) |
625 | { |
626 | unsigned int stopped = ep->stopped; |
627 | uint32_t index; |
628 | |
629 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
630 | list_del_init(&req->queue); |
631 | |
632 | if (likely(req->req.status == -EINPROGRESS)) |
633 | req->req.status = status; |
634 | else |
635 | status = req->req.status; |
636 | |
637 | if (status && status != -ESHUTDOWN) |
638 | DEBUG("complete %s req %p stat %d len %u/%u\n", |
639 | ep->ep.name, &req->req, status, |
640 | req->req.actual, req->req.length); |
641 | |
642 | /* don't modify queue heads during completion callback */ |
643 | ep->stopped = 1; |
644 | /* Read current index (completion may modify it) */ |
645 | index = usb_readb(ep->dev, JZ_REG_UDC_INDEX); |
646 | spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags); |
647 | |
648 | req->req.complete(&ep->ep, &req->req); |
649 | |
650 | spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags); |
651 | /* Restore index */ |
652 | jz_udc_set_index(ep->dev, index); |
653 | ep->stopped = stopped; |
654 | } |
655 | |
656 | static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep) |
657 | { |
658 | if (ep_is_in(ep)) |
659 | return JZ_REG_UDC_INTRINE; |
660 | else |
661 | return JZ_REG_UDC_INTROUTE; |
662 | } |
663 | |
664 | /** Enable EP interrupt */ |
665 | static void pio_irq_enable(struct jz4740_ep *ep) |
666 | { |
667 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
668 | |
669 | usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep))); |
670 | } |
671 | |
672 | /** Disable EP interrupt */ |
673 | static void pio_irq_disable(struct jz4740_ep *ep) |
674 | { |
675 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
676 | |
677 | usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep))); |
678 | } |
679 | |
680 | /* |
681 | * nuke - dequeue ALL requests |
682 | */ |
683 | static void nuke(struct jz4740_ep *ep, int status) |
684 | { |
685 | struct jz4740_request *req; |
686 | |
687 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
688 | |
689 | /* Flush FIFO */ |
690 | flush(ep); |
691 | |
692 | /* called with irqs blocked */ |
693 | while (!list_empty(&ep->queue)) { |
694 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
695 | done(ep, req, status); |
696 | } |
697 | |
698 | /* Disable IRQ if EP is enabled (has descriptor) */ |
699 | if (ep->desc) |
700 | pio_irq_disable(ep); |
701 | } |
702 | |
703 | /** Flush EP FIFO |
704 | * NOTE: INDEX register must be set before this call |
705 | */ |
706 | static void flush(struct jz4740_ep *ep) |
707 | { |
708 | DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name); |
709 | |
710 | switch (ep->type) { |
711 | case ep_bulk_in: |
712 | case ep_interrupt: |
713 | usb_setb(ep->dev, ep->csr, USB_INCSR_FF); |
714 | break; |
715 | case ep_bulk_out: |
716 | usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF); |
717 | break; |
718 | case ep_control: |
719 | break; |
720 | } |
721 | } |
722 | |
723 | /** |
724 | * jz4740_in_epn - handle IN interrupt |
725 | */ |
726 | static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
727 | { |
728 | uint32_t csr; |
729 | struct jz4740_ep *ep = &dev->ep[ep_idx + 1]; |
730 | struct jz4740_request *req; |
731 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
732 | |
733 | jz_udc_select_ep(ep); |
734 | |
735 | csr = usb_readb(dev, ep->csr); |
736 | DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr); |
737 | |
738 | if (csr & USB_INCSR_SENTSTALL) { |
739 | DEBUG("USB_INCSR_SENTSTALL\n"); |
740 | usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL); |
741 | return; |
742 | } |
743 | |
744 | if (!ep->desc) { |
745 | DEBUG("%s: NO EP DESC\n", __FUNCTION__); |
746 | return; |
747 | } |
748 | |
749 | if (!list_empty(&ep->queue)) { |
750 | req = list_first_entry(&ep->queue, struct jz4740_request, queue); |
751 | write_fifo(ep, req); |
752 | } |
753 | } |
754 | |
755 | /* |
756 | * Bulk OUT (recv) |
757 | */ |
758 | static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
759 | { |
760 | struct jz4740_ep *ep = &dev->ep[ep_idx]; |
761 | struct jz4740_request *req; |
762 | |
763 | DEBUG("%s: %d\n", __FUNCTION__, ep_idx); |
764 | |
765 | jz_udc_select_ep(ep); |
766 | if (ep->desc) { |
767 | uint32_t csr; |
768 | |
769 | while ((csr = usb_readb(dev, ep->csr)) & |
770 | (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) { |
771 | DEBUG("%s: %x\n", __FUNCTION__, csr); |
772 | |
773 | if (csr & USB_OUTCSR_SENTSTALL) { |
774 | DEBUG("%s: stall sent, flush fifo\n", |
775 | __FUNCTION__); |
776 | /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */ |
777 | flush(ep); |
778 | } else if (csr & USB_OUTCSR_OUTPKTRDY) { |
779 | if (list_empty(&ep->queue)) |
780 | req = 0; |
781 | else |
782 | req = |
783 | list_entry(ep->queue.next, |
784 | struct jz4740_request, |
785 | queue); |
786 | |
787 | if (!req) { |
788 | DEBUG("%s: NULL REQ %d\n", |
789 | __FUNCTION__, ep_idx); |
790 | break; |
791 | } else { |
792 | read_fifo(ep, req); |
793 | } |
794 | } |
795 | } |
796 | } else { |
797 | /* Throw packet away.. */ |
798 | DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx); |
799 | flush(ep); |
800 | } |
801 | } |
802 | |
803 | /** Halt specific EP |
804 | * Return 0 if success |
805 | * NOTE: Sets INDEX register to EP ! |
806 | */ |
807 | static int jz4740_set_halt(struct usb_ep *_ep, int value) |
808 | { |
809 | struct jz4740_udc *dev; |
810 | struct jz4740_ep *ep; |
811 | unsigned long flags; |
812 | |
813 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
814 | |
815 | ep = container_of(_ep, struct jz4740_ep, ep); |
816 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
817 | DEBUG("%s, bad ep\n", __FUNCTION__); |
818 | return -EINVAL; |
819 | } |
820 | |
821 | dev = ep->dev; |
822 | |
823 | spin_lock_irqsave(&dev->lock, flags); |
824 | |
825 | jz_udc_select_ep(ep); |
826 | |
827 | DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value); |
828 | |
829 | if (ep_index(ep) == 0) { |
830 | /* EP0 */ |
831 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL); |
832 | } else if (ep_is_in(ep)) { |
833 | uint32_t csr = usb_readb(dev, ep->csr); |
834 | if (value && ((csr & USB_INCSR_FFNOTEMPT) |
835 | || !list_empty(&ep->queue))) { |
836 | /* |
837 | * Attempts to halt IN endpoints will fail (returning -EAGAIN) |
838 | * if any transfer requests are still queued, or if the controller |
839 | * FIFO still holds bytes that the host hasnÂ’t collected. |
840 | */ |
841 | spin_unlock_irqrestore(&dev->lock, flags); |
842 | DEBUG |
843 | ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n", |
844 | (csr & USB_INCSR_FFNOTEMPT), |
845 | !list_empty(&ep->queue)); |
846 | return -EAGAIN; |
847 | } |
848 | flush(ep); |
849 | if (value) { |
850 | usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL); |
851 | } else { |
852 | usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL); |
853 | usb_setb(dev, ep->csr, USB_INCSR_CDT); |
854 | } |
855 | } else { |
856 | |
857 | flush(ep); |
858 | if (value) { |
859 | usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
860 | } else { |
861 | usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
862 | usb_setb(dev, ep->csr, USB_OUTCSR_CDT); |
863 | } |
864 | } |
865 | |
866 | ep->stopped = value; |
867 | |
868 | spin_unlock_irqrestore(&dev->lock, flags); |
869 | |
870 | DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS"); |
871 | |
872 | return 0; |
873 | } |
874 | |
875 | |
876 | static int jz4740_ep_enable(struct usb_ep *_ep, |
877 | const struct usb_endpoint_descriptor *desc) |
878 | { |
879 | struct jz4740_ep *ep; |
880 | struct jz4740_udc *dev; |
881 | unsigned long flags; |
882 | uint32_t max, csrh = 0; |
883 | |
884 | DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name); |
885 | |
886 | if (!_ep || !desc) |
887 | return -EINVAL; |
888 | |
889 | ep = container_of(_ep, struct jz4740_ep, ep); |
890 | if (ep->desc || ep->type == ep_control |
891 | || desc->bDescriptorType != USB_DT_ENDPOINT |
892 | || ep->bEndpointAddress != desc->bEndpointAddress) { |
893 | DEBUG("%s, bad ep or descriptor\n", __FUNCTION__); |
894 | return -EINVAL; |
895 | } |
896 | |
897 | /* xfer types must match, except that interrupt ~= bulk */ |
898 | if (ep->bmAttributes != desc->bmAttributes |
899 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK |
900 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { |
901 | DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); |
902 | return -EINVAL; |
903 | } |
904 | |
905 | dev = ep->dev; |
906 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { |
907 | DEBUG("%s, bogus device state\n", __FUNCTION__); |
908 | return -ESHUTDOWN; |
909 | } |
910 | |
911 | max = le16_to_cpu(desc->wMaxPacketSize); |
912 | |
913 | spin_lock_irqsave(&ep->dev->lock, flags); |
914 | |
915 | /* Configure the endpoint */ |
916 | jz_udc_select_ep(ep); |
917 | if (ep_is_in(ep)) { |
918 | usb_writew(dev, JZ_REG_UDC_INMAXP, max); |
919 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
920 | case USB_ENDPOINT_XFER_BULK: |
921 | case USB_ENDPOINT_XFER_INT: |
922 | csrh &= ~USB_INCSRH_ISO; |
923 | break; |
924 | case USB_ENDPOINT_XFER_ISOC: |
925 | csrh |= USB_INCSRH_ISO; |
926 | break; |
927 | } |
928 | usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh); |
929 | } |
930 | else { |
931 | usb_writew(dev, JZ_REG_UDC_OUTMAXP, max); |
932 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
933 | case USB_ENDPOINT_XFER_BULK: |
934 | csrh &= ~USB_OUTCSRH_ISO; |
935 | break; |
936 | case USB_ENDPOINT_XFER_INT: |
937 | csrh &= ~USB_OUTCSRH_ISO; |
938 | csrh |= USB_OUTCSRH_DNYT; |
939 | break; |
940 | case USB_ENDPOINT_XFER_ISOC: |
941 | csrh |= USB_OUTCSRH_ISO; |
942 | break; |
943 | } |
944 | usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh); |
945 | } |
946 | |
947 | |
948 | ep->stopped = 0; |
949 | ep->desc = desc; |
950 | ep->ep.maxpacket = max; |
951 | |
952 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
953 | |
954 | /* Reset halt state (does flush) */ |
955 | jz4740_set_halt(_ep, 0); |
956 | |
957 | DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name); |
958 | |
959 | return 0; |
960 | } |
961 | |
962 | /** Disable EP |
963 | * NOTE: Sets INDEX register |
964 | */ |
965 | static int jz4740_ep_disable(struct usb_ep *_ep) |
966 | { |
967 | struct jz4740_ep *ep; |
968 | unsigned long flags; |
969 | |
970 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
971 | |
972 | ep = container_of(_ep, struct jz4740_ep, ep); |
973 | if (!_ep || !ep->desc) { |
974 | DEBUG("%s, %s not enabled\n", __FUNCTION__, |
975 | _ep ? ep->ep.name : NULL); |
976 | return -EINVAL; |
977 | } |
978 | |
979 | spin_lock_irqsave(&ep->dev->lock, flags); |
980 | |
981 | jz_udc_select_ep(ep); |
982 | |
983 | /* Nuke all pending requests (does flush) */ |
984 | nuke(ep, -ESHUTDOWN); |
985 | |
986 | /* Disable ep IRQ */ |
987 | pio_irq_disable(ep); |
988 | |
989 | ep->desc = 0; |
990 | ep->stopped = 1; |
991 | |
992 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
993 | |
994 | DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name); |
995 | return 0; |
996 | } |
997 | |
998 | static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
999 | { |
1000 | struct jz4740_request *req; |
1001 | |
1002 | req = kzalloc(sizeof(*req), gfp_flags); |
1003 | if (!req) |
1004 | return NULL; |
1005 | |
1006 | INIT_LIST_HEAD(&req->queue); |
1007 | |
1008 | return &req->req; |
1009 | } |
1010 | |
1011 | static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req) |
1012 | { |
1013 | struct jz4740_request *req; |
1014 | |
1015 | req = container_of(_req, struct jz4740_request, req); |
1016 | WARN_ON(!list_empty(&req->queue)); |
1017 | |
1018 | kfree(req); |
1019 | } |
1020 | |
1021 | /*--------------------------------------------------------------------*/ |
1022 | |
1023 | /** Queue one request |
1024 | * Kickstart transfer if needed |
1025 | * NOTE: Sets INDEX register |
1026 | */ |
1027 | static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req, |
1028 | gfp_t gfp_flags) |
1029 | { |
1030 | struct jz4740_request *req; |
1031 | struct jz4740_ep *ep; |
1032 | struct jz4740_udc *dev; |
1033 | |
1034 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1035 | |
1036 | req = container_of(_req, struct jz4740_request, req); |
1037 | if (unlikely |
1038 | (!_req || !_req->complete || !_req->buf |
1039 | || !list_empty(&req->queue))) { |
1040 | DEBUG("%s, bad params\n", __FUNCTION__); |
1041 | return -EINVAL; |
1042 | } |
1043 | |
1044 | ep = container_of(_ep, struct jz4740_ep, ep); |
1045 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
1046 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1047 | return -EINVAL; |
1048 | } |
1049 | |
1050 | dev = ep->dev; |
1051 | if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { |
1052 | DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver); |
1053 | return -ESHUTDOWN; |
1054 | } |
1055 | |
1056 | DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length, |
1057 | _req->buf); |
1058 | |
1059 | spin_lock_irqsave(&dev->lock, dev->lock_flags); |
1060 | |
1061 | _req->status = -EINPROGRESS; |
1062 | _req->actual = 0; |
1063 | |
1064 | /* kickstart this i/o queue? */ |
1065 | DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue), |
1066 | ep->stopped); |
1067 | if (list_empty(&ep->queue) && likely(!ep->stopped)) { |
1068 | uint32_t csr; |
1069 | |
1070 | if (unlikely(ep_index(ep) == 0)) { |
1071 | /* EP0 */ |
1072 | list_add_tail(&req->queue, &ep->queue); |
1073 | jz4740_ep0_kick(dev, ep); |
1074 | req = 0; |
1075 | } |
1076 | else if (ep_is_in(ep)) { |
1077 | /* EP1 & EP2 */ |
1078 | jz_udc_select_ep(ep); |
1079 | csr = usb_readb(dev, ep->csr); |
1080 | pio_irq_enable(ep); |
1081 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
1082 | if (write_fifo(ep, req) == 1) |
1083 | req = 0; |
1084 | } |
1085 | } else { |
1086 | /* EP1 */ |
1087 | jz_udc_select_ep(ep); |
1088 | csr = usb_readb(dev, ep->csr); |
1089 | pio_irq_enable(ep); |
1090 | if (csr & USB_OUTCSR_OUTPKTRDY) { |
1091 | if (read_fifo(ep, req) == 1) |
1092 | req = 0; |
1093 | } |
1094 | } |
1095 | } |
1096 | |
1097 | /* pio or dma irq handler advances the queue. */ |
1098 | if (likely(req != 0)) |
1099 | list_add_tail(&req->queue, &ep->queue); |
1100 | |
1101 | spin_unlock_irqrestore(&dev->lock, dev->lock_flags); |
1102 | |
1103 | return 0; |
1104 | } |
1105 | |
1106 | /* dequeue JUST ONE request */ |
1107 | static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
1108 | { |
1109 | struct jz4740_ep *ep; |
1110 | struct jz4740_request *req; |
1111 | unsigned long flags; |
1112 | |
1113 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1114 | |
1115 | ep = container_of(_ep, struct jz4740_ep, ep); |
1116 | if (!_ep || ep->type == ep_control) |
1117 | return -EINVAL; |
1118 | |
1119 | spin_lock_irqsave(&ep->dev->lock, flags); |
1120 | |
1121 | /* make sure it's actually queued on this endpoint */ |
1122 | list_for_each_entry(req, &ep->queue, queue) { |
1123 | if (&req->req == _req) |
1124 | break; |
1125 | } |
1126 | if (&req->req != _req) { |
1127 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1128 | return -EINVAL; |
1129 | } |
1130 | done(ep, req, -ECONNRESET); |
1131 | |
1132 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1133 | return 0; |
1134 | } |
1135 | |
1136 | /** Return bytes in EP FIFO |
1137 | * NOTE: Sets INDEX register to EP |
1138 | */ |
1139 | static int jz4740_fifo_status(struct usb_ep *_ep) |
1140 | { |
1141 | uint32_t csr; |
1142 | int count = 0; |
1143 | struct jz4740_ep *ep; |
1144 | unsigned long flags; |
1145 | |
1146 | ep = container_of(_ep, struct jz4740_ep, ep); |
1147 | if (!_ep) { |
1148 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1149 | return -ENODEV; |
1150 | } |
1151 | |
1152 | DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep)); |
1153 | |
1154 | /* LPD can't report unclaimed bytes from IN fifos */ |
1155 | if (ep_is_in(ep)) |
1156 | return -EOPNOTSUPP; |
1157 | |
1158 | spin_lock_irqsave(&ep->dev->lock, flags); |
1159 | jz_udc_select_ep(ep); |
1160 | |
1161 | csr = usb_readb(ep->dev, ep->csr); |
1162 | if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN || |
1163 | csr & 0x1) { |
1164 | count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1165 | } |
1166 | |
1167 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1168 | |
1169 | return count; |
1170 | } |
1171 | |
1172 | /** Flush EP FIFO |
1173 | * NOTE: Sets INDEX register to EP |
1174 | */ |
1175 | static void jz4740_fifo_flush(struct usb_ep *_ep) |
1176 | { |
1177 | struct jz4740_ep *ep; |
1178 | unsigned long flags; |
1179 | |
1180 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1181 | |
1182 | ep = container_of(_ep, struct jz4740_ep, ep); |
1183 | if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) { |
1184 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1185 | return; |
1186 | } |
1187 | |
1188 | spin_lock_irqsave(&ep->dev->lock, flags); |
1189 | |
1190 | jz_udc_select_ep(ep); |
1191 | flush(ep); |
1192 | |
1193 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1194 | } |
1195 | |
1196 | /****************************************************************/ |
1197 | /* End Point 0 related functions */ |
1198 | /****************************************************************/ |
1199 | |
1200 | /* return: 0 = still running, 1 = completed, negative = errno */ |
1201 | static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1202 | { |
1203 | uint32_t max; |
1204 | unsigned count; |
1205 | int is_last; |
1206 | |
1207 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1208 | max = ep_maxpacket(ep); |
1209 | |
1210 | count = write_packet(ep, req, max); |
1211 | |
1212 | /* last packet is usually short (or a zlp) */ |
1213 | if (unlikely(count != max)) |
1214 | is_last = 1; |
1215 | else { |
1216 | if (likely(req->req.length != req->req.actual) || req->req.zero) |
1217 | is_last = 0; |
1218 | else |
1219 | is_last = 1; |
1220 | } |
1221 | |
1222 | DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__, |
1223 | ep->ep.name, count, |
1224 | is_last ? "/L" : "", req->req.length - req->req.actual, req); |
1225 | |
1226 | /* requests complete when all IN data is in the FIFO */ |
1227 | if (is_last) { |
1228 | done(ep, req, 0); |
1229 | return 1; |
1230 | } |
1231 | |
1232 | return 0; |
1233 | } |
1234 | |
1235 | static inline int jz4740_fifo_read(struct jz4740_ep *ep, |
1236 | unsigned char *cp, int max) |
1237 | { |
1238 | int bytes; |
1239 | int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1240 | |
1241 | if (count > max) |
1242 | count = max; |
1243 | bytes = count; |
1244 | while (count--) |
1245 | *cp++ = usb_readb(ep->dev, ep->fifo); |
1246 | |
1247 | return bytes; |
1248 | } |
1249 | |
1250 | static inline void jz4740_fifo_write(struct jz4740_ep *ep, |
1251 | unsigned char *cp, int count) |
1252 | { |
1253 | DEBUG("fifo_write: %d %d\n", ep_index(ep), count); |
1254 | while (count--) |
1255 | usb_writeb(ep->dev, ep->fifo, *cp++); |
1256 | } |
1257 | |
1258 | static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1259 | { |
1260 | struct jz4740_udc *dev = ep->dev; |
1261 | uint32_t csr; |
1262 | uint8_t *buf; |
1263 | unsigned bufferspace, count, is_short; |
1264 | |
1265 | DEBUG_EP0("%s\n", __FUNCTION__); |
1266 | |
1267 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1268 | if (!(csr & USB_CSR0_OUTPKTRDY)) |
1269 | return 0; |
1270 | |
1271 | buf = req->req.buf + req->req.actual; |
1272 | prefetchw(buf); |
1273 | bufferspace = req->req.length - req->req.actual; |
1274 | |
1275 | /* read all bytes from this packet */ |
1276 | if (likely(csr & USB_CSR0_OUTPKTRDY)) { |
1277 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
1278 | req->req.actual += min(count, bufferspace); |
1279 | } else /* zlp */ |
1280 | count = 0; |
1281 | |
1282 | is_short = (count < ep->ep.maxpacket); |
1283 | DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n", |
1284 | ep->ep.name, csr, count, |
1285 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
1286 | |
1287 | while (likely(count-- != 0)) { |
1288 | uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo); |
1289 | |
1290 | if (unlikely(bufferspace == 0)) { |
1291 | /* this happens when the driver's buffer |
1292 | * is smaller than what the host sent. |
1293 | * discard the extra data. |
1294 | */ |
1295 | if (req->req.status != -EOVERFLOW) |
1296 | DEBUG_EP0("%s overflow %d\n", ep->ep.name, |
1297 | count); |
1298 | req->req.status = -EOVERFLOW; |
1299 | } else { |
1300 | *buf++ = byte; |
1301 | bufferspace--; |
1302 | } |
1303 | } |
1304 | |
1305 | /* completion */ |
1306 | if (is_short || req->req.actual == req->req.length) { |
1307 | done(ep, req, 0); |
1308 | return 1; |
1309 | } |
1310 | |
1311 | /* finished that packet. the next one may be waiting... */ |
1312 | return 0; |
1313 | } |
1314 | |
1315 | /** |
1316 | * udc_set_address - set the USB address for this device |
1317 | * @address: |
1318 | * |
1319 | * Called from control endpoint function after it decodes a set address setup packet. |
1320 | */ |
1321 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address) |
1322 | { |
1323 | DEBUG_EP0("%s: %d\n", __FUNCTION__, address); |
1324 | |
1325 | usb_writeb(dev, JZ_REG_UDC_FADDR, address); |
1326 | } |
1327 | |
1328 | /* |
1329 | * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY) |
1330 | * - if error |
1331 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1332 | * - else |
1333 | * set USB_CSR0_SVDOUTPKTRDY bit |
1334 | if last set USB_CSR0_DATAEND bit |
1335 | */ |
1336 | static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart) |
1337 | { |
1338 | struct jz4740_request *req; |
1339 | struct jz4740_ep *ep = &dev->ep[0]; |
1340 | int ret; |
1341 | |
1342 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1343 | |
1344 | if (list_empty(&ep->queue)) |
1345 | req = 0; |
1346 | else |
1347 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1348 | |
1349 | if (req) { |
1350 | if (req->req.length == 0) { |
1351 | DEBUG_EP0("ZERO LENGTH OUT!\n"); |
1352 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1353 | dev->ep0state = WAIT_FOR_SETUP; |
1354 | return; |
1355 | } else if (kickstart) { |
1356 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY)); |
1357 | return; |
1358 | } |
1359 | ret = read_fifo_ep0(ep, req); |
1360 | if (ret) { |
1361 | /* Done! */ |
1362 | DEBUG_EP0("%s: finished, waiting for status\n", |
1363 | __FUNCTION__); |
1364 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1365 | dev->ep0state = WAIT_FOR_SETUP; |
1366 | } else { |
1367 | /* Not done yet.. */ |
1368 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1369 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1370 | } |
1371 | } else { |
1372 | DEBUG_EP0("NO REQ??!\n"); |
1373 | } |
1374 | } |
1375 | |
1376 | /* |
1377 | * DATA_STATE_XMIT |
1378 | */ |
1379 | static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr) |
1380 | { |
1381 | struct jz4740_request *req; |
1382 | struct jz4740_ep *ep = &dev->ep[0]; |
1383 | int ret, need_zlp = 0; |
1384 | |
1385 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1386 | |
1387 | if (list_empty(&ep->queue)) |
1388 | req = 0; |
1389 | else |
1390 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1391 | |
1392 | if (!req) { |
1393 | DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__); |
1394 | return 0; |
1395 | } |
1396 | |
1397 | if (req->req.length == 0) { |
1398 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1399 | dev->ep0state = WAIT_FOR_SETUP; |
1400 | return 1; |
1401 | } |
1402 | |
1403 | if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) { |
1404 | /* Next write will end with the packet size, */ |
1405 | /* so we need zero-length-packet */ |
1406 | need_zlp = 1; |
1407 | } |
1408 | |
1409 | ret = write_fifo_ep0(ep, req); |
1410 | |
1411 | if (ret == 1 && !need_zlp) { |
1412 | /* Last packet */ |
1413 | DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__); |
1414 | |
1415 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1416 | dev->ep0state = WAIT_FOR_SETUP; |
1417 | } else { |
1418 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1419 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1420 | } |
1421 | |
1422 | if (need_zlp) { |
1423 | DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__); |
1424 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1425 | dev->ep0state = DATA_STATE_NEED_ZLP; |
1426 | } |
1427 | |
1428 | return 1; |
1429 | } |
1430 | |
1431 | static int jz4740_handle_get_status(struct jz4740_udc *dev, |
1432 | struct usb_ctrlrequest *ctrl) |
1433 | { |
1434 | struct jz4740_ep *ep0 = &dev->ep[0]; |
1435 | struct jz4740_ep *qep; |
1436 | int reqtype = (ctrl->bRequestType & USB_RECIP_MASK); |
1437 | uint16_t val = 0; |
1438 | |
1439 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1440 | |
1441 | if (reqtype == USB_RECIP_INTERFACE) { |
1442 | /* This is not supported. |
1443 | * And according to the USB spec, this one does nothing.. |
1444 | * Just return 0 |
1445 | */ |
1446 | DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n"); |
1447 | } else if (reqtype == USB_RECIP_DEVICE) { |
1448 | DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n"); |
1449 | val |= (1 << 0); /* Self powered */ |
1450 | /*val |= (1<<1); *//* Remote wakeup */ |
1451 | } else if (reqtype == USB_RECIP_ENDPOINT) { |
1452 | int ep_num = (ctrl->wIndex & ~USB_DIR_IN); |
1453 | |
1454 | DEBUG_SETUP |
1455 | ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n", |
1456 | ep_num, ctrl->wLength); |
1457 | |
1458 | if (ctrl->wLength > 2 || ep_num > 3) |
1459 | return -EOPNOTSUPP; |
1460 | |
1461 | qep = &dev->ep[ep_num]; |
1462 | if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0) |
1463 | && ep_index(qep) != 0) { |
1464 | return -EOPNOTSUPP; |
1465 | } |
1466 | |
1467 | jz_udc_select_ep(qep); |
1468 | |
1469 | /* Return status on next IN token */ |
1470 | switch (qep->type) { |
1471 | case ep_control: |
1472 | val = |
1473 | (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) == |
1474 | USB_CSR0_SENDSTALL; |
1475 | break; |
1476 | case ep_bulk_in: |
1477 | case ep_interrupt: |
1478 | val = |
1479 | (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) == |
1480 | USB_INCSR_SENDSTALL; |
1481 | break; |
1482 | case ep_bulk_out: |
1483 | val = |
1484 | (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) == |
1485 | USB_OUTCSR_SENDSTALL; |
1486 | break; |
1487 | } |
1488 | |
1489 | /* Back to EP0 index */ |
1490 | jz_udc_set_index(dev, 0); |
1491 | |
1492 | DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num, |
1493 | ctrl->wIndex, val); |
1494 | } else { |
1495 | DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype); |
1496 | return -EOPNOTSUPP; |
1497 | } |
1498 | |
1499 | /* Clear "out packet ready" */ |
1500 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1501 | /* Put status to FIFO */ |
1502 | jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val)); |
1503 | /* Issue "In packet ready" */ |
1504 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1505 | |
1506 | return 0; |
1507 | } |
1508 | |
1509 | /* |
1510 | * WAIT_FOR_SETUP (OUTPKTRDY) |
1511 | * - read data packet from EP0 FIFO |
1512 | * - decode command |
1513 | * - if error |
1514 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1515 | * - else |
1516 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits |
1517 | */ |
1518 | static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr) |
1519 | { |
1520 | struct jz4740_ep *ep = &dev->ep[0]; |
1521 | struct usb_ctrlrequest ctrl; |
1522 | int i; |
1523 | |
1524 | DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr); |
1525 | |
1526 | /* Nuke all previous transfers */ |
1527 | nuke(ep, -EPROTO); |
1528 | |
1529 | /* read control req from fifo (8 bytes) */ |
1530 | jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8); |
1531 | |
1532 | DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n", |
1533 | ctrl.bRequestType, ctrl.bRequest, |
1534 | ctrl.wValue, ctrl.wIndex, ctrl.wLength); |
1535 | |
1536 | /* Set direction of EP0 */ |
1537 | if (likely(ctrl.bRequestType & USB_DIR_IN)) { |
1538 | ep->bEndpointAddress |= USB_DIR_IN; |
1539 | } else { |
1540 | ep->bEndpointAddress &= ~USB_DIR_IN; |
1541 | } |
1542 | |
1543 | /* Handle some SETUP packets ourselves */ |
1544 | switch (ctrl.bRequest) { |
1545 | case USB_REQ_SET_ADDRESS: |
1546 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1547 | break; |
1548 | |
1549 | DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue); |
1550 | udc_set_address(dev, ctrl.wValue); |
1551 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1552 | return; |
1553 | |
1554 | case USB_REQ_SET_CONFIGURATION: |
1555 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1556 | break; |
1557 | |
1558 | DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue); |
1559 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1560 | |
1561 | /* Enable RESUME and SUSPEND interrupts */ |
1562 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND)); |
1563 | break; |
1564 | |
1565 | case USB_REQ_SET_INTERFACE: |
1566 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1567 | break; |
1568 | |
1569 | DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue); |
1570 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1571 | break; |
1572 | |
1573 | case USB_REQ_GET_STATUS: |
1574 | if (jz4740_handle_get_status(dev, &ctrl) == 0) |
1575 | return; |
1576 | |
1577 | case USB_REQ_CLEAR_FEATURE: |
1578 | case USB_REQ_SET_FEATURE: |
1579 | if (ctrl.bRequestType == USB_RECIP_ENDPOINT) { |
1580 | struct jz4740_ep *qep; |
1581 | int ep_num = (ctrl.wIndex & 0x0f); |
1582 | |
1583 | /* Support only HALT feature */ |
1584 | if (ctrl.wValue != 0 || ctrl.wLength != 0 |
1585 | || ep_num > 3 || ep_num < 1) |
1586 | break; |
1587 | |
1588 | qep = &dev->ep[ep_num]; |
1589 | spin_unlock(&dev->lock); |
1590 | if (ctrl.bRequest == USB_REQ_SET_FEATURE) { |
1591 | DEBUG_SETUP("SET_FEATURE (%d)\n", |
1592 | ep_num); |
1593 | jz4740_set_halt(&qep->ep, 1); |
1594 | } else { |
1595 | DEBUG_SETUP("CLR_FEATURE (%d)\n", |
1596 | ep_num); |
1597 | jz4740_set_halt(&qep->ep, 0); |
1598 | } |
1599 | spin_lock(&dev->lock); |
1600 | |
1601 | jz_udc_set_index(dev, 0); |
1602 | |
1603 | /* Reply with a ZLP on next IN token */ |
1604 | usb_setb(dev, JZ_REG_UDC_CSR0, |
1605 | (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1606 | return; |
1607 | } |
1608 | break; |
1609 | |
1610 | default: |
1611 | break; |
1612 | } |
1613 | |
1614 | /* gadget drivers see class/vendor specific requests, |
1615 | * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, |
1616 | * and more. |
1617 | */ |
1618 | if (dev->driver) { |
1619 | /* device-2-host (IN) or no data setup command, process immediately */ |
1620 | spin_unlock(&dev->lock); |
1621 | |
1622 | i = dev->driver->setup(&dev->gadget, &ctrl); |
1623 | spin_lock(&dev->lock); |
1624 | |
1625 | if (unlikely(i < 0)) { |
1626 | /* setup processing failed, force stall */ |
1627 | DEBUG_SETUP |
1628 | (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n", |
1629 | i); |
1630 | jz_udc_set_index(dev, 0); |
1631 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL)); |
1632 | |
1633 | /* ep->stopped = 1; */ |
1634 | dev->ep0state = WAIT_FOR_SETUP; |
1635 | } |
1636 | else { |
1637 | DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength); |
1638 | /* if (!ctrl.wLength) { |
1639 | usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1640 | }*/ |
1641 | } |
1642 | } |
1643 | } |
1644 | |
1645 | /* |
1646 | * DATA_STATE_NEED_ZLP |
1647 | */ |
1648 | static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr) |
1649 | { |
1650 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1651 | |
1652 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1653 | dev->ep0state = WAIT_FOR_SETUP; |
1654 | } |
1655 | |
1656 | /* |
1657 | * handle ep0 interrupt |
1658 | */ |
1659 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr) |
1660 | { |
1661 | struct jz4740_ep *ep = &dev->ep[0]; |
1662 | uint32_t csr; |
1663 | |
1664 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1665 | /* Set index 0 */ |
1666 | jz_udc_set_index(dev, 0); |
1667 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1668 | |
1669 | DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]); |
1670 | |
1671 | /* |
1672 | * if SENT_STALL is set |
1673 | * - clear the SENT_STALL bit |
1674 | */ |
1675 | if (csr & USB_CSR0_SENTSTALL) { |
1676 | DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr); |
1677 | usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL); |
1678 | nuke(ep, -ECONNABORTED); |
1679 | dev->ep0state = WAIT_FOR_SETUP; |
1680 | return; |
1681 | } |
1682 | |
1683 | /* |
1684 | * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear |
1685 | * - fill EP0 FIFO |
1686 | * - if last packet |
1687 | * - set IN_PKT_RDY | DATA_END |
1688 | * - else |
1689 | * set IN_PKT_RDY |
1690 | */ |
1691 | if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) { |
1692 | DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n", |
1693 | __FUNCTION__); |
1694 | |
1695 | switch (dev->ep0state) { |
1696 | case DATA_STATE_XMIT: |
1697 | DEBUG_EP0("continue with DATA_STATE_XMIT\n"); |
1698 | jz4740_ep0_in(dev, csr); |
1699 | return; |
1700 | case DATA_STATE_NEED_ZLP: |
1701 | DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n"); |
1702 | jz4740_ep0_in_zlp(dev, csr); |
1703 | return; |
1704 | default: |
1705 | /* Stall? */ |
1706 | // DEBUG_EP0("Odd state!! state = %s\n", |
1707 | // state_names[dev->ep0state]); |
1708 | dev->ep0state = WAIT_FOR_SETUP; |
1709 | /* nuke(ep, 0); */ |
1710 | /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */ |
1711 | // break; |
1712 | return; |
1713 | } |
1714 | } |
1715 | |
1716 | /* |
1717 | * if SETUPEND is set |
1718 | * - abort the last transfer |
1719 | * - set SERVICED_SETUP_END_BIT |
1720 | */ |
1721 | if (csr & USB_CSR0_SETUPEND) { |
1722 | DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr); |
1723 | |
1724 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND); |
1725 | nuke(ep, 0); |
1726 | dev->ep0state = WAIT_FOR_SETUP; |
1727 | } |
1728 | |
1729 | /* |
1730 | * if USB_CSR0_OUTPKTRDY is set |
1731 | * - read data packet from EP0 FIFO |
1732 | * - decode command |
1733 | * - if error |
1734 | * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits |
1735 | * - else |
1736 | * set SVDOUTPKTRDY | DATAEND bits |
1737 | */ |
1738 | if (csr & USB_CSR0_OUTPKTRDY) { |
1739 | |
1740 | DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__, |
1741 | csr); |
1742 | |
1743 | switch (dev->ep0state) { |
1744 | case WAIT_FOR_SETUP: |
1745 | DEBUG_EP0("WAIT_FOR_SETUP\n"); |
1746 | jz4740_ep0_setup(dev, csr); |
1747 | break; |
1748 | |
1749 | case DATA_STATE_RECV: |
1750 | DEBUG_EP0("DATA_STATE_RECV\n"); |
1751 | jz4740_ep0_out(dev, csr, 0); |
1752 | break; |
1753 | |
1754 | default: |
1755 | /* send stall? */ |
1756 | DEBUG_EP0("strange state!! 2. send stall? state = %d\n", |
1757 | dev->ep0state); |
1758 | break; |
1759 | } |
1760 | } |
1761 | } |
1762 | |
1763 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep) |
1764 | { |
1765 | uint32_t csr; |
1766 | |
1767 | jz_udc_set_index(dev, 0); |
1768 | |
1769 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1770 | |
1771 | /* Clear "out packet ready" */ |
1772 | |
1773 | if (ep_is_in(ep)) { |
1774 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1775 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1776 | dev->ep0state = DATA_STATE_XMIT; |
1777 | jz4740_ep0_in(dev, csr); |
1778 | } else { |
1779 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1780 | dev->ep0state = DATA_STATE_RECV; |
1781 | jz4740_ep0_out(dev, csr, 1); |
1782 | } |
1783 | } |
1784 | |
1785 | /** Handle USB RESET interrupt |
1786 | */ |
1787 | static void jz4740_reset_irq(struct jz4740_udc *dev) |
1788 | { |
1789 | dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ? |
1790 | USB_SPEED_HIGH : USB_SPEED_FULL; |
1791 | |
1792 | DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0, |
1793 | (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" ); |
1794 | } |
1795 | |
1796 | /* |
1797 | * jz4740 usb device interrupt handler. |
1798 | */ |
1799 | static irqreturn_t jz4740_udc_irq(int irq, void *devid) |
1800 | { |
1801 | struct jz4740_udc *jz4740_udc = devid; |
1802 | uint8_t index; |
1803 | |
1804 | uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */ |
1805 | uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN); |
1806 | uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT); |
1807 | uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR); |
1808 | |
1809 | if (!intr_usb && !intr_in && !intr_out && !intr_dma) |
1810 | return IRQ_HANDLED; |
1811 | |
1812 | |
1813 | DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n", |
1814 | intr_out, intr_in, intr_usb); |
1815 | |
1816 | spin_lock(&jz4740_udc->lock); |
1817 | index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX); |
1818 | |
1819 | /* Check for resume from suspend mode */ |
1820 | if ((intr_usb & USB_INTR_RESUME) && |
1821 | (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) { |
1822 | DEBUG("USB resume\n"); |
1823 | jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */ |
1824 | } |
1825 | |
1826 | /* Check for system interrupts */ |
1827 | if (intr_usb & USB_INTR_RESET) { |
1828 | DEBUG("USB reset\n"); |
1829 | jz4740_reset_irq(jz4740_udc); |
1830 | } |
1831 | |
1832 | /* Check for endpoint 0 interrupt */ |
1833 | if (intr_in & USB_INTR_EP0) { |
1834 | DEBUG("USB_INTR_EP0 (control)\n"); |
1835 | jz4740_handle_ep0(jz4740_udc, intr_in); |
1836 | } |
1837 | |
1838 | /* Check for Bulk-IN DMA interrupt */ |
1839 | if (intr_dma & 0x1) { |
1840 | int ep_num; |
1841 | struct jz4740_ep *ep; |
1842 | ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf; |
1843 | ep = &jz4740_udc->ep[ep_num + 1]; |
1844 | jz_udc_select_ep(ep); |
1845 | usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY); |
1846 | /* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/ |
1847 | } |
1848 | |
1849 | /* Check for Bulk-OUT DMA interrupt */ |
1850 | if (intr_dma & 0x2) { |
1851 | int ep_num; |
1852 | ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf; |
1853 | jz4740_out_epn(jz4740_udc, ep_num, intr_out); |
1854 | } |
1855 | |
1856 | /* Check for each configured endpoint interrupt */ |
1857 | if (intr_in & USB_INTR_INEP1) { |
1858 | DEBUG("USB_INTR_INEP1\n"); |
1859 | jz4740_in_epn(jz4740_udc, 1, intr_in); |
1860 | } |
1861 | |
1862 | if (intr_in & USB_INTR_INEP2) { |
1863 | DEBUG("USB_INTR_INEP2\n"); |
1864 | jz4740_in_epn(jz4740_udc, 2, intr_in); |
1865 | } |
1866 | |
1867 | if (intr_out & USB_INTR_OUTEP1) { |
1868 | DEBUG("USB_INTR_OUTEP1\n"); |
1869 | jz4740_out_epn(jz4740_udc, 1, intr_out); |
1870 | } |
1871 | |
1872 | /* Check for suspend mode */ |
1873 | if ((intr_usb & USB_INTR_SUSPEND) && |
1874 | (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) { |
1875 | DEBUG("USB suspend\n"); |
1876 | jz4740_udc->driver->suspend(&jz4740_udc->gadget); |
1877 | /* Host unloaded from us, can do something, such as flushing |
1878 | the NAND block cache etc. */ |
1879 | } |
1880 | |
1881 | jz_udc_set_index(jz4740_udc, index); |
1882 | |
1883 | spin_unlock(&jz4740_udc->lock); |
1884 | |
1885 | return IRQ_HANDLED; |
1886 | } |
1887 | |
1888 | |
1889 | |
1890 | /*-------------------------------------------------------------------------*/ |
1891 | |
1892 | |
1893 | static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget) |
1894 | { |
1895 | return container_of(gadget, struct jz4740_udc, gadget); |
1896 | } |
1897 | |
1898 | static int jz4740_udc_get_frame(struct usb_gadget *_gadget) |
1899 | { |
1900 | DEBUG("%s, %p\n", __FUNCTION__, _gadget); |
1901 | return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME); |
1902 | } |
1903 | |
1904 | static int jz4740_udc_wakeup(struct usb_gadget *_gadget) |
1905 | { |
1906 | /* host may not have enabled remote wakeup */ |
1907 | /*if ((UDCCS0 & UDCCS0_DRWF) == 0) |
1908 | return -EHOSTUNREACH; |
1909 | udc_set_mask_UDCCR(UDCCR_RSM); */ |
1910 | return -ENOTSUPP; |
1911 | } |
1912 | |
1913 | static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on) |
1914 | { |
1915 | struct jz4740_udc *udc = gadget_to_udc(_gadget); |
1916 | unsigned long flags; |
1917 | |
1918 | local_irq_save(flags); |
1919 | |
1920 | if (on) { |
1921 | udc->state = UDC_STATE_ENABLE; |
1922 | udc_enable(udc); |
1923 | } else { |
1924 | udc->state = UDC_STATE_DISABLE; |
1925 | udc_disable(udc); |
1926 | } |
1927 | |
1928 | local_irq_restore(flags); |
1929 | |
1930 | return 0; |
1931 | } |
1932 | |
1933 | |
1934 | static const struct usb_gadget_ops jz4740_udc_ops = { |
1935 | .get_frame = jz4740_udc_get_frame, |
1936 | .wakeup = jz4740_udc_wakeup, |
1937 | .pullup = jz4740_udc_pullup, |
1938 | .start = jz4740_udc_start, |
1939 | .stop = jz4740_udc_stop, |
1940 | }; |
1941 | |
1942 | static struct usb_ep_ops jz4740_ep_ops = { |
1943 | .enable = jz4740_ep_enable, |
1944 | .disable = jz4740_ep_disable, |
1945 | |
1946 | .alloc_request = jz4740_alloc_request, |
1947 | .free_request = jz4740_free_request, |
1948 | |
1949 | .queue = jz4740_queue, |
1950 | .dequeue = jz4740_dequeue, |
1951 | |
1952 | .set_halt = jz4740_set_halt, |
1953 | .fifo_status = jz4740_fifo_status, |
1954 | .fifo_flush = jz4740_fifo_flush, |
1955 | }; |
1956 | |
1957 | |
1958 | /*-------------------------------------------------------------------------*/ |
1959 | |
1960 | static struct jz4740_udc jz4740_udc_controller = { |
1961 | .gadget = { |
1962 | .ops = &jz4740_udc_ops, |
1963 | .ep0 = &jz4740_udc_controller.ep[0].ep, |
1964 | .name = "jz4740-udc", |
1965 | .dev = { |
1966 | .init_name = "gadget", |
1967 | }, |
1968 | }, |
1969 | |
1970 | /* control endpoint */ |
1971 | .ep[0] = { |
1972 | .ep = { |
1973 | .name = "ep0", |
1974 | .ops = &jz4740_ep_ops, |
1975 | .maxpacket = EP0_MAXPACKETSIZE, |
1976 | }, |
1977 | .dev = &jz4740_udc_controller, |
1978 | |
1979 | .bEndpointAddress = 0, |
1980 | .bmAttributes = 0, |
1981 | |
1982 | .type = ep_control, |
1983 | .fifo = JZ_REG_UDC_EP_FIFO(0), |
1984 | .csr = JZ_REG_UDC_CSR0, |
1985 | }, |
1986 | |
1987 | /* bulk out endpoint */ |
1988 | .ep[1] = { |
1989 | .ep = { |
1990 | .name = "ep1out-bulk", |
1991 | .ops = &jz4740_ep_ops, |
1992 | .maxpacket = EPBULK_MAXPACKETSIZE, |
1993 | }, |
1994 | .dev = &jz4740_udc_controller, |
1995 | |
1996 | .bEndpointAddress = 1, |
1997 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
1998 | |
1999 | .type = ep_bulk_out, |
2000 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2001 | .csr = JZ_REG_UDC_OUTCSR, |
2002 | }, |
2003 | |
2004 | /* bulk in endpoint */ |
2005 | .ep[2] = { |
2006 | .ep = { |
2007 | .name = "ep1in-bulk", |
2008 | .ops = &jz4740_ep_ops, |
2009 | .maxpacket = EPBULK_MAXPACKETSIZE, |
2010 | }, |
2011 | .dev = &jz4740_udc_controller, |
2012 | |
2013 | .bEndpointAddress = 1 | USB_DIR_IN, |
2014 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2015 | |
2016 | .type = ep_bulk_in, |
2017 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2018 | .csr = JZ_REG_UDC_INCSR, |
2019 | }, |
2020 | |
2021 | /* interrupt in endpoint */ |
2022 | .ep[3] = { |
2023 | .ep = { |
2024 | .name = "ep2in-int", |
2025 | .ops = &jz4740_ep_ops, |
2026 | .maxpacket = EPINTR_MAXPACKETSIZE, |
2027 | }, |
2028 | .dev = &jz4740_udc_controller, |
2029 | |
2030 | .bEndpointAddress = 2 | USB_DIR_IN, |
2031 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2032 | |
2033 | .type = ep_interrupt, |
2034 | .fifo = JZ_REG_UDC_EP_FIFO(2), |
2035 | .csr = JZ_REG_UDC_INCSR, |
2036 | }, |
2037 | }; |
2038 | |
2039 | static int __devinit jz4740_udc_probe(struct platform_device *pdev) |
2040 | { |
2041 | struct jz4740_udc *jz4740_udc = &jz4740_udc_controller; |
2042 | int ret; |
2043 | |
2044 | spin_lock_init(&jz4740_udc->lock); |
2045 | |
2046 | jz4740_udc->dev = &pdev->dev; |
2047 | jz4740_udc->gadget.dev.parent = &pdev->dev; |
2048 | jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask; |
2049 | |
2050 | ret = device_register(&jz4740_udc->gadget.dev); |
2051 | if (ret) |
2052 | return ret; |
2053 | |
2054 | jz4740_udc->clk = clk_get(&pdev->dev, "udc"); |
2055 | if (IS_ERR(jz4740_udc->clk)) { |
2056 | ret = PTR_ERR(jz4740_udc->clk); |
2057 | dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret); |
2058 | goto err_device_unregister; |
2059 | } |
2060 | |
2061 | platform_set_drvdata(pdev, jz4740_udc); |
2062 | |
2063 | jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2064 | |
2065 | if (!jz4740_udc->mem) { |
2066 | ret = -ENOENT; |
2067 | dev_err(&pdev->dev, "Failed to get mmio memory resource\n"); |
2068 | goto err_clk_put; |
2069 | } |
2070 | |
2071 | jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start, |
2072 | resource_size(jz4740_udc->mem), pdev->name); |
2073 | |
2074 | if (!jz4740_udc->mem) { |
2075 | ret = -EBUSY; |
2076 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
2077 | goto err_device_unregister; |
2078 | } |
2079 | |
2080 | jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem)); |
2081 | |
2082 | if (!jz4740_udc->base) { |
2083 | ret = -EBUSY; |
2084 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
2085 | goto err_release_mem_region; |
2086 | } |
2087 | |
2088 | jz4740_udc->irq = platform_get_irq(pdev, 0); |
2089 | ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name, |
2090 | jz4740_udc); |
2091 | if (ret) { |
2092 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
2093 | goto err_iounmap; |
2094 | } |
2095 | |
2096 | ret = usb_add_gadget_udc(&pdev->dev, &jz4740_udc->gadget); |
2097 | if (ret) { |
2098 | dev_err(&pdev->dev, "Failed to add gadget: %d\n", ret); |
2099 | goto err_free_irq; |
2100 | } |
2101 | |
2102 | udc_disable(jz4740_udc); |
2103 | udc_reinit(jz4740_udc); |
2104 | |
2105 | return 0; |
2106 | |
2107 | err_free_irq: |
2108 | free_irq(jz4740_udc->irq, pdev); |
2109 | err_iounmap: |
2110 | iounmap(jz4740_udc->base); |
2111 | err_release_mem_region: |
2112 | release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem)); |
2113 | err_clk_put: |
2114 | clk_put(jz4740_udc->clk); |
2115 | err_device_unregister: |
2116 | device_unregister(&jz4740_udc->gadget.dev); |
2117 | platform_set_drvdata(pdev, NULL); |
2118 | |
2119 | return ret; |
2120 | } |
2121 | |
2122 | static int __devexit jz4740_udc_remove(struct platform_device *pdev) |
2123 | { |
2124 | struct jz4740_udc *dev = platform_get_drvdata(pdev); |
2125 | |
2126 | usb_del_gadget_udc(&dev->gadget); |
2127 | if (dev->driver) |
2128 | return -EBUSY; |
2129 | |
2130 | udc_disable(dev); |
2131 | |
2132 | free_irq(dev->irq, dev); |
2133 | iounmap(dev->base); |
2134 | release_mem_region(dev->mem->start, resource_size(dev->mem)); |
2135 | clk_put(dev->clk); |
2136 | |
2137 | platform_set_drvdata(pdev, NULL); |
2138 | device_unregister(&dev->gadget.dev); |
2139 | |
2140 | return 0; |
2141 | } |
2142 | |
2143 | #ifdef CONFIG_PM |
2144 | |
2145 | static int jz4740_udc_suspend(struct device *dev) |
2146 | { |
2147 | struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev); |
2148 | |
2149 | if (jz4740_udc->state == UDC_STATE_ENABLE) |
2150 | udc_disable(jz4740_udc); |
2151 | |
2152 | return 0; |
2153 | } |
2154 | |
2155 | static int jz4740_udc_resume(struct device *dev) |
2156 | { |
2157 | struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev); |
2158 | |
2159 | if (jz4740_udc->state == UDC_STATE_ENABLE) |
2160 | udc_enable(jz4740_udc); |
2161 | |
2162 | return 0; |
2163 | } |
2164 | |
2165 | static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume); |
2166 | #define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops) |
2167 | |
2168 | #else |
2169 | #define JZ4740_UDC_PM_OPS NULL |
2170 | #endif |
2171 | |
2172 | static struct platform_driver udc_driver = { |
2173 | .probe = jz4740_udc_probe, |
2174 | .remove = __devexit_p(jz4740_udc_remove), |
2175 | .driver = { |
2176 | .name = "jz-udc", |
2177 | .owner = THIS_MODULE, |
2178 | .pm = JZ4740_UDC_PM_OPS, |
2179 | }, |
2180 | }; |
2181 | |
2182 | /*-------------------------------------------------------------------------*/ |
2183 | |
2184 | static int __init udc_init (void) |
2185 | { |
2186 | return platform_driver_register(&udc_driver); |
2187 | } |
2188 | module_init(udc_init); |
2189 | |
2190 | static void __exit udc_exit (void) |
2191 | { |
2192 | platform_driver_unregister(&udc_driver); |
2193 | } |
2194 | module_exit(udc_exit); |
2195 | |
2196 | MODULE_DESCRIPTION("JZ4740 USB Device Controller"); |
2197 | MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>"); |
2198 | MODULE_LICENSE("GPL"); |
2199 |
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