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Source at commit ef60fc3200a68f7ebd2a5a9fff585073f233bb5e created 14 years 3 months ago. By xiangfu, file | |
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1 | /* |
2 | * linux/arch/mips/jz4740/reset.c |
3 | * |
4 | * JZ4740 reset routines. |
5 | * |
6 | * Copyright (c) 2006-2007 Ingenic Semiconductor Inc. |
7 | * Author: <yliu@ingenic.cn> |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 as |
11 | * published by the Free Software Foundation. |
12 | */ |
13 | #include <linux/sched.h> |
14 | #include <linux/mm.h> |
15 | #include <asm/io.h> |
16 | #include <asm/pgtable.h> |
17 | #include <asm/processor.h> |
18 | #include <asm/reboot.h> |
19 | #include <asm/system.h> |
20 | #include <asm/mach-jz4740/regs.h> |
21 | #include <asm/mach-jz4740/jz4740.h> |
22 | |
23 | void jz_restart(char *command) |
24 | { |
25 | printk(KERN_NOTICE "Restarting after 4 ms\n"); |
26 | REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN; |
27 | REG_WDT_TCNT = 0; |
28 | REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */ |
29 | REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */ |
30 | REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */ |
31 | while (1); |
32 | } |
33 | |
34 | void jz_halt(void) |
35 | { |
36 | /* Put CPU to power down mode */ |
37 | while (!(REG_RTC_RCR & RTC_RCR_WRDY)); |
38 | REG_RTC_HCR = RTC_HCR_PD; |
39 | |
40 | while (1) |
41 | __asm__(".set\tmips3\n\t" |
42 | "wait\n\t" |
43 | ".set\tmips0"); |
44 | } |
45 | |
46 | void jz_power_off(void) |
47 | { |
48 | jz_halt(); |
49 | } |
50 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9