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Source at commit ef60fc3200a68f7ebd2a5a9fff585073f233bb5e created 14 years 3 months ago. By xiangfu, file | |
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1 | /* |
2 | * linux/drivers/usb/gadget/jz4740_udc.c |
3 | * |
4 | * Ingenic JZ4740 on-chip high speed USB device controller |
5 | * |
6 | * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc. |
7 | * Author: <jlwei@ingenic.cn> |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or |
12 | * (at your option) any later version. |
13 | */ |
14 | |
15 | /* |
16 | * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint. |
17 | * |
18 | * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk. |
19 | * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints. |
20 | */ |
21 | |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> |
24 | #include <linux/platform_device.h> |
25 | #include <linux/delay.h> |
26 | #include <linux/ioport.h> |
27 | #include <linux/slab.h> |
28 | #include <linux/errno.h> |
29 | #include <linux/init.h> |
30 | #include <linux/list.h> |
31 | #include <linux/interrupt.h> |
32 | #include <linux/proc_fs.h> |
33 | #include <linux/usb.h> |
34 | #include <linux/usb/gadget.h> |
35 | |
36 | #include <asm/byteorder.h> |
37 | #include <asm/io.h> |
38 | #include <asm/irq.h> |
39 | #include <asm/system.h> |
40 | #include <asm/mach-jz4740/regs.h> |
41 | #include <asm/mach-jz4740/clock.h> |
42 | |
43 | #include "jz4740_udc.h" |
44 | |
45 | #define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */ |
46 | #define JZ_REG_UDC_POWER 0x01 /* Power Managemetn 8-bit */ |
47 | #define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */ |
48 | #define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */ |
49 | #define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */ |
50 | #define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */ |
51 | #define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */ |
52 | #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */ |
53 | #define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */ |
54 | #define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */ |
55 | #define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */ |
56 | |
57 | #define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */ |
58 | #define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */ |
59 | #define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */ |
60 | #define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */ |
61 | #define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */ |
62 | #define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */ |
63 | #define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */ |
64 | #define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */ |
65 | |
66 | #define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20) |
67 | |
68 | #define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */ |
69 | #define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */ |
70 | |
71 | #define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */ |
72 | #define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */ |
73 | #define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */ |
74 | #define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */ |
75 | #define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */ |
76 | #define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */ |
77 | #define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */ |
78 | |
79 | #ifndef DEBUG |
80 | # define DEBUG(fmt,args...) do {} while(0) |
81 | #endif |
82 | #ifndef DEBUG_EP0 |
83 | # define NO_STATES |
84 | # define DEBUG_EP0(fmt,args...) do {} while(0) |
85 | #endif |
86 | #ifndef DEBUG_SETUP |
87 | # define DEBUG_SETUP(fmt,args...) do {} while(0) |
88 | #endif |
89 | |
90 | static unsigned int udc_debug = 0; /* 0: normal mode, 1: test udc cable type mode */ |
91 | |
92 | module_param(udc_debug, int, 0); |
93 | MODULE_PARM_DESC(udc_debug, "test udc cable or power type"); |
94 | |
95 | static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */ |
96 | |
97 | module_param(use_dma, int, 0); |
98 | MODULE_PARM_DESC(use_dma, "DMA mode enable flag"); |
99 | |
100 | struct jz4740_udc *the_controller; |
101 | |
102 | /* |
103 | * Local declarations. |
104 | */ |
105 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep); |
106 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr); |
107 | |
108 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, |
109 | int status); |
110 | static void pio_irq_enable(struct jz4740_ep *ep); |
111 | static void pio_irq_disable(struct jz4740_ep *ep); |
112 | static void stop_activity(struct jz4740_udc *dev, |
113 | struct usb_gadget_driver *driver); |
114 | static void nuke(struct jz4740_ep *ep, int status); |
115 | static void flush(struct jz4740_ep *ep); |
116 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address); |
117 | |
118 | /*-------------------------------------------------------------------------*/ |
119 | |
120 | /* inline functions of register read/write/set/clear */ |
121 | |
122 | static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg) |
123 | { |
124 | return readb(udc->base + reg); |
125 | } |
126 | |
127 | static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg) |
128 | { |
129 | return readw(udc->base + reg); |
130 | } |
131 | |
132 | static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg) |
133 | { |
134 | return readl(udc->base + reg); |
135 | } |
136 | |
137 | static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val) |
138 | { |
139 | writeb(val, udc->base + reg); |
140 | } |
141 | |
142 | static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val) |
143 | { |
144 | writew(val, udc->base + reg); |
145 | } |
146 | |
147 | static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val) |
148 | { |
149 | writel(val, udc->base + reg); |
150 | } |
151 | |
152 | static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
153 | { |
154 | usb_writeb(udc, reg, usb_readb(udc, reg) | mask); |
155 | } |
156 | |
157 | static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
158 | { |
159 | usb_writew(udc, reg, usb_readw(udc, reg) | mask); |
160 | } |
161 | |
162 | static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask) |
163 | { |
164 | usb_writel(udc, reg, usb_readl(udc, reg) | mask); |
165 | } |
166 | |
167 | static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
168 | { |
169 | usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask); |
170 | } |
171 | |
172 | static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
173 | { |
174 | usb_writew(udc, reg, usb_readw(udc, reg) & ~mask); |
175 | } |
176 | |
177 | static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask) |
178 | { |
179 | usb_writel(udc, reg, usb_readl(udc, reg) & ~mask); |
180 | } |
181 | |
182 | /*-------------------------------------------------------------------------*/ |
183 | |
184 | static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index) |
185 | { |
186 | usb_writeb(udc, JZ_REG_UDC_INDEX, index); |
187 | } |
188 | |
189 | static inline void jz_udc_select_ep(struct jz4740_ep *ep) |
190 | { |
191 | jz_udc_set_index(ep->dev, ep_index(ep)); |
192 | } |
193 | |
194 | static inline int write_packet(struct jz4740_ep *ep, |
195 | struct jz4740_request *req, int max) |
196 | { |
197 | uint8_t *buf; |
198 | int length, nlong, nbyte; |
199 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
200 | |
201 | buf = req->req.buf + req->req.actual; |
202 | prefetch(buf); |
203 | |
204 | length = req->req.length - req->req.actual; |
205 | length = min(length, max); |
206 | req->req.actual += length; |
207 | |
208 | DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo); |
209 | |
210 | nlong = length >> 2; |
211 | nbyte = length & 0x3; |
212 | while (nlong--) { |
213 | usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf)); |
214 | buf += 4; |
215 | } |
216 | while (nbyte--) { |
217 | usb_writeb(ep->dev, ep->fifo, *buf++); |
218 | } |
219 | |
220 | return length; |
221 | } |
222 | |
223 | static inline int read_packet(struct jz4740_ep *ep, |
224 | struct jz4740_request *req, int count) |
225 | { |
226 | uint8_t *buf; |
227 | int length, nlong, nbyte; |
228 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
229 | |
230 | buf = req->req.buf + req->req.actual; |
231 | prefetchw(buf); |
232 | |
233 | length = req->req.length - req->req.actual; |
234 | length = min(length, count); |
235 | req->req.actual += length; |
236 | |
237 | DEBUG("Read %d, fifo %x\n", length, ep->fifo); |
238 | |
239 | nlong = length >> 2; |
240 | nbyte = length & 0x3; |
241 | while (nlong--) { |
242 | *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo); |
243 | buf += 4; |
244 | } |
245 | while (nbyte--) { |
246 | *buf++ = usb_readb(ep->dev, ep->fifo); |
247 | } |
248 | |
249 | return length; |
250 | } |
251 | |
252 | /*-------------------------------------------------------------------------*/ |
253 | |
254 | /* |
255 | * udc_disable - disable USB device controller |
256 | */ |
257 | static void udc_disable(struct jz4740_udc *dev) |
258 | { |
259 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
260 | |
261 | udc_set_address(dev, 0); |
262 | |
263 | /* Disable interrupts */ |
264 | usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
265 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
266 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0); |
267 | |
268 | /* Disable DMA */ |
269 | usb_writel(dev, JZ_REG_UDC_CNTL1, 0); |
270 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
271 | |
272 | /* Disconnect from usb */ |
273 | usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
274 | |
275 | /* Disable the USB PHY */ |
276 | #ifdef CONFIG_SOC_JZ4740 |
277 | REG_CPM_SCR &= ~CPM_SCR_USBPHY_ENABLE; |
278 | #elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D) |
279 | REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE; |
280 | #endif |
281 | |
282 | dev->ep0state = WAIT_FOR_SETUP; |
283 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
284 | |
285 | return; |
286 | } |
287 | |
288 | /* |
289 | * udc_reinit - initialize software state |
290 | */ |
291 | static void udc_reinit(struct jz4740_udc *dev) |
292 | { |
293 | int i; |
294 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
295 | |
296 | /* device/ep0 records init */ |
297 | INIT_LIST_HEAD(&dev->gadget.ep_list); |
298 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); |
299 | dev->ep0state = WAIT_FOR_SETUP; |
300 | |
301 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
302 | struct jz4740_ep *ep = &dev->ep[i]; |
303 | |
304 | if (i != 0) |
305 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); |
306 | |
307 | INIT_LIST_HEAD(&ep->queue); |
308 | ep->desc = 0; |
309 | ep->stopped = 0; |
310 | ep->pio_irqs = 0; |
311 | } |
312 | } |
313 | |
314 | /* until it's enabled, this UDC should be completely invisible |
315 | * to any USB host. |
316 | */ |
317 | static void udc_enable(struct jz4740_udc *dev) |
318 | { |
319 | int i; |
320 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
321 | |
322 | /* UDC state is incorrect - Added by River */ |
323 | if (dev->state != UDC_STATE_ENABLE) { |
324 | return; |
325 | } |
326 | |
327 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
328 | |
329 | /* Flush FIFO for each */ |
330 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
331 | struct jz4740_ep *ep = &dev->ep[i]; |
332 | |
333 | jz_udc_set_index(dev, ep_index(ep)); |
334 | flush(ep); |
335 | } |
336 | |
337 | /* Set this bit to allow the UDC entering low-power mode when |
338 | * there are no actions on the USB bus. |
339 | * UDC still works during this bit was set. |
340 | */ |
341 | __cpm_stop_udc(); |
342 | |
343 | /* Enable the USB PHY */ |
344 | #ifdef CONFIG_SOC_JZ4740 |
345 | REG_CPM_SCR |= CPM_SCR_USBPHY_ENABLE; |
346 | #elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D) |
347 | REG_CPM_OPCR |= CPM_OPCR_UDCPHY_ENABLE; |
348 | #endif |
349 | |
350 | /* Disable interrupts */ |
351 | /* usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
352 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
353 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/ |
354 | |
355 | /* Enable interrupts */ |
356 | usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0); |
357 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET); |
358 | /* Don't enable rest of the interrupts */ |
359 | /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2); |
360 | usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */ |
361 | |
362 | /* Enable SUSPEND */ |
363 | /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */ |
364 | |
365 | /* Enable HS Mode */ |
366 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB); |
367 | |
368 | /* Let host detect UDC: |
369 | * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this |
370 | * transistor on and pull the USBDP pin HIGH. |
371 | */ |
372 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
373 | |
374 | return; |
375 | } |
376 | |
377 | /*-------------------------------------------------------------------------*/ |
378 | |
379 | /* keeping it simple: |
380 | * - one bus driver, initted first; |
381 | * - one function driver, initted second |
382 | */ |
383 | |
384 | /* |
385 | * Register entry point for the peripheral controller driver. |
386 | */ |
387 | |
388 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) |
389 | { |
390 | struct jz4740_udc *dev = the_controller; |
391 | int retval; |
392 | |
393 | if (!driver || !driver->bind) { |
394 | return -EINVAL; |
395 | } |
396 | |
397 | if (!dev) { |
398 | return -ENODEV; |
399 | } |
400 | |
401 | if (dev->driver) { |
402 | return -EBUSY; |
403 | } |
404 | |
405 | /* hook up the driver */ |
406 | dev->driver = driver; |
407 | dev->gadget.dev.driver = &driver->driver; |
408 | |
409 | retval = driver->bind(&dev->gadget); |
410 | if (retval) { |
411 | DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name, |
412 | driver->driver.name, retval); |
413 | dev->driver = 0; |
414 | return retval; |
415 | } |
416 | |
417 | /* then enable host detection and ep0; and we're ready |
418 | * for set_configuration as well as eventual disconnect. |
419 | */ |
420 | udc_enable(dev); |
421 | |
422 | DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name, |
423 | driver->driver.name); |
424 | |
425 | return 0; |
426 | } |
427 | |
428 | EXPORT_SYMBOL(usb_gadget_register_driver); |
429 | |
430 | static void stop_activity(struct jz4740_udc *dev, |
431 | struct usb_gadget_driver *driver) |
432 | { |
433 | int i; |
434 | |
435 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
436 | |
437 | /* don't disconnect drivers more than once */ |
438 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) |
439 | driver = 0; |
440 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
441 | |
442 | /* prevent new request submissions, kill any outstanding requests */ |
443 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
444 | struct jz4740_ep *ep = &dev->ep[i]; |
445 | |
446 | ep->stopped = 1; |
447 | |
448 | jz_udc_set_index(dev, ep_index(ep)); |
449 | nuke(ep, -ESHUTDOWN); |
450 | } |
451 | |
452 | /* report disconnect; the driver is already quiesced */ |
453 | if (driver) { |
454 | spin_unlock(&dev->lock); |
455 | driver->disconnect(&dev->gadget); |
456 | spin_lock(&dev->lock); |
457 | } |
458 | |
459 | /* re-init driver-visible data structures */ |
460 | udc_reinit(dev); |
461 | } |
462 | |
463 | |
464 | /* |
465 | * Unregister entry point for the peripheral controller driver. |
466 | */ |
467 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
468 | { |
469 | struct jz4740_udc *dev = the_controller; |
470 | unsigned long flags; |
471 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
472 | |
473 | if (!dev) |
474 | return -ENODEV; |
475 | if (!driver || driver != dev->driver) |
476 | return -EINVAL; |
477 | if (!driver->unbind) |
478 | return -EBUSY; |
479 | |
480 | spin_lock_irqsave(&dev->lock, flags); |
481 | dev->driver = 0; |
482 | stop_activity(dev, driver); |
483 | spin_unlock_irqrestore(&dev->lock, flags); |
484 | |
485 | driver->unbind(&dev->gadget); |
486 | |
487 | udc_disable(dev); |
488 | |
489 | DEBUG("unregistered driver '%s'\n", driver->driver.name); |
490 | |
491 | return 0; |
492 | } |
493 | |
494 | EXPORT_SYMBOL(usb_gadget_unregister_driver); |
495 | |
496 | /*-------------------------------------------------------------------------*/ |
497 | |
498 | /* |
499 | * Starting DMA using mode 1 |
500 | */ |
501 | static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req) |
502 | { |
503 | struct jz4740_udc *dev = ep->dev; |
504 | uint32_t count = req->req.length; |
505 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
506 | |
507 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
508 | |
509 | jz_udc_select_ep(ep); |
510 | |
511 | if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */ |
512 | ep->reg_addr = JZ_REG_UDC_ADDR1; |
513 | |
514 | dma_cache_wback_inv((unsigned long)req->req.buf, count); |
515 | |
516 | pio_irq_enable(ep); |
517 | |
518 | usb_writeb(dev, JZ_REG_UDC_INCSRH, |
519 | USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE); |
520 | |
521 | usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr); |
522 | usb_writel(dev, JZ_REG_UDC_COUNT1, count); |
523 | usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 | |
524 | USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep))); |
525 | } |
526 | else { /* Bulk-OUT transfer using DMA channel 2 */ |
527 | ep->reg_addr = JZ_REG_UDC_ADDR2; |
528 | |
529 | dma_cache_wback_inv((unsigned long)req->req.buf, count); |
530 | |
531 | pio_irq_enable(ep); |
532 | |
533 | usb_setb(dev, JZ_REG_UDC_OUTCSRH, |
534 | USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE); |
535 | |
536 | usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr); |
537 | usb_writel(dev, JZ_REG_UDC_COUNT2, count); |
538 | usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 | |
539 | USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep))); |
540 | } |
541 | } |
542 | |
543 | /*-------------------------------------------------------------------------*/ |
544 | |
545 | /** Write request to FIFO (max write == maxp size) |
546 | * Return: 0 = still running, 1 = completed, negative = errno |
547 | * NOTE: INDEX register must be set for EP |
548 | */ |
549 | static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
550 | { |
551 | struct jz4740_udc *dev = ep->dev; |
552 | uint32_t max, csr; |
553 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
554 | |
555 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
556 | max = le16_to_cpu(ep->desc->wMaxPacketSize); |
557 | |
558 | if (use_dma) { |
559 | uint32_t dma_count; |
560 | |
561 | /* DMA interrupt generated due to the last packet loaded into the FIFO */ |
562 | |
563 | dma_count = usb_readl(dev, ep->reg_addr) - physaddr; |
564 | req->req.actual += dma_count; |
565 | |
566 | if (dma_count % max) { |
567 | /* If the last packet is less than MAXP, set INPKTRDY manually */ |
568 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
569 | } |
570 | |
571 | done(ep, req, 0); |
572 | if (list_empty(&ep->queue)) { |
573 | pio_irq_disable(ep); |
574 | return 1; |
575 | } |
576 | else { |
577 | /* advance the request queue */ |
578 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
579 | kick_dma(ep, req); |
580 | return 0; |
581 | } |
582 | } |
583 | |
584 | /* |
585 | * PIO mode handling starts here ... |
586 | */ |
587 | |
588 | csr = usb_readb(dev, ep->csr); |
589 | |
590 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
591 | unsigned count; |
592 | int is_last, is_short; |
593 | |
594 | count = write_packet(ep, req, max); |
595 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
596 | |
597 | /* last packet is usually short (or a zlp) */ |
598 | if (unlikely(count != max)) |
599 | is_last = is_short = 1; |
600 | else { |
601 | if (likely(req->req.length != req->req.actual) |
602 | || req->req.zero) |
603 | is_last = 0; |
604 | else |
605 | is_last = 1; |
606 | /* interrupt/iso maxpacket may not fill the fifo */ |
607 | is_short = unlikely(max < ep_maxpacket(ep)); |
608 | } |
609 | |
610 | DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__, |
611 | ep->ep.name, count, |
612 | is_last ? "/L" : "", is_short ? "/S" : "", |
613 | req->req.length - req->req.actual, req); |
614 | |
615 | /* requests complete when all IN data is in the FIFO */ |
616 | if (is_last) { |
617 | done(ep, req, 0); |
618 | if (list_empty(&ep->queue)) { |
619 | pio_irq_disable(ep); |
620 | } |
621 | return 1; |
622 | } |
623 | } else { |
624 | DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep)); |
625 | } |
626 | |
627 | return 0; |
628 | } |
629 | |
630 | /** Read to request from FIFO (max read == bytes in fifo) |
631 | * Return: 0 = still running, 1 = completed, negative = errno |
632 | * NOTE: INDEX register must be set for EP |
633 | */ |
634 | static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
635 | { |
636 | struct jz4740_udc *dev = ep->dev; |
637 | uint32_t csr; |
638 | unsigned count, is_short; |
639 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
640 | |
641 | if (use_dma) { |
642 | uint32_t dma_count; |
643 | |
644 | /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */ |
645 | |
646 | dma_count = usb_readl(dev, ep->reg_addr) - physaddr; |
647 | req->req.actual += dma_count; |
648 | |
649 | /* Disable interrupt and DMA */ |
650 | pio_irq_disable(ep); |
651 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
652 | |
653 | /* Read all bytes from this packet */ |
654 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
655 | count = read_packet(ep, req, count); |
656 | |
657 | if (count) { |
658 | /* If the last packet is greater than zero, clear OUTPKTRDY manually */ |
659 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
660 | } |
661 | done(ep, req, 0); |
662 | |
663 | if (!list_empty(&ep->queue)) { |
664 | /* advance the request queue */ |
665 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
666 | kick_dma(ep, req); |
667 | } |
668 | |
669 | return 1; |
670 | } |
671 | |
672 | /* |
673 | * PIO mode handling starts here ... |
674 | */ |
675 | |
676 | /* make sure there's a packet in the FIFO. */ |
677 | csr = usb_readb(dev, ep->csr); |
678 | if (!(csr & USB_OUTCSR_OUTPKTRDY)) { |
679 | DEBUG("%s: Packet NOT ready!\n", __FUNCTION__); |
680 | return -EINVAL; |
681 | } |
682 | |
683 | /* read all bytes from this packet */ |
684 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
685 | |
686 | is_short = (count < ep->ep.maxpacket); |
687 | |
688 | count = read_packet(ep, req, count); |
689 | |
690 | DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n", |
691 | ep->ep.name, csr, count, |
692 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
693 | |
694 | /* Clear OutPktRdy */ |
695 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
696 | |
697 | /* completion */ |
698 | if (is_short || req->req.actual == req->req.length) { |
699 | done(ep, req, 0); |
700 | |
701 | if (list_empty(&ep->queue)) |
702 | pio_irq_disable(ep); |
703 | return 1; |
704 | } |
705 | |
706 | /* finished that packet. the next one may be waiting... */ |
707 | return 0; |
708 | } |
709 | |
710 | /* |
711 | * done - retire a request; caller blocked irqs |
712 | * INDEX register is preserved to keep same |
713 | */ |
714 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status) |
715 | { |
716 | unsigned int stopped = ep->stopped; |
717 | unsigned long flags; |
718 | uint32_t index; |
719 | |
720 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
721 | list_del_init(&req->queue); |
722 | |
723 | if (likely(req->req.status == -EINPROGRESS)) |
724 | req->req.status = status; |
725 | else |
726 | status = req->req.status; |
727 | |
728 | if (status && status != -ESHUTDOWN) |
729 | DEBUG("complete %s req %p stat %d len %u/%u\n", |
730 | ep->ep.name, &req->req, status, |
731 | req->req.actual, req->req.length); |
732 | |
733 | /* don't modify queue heads during completion callback */ |
734 | ep->stopped = 1; |
735 | /* Read current index (completion may modify it) */ |
736 | spin_lock_irqsave(&ep->dev->lock, flags); |
737 | index = usb_readb(ep->dev, JZ_REG_UDC_INDEX); |
738 | |
739 | req->req.complete(&ep->ep, &req->req); |
740 | |
741 | /* Restore index */ |
742 | jz_udc_set_index(ep->dev, index); |
743 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
744 | ep->stopped = stopped; |
745 | } |
746 | |
747 | /** Enable EP interrupt */ |
748 | static void pio_irq_enable(struct jz4740_ep *ep) |
749 | { |
750 | uint8_t index = ep_index(ep); |
751 | struct jz4740_udc *dev = ep->dev; |
752 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
753 | |
754 | if (ep_is_in(ep)) { |
755 | switch (index) { |
756 | case 1: |
757 | case 2: |
758 | usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index)); |
759 | dev->in_mask |= BIT(index); |
760 | break; |
761 | default: |
762 | DEBUG("Unknown endpoint: %d\n", index); |
763 | break; |
764 | } |
765 | } |
766 | else { |
767 | switch (index) { |
768 | case 1: |
769 | usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index)); |
770 | dev->out_mask |= BIT(index); |
771 | break; |
772 | default: |
773 | DEBUG("Unknown endpoint: %d\n", index); |
774 | break; |
775 | } |
776 | } |
777 | } |
778 | |
779 | /** Disable EP interrupt */ |
780 | static void pio_irq_disable(struct jz4740_ep *ep) |
781 | { |
782 | uint8_t index = ep_index(ep); |
783 | struct jz4740_udc *dev = ep->dev; |
784 | |
785 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
786 | |
787 | if (ep_is_in(ep)) { |
788 | switch (ep_index(ep)) { |
789 | case 1: |
790 | case 2: |
791 | usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index)); |
792 | dev->in_mask &= ~BIT(index); |
793 | break; |
794 | default: |
795 | DEBUG("Unknown endpoint: %d\n", index); |
796 | break; |
797 | } |
798 | } |
799 | else { |
800 | switch (ep_index(ep)) { |
801 | case 1: |
802 | usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index)); |
803 | dev->out_mask &= ~BIT(index); |
804 | break; |
805 | default: |
806 | DEBUG("Unknown endpoint: %d\n", index); |
807 | break; |
808 | } |
809 | } |
810 | } |
811 | |
812 | /* |
813 | * nuke - dequeue ALL requests |
814 | */ |
815 | static void nuke(struct jz4740_ep *ep, int status) |
816 | { |
817 | struct jz4740_request *req; |
818 | |
819 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
820 | |
821 | /* Flush FIFO */ |
822 | flush(ep); |
823 | |
824 | /* called with irqs blocked */ |
825 | while (!list_empty(&ep->queue)) { |
826 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
827 | done(ep, req, status); |
828 | } |
829 | |
830 | /* Disable IRQ if EP is enabled (has descriptor) */ |
831 | if (ep->desc) |
832 | pio_irq_disable(ep); |
833 | } |
834 | |
835 | /** Flush EP FIFO |
836 | * NOTE: INDEX register must be set before this call |
837 | */ |
838 | static void flush(struct jz4740_ep *ep) |
839 | { |
840 | DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name); |
841 | |
842 | switch (ep->type) { |
843 | case ep_bulk_in: |
844 | case ep_interrupt: |
845 | usb_setb(ep->dev, ep->csr, USB_INCSR_FF); |
846 | break; |
847 | case ep_bulk_out: |
848 | usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF); |
849 | break; |
850 | case ep_control: |
851 | break; |
852 | } |
853 | } |
854 | |
855 | /** |
856 | * jz4740_in_epn - handle IN interrupt |
857 | */ |
858 | static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
859 | { |
860 | uint32_t csr; |
861 | struct jz4740_ep *ep = &dev->ep[ep_idx + 1]; |
862 | struct jz4740_request *req; |
863 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
864 | |
865 | jz_udc_set_index(dev, ep_index(ep)); |
866 | |
867 | csr = usb_readb(dev, ep->csr); |
868 | DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr); |
869 | |
870 | if (csr & USB_INCSR_SENTSTALL) { |
871 | DEBUG("USB_INCSR_SENTSTALL\n"); |
872 | usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL); |
873 | return; |
874 | } |
875 | |
876 | if (!ep->desc) { |
877 | DEBUG("%s: NO EP DESC\n", __FUNCTION__); |
878 | return; |
879 | } |
880 | |
881 | if (list_empty(&ep->queue)) |
882 | req = 0; |
883 | else |
884 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
885 | |
886 | DEBUG("req: %p\n", req); |
887 | |
888 | if (!req) |
889 | return; |
890 | |
891 | write_fifo(ep, req); |
892 | } |
893 | |
894 | /* |
895 | * Bulk OUT (recv) |
896 | */ |
897 | static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
898 | { |
899 | struct jz4740_ep *ep = &dev->ep[ep_idx]; |
900 | struct jz4740_request *req; |
901 | |
902 | DEBUG("%s: %d\n", __FUNCTION__, ep_idx); |
903 | |
904 | jz_udc_set_index(dev, ep_index(ep)); |
905 | if (ep->desc) { |
906 | uint32_t csr; |
907 | |
908 | if (use_dma) { |
909 | /* DMA starts here ... */ |
910 | if (list_empty(&ep->queue)) |
911 | req = 0; |
912 | else |
913 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
914 | |
915 | if (req) |
916 | read_fifo(ep, req); |
917 | return; |
918 | } |
919 | |
920 | /* |
921 | * PIO mode starts here ... |
922 | */ |
923 | |
924 | while ((csr = usb_readb(dev, ep->csr)) & |
925 | (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) { |
926 | DEBUG("%s: %x\n", __FUNCTION__, csr); |
927 | |
928 | if (csr & USB_OUTCSR_SENTSTALL) { |
929 | DEBUG("%s: stall sent, flush fifo\n", |
930 | __FUNCTION__); |
931 | /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */ |
932 | flush(ep); |
933 | } else if (csr & USB_OUTCSR_OUTPKTRDY) { |
934 | if (list_empty(&ep->queue)) |
935 | req = 0; |
936 | else |
937 | req = |
938 | list_entry(ep->queue.next, |
939 | struct jz4740_request, |
940 | queue); |
941 | |
942 | if (!req) { |
943 | DEBUG("%s: NULL REQ %d\n", |
944 | __FUNCTION__, ep_idx); |
945 | break; |
946 | } else { |
947 | read_fifo(ep, req); |
948 | } |
949 | } |
950 | } |
951 | } else { |
952 | /* Throw packet away.. */ |
953 | DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx); |
954 | flush(ep); |
955 | } |
956 | } |
957 | |
958 | /** Halt specific EP |
959 | * Return 0 if success |
960 | * NOTE: Sets INDEX register to EP ! |
961 | */ |
962 | static int jz4740_set_halt(struct usb_ep *_ep, int value) |
963 | { |
964 | struct jz4740_udc *dev; |
965 | struct jz4740_ep *ep; |
966 | unsigned long flags; |
967 | |
968 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
969 | |
970 | ep = container_of(_ep, struct jz4740_ep, ep); |
971 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
972 | DEBUG("%s, bad ep\n", __FUNCTION__); |
973 | return -EINVAL; |
974 | } |
975 | |
976 | dev = ep->dev; |
977 | |
978 | spin_lock_irqsave(&dev->lock, flags); |
979 | |
980 | jz_udc_select_ep(ep); |
981 | |
982 | DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value); |
983 | |
984 | if (ep_index(ep) == 0) { |
985 | /* EP0 */ |
986 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL); |
987 | } else if (ep_is_in(ep)) { |
988 | uint32_t csr = usb_readb(dev, ep->csr); |
989 | if (value && ((csr & USB_INCSR_FFNOTEMPT) |
990 | || !list_empty(&ep->queue))) { |
991 | /* |
992 | * Attempts to halt IN endpoints will fail (returning -EAGAIN) |
993 | * if any transfer requests are still queued, or if the controller |
994 | * FIFO still holds bytes that the host hasnÂ’t collected. |
995 | */ |
996 | spin_unlock_irqrestore(&dev->lock, flags); |
997 | DEBUG |
998 | ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n", |
999 | (csr & USB_INCSR_FFNOTEMPT), |
1000 | !list_empty(&ep->queue)); |
1001 | return -EAGAIN; |
1002 | } |
1003 | flush(ep); |
1004 | if (value) { |
1005 | usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL); |
1006 | } |
1007 | else { |
1008 | usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL); |
1009 | usb_setb(dev, ep->csr, USB_INCSR_CDT); |
1010 | } |
1011 | } else { |
1012 | |
1013 | flush(ep); |
1014 | if (value) { |
1015 | usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
1016 | } |
1017 | else { |
1018 | usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
1019 | usb_setb(dev, ep->csr, USB_OUTCSR_CDT); |
1020 | } |
1021 | } |
1022 | |
1023 | if (value) { |
1024 | ep->stopped = 1; |
1025 | } else { |
1026 | ep->stopped = 0; |
1027 | } |
1028 | |
1029 | spin_unlock_irqrestore(&dev->lock, flags); |
1030 | |
1031 | DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS"); |
1032 | |
1033 | return 0; |
1034 | } |
1035 | |
1036 | |
1037 | static int jz4740_ep_enable(struct usb_ep *_ep, |
1038 | const struct usb_endpoint_descriptor *desc) |
1039 | { |
1040 | struct jz4740_ep *ep; |
1041 | struct jz4740_udc *dev; |
1042 | unsigned long flags; |
1043 | uint32_t max, csrh = 0; |
1044 | |
1045 | DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name); |
1046 | |
1047 | if (!_ep || !desc) |
1048 | return -EINVAL; |
1049 | |
1050 | ep = container_of(_ep, struct jz4740_ep, ep); |
1051 | if (ep->desc || ep->type == ep_control |
1052 | || desc->bDescriptorType != USB_DT_ENDPOINT |
1053 | || ep->bEndpointAddress != desc->bEndpointAddress) { |
1054 | DEBUG("%s, bad ep or descriptor\n", __FUNCTION__); |
1055 | return -EINVAL; |
1056 | } |
1057 | |
1058 | /* xfer types must match, except that interrupt ~= bulk */ |
1059 | if (ep->bmAttributes != desc->bmAttributes |
1060 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK |
1061 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { |
1062 | DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); |
1063 | return -EINVAL; |
1064 | } |
1065 | |
1066 | dev = ep->dev; |
1067 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { |
1068 | DEBUG("%s, bogus device state\n", __FUNCTION__); |
1069 | return -ESHUTDOWN; |
1070 | } |
1071 | |
1072 | max = le16_to_cpu(desc->wMaxPacketSize); |
1073 | |
1074 | spin_lock_irqsave(&ep->dev->lock, flags); |
1075 | |
1076 | /* Configure the endpoint */ |
1077 | jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F); |
1078 | if (ep_is_in(ep)) { |
1079 | usb_writew(dev, JZ_REG_UDC_INMAXP, max); |
1080 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
1081 | case USB_ENDPOINT_XFER_BULK: |
1082 | case USB_ENDPOINT_XFER_INT: |
1083 | csrh &= ~USB_INCSRH_ISO; |
1084 | break; |
1085 | case USB_ENDPOINT_XFER_ISOC: |
1086 | csrh |= USB_INCSRH_ISO; |
1087 | break; |
1088 | } |
1089 | usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh); |
1090 | } |
1091 | else { |
1092 | usb_writew(dev, JZ_REG_UDC_OUTMAXP, max); |
1093 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
1094 | case USB_ENDPOINT_XFER_BULK: |
1095 | csrh &= ~USB_OUTCSRH_ISO; |
1096 | break; |
1097 | case USB_ENDPOINT_XFER_INT: |
1098 | csrh &= ~USB_OUTCSRH_ISO; |
1099 | csrh |= USB_OUTCSRH_DNYT; |
1100 | break; |
1101 | case USB_ENDPOINT_XFER_ISOC: |
1102 | csrh |= USB_OUTCSRH_ISO; |
1103 | break; |
1104 | } |
1105 | usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh); |
1106 | } |
1107 | |
1108 | |
1109 | ep->stopped = 0; |
1110 | ep->desc = desc; |
1111 | ep->pio_irqs = 0; |
1112 | ep->ep.maxpacket = max; |
1113 | |
1114 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1115 | |
1116 | /* Reset halt state (does flush) */ |
1117 | jz4740_set_halt(_ep, 0); |
1118 | |
1119 | DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name); |
1120 | |
1121 | return 0; |
1122 | } |
1123 | |
1124 | /** Disable EP |
1125 | * NOTE: Sets INDEX register |
1126 | */ |
1127 | static int jz4740_ep_disable(struct usb_ep *_ep) |
1128 | { |
1129 | struct jz4740_ep *ep; |
1130 | unsigned long flags; |
1131 | |
1132 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1133 | |
1134 | ep = container_of(_ep, struct jz4740_ep, ep); |
1135 | if (!_ep || !ep->desc) { |
1136 | DEBUG("%s, %s not enabled\n", __FUNCTION__, |
1137 | _ep ? ep->ep.name : NULL); |
1138 | return -EINVAL; |
1139 | } |
1140 | |
1141 | spin_lock_irqsave(&ep->dev->lock, flags); |
1142 | |
1143 | jz_udc_select_ep(ep); |
1144 | |
1145 | /* Nuke all pending requests (does flush) */ |
1146 | nuke(ep, -ESHUTDOWN); |
1147 | |
1148 | /* Disable ep IRQ */ |
1149 | pio_irq_disable(ep); |
1150 | |
1151 | ep->desc = 0; |
1152 | ep->stopped = 1; |
1153 | |
1154 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1155 | |
1156 | DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name); |
1157 | return 0; |
1158 | } |
1159 | |
1160 | static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
1161 | { |
1162 | struct jz4740_request *req; |
1163 | |
1164 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
1165 | |
1166 | req = kzalloc(sizeof(*req), gfp_flags); |
1167 | if (!req) |
1168 | return 0; |
1169 | |
1170 | INIT_LIST_HEAD(&req->queue); |
1171 | |
1172 | return &req->req; |
1173 | } |
1174 | |
1175 | static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req) |
1176 | { |
1177 | struct jz4740_request *req; |
1178 | |
1179 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
1180 | |
1181 | req = container_of(_req, struct jz4740_request, req); |
1182 | WARN_ON(!list_empty(&req->queue)); |
1183 | kfree(req); |
1184 | } |
1185 | |
1186 | /*--------------------------------------------------------------------*/ |
1187 | |
1188 | /** Queue one request |
1189 | * Kickstart transfer if needed |
1190 | * NOTE: Sets INDEX register |
1191 | */ |
1192 | static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req, |
1193 | gfp_t gfp_flags) |
1194 | { |
1195 | struct jz4740_request *req; |
1196 | struct jz4740_ep *ep; |
1197 | struct jz4740_udc *dev; |
1198 | unsigned long flags; |
1199 | |
1200 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1201 | |
1202 | req = container_of(_req, struct jz4740_request, req); |
1203 | if (unlikely |
1204 | (!_req || !_req->complete || !_req->buf |
1205 | || !list_empty(&req->queue))) { |
1206 | DEBUG("%s, bad params\n", __FUNCTION__); |
1207 | return -EINVAL; |
1208 | } |
1209 | |
1210 | ep = container_of(_ep, struct jz4740_ep, ep); |
1211 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
1212 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1213 | return -EINVAL; |
1214 | } |
1215 | |
1216 | dev = ep->dev; |
1217 | if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { |
1218 | DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver); |
1219 | return -ESHUTDOWN; |
1220 | } |
1221 | |
1222 | DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length, |
1223 | _req->buf); |
1224 | |
1225 | spin_lock_irqsave(&dev->lock, flags); |
1226 | |
1227 | _req->status = -EINPROGRESS; |
1228 | _req->actual = 0; |
1229 | |
1230 | /* kickstart this i/o queue? */ |
1231 | DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue), |
1232 | ep->stopped); |
1233 | if (list_empty(&ep->queue) && likely(!ep->stopped)) { |
1234 | uint32_t csr; |
1235 | |
1236 | if (unlikely(ep_index(ep) == 0)) { |
1237 | /* EP0 */ |
1238 | list_add_tail(&req->queue, &ep->queue); |
1239 | jz4740_ep0_kick(dev, ep); |
1240 | req = 0; |
1241 | } else if (use_dma) { |
1242 | /* DMA */ |
1243 | kick_dma(ep, req); |
1244 | } |
1245 | /* PIO */ |
1246 | else if (ep_is_in(ep)) { |
1247 | /* EP1 & EP2 */ |
1248 | jz_udc_set_index(dev, ep_index(ep)); |
1249 | csr = usb_readb(dev, ep->csr); |
1250 | pio_irq_enable(ep); |
1251 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
1252 | if (write_fifo(ep, req) == 1) |
1253 | req = 0; |
1254 | } |
1255 | } else { |
1256 | /* EP1 */ |
1257 | jz_udc_set_index(dev, ep_index(ep)); |
1258 | csr = usb_readb(dev, ep->csr); |
1259 | pio_irq_enable(ep); |
1260 | if (csr & USB_OUTCSR_OUTPKTRDY) { |
1261 | if (read_fifo(ep, req) == 1) |
1262 | req = 0; |
1263 | } |
1264 | } |
1265 | } |
1266 | |
1267 | /* pio or dma irq handler advances the queue. */ |
1268 | if (likely(req != 0)) |
1269 | list_add_tail(&req->queue, &ep->queue); |
1270 | |
1271 | spin_unlock_irqrestore(&dev->lock, flags); |
1272 | |
1273 | return 0; |
1274 | } |
1275 | |
1276 | /* dequeue JUST ONE request */ |
1277 | static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
1278 | { |
1279 | struct jz4740_ep *ep; |
1280 | struct jz4740_request *req; |
1281 | unsigned long flags; |
1282 | |
1283 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1284 | |
1285 | ep = container_of(_ep, struct jz4740_ep, ep); |
1286 | if (!_ep || ep->type == ep_control) |
1287 | return -EINVAL; |
1288 | |
1289 | spin_lock_irqsave(&ep->dev->lock, flags); |
1290 | |
1291 | /* make sure it's actually queued on this endpoint */ |
1292 | list_for_each_entry(req, &ep->queue, queue) { |
1293 | if (&req->req == _req) |
1294 | break; |
1295 | } |
1296 | if (&req->req != _req) { |
1297 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1298 | return -EINVAL; |
1299 | } |
1300 | done(ep, req, -ECONNRESET); |
1301 | |
1302 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1303 | return 0; |
1304 | } |
1305 | |
1306 | /** Return bytes in EP FIFO |
1307 | * NOTE: Sets INDEX register to EP |
1308 | */ |
1309 | static int jz4740_fifo_status(struct usb_ep *_ep) |
1310 | { |
1311 | uint32_t csr; |
1312 | int count = 0; |
1313 | struct jz4740_ep *ep; |
1314 | unsigned long flags; |
1315 | |
1316 | ep = container_of(_ep, struct jz4740_ep, ep); |
1317 | if (!_ep) { |
1318 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1319 | return -ENODEV; |
1320 | } |
1321 | |
1322 | DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep)); |
1323 | |
1324 | /* LPD can't report unclaimed bytes from IN fifos */ |
1325 | if (ep_is_in(ep)) |
1326 | return -EOPNOTSUPP; |
1327 | |
1328 | spin_lock_irqsave(&ep->dev->lock, flags); |
1329 | jz_udc_set_index(ep->dev, ep_index(ep)); |
1330 | |
1331 | csr = usb_readb(ep->dev, ep->csr); |
1332 | if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN || |
1333 | csr & 0x1) { |
1334 | count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1335 | } |
1336 | |
1337 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1338 | |
1339 | return count; |
1340 | } |
1341 | |
1342 | /** Flush EP FIFO |
1343 | * NOTE: Sets INDEX register to EP |
1344 | */ |
1345 | static void jz4740_fifo_flush(struct usb_ep *_ep) |
1346 | { |
1347 | struct jz4740_ep *ep; |
1348 | unsigned long flags; |
1349 | |
1350 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1351 | |
1352 | ep = container_of(_ep, struct jz4740_ep, ep); |
1353 | if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) { |
1354 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1355 | return; |
1356 | } |
1357 | |
1358 | spin_lock_irqsave(&ep->dev->lock, flags); |
1359 | |
1360 | jz_udc_set_index(ep->dev, ep_index(ep)); |
1361 | flush(ep); |
1362 | |
1363 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1364 | } |
1365 | |
1366 | /****************************************************************/ |
1367 | /* End Point 0 related functions */ |
1368 | /****************************************************************/ |
1369 | |
1370 | /* return: 0 = still running, 1 = completed, negative = errno */ |
1371 | static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1372 | { |
1373 | uint32_t max; |
1374 | unsigned count; |
1375 | int is_last; |
1376 | |
1377 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1378 | max = ep_maxpacket(ep); |
1379 | |
1380 | count = write_packet(ep, req, max); |
1381 | |
1382 | /* last packet is usually short (or a zlp) */ |
1383 | if (unlikely(count != max)) |
1384 | is_last = 1; |
1385 | else { |
1386 | if (likely(req->req.length != req->req.actual) || req->req.zero) |
1387 | is_last = 0; |
1388 | else |
1389 | is_last = 1; |
1390 | } |
1391 | |
1392 | DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__, |
1393 | ep->ep.name, count, |
1394 | is_last ? "/L" : "", req->req.length - req->req.actual, req); |
1395 | |
1396 | /* requests complete when all IN data is in the FIFO */ |
1397 | if (is_last) { |
1398 | done(ep, req, 0); |
1399 | return 1; |
1400 | } |
1401 | |
1402 | return 0; |
1403 | } |
1404 | |
1405 | static inline int jz4740_fifo_read(struct jz4740_ep *ep, |
1406 | unsigned char *cp, int max) |
1407 | { |
1408 | int bytes; |
1409 | int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1410 | |
1411 | if (count > max) |
1412 | count = max; |
1413 | bytes = count; |
1414 | while (count--) |
1415 | *cp++ = usb_readb(ep->dev, ep->fifo); |
1416 | |
1417 | return bytes; |
1418 | } |
1419 | |
1420 | static inline void jz4740_fifo_write(struct jz4740_ep *ep, |
1421 | unsigned char *cp, int count) |
1422 | { |
1423 | DEBUG("fifo_write: %d %d\n", ep_index(ep), count); |
1424 | while (count--) |
1425 | usb_writeb(ep->dev, ep->fifo, *cp++); |
1426 | } |
1427 | |
1428 | static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1429 | { |
1430 | struct jz4740_udc *dev = ep->dev; |
1431 | uint32_t csr; |
1432 | uint8_t *buf; |
1433 | unsigned bufferspace, count, is_short; |
1434 | |
1435 | DEBUG_EP0("%s\n", __FUNCTION__); |
1436 | |
1437 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1438 | if (!(csr & USB_CSR0_OUTPKTRDY)) |
1439 | return 0; |
1440 | |
1441 | buf = req->req.buf + req->req.actual; |
1442 | prefetchw(buf); |
1443 | bufferspace = req->req.length - req->req.actual; |
1444 | |
1445 | /* read all bytes from this packet */ |
1446 | if (likely(csr & USB_CSR0_OUTPKTRDY)) { |
1447 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
1448 | req->req.actual += min(count, bufferspace); |
1449 | } else /* zlp */ |
1450 | count = 0; |
1451 | |
1452 | is_short = (count < ep->ep.maxpacket); |
1453 | DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n", |
1454 | ep->ep.name, csr, count, |
1455 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
1456 | |
1457 | while (likely(count-- != 0)) { |
1458 | uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo); |
1459 | |
1460 | if (unlikely(bufferspace == 0)) { |
1461 | /* this happens when the driver's buffer |
1462 | * is smaller than what the host sent. |
1463 | * discard the extra data. |
1464 | */ |
1465 | if (req->req.status != -EOVERFLOW) |
1466 | DEBUG_EP0("%s overflow %d\n", ep->ep.name, |
1467 | count); |
1468 | req->req.status = -EOVERFLOW; |
1469 | } else { |
1470 | *buf++ = byte; |
1471 | bufferspace--; |
1472 | } |
1473 | } |
1474 | |
1475 | /* completion */ |
1476 | if (is_short || req->req.actual == req->req.length) { |
1477 | done(ep, req, 0); |
1478 | return 1; |
1479 | } |
1480 | |
1481 | /* finished that packet. the next one may be waiting... */ |
1482 | return 0; |
1483 | } |
1484 | |
1485 | /** |
1486 | * udc_set_address - set the USB address for this device |
1487 | * @address: |
1488 | * |
1489 | * Called from control endpoint function after it decodes a set address setup packet. |
1490 | */ |
1491 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address) |
1492 | { |
1493 | DEBUG_EP0("%s: %d\n", __FUNCTION__, address); |
1494 | |
1495 | dev->usb_address = address; |
1496 | usb_writeb(dev, JZ_REG_UDC_FADDR, address); |
1497 | } |
1498 | |
1499 | /* |
1500 | * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY) |
1501 | * - if error |
1502 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1503 | * - else |
1504 | * set USB_CSR0_SVDOUTPKTRDY bit |
1505 | if last set USB_CSR0_DATAEND bit |
1506 | */ |
1507 | static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart) |
1508 | { |
1509 | struct jz4740_request *req; |
1510 | struct jz4740_ep *ep = &dev->ep[0]; |
1511 | int ret; |
1512 | |
1513 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1514 | |
1515 | if (list_empty(&ep->queue)) |
1516 | req = 0; |
1517 | else |
1518 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1519 | |
1520 | if (req) { |
1521 | if (req->req.length == 0) { |
1522 | DEBUG_EP0("ZERO LENGTH OUT!\n"); |
1523 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1524 | dev->ep0state = WAIT_FOR_SETUP; |
1525 | return; |
1526 | } else if (kickstart) { |
1527 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY)); |
1528 | return; |
1529 | } |
1530 | ret = read_fifo_ep0(ep, req); |
1531 | if (ret) { |
1532 | /* Done! */ |
1533 | DEBUG_EP0("%s: finished, waiting for status\n", |
1534 | __FUNCTION__); |
1535 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1536 | dev->ep0state = WAIT_FOR_SETUP; |
1537 | } else { |
1538 | /* Not done yet.. */ |
1539 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1540 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1541 | } |
1542 | } else { |
1543 | DEBUG_EP0("NO REQ??!\n"); |
1544 | } |
1545 | } |
1546 | |
1547 | /* |
1548 | * DATA_STATE_XMIT |
1549 | */ |
1550 | static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr) |
1551 | { |
1552 | struct jz4740_request *req; |
1553 | struct jz4740_ep *ep = &dev->ep[0]; |
1554 | int ret, need_zlp = 0; |
1555 | |
1556 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1557 | |
1558 | if (list_empty(&ep->queue)) |
1559 | req = 0; |
1560 | else |
1561 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1562 | |
1563 | if (!req) { |
1564 | DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__); |
1565 | return 0; |
1566 | } |
1567 | |
1568 | if (req->req.length == 0) { |
1569 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1570 | dev->ep0state = WAIT_FOR_SETUP; |
1571 | return 1; |
1572 | } |
1573 | |
1574 | if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) { |
1575 | /* Next write will end with the packet size, */ |
1576 | /* so we need zero-length-packet */ |
1577 | need_zlp = 1; |
1578 | } |
1579 | |
1580 | ret = write_fifo_ep0(ep, req); |
1581 | |
1582 | if (ret == 1 && !need_zlp) { |
1583 | /* Last packet */ |
1584 | DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__); |
1585 | |
1586 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1587 | dev->ep0state = WAIT_FOR_SETUP; |
1588 | } else { |
1589 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1590 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1591 | } |
1592 | |
1593 | if (need_zlp) { |
1594 | DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__); |
1595 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1596 | dev->ep0state = DATA_STATE_NEED_ZLP; |
1597 | } |
1598 | |
1599 | return 1; |
1600 | } |
1601 | |
1602 | static int jz4740_handle_get_status(struct jz4740_udc *dev, |
1603 | struct usb_ctrlrequest *ctrl) |
1604 | { |
1605 | struct jz4740_ep *ep0 = &dev->ep[0]; |
1606 | struct jz4740_ep *qep; |
1607 | int reqtype = (ctrl->bRequestType & USB_RECIP_MASK); |
1608 | uint16_t val = 0; |
1609 | |
1610 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1611 | |
1612 | if (reqtype == USB_RECIP_INTERFACE) { |
1613 | /* This is not supported. |
1614 | * And according to the USB spec, this one does nothing.. |
1615 | * Just return 0 |
1616 | */ |
1617 | DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n"); |
1618 | } else if (reqtype == USB_RECIP_DEVICE) { |
1619 | DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n"); |
1620 | val |= (1 << 0); /* Self powered */ |
1621 | /*val |= (1<<1); *//* Remote wakeup */ |
1622 | } else if (reqtype == USB_RECIP_ENDPOINT) { |
1623 | int ep_num = (ctrl->wIndex & ~USB_DIR_IN); |
1624 | |
1625 | DEBUG_SETUP |
1626 | ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n", |
1627 | ep_num, ctrl->wLength); |
1628 | |
1629 | if (ctrl->wLength > 2 || ep_num > 3) |
1630 | return -EOPNOTSUPP; |
1631 | |
1632 | qep = &dev->ep[ep_num]; |
1633 | if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0) |
1634 | && ep_index(qep) != 0) { |
1635 | return -EOPNOTSUPP; |
1636 | } |
1637 | |
1638 | jz_udc_set_index(dev, ep_index(qep)); |
1639 | |
1640 | /* Return status on next IN token */ |
1641 | switch (qep->type) { |
1642 | case ep_control: |
1643 | val = |
1644 | (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) == |
1645 | USB_CSR0_SENDSTALL; |
1646 | break; |
1647 | case ep_bulk_in: |
1648 | case ep_interrupt: |
1649 | val = |
1650 | (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) == |
1651 | USB_INCSR_SENDSTALL; |
1652 | break; |
1653 | case ep_bulk_out: |
1654 | val = |
1655 | (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) == |
1656 | USB_OUTCSR_SENDSTALL; |
1657 | break; |
1658 | } |
1659 | |
1660 | /* Back to EP0 index */ |
1661 | jz_udc_set_index(dev, 0); |
1662 | |
1663 | DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num, |
1664 | ctrl->wIndex, val); |
1665 | } else { |
1666 | DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype); |
1667 | return -EOPNOTSUPP; |
1668 | } |
1669 | |
1670 | /* Clear "out packet ready" */ |
1671 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1672 | /* Put status to FIFO */ |
1673 | jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val)); |
1674 | /* Issue "In packet ready" */ |
1675 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1676 | |
1677 | return 0; |
1678 | } |
1679 | |
1680 | /* |
1681 | * WAIT_FOR_SETUP (OUTPKTRDY) |
1682 | * - read data packet from EP0 FIFO |
1683 | * - decode command |
1684 | * - if error |
1685 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1686 | * - else |
1687 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits |
1688 | */ |
1689 | static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr) |
1690 | { |
1691 | struct jz4740_ep *ep = &dev->ep[0]; |
1692 | struct usb_ctrlrequest ctrl; |
1693 | int i; |
1694 | |
1695 | DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr); |
1696 | |
1697 | /* Nuke all previous transfers */ |
1698 | nuke(ep, -EPROTO); |
1699 | |
1700 | /* read control req from fifo (8 bytes) */ |
1701 | jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8); |
1702 | |
1703 | DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n", |
1704 | ctrl.bRequestType, ctrl.bRequest, |
1705 | ctrl.wValue, ctrl.wIndex, ctrl.wLength); |
1706 | |
1707 | /* Set direction of EP0 */ |
1708 | if (likely(ctrl.bRequestType & USB_DIR_IN)) { |
1709 | ep->bEndpointAddress |= USB_DIR_IN; |
1710 | } else { |
1711 | ep->bEndpointAddress &= ~USB_DIR_IN; |
1712 | } |
1713 | |
1714 | /* Handle some SETUP packets ourselves */ |
1715 | switch (ctrl.bRequest) { |
1716 | case USB_REQ_SET_ADDRESS: |
1717 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1718 | break; |
1719 | |
1720 | DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue); |
1721 | udc_set_address(dev, ctrl.wValue); |
1722 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1723 | return; |
1724 | |
1725 | case USB_REQ_SET_CONFIGURATION: |
1726 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1727 | break; |
1728 | |
1729 | DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue); |
1730 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1731 | |
1732 | /* Enable RESUME and SUSPEND interrupts */ |
1733 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND)); |
1734 | break; |
1735 | |
1736 | case USB_REQ_SET_INTERFACE: |
1737 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1738 | break; |
1739 | |
1740 | DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue); |
1741 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1742 | break; |
1743 | |
1744 | case USB_REQ_GET_STATUS: |
1745 | if (jz4740_handle_get_status(dev, &ctrl) == 0) |
1746 | return; |
1747 | |
1748 | case USB_REQ_CLEAR_FEATURE: |
1749 | case USB_REQ_SET_FEATURE: |
1750 | if (ctrl.bRequestType == USB_RECIP_ENDPOINT) { |
1751 | struct jz4740_ep *qep; |
1752 | int ep_num = (ctrl.wIndex & 0x0f); |
1753 | |
1754 | /* Support only HALT feature */ |
1755 | if (ctrl.wValue != 0 || ctrl.wLength != 0 |
1756 | || ep_num > 3 || ep_num < 1) |
1757 | break; |
1758 | |
1759 | qep = &dev->ep[ep_num]; |
1760 | spin_unlock(&dev->lock); |
1761 | if (ctrl.bRequest == USB_REQ_SET_FEATURE) { |
1762 | DEBUG_SETUP("SET_FEATURE (%d)\n", |
1763 | ep_num); |
1764 | jz4740_set_halt(&qep->ep, 1); |
1765 | } else { |
1766 | DEBUG_SETUP("CLR_FEATURE (%d)\n", |
1767 | ep_num); |
1768 | jz4740_set_halt(&qep->ep, 0); |
1769 | } |
1770 | spin_lock(&dev->lock); |
1771 | |
1772 | jz_udc_set_index(dev, 0); |
1773 | |
1774 | /* Reply with a ZLP on next IN token */ |
1775 | usb_setb(dev, JZ_REG_UDC_CSR0, |
1776 | (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1777 | return; |
1778 | } |
1779 | break; |
1780 | |
1781 | default: |
1782 | break; |
1783 | } |
1784 | |
1785 | /* gadget drivers see class/vendor specific requests, |
1786 | * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, |
1787 | * and more. |
1788 | */ |
1789 | if (dev->driver) { |
1790 | /* device-2-host (IN) or no data setup command, process immediately */ |
1791 | spin_unlock(&dev->lock); |
1792 | |
1793 | i = dev->driver->setup(&dev->gadget, &ctrl); |
1794 | spin_lock(&dev->lock); |
1795 | |
1796 | if (unlikely(i < 0)) { |
1797 | /* setup processing failed, force stall */ |
1798 | DEBUG_SETUP |
1799 | (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n", |
1800 | i); |
1801 | jz_udc_set_index(dev, 0); |
1802 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL)); |
1803 | |
1804 | /* ep->stopped = 1; */ |
1805 | dev->ep0state = WAIT_FOR_SETUP; |
1806 | } |
1807 | else { |
1808 | DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength); |
1809 | /* if (!ctrl.wLength) { |
1810 | usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1811 | }*/ |
1812 | } |
1813 | } |
1814 | } |
1815 | |
1816 | /* |
1817 | * DATA_STATE_NEED_ZLP |
1818 | */ |
1819 | static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr) |
1820 | { |
1821 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1822 | |
1823 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1824 | dev->ep0state = WAIT_FOR_SETUP; |
1825 | } |
1826 | |
1827 | /* |
1828 | * handle ep0 interrupt |
1829 | */ |
1830 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr) |
1831 | { |
1832 | struct jz4740_ep *ep = &dev->ep[0]; |
1833 | uint32_t csr; |
1834 | |
1835 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1836 | /* Set index 0 */ |
1837 | jz_udc_set_index(dev, 0); |
1838 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1839 | |
1840 | DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]); |
1841 | |
1842 | /* |
1843 | * if SENT_STALL is set |
1844 | * - clear the SENT_STALL bit |
1845 | */ |
1846 | if (csr & USB_CSR0_SENTSTALL) { |
1847 | DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr); |
1848 | usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL); |
1849 | nuke(ep, -ECONNABORTED); |
1850 | dev->ep0state = WAIT_FOR_SETUP; |
1851 | return; |
1852 | } |
1853 | |
1854 | /* |
1855 | * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear |
1856 | * - fill EP0 FIFO |
1857 | * - if last packet |
1858 | * - set IN_PKT_RDY | DATA_END |
1859 | * - else |
1860 | * set IN_PKT_RDY |
1861 | */ |
1862 | if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) { |
1863 | DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n", |
1864 | __FUNCTION__); |
1865 | |
1866 | switch (dev->ep0state) { |
1867 | case DATA_STATE_XMIT: |
1868 | DEBUG_EP0("continue with DATA_STATE_XMIT\n"); |
1869 | jz4740_ep0_in(dev, csr); |
1870 | return; |
1871 | case DATA_STATE_NEED_ZLP: |
1872 | DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n"); |
1873 | jz4740_ep0_in_zlp(dev, csr); |
1874 | return; |
1875 | default: |
1876 | /* Stall? */ |
1877 | // DEBUG_EP0("Odd state!! state = %s\n", |
1878 | // state_names[dev->ep0state]); |
1879 | dev->ep0state = WAIT_FOR_SETUP; |
1880 | /* nuke(ep, 0); */ |
1881 | /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */ |
1882 | // break; |
1883 | return; |
1884 | } |
1885 | } |
1886 | |
1887 | /* |
1888 | * if SETUPEND is set |
1889 | * - abort the last transfer |
1890 | * - set SERVICED_SETUP_END_BIT |
1891 | */ |
1892 | if (csr & USB_CSR0_SETUPEND) { |
1893 | DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr); |
1894 | |
1895 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND); |
1896 | nuke(ep, 0); |
1897 | dev->ep0state = WAIT_FOR_SETUP; |
1898 | } |
1899 | |
1900 | /* |
1901 | * if USB_CSR0_OUTPKTRDY is set |
1902 | * - read data packet from EP0 FIFO |
1903 | * - decode command |
1904 | * - if error |
1905 | * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits |
1906 | * - else |
1907 | * set SVDOUTPKTRDY | DATAEND bits |
1908 | */ |
1909 | if (csr & USB_CSR0_OUTPKTRDY) { |
1910 | |
1911 | DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__, |
1912 | csr); |
1913 | |
1914 | switch (dev->ep0state) { |
1915 | case WAIT_FOR_SETUP: |
1916 | DEBUG_EP0("WAIT_FOR_SETUP\n"); |
1917 | jz4740_ep0_setup(dev, csr); |
1918 | break; |
1919 | |
1920 | case DATA_STATE_RECV: |
1921 | DEBUG_EP0("DATA_STATE_RECV\n"); |
1922 | jz4740_ep0_out(dev, csr, 0); |
1923 | break; |
1924 | |
1925 | default: |
1926 | /* send stall? */ |
1927 | DEBUG_EP0("strange state!! 2. send stall? state = %d\n", |
1928 | dev->ep0state); |
1929 | break; |
1930 | } |
1931 | } |
1932 | } |
1933 | |
1934 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep) |
1935 | { |
1936 | uint32_t csr; |
1937 | |
1938 | jz_udc_set_index(dev, 0); |
1939 | |
1940 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1941 | |
1942 | /* Clear "out packet ready" */ |
1943 | |
1944 | if (ep_is_in(ep)) { |
1945 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1946 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1947 | dev->ep0state = DATA_STATE_XMIT; |
1948 | jz4740_ep0_in(dev, csr); |
1949 | } else { |
1950 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1951 | dev->ep0state = DATA_STATE_RECV; |
1952 | jz4740_ep0_out(dev, csr, 1); |
1953 | } |
1954 | } |
1955 | |
1956 | /** Handle USB RESET interrupt |
1957 | */ |
1958 | static void jz4740_reset_irq(struct jz4740_udc *dev) |
1959 | { |
1960 | dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ? |
1961 | USB_SPEED_HIGH : USB_SPEED_FULL; |
1962 | |
1963 | DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address, |
1964 | (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" ); |
1965 | } |
1966 | |
1967 | /* |
1968 | * jz4740 usb device interrupt handler. |
1969 | */ |
1970 | static irqreturn_t jz4740_udc_irq(int irq, void *_dev) |
1971 | { |
1972 | struct jz4740_udc *dev = _dev; |
1973 | uint8_t index; |
1974 | |
1975 | uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */ |
1976 | uint32_t intr_in = usb_readw(dev, JZ_REG_UDC_INTRIN); |
1977 | uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT); |
1978 | uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR); |
1979 | |
1980 | if (!intr_usb && !intr_in && !intr_out && !intr_dma) |
1981 | return IRQ_HANDLED; |
1982 | |
1983 | |
1984 | DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n", |
1985 | intr_out, intr_in, intr_usb); |
1986 | |
1987 | spin_lock(&dev->lock); |
1988 | index = usb_readb(dev, JZ_REG_UDC_INDEX); |
1989 | |
1990 | /* Check for resume from suspend mode */ |
1991 | if ((intr_usb & USB_INTR_RESUME) && |
1992 | (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) { |
1993 | DEBUG("USB resume\n"); |
1994 | dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */ |
1995 | } |
1996 | |
1997 | /* Check for system interrupts */ |
1998 | if (intr_usb & USB_INTR_RESET) { |
1999 | DEBUG("USB reset\n"); |
2000 | jz4740_reset_irq(dev); |
2001 | } |
2002 | |
2003 | /* Check for endpoint 0 interrupt */ |
2004 | if (intr_in & USB_INTR_EP0) { |
2005 | DEBUG("USB_INTR_EP0 (control)\n"); |
2006 | jz4740_handle_ep0(dev, intr_in); |
2007 | } |
2008 | |
2009 | /* Check for Bulk-IN DMA interrupt */ |
2010 | if (intr_dma & 0x1) { |
2011 | int ep_num; |
2012 | struct jz4740_ep *ep; |
2013 | ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf; |
2014 | ep = &dev->ep[ep_num + 1]; |
2015 | jz_udc_set_index(dev, ep_num); |
2016 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
2017 | /* jz4740_in_epn(dev, ep_num, intr_in);*/ |
2018 | } |
2019 | |
2020 | /* Check for Bulk-OUT DMA interrupt */ |
2021 | if (intr_dma & 0x2) { |
2022 | int ep_num; |
2023 | ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf; |
2024 | jz4740_out_epn(dev, ep_num, intr_out); |
2025 | } |
2026 | |
2027 | /* Check for each configured endpoint interrupt */ |
2028 | if (intr_in & USB_INTR_INEP1) { |
2029 | DEBUG("USB_INTR_INEP1\n"); |
2030 | jz4740_in_epn(dev, 1, intr_in); |
2031 | } |
2032 | |
2033 | if (intr_in & USB_INTR_INEP2) { |
2034 | DEBUG("USB_INTR_INEP2\n"); |
2035 | jz4740_in_epn(dev, 2, intr_in); |
2036 | } |
2037 | |
2038 | if (intr_out & USB_INTR_OUTEP1) { |
2039 | DEBUG("USB_INTR_OUTEP1\n"); |
2040 | jz4740_out_epn(dev, 1, intr_out); |
2041 | } |
2042 | |
2043 | /* Check for suspend mode */ |
2044 | if ((intr_usb & USB_INTR_SUSPEND) && |
2045 | (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) { |
2046 | DEBUG("USB suspend\n"); |
2047 | dev->driver->suspend(&dev->gadget); |
2048 | /* Host unloaded from us, can do something, such as flushing |
2049 | the NAND block cache etc. */ |
2050 | } |
2051 | |
2052 | jz_udc_set_index(dev, index); |
2053 | |
2054 | spin_unlock(&dev->lock); |
2055 | |
2056 | return IRQ_HANDLED; |
2057 | } |
2058 | |
2059 | |
2060 | |
2061 | /*-------------------------------------------------------------------------*/ |
2062 | |
2063 | /* Common functions - Added by River */ |
2064 | static struct jz4740_udc udc_dev; |
2065 | |
2066 | static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget) |
2067 | { |
2068 | return container_of(gadget, struct jz4740_udc, gadget); |
2069 | } |
2070 | /* End added */ |
2071 | |
2072 | static int jz4740_udc_get_frame(struct usb_gadget *_gadget) |
2073 | { |
2074 | DEBUG("%s, %p\n", __FUNCTION__, _gadget); |
2075 | return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME); |
2076 | } |
2077 | |
2078 | static int jz4740_udc_wakeup(struct usb_gadget *_gadget) |
2079 | { |
2080 | /* host may not have enabled remote wakeup */ |
2081 | /*if ((UDCCS0 & UDCCS0_DRWF) == 0) |
2082 | return -EHOSTUNREACH; |
2083 | udc_set_mask_UDCCR(UDCCR_RSM); */ |
2084 | return -ENOTSUPP; |
2085 | } |
2086 | |
2087 | static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on) |
2088 | { |
2089 | struct jz4740_udc *udc = gadget_to_udc(_gadget); |
2090 | |
2091 | unsigned long flags; |
2092 | |
2093 | local_irq_save(flags); |
2094 | |
2095 | if (on) { |
2096 | udc->state = UDC_STATE_ENABLE; |
2097 | udc_enable(udc); |
2098 | } else { |
2099 | udc->state = UDC_STATE_DISABLE; |
2100 | udc_disable(udc); |
2101 | } |
2102 | |
2103 | local_irq_restore(flags); |
2104 | |
2105 | return 0; |
2106 | } |
2107 | |
2108 | static const struct usb_gadget_ops jz4740_udc_ops = { |
2109 | .get_frame = jz4740_udc_get_frame, |
2110 | .wakeup = jz4740_udc_wakeup, |
2111 | .pullup = jz4740_udc_pullup, |
2112 | /* current versions must always be self-powered */ |
2113 | }; |
2114 | |
2115 | static struct usb_ep_ops jz4740_ep_ops = { |
2116 | .enable = jz4740_ep_enable, |
2117 | .disable = jz4740_ep_disable, |
2118 | |
2119 | .alloc_request = jz4740_alloc_request, |
2120 | .free_request = jz4740_free_request, |
2121 | |
2122 | .queue = jz4740_queue, |
2123 | .dequeue = jz4740_dequeue, |
2124 | |
2125 | .set_halt = jz4740_set_halt, |
2126 | .fifo_status = jz4740_fifo_status, |
2127 | .fifo_flush = jz4740_fifo_flush, |
2128 | }; |
2129 | |
2130 | |
2131 | /*-------------------------------------------------------------------------*/ |
2132 | |
2133 | static struct jz4740_udc udc_dev = { |
2134 | .usb_address = 0, |
2135 | .gadget = { |
2136 | .ops = &jz4740_udc_ops, |
2137 | .ep0 = &udc_dev.ep[0].ep, |
2138 | .name = "jz-udc", |
2139 | .dev = { |
2140 | .init_name = "gadget", |
2141 | }, |
2142 | }, |
2143 | |
2144 | /* control endpoint */ |
2145 | .ep[0] = { |
2146 | .ep = { |
2147 | .name = "ep0", |
2148 | .ops = &jz4740_ep_ops, |
2149 | .maxpacket = EP0_MAXPACKETSIZE, |
2150 | }, |
2151 | .dev = &udc_dev, |
2152 | |
2153 | .bEndpointAddress = 0, |
2154 | .bmAttributes = 0, |
2155 | |
2156 | .type = ep_control, |
2157 | .fifo = JZ_REG_UDC_EP_FIFO(0), |
2158 | .csr = JZ_REG_UDC_CSR0, |
2159 | }, |
2160 | |
2161 | /* bulk out endpoint */ |
2162 | .ep[1] = { |
2163 | .ep = { |
2164 | .name = "ep1out-bulk", |
2165 | .ops = &jz4740_ep_ops, |
2166 | .maxpacket = EPBULK_MAXPACKETSIZE, |
2167 | }, |
2168 | .dev = &udc_dev, |
2169 | |
2170 | .bEndpointAddress = 1, |
2171 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2172 | |
2173 | .type = ep_bulk_out, |
2174 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2175 | .csr = JZ_REG_UDC_OUTCSR, |
2176 | }, |
2177 | |
2178 | /* bulk in endpoint */ |
2179 | .ep[2] = { |
2180 | .ep = { |
2181 | .name = "ep1in-bulk", |
2182 | .ops = &jz4740_ep_ops, |
2183 | .maxpacket = EPBULK_MAXPACKETSIZE, |
2184 | }, |
2185 | .dev = &udc_dev, |
2186 | |
2187 | .bEndpointAddress = 1 | USB_DIR_IN, |
2188 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2189 | |
2190 | .type = ep_bulk_in, |
2191 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2192 | .csr = JZ_REG_UDC_INCSR, |
2193 | }, |
2194 | |
2195 | /* interrupt in endpoint */ |
2196 | .ep[3] = { |
2197 | .ep = { |
2198 | .name = "ep2in-int", |
2199 | .ops = &jz4740_ep_ops, |
2200 | .maxpacket = EPINTR_MAXPACKETSIZE, |
2201 | }, |
2202 | .dev = &udc_dev, |
2203 | |
2204 | .bEndpointAddress = 2 | USB_DIR_IN, |
2205 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2206 | |
2207 | .type = ep_interrupt, |
2208 | .fifo = JZ_REG_UDC_EP_FIFO(2), |
2209 | .csr = JZ_REG_UDC_INCSR, |
2210 | }, |
2211 | }; |
2212 | |
2213 | static void gadget_release(struct device *_dev) |
2214 | { |
2215 | } |
2216 | |
2217 | |
2218 | static int jz4740_udc_probe(struct platform_device *pdev) |
2219 | { |
2220 | struct jz4740_udc *dev = &udc_dev; |
2221 | int ret; |
2222 | |
2223 | spin_lock_init(&dev->lock); |
2224 | the_controller = dev; |
2225 | |
2226 | dev->dev = &pdev->dev; |
2227 | dev_set_name(&dev->gadget.dev, "gadget"); |
2228 | dev->gadget.dev.parent = &pdev->dev; |
2229 | dev->gadget.dev.dma_mask = pdev->dev.dma_mask; |
2230 | dev->gadget.dev.release = gadget_release; |
2231 | |
2232 | ret = device_register(&dev->gadget.dev); |
2233 | if (ret) |
2234 | return ret; |
2235 | |
2236 | platform_set_drvdata(pdev, dev); |
2237 | |
2238 | dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2239 | |
2240 | if (!dev->mem) { |
2241 | ret = -ENOENT; |
2242 | dev_err(&pdev->dev, "Failed to get mmio memory resource\n"); |
2243 | goto err_device_unregister; |
2244 | } |
2245 | |
2246 | dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name); |
2247 | |
2248 | if (!dev->mem) { |
2249 | ret = -EBUSY; |
2250 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
2251 | goto err_device_unregister; |
2252 | } |
2253 | |
2254 | dev->base = ioremap(dev->mem->start, resource_size(dev->mem)); |
2255 | |
2256 | if (!dev->base) { |
2257 | ret = -EBUSY; |
2258 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
2259 | goto err_release_mem_region; |
2260 | } |
2261 | |
2262 | dev->irq = platform_get_irq(pdev, 0); |
2263 | |
2264 | ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED, |
2265 | pdev->name, dev); |
2266 | if (ret) { |
2267 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
2268 | goto err_iounmap; |
2269 | } |
2270 | |
2271 | udc_disable(dev); |
2272 | udc_reinit(dev); |
2273 | |
2274 | return 0; |
2275 | |
2276 | err_iounmap: |
2277 | iounmap(dev->base); |
2278 | err_release_mem_region: |
2279 | release_mem_region(dev->mem->start, resource_size(dev->mem)); |
2280 | err_device_unregister: |
2281 | device_unregister(&dev->gadget.dev); |
2282 | platform_set_drvdata(pdev, NULL); |
2283 | |
2284 | the_controller = 0; |
2285 | |
2286 | return ret; |
2287 | } |
2288 | |
2289 | static int jz4740_udc_remove(struct platform_device *pdev) |
2290 | { |
2291 | struct jz4740_udc *dev = platform_get_drvdata(pdev); |
2292 | |
2293 | if (dev->driver) |
2294 | return -EBUSY; |
2295 | |
2296 | udc_disable(dev); |
2297 | #ifdef UDC_PROC_FILE |
2298 | remove_proc_entry(proc_node_name, NULL); |
2299 | #endif |
2300 | |
2301 | free_irq(dev->irq, dev); |
2302 | iounmap(dev->base); |
2303 | release_mem_region(dev->mem->start, resource_size(dev->mem)); |
2304 | |
2305 | platform_set_drvdata(pdev, NULL); |
2306 | device_unregister(&dev->gadget.dev); |
2307 | the_controller = NULL; |
2308 | |
2309 | return 0; |
2310 | } |
2311 | |
2312 | static struct platform_driver udc_driver = { |
2313 | .probe = jz4740_udc_probe, |
2314 | .remove = jz4740_udc_remove, |
2315 | .driver = { |
2316 | .name = "jz-udc", |
2317 | .owner = THIS_MODULE, |
2318 | }, |
2319 | }; |
2320 | |
2321 | /*-------------------------------------------------------------------------*/ |
2322 | |
2323 | static int __init udc_init (void) |
2324 | { |
2325 | return platform_driver_register(&udc_driver); |
2326 | } |
2327 | |
2328 | static void __exit udc_exit (void) |
2329 | { |
2330 | platform_driver_unregister(&udc_driver); |
2331 | } |
2332 | |
2333 | module_init(udc_init); |
2334 | module_exit(udc_exit); |
2335 | |
2336 | MODULE_DESCRIPTION("JZ4740 USB Device Controller"); |
2337 | MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>"); |
2338 | MODULE_LICENSE("GPL"); |
2339 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9