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Source at commit f39709ba061049463b1a607369e476512da9ec5b created 13 years 10 months ago. By Lars-Peter Clausen, Add jz4740 udc driver | |
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1 | /* |
2 | * linux/drivers/usb/gadget/jz4740_udc.c |
3 | * |
4 | * Ingenic JZ4740 on-chip high speed USB device controller |
5 | * |
6 | * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc. |
7 | * Author: <jlwei@ingenic.cn> |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or |
12 | * (at your option) any later version. |
13 | */ |
14 | |
15 | /* |
16 | * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint. |
17 | * |
18 | * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk. |
19 | * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints. |
20 | */ |
21 | |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> |
24 | #include <linux/platform_device.h> |
25 | #include <linux/delay.h> |
26 | #include <linux/ioport.h> |
27 | #include <linux/slab.h> |
28 | #include <linux/errno.h> |
29 | #include <linux/init.h> |
30 | #include <linux/list.h> |
31 | #include <linux/interrupt.h> |
32 | #include <linux/proc_fs.h> |
33 | #include <linux/usb.h> |
34 | #include <linux/usb/gadget.h> |
35 | #include <linux/clk.h> |
36 | |
37 | #include <asm/byteorder.h> |
38 | #include <asm/io.h> |
39 | #include <asm/irq.h> |
40 | #include <asm/system.h> |
41 | #include <asm/mach-jz4740/clock.h> |
42 | |
43 | #include "jz4740_udc.h" |
44 | |
45 | #define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */ |
46 | #define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */ |
47 | #define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */ |
48 | #define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */ |
49 | #define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */ |
50 | #define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */ |
51 | #define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */ |
52 | #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */ |
53 | #define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */ |
54 | #define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */ |
55 | #define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */ |
56 | |
57 | #define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */ |
58 | #define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */ |
59 | #define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */ |
60 | #define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */ |
61 | #define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */ |
62 | #define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */ |
63 | #define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */ |
64 | #define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */ |
65 | |
66 | #define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20) |
67 | |
68 | #define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */ |
69 | #define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */ |
70 | |
71 | #define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */ |
72 | #define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */ |
73 | #define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */ |
74 | #define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */ |
75 | #define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */ |
76 | #define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */ |
77 | #define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */ |
78 | |
79 | /* Power register bit masks */ |
80 | #define USB_POWER_SUSPENDM 0x01 |
81 | #define USB_POWER_RESUME 0x04 |
82 | #define USB_POWER_HSMODE 0x10 |
83 | #define USB_POWER_HSENAB 0x20 |
84 | #define USB_POWER_SOFTCONN 0x40 |
85 | |
86 | /* Interrupt register bit masks */ |
87 | #define USB_INTR_SUSPEND 0x01 |
88 | #define USB_INTR_RESUME 0x02 |
89 | #define USB_INTR_RESET 0x04 |
90 | |
91 | #define USB_INTR_EP0 0x0001 |
92 | #define USB_INTR_INEP1 0x0002 |
93 | #define USB_INTR_INEP2 0x0004 |
94 | #define USB_INTR_OUTEP1 0x0002 |
95 | |
96 | /* CSR0 bit masks */ |
97 | #define USB_CSR0_OUTPKTRDY 0x01 |
98 | #define USB_CSR0_INPKTRDY 0x02 |
99 | #define USB_CSR0_SENTSTALL 0x04 |
100 | #define USB_CSR0_DATAEND 0x08 |
101 | #define USB_CSR0_SETUPEND 0x10 |
102 | #define USB_CSR0_SENDSTALL 0x20 |
103 | #define USB_CSR0_SVDOUTPKTRDY 0x40 |
104 | #define USB_CSR0_SVDSETUPEND 0x80 |
105 | |
106 | /* Endpoint CSR register bits */ |
107 | #define USB_INCSRH_AUTOSET 0x80 |
108 | #define USB_INCSRH_ISO 0x40 |
109 | #define USB_INCSRH_MODE 0x20 |
110 | #define USB_INCSRH_DMAREQENAB 0x10 |
111 | #define USB_INCSRH_DMAREQMODE 0x04 |
112 | #define USB_INCSR_CDT 0x40 |
113 | #define USB_INCSR_SENTSTALL 0x20 |
114 | #define USB_INCSR_SENDSTALL 0x10 |
115 | #define USB_INCSR_FF 0x08 |
116 | #define USB_INCSR_UNDERRUN 0x04 |
117 | #define USB_INCSR_FFNOTEMPT 0x02 |
118 | #define USB_INCSR_INPKTRDY 0x01 |
119 | #define USB_OUTCSRH_AUTOCLR 0x80 |
120 | #define USB_OUTCSRH_ISO 0x40 |
121 | #define USB_OUTCSRH_DMAREQENAB 0x20 |
122 | #define USB_OUTCSRH_DNYT 0x10 |
123 | #define USB_OUTCSRH_DMAREQMODE 0x08 |
124 | #define USB_OUTCSR_CDT 0x80 |
125 | #define USB_OUTCSR_SENTSTALL 0x40 |
126 | #define USB_OUTCSR_SENDSTALL 0x20 |
127 | #define USB_OUTCSR_FF 0x10 |
128 | #define USB_OUTCSR_DATAERR 0x08 |
129 | #define USB_OUTCSR_OVERRUN 0x04 |
130 | #define USB_OUTCSR_FFFULL 0x02 |
131 | #define USB_OUTCSR_OUTPKTRDY 0x01 |
132 | |
133 | /* DMA control bits */ |
134 | #define USB_CNTL_ENA 0x01 |
135 | #define USB_CNTL_DIR_IN 0x02 |
136 | #define USB_CNTL_MODE_1 0x04 |
137 | #define USB_CNTL_INTR_EN 0x08 |
138 | #define USB_CNTL_EP(n) ((n) << 4) |
139 | #define USB_CNTL_BURST_0 (0 << 9) |
140 | #define USB_CNTL_BURST_4 (1 << 9) |
141 | #define USB_CNTL_BURST_8 (2 << 9) |
142 | #define USB_CNTL_BURST_16 (3 << 9) |
143 | |
144 | |
145 | #ifndef DEBUG |
146 | # define DEBUG(fmt,args...) do {} while(0) |
147 | #endif |
148 | #ifndef DEBUG_EP0 |
149 | # define NO_STATES |
150 | # define DEBUG_EP0(fmt,args...) do {} while(0) |
151 | #endif |
152 | #ifndef DEBUG_SETUP |
153 | # define DEBUG_SETUP(fmt,args...) do {} while(0) |
154 | #endif |
155 | |
156 | static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */ |
157 | |
158 | module_param(use_dma, int, 0); |
159 | MODULE_PARM_DESC(use_dma, "DMA mode enable flag"); |
160 | |
161 | static struct jz4740_udc jz4740_udc_controller; |
162 | |
163 | /* |
164 | * Local declarations. |
165 | */ |
166 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep); |
167 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr); |
168 | |
169 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, |
170 | int status); |
171 | static void pio_irq_enable(struct jz4740_ep *ep); |
172 | static void pio_irq_disable(struct jz4740_ep *ep); |
173 | static void stop_activity(struct jz4740_udc *dev, |
174 | struct usb_gadget_driver *driver); |
175 | static void nuke(struct jz4740_ep *ep, int status); |
176 | static void flush(struct jz4740_ep *ep); |
177 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address); |
178 | |
179 | /*-------------------------------------------------------------------------*/ |
180 | |
181 | /* inline functions of register read/write/set/clear */ |
182 | |
183 | static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg) |
184 | { |
185 | return readb(udc->base + reg); |
186 | } |
187 | |
188 | static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg) |
189 | { |
190 | return readw(udc->base + reg); |
191 | } |
192 | |
193 | static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg) |
194 | { |
195 | return readl(udc->base + reg); |
196 | } |
197 | |
198 | static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val) |
199 | { |
200 | writeb(val, udc->base + reg); |
201 | } |
202 | |
203 | static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val) |
204 | { |
205 | writew(val, udc->base + reg); |
206 | } |
207 | |
208 | static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val) |
209 | { |
210 | writel(val, udc->base + reg); |
211 | } |
212 | |
213 | static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
214 | { |
215 | usb_writeb(udc, reg, usb_readb(udc, reg) | mask); |
216 | } |
217 | |
218 | static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
219 | { |
220 | usb_writew(udc, reg, usb_readw(udc, reg) | mask); |
221 | } |
222 | |
223 | static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
224 | { |
225 | usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask); |
226 | } |
227 | |
228 | static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
229 | { |
230 | usb_writew(udc, reg, usb_readw(udc, reg) & ~mask); |
231 | } |
232 | |
233 | /*-------------------------------------------------------------------------*/ |
234 | |
235 | static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index) |
236 | { |
237 | usb_writeb(udc, JZ_REG_UDC_INDEX, index); |
238 | } |
239 | |
240 | static inline void jz_udc_select_ep(struct jz4740_ep *ep) |
241 | { |
242 | jz_udc_set_index(ep->dev, ep_index(ep)); |
243 | } |
244 | |
245 | static inline int write_packet(struct jz4740_ep *ep, |
246 | struct jz4740_request *req, unsigned int count) |
247 | { |
248 | uint8_t *buf; |
249 | unsigned int length, nlong, nbyte; |
250 | void __iomem *fifo = ep->dev->base + ep->fifo; |
251 | |
252 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
253 | |
254 | buf = req->req.buf + req->req.actual; |
255 | prefetch(buf); |
256 | |
257 | length = req->req.length - req->req.actual; |
258 | if (length > count) |
259 | length = count; |
260 | req->req.actual += length; |
261 | |
262 | DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo); |
263 | |
264 | nlong = length >> 2; |
265 | nbyte = length & 0x3; |
266 | while (nlong--) { |
267 | writel(*((uint32_t *)buf), fifo); |
268 | buf += 4; |
269 | } |
270 | while (nbyte--) |
271 | writeb(*buf++, fifo); |
272 | |
273 | return length; |
274 | } |
275 | |
276 | static int read_packet(struct jz4740_ep *ep, |
277 | struct jz4740_request *req, unsigned int count) |
278 | { |
279 | uint8_t *buf; |
280 | unsigned int length, nlong, nbyte; |
281 | void __iomem *fifo = ep->dev->base + ep->fifo; |
282 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
283 | |
284 | buf = req->req.buf + req->req.actual; |
285 | prefetchw(buf); |
286 | |
287 | length = req->req.length - req->req.actual; |
288 | if (length > count) |
289 | length = count; |
290 | req->req.actual += length; |
291 | |
292 | DEBUG("Read %d, fifo %x\n", length, ep->fifo); |
293 | nlong = length >> 2; |
294 | nbyte = length & 0x3; |
295 | while (nlong--) { |
296 | *((uint32_t *)buf) = readl(fifo); |
297 | buf += 4; |
298 | } |
299 | while (nbyte--) |
300 | *buf++ = readb(fifo); |
301 | |
302 | return length; |
303 | } |
304 | |
305 | /*-------------------------------------------------------------------------*/ |
306 | |
307 | /* |
308 | * udc_disable - disable USB device controller |
309 | */ |
310 | static void udc_disable(struct jz4740_udc *dev) |
311 | { |
312 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
313 | |
314 | udc_set_address(dev, 0); |
315 | |
316 | /* Disable interrupts */ |
317 | usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
318 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
319 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0); |
320 | |
321 | /* Disable DMA */ |
322 | usb_writel(dev, JZ_REG_UDC_CNTL1, 0); |
323 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
324 | |
325 | /* Disconnect from usb */ |
326 | usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
327 | |
328 | /* Disable the USB PHY */ |
329 | clk_disable(dev->clk); |
330 | |
331 | dev->ep0state = WAIT_FOR_SETUP; |
332 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
333 | |
334 | return; |
335 | } |
336 | |
337 | /* |
338 | * udc_reinit - initialize software state |
339 | */ |
340 | static void udc_reinit(struct jz4740_udc *dev) |
341 | { |
342 | int i; |
343 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
344 | |
345 | /* device/ep0 records init */ |
346 | INIT_LIST_HEAD(&dev->gadget.ep_list); |
347 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); |
348 | dev->ep0state = WAIT_FOR_SETUP; |
349 | |
350 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
351 | struct jz4740_ep *ep = &dev->ep[i]; |
352 | |
353 | if (i != 0) |
354 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); |
355 | |
356 | INIT_LIST_HEAD(&ep->queue); |
357 | ep->desc = 0; |
358 | ep->stopped = 0; |
359 | } |
360 | } |
361 | |
362 | /* until it's enabled, this UDC should be completely invisible |
363 | * to any USB host. |
364 | */ |
365 | static void udc_enable(struct jz4740_udc *dev) |
366 | { |
367 | int i; |
368 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
369 | |
370 | /* UDC state is incorrect - Added by River */ |
371 | if (dev->state != UDC_STATE_ENABLE) { |
372 | return; |
373 | } |
374 | |
375 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
376 | |
377 | /* Flush FIFO for each */ |
378 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
379 | struct jz4740_ep *ep = &dev->ep[i]; |
380 | |
381 | jz_udc_set_index(dev, ep_index(ep)); |
382 | flush(ep); |
383 | } |
384 | |
385 | /* Set this bit to allow the UDC entering low-power mode when |
386 | * there are no actions on the USB bus. |
387 | * UDC still works during this bit was set. |
388 | */ |
389 | jz4740_clock_udc_enable_auto_suspend(); |
390 | |
391 | /* Enable the USB PHY */ |
392 | clk_enable(dev->clk); |
393 | |
394 | /* Disable interrupts */ |
395 | /* usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
396 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
397 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/ |
398 | |
399 | /* Enable interrupts */ |
400 | usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0); |
401 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET); |
402 | /* Don't enable rest of the interrupts */ |
403 | /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2); |
404 | usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */ |
405 | |
406 | /* Enable SUSPEND */ |
407 | /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */ |
408 | |
409 | /* Enable HS Mode */ |
410 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB); |
411 | |
412 | /* Let host detect UDC: |
413 | * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this |
414 | * transistor on and pull the USBDP pin HIGH. |
415 | */ |
416 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
417 | |
418 | return; |
419 | } |
420 | |
421 | /*-------------------------------------------------------------------------*/ |
422 | |
423 | /* keeping it simple: |
424 | * - one bus driver, initted first; |
425 | * - one function driver, initted second |
426 | */ |
427 | |
428 | /* |
429 | * Register entry point for the peripheral controller driver. |
430 | */ |
431 | |
432 | int usb_gadget_probe_driver(struct usb_gadget_driver *driver, |
433 | int (*bind)(struct usb_gadget *)) |
434 | { |
435 | struct jz4740_udc *dev = &jz4740_udc_controller; |
436 | int retval; |
437 | |
438 | if (!driver || !bind) |
439 | return -EINVAL; |
440 | |
441 | if (!dev) |
442 | return -ENODEV; |
443 | |
444 | if (dev->driver) |
445 | return -EBUSY; |
446 | |
447 | /* hook up the driver */ |
448 | dev->driver = driver; |
449 | dev->gadget.dev.driver = &driver->driver; |
450 | |
451 | retval = bind(&dev->gadget); |
452 | if (retval) { |
453 | DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name, |
454 | driver->driver.name, retval); |
455 | dev->driver = 0; |
456 | return retval; |
457 | } |
458 | |
459 | /* then enable host detection and ep0; and we're ready |
460 | * for set_configuration as well as eventual disconnect. |
461 | */ |
462 | udc_enable(dev); |
463 | |
464 | DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name, |
465 | driver->driver.name); |
466 | |
467 | return 0; |
468 | } |
469 | EXPORT_SYMBOL(usb_gadget_probe_driver); |
470 | |
471 | static void stop_activity(struct jz4740_udc *dev, |
472 | struct usb_gadget_driver *driver) |
473 | { |
474 | int i; |
475 | |
476 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
477 | |
478 | /* don't disconnect drivers more than once */ |
479 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) |
480 | driver = 0; |
481 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
482 | |
483 | /* prevent new request submissions, kill any outstanding requests */ |
484 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
485 | struct jz4740_ep *ep = &dev->ep[i]; |
486 | |
487 | ep->stopped = 1; |
488 | |
489 | jz_udc_set_index(dev, ep_index(ep)); |
490 | nuke(ep, -ESHUTDOWN); |
491 | } |
492 | |
493 | /* report disconnect; the driver is already quiesced */ |
494 | if (driver) { |
495 | spin_unlock(&dev->lock); |
496 | driver->disconnect(&dev->gadget); |
497 | spin_lock(&dev->lock); |
498 | } |
499 | |
500 | /* re-init driver-visible data structures */ |
501 | udc_reinit(dev); |
502 | } |
503 | |
504 | |
505 | /* |
506 | * Unregister entry point for the peripheral controller driver. |
507 | */ |
508 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
509 | { |
510 | struct jz4740_udc *dev = &jz4740_udc_controller; |
511 | unsigned long flags; |
512 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
513 | |
514 | if (!dev) |
515 | return -ENODEV; |
516 | if (!driver || driver != dev->driver) |
517 | return -EINVAL; |
518 | if (!driver->unbind) |
519 | return -EBUSY; |
520 | |
521 | spin_lock_irqsave(&dev->lock, flags); |
522 | dev->driver = 0; |
523 | stop_activity(dev, driver); |
524 | spin_unlock_irqrestore(&dev->lock, flags); |
525 | |
526 | driver->unbind(&dev->gadget); |
527 | |
528 | udc_disable(dev); |
529 | |
530 | DEBUG("unregistered driver '%s'\n", driver->driver.name); |
531 | |
532 | return 0; |
533 | } |
534 | |
535 | EXPORT_SYMBOL(usb_gadget_unregister_driver); |
536 | |
537 | /*-------------------------------------------------------------------------*/ |
538 | |
539 | /* |
540 | * Starting DMA using mode 1 |
541 | */ |
542 | static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req) |
543 | { |
544 | struct jz4740_udc *dev = ep->dev; |
545 | uint32_t count = req->req.length; |
546 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
547 | |
548 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
549 | |
550 | jz_udc_select_ep(ep); |
551 | |
552 | if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */ |
553 | ep->reg_addr = JZ_REG_UDC_ADDR1; |
554 | |
555 | dma_cache_wback_inv((unsigned long)req->req.buf, count); |
556 | |
557 | pio_irq_enable(ep); |
558 | |
559 | usb_writeb(dev, JZ_REG_UDC_INCSRH, |
560 | USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE); |
561 | |
562 | usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr); |
563 | usb_writel(dev, JZ_REG_UDC_COUNT1, count); |
564 | usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 | |
565 | USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep))); |
566 | } |
567 | else { /* Bulk-OUT transfer using DMA channel 2 */ |
568 | ep->reg_addr = JZ_REG_UDC_ADDR2; |
569 | |
570 | dma_cache_wback_inv((unsigned long)req->req.buf, count); |
571 | |
572 | pio_irq_enable(ep); |
573 | |
574 | usb_setb(dev, JZ_REG_UDC_OUTCSRH, |
575 | USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE); |
576 | |
577 | usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr); |
578 | usb_writel(dev, JZ_REG_UDC_COUNT2, count); |
579 | usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 | |
580 | USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep))); |
581 | } |
582 | } |
583 | |
584 | /*-------------------------------------------------------------------------*/ |
585 | |
586 | /** Write request to FIFO (max write == maxp size) |
587 | * Return: 0 = still running, 1 = completed, negative = errno |
588 | * NOTE: INDEX register must be set for EP |
589 | */ |
590 | static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
591 | { |
592 | struct jz4740_udc *dev = ep->dev; |
593 | uint32_t max, csr; |
594 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
595 | |
596 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
597 | max = le16_to_cpu(ep->desc->wMaxPacketSize); |
598 | |
599 | if (use_dma) { |
600 | uint32_t dma_count; |
601 | |
602 | /* DMA interrupt generated due to the last packet loaded into the FIFO */ |
603 | |
604 | dma_count = usb_readl(dev, ep->reg_addr) - physaddr; |
605 | req->req.actual += dma_count; |
606 | |
607 | if (dma_count % max) { |
608 | /* If the last packet is less than MAXP, set INPKTRDY manually */ |
609 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
610 | } |
611 | |
612 | done(ep, req, 0); |
613 | if (list_empty(&ep->queue)) { |
614 | pio_irq_disable(ep); |
615 | return 1; |
616 | } |
617 | else { |
618 | /* advance the request queue */ |
619 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
620 | kick_dma(ep, req); |
621 | return 0; |
622 | } |
623 | } |
624 | |
625 | /* |
626 | * PIO mode handling starts here ... |
627 | */ |
628 | |
629 | csr = usb_readb(dev, ep->csr); |
630 | |
631 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
632 | unsigned count; |
633 | int is_last, is_short; |
634 | |
635 | count = write_packet(ep, req, max); |
636 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
637 | |
638 | /* last packet is usually short (or a zlp) */ |
639 | if (unlikely(count != max)) |
640 | is_last = is_short = 1; |
641 | else { |
642 | if (likely(req->req.length != req->req.actual) |
643 | || req->req.zero) |
644 | is_last = 0; |
645 | else |
646 | is_last = 1; |
647 | /* interrupt/iso maxpacket may not fill the fifo */ |
648 | is_short = unlikely(max < ep_maxpacket(ep)); |
649 | } |
650 | |
651 | DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__, |
652 | ep->ep.name, count, |
653 | is_last ? "/L" : "", is_short ? "/S" : "", |
654 | req->req.length - req->req.actual, req); |
655 | |
656 | /* requests complete when all IN data is in the FIFO */ |
657 | if (is_last) { |
658 | done(ep, req, 0); |
659 | if (list_empty(&ep->queue)) { |
660 | pio_irq_disable(ep); |
661 | } |
662 | return 1; |
663 | } |
664 | } else { |
665 | DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep)); |
666 | } |
667 | |
668 | return 0; |
669 | } |
670 | |
671 | /** Read to request from FIFO (max read == bytes in fifo) |
672 | * Return: 0 = still running, 1 = completed, negative = errno |
673 | * NOTE: INDEX register must be set for EP |
674 | */ |
675 | static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
676 | { |
677 | struct jz4740_udc *dev = ep->dev; |
678 | uint32_t csr; |
679 | unsigned count, is_short; |
680 | |
681 | #if 0 |
682 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
683 | |
684 | if (use_dma) { |
685 | uint32_t dma_count; |
686 | |
687 | /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */ |
688 | |
689 | dma_count = usb_readl(dev, ep->reg_addr) - physaddr; |
690 | req->req.actual += dma_count; |
691 | |
692 | /* Disable interrupt and DMA */ |
693 | pio_irq_disable(ep); |
694 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
695 | |
696 | /* Read all bytes from this packet */ |
697 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
698 | count = read_packet(ep, req, count); |
699 | |
700 | if (count) { |
701 | /* If the last packet is greater than zero, clear OUTPKTRDY manually */ |
702 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
703 | } |
704 | done(ep, req, 0); |
705 | |
706 | if (!list_empty(&ep->queue)) { |
707 | /* advance the request queue */ |
708 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
709 | kick_dma(ep, req); |
710 | } |
711 | |
712 | return 1; |
713 | } |
714 | #endif |
715 | /* |
716 | * PIO mode handling starts here ... |
717 | */ |
718 | |
719 | /* make sure there's a packet in the FIFO. */ |
720 | csr = usb_readb(dev, ep->csr); |
721 | if (!(csr & USB_OUTCSR_OUTPKTRDY)) { |
722 | DEBUG("%s: Packet NOT ready!\n", __FUNCTION__); |
723 | return -EINVAL; |
724 | } |
725 | |
726 | /* read all bytes from this packet */ |
727 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
728 | |
729 | is_short = (count < ep->ep.maxpacket); |
730 | |
731 | count = read_packet(ep, req, count); |
732 | |
733 | DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n", |
734 | ep->ep.name, csr, count, |
735 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
736 | |
737 | /* Clear OutPktRdy */ |
738 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
739 | |
740 | /* completion */ |
741 | if (is_short || req->req.actual == req->req.length) { |
742 | done(ep, req, 0); |
743 | |
744 | if (list_empty(&ep->queue)) |
745 | pio_irq_disable(ep); |
746 | return 1; |
747 | } |
748 | |
749 | /* finished that packet. the next one may be waiting... */ |
750 | return 0; |
751 | } |
752 | |
753 | /* |
754 | * done - retire a request; caller blocked irqs |
755 | * INDEX register is preserved to keep same |
756 | */ |
757 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status) |
758 | { |
759 | unsigned int stopped = ep->stopped; |
760 | uint32_t index; |
761 | |
762 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
763 | list_del_init(&req->queue); |
764 | |
765 | if (likely(req->req.status == -EINPROGRESS)) |
766 | req->req.status = status; |
767 | else |
768 | status = req->req.status; |
769 | |
770 | if (status && status != -ESHUTDOWN) |
771 | DEBUG("complete %s req %p stat %d len %u/%u\n", |
772 | ep->ep.name, &req->req, status, |
773 | req->req.actual, req->req.length); |
774 | |
775 | /* don't modify queue heads during completion callback */ |
776 | ep->stopped = 1; |
777 | /* Read current index (completion may modify it) */ |
778 | index = usb_readb(ep->dev, JZ_REG_UDC_INDEX); |
779 | spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags); |
780 | |
781 | req->req.complete(&ep->ep, &req->req); |
782 | |
783 | spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags); |
784 | /* Restore index */ |
785 | jz_udc_set_index(ep->dev, index); |
786 | ep->stopped = stopped; |
787 | } |
788 | |
789 | /** Enable EP interrupt */ |
790 | static void pio_irq_enable(struct jz4740_ep *ep) |
791 | { |
792 | uint8_t index = ep_index(ep); |
793 | struct jz4740_udc *dev = ep->dev; |
794 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
795 | |
796 | if (ep_is_in(ep)) { |
797 | switch (index) { |
798 | case 1: |
799 | case 2: |
800 | usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index)); |
801 | break; |
802 | default: |
803 | DEBUG("Unknown endpoint: %d\n", index); |
804 | break; |
805 | } |
806 | } |
807 | else { |
808 | switch (index) { |
809 | case 1: |
810 | usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index)); |
811 | break; |
812 | default: |
813 | DEBUG("Unknown endpoint: %d\n", index); |
814 | break; |
815 | } |
816 | } |
817 | } |
818 | |
819 | /** Disable EP interrupt */ |
820 | static void pio_irq_disable(struct jz4740_ep *ep) |
821 | { |
822 | uint8_t index = ep_index(ep); |
823 | |
824 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
825 | |
826 | if (ep_is_in(ep)) { |
827 | switch (ep_index(ep)) { |
828 | case 1: |
829 | case 2: |
830 | usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index)); |
831 | break; |
832 | default: |
833 | DEBUG("Unknown endpoint: %d\n", index); |
834 | break; |
835 | } |
836 | } |
837 | else { |
838 | switch (ep_index(ep)) { |
839 | case 1: |
840 | usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index)); |
841 | break; |
842 | default: |
843 | DEBUG("Unknown endpoint: %d\n", index); |
844 | break; |
845 | } |
846 | } |
847 | } |
848 | |
849 | /* |
850 | * nuke - dequeue ALL requests |
851 | */ |
852 | static void nuke(struct jz4740_ep *ep, int status) |
853 | { |
854 | struct jz4740_request *req; |
855 | |
856 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
857 | |
858 | /* Flush FIFO */ |
859 | flush(ep); |
860 | |
861 | /* called with irqs blocked */ |
862 | while (!list_empty(&ep->queue)) { |
863 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
864 | done(ep, req, status); |
865 | } |
866 | |
867 | /* Disable IRQ if EP is enabled (has descriptor) */ |
868 | if (ep->desc) |
869 | pio_irq_disable(ep); |
870 | } |
871 | |
872 | /** Flush EP FIFO |
873 | * NOTE: INDEX register must be set before this call |
874 | */ |
875 | static void flush(struct jz4740_ep *ep) |
876 | { |
877 | DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name); |
878 | |
879 | switch (ep->type) { |
880 | case ep_bulk_in: |
881 | case ep_interrupt: |
882 | usb_setb(ep->dev, ep->csr, USB_INCSR_FF); |
883 | break; |
884 | case ep_bulk_out: |
885 | usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF); |
886 | break; |
887 | case ep_control: |
888 | break; |
889 | } |
890 | } |
891 | |
892 | /** |
893 | * jz4740_in_epn - handle IN interrupt |
894 | */ |
895 | static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
896 | { |
897 | uint32_t csr; |
898 | struct jz4740_ep *ep = &dev->ep[ep_idx + 1]; |
899 | struct jz4740_request *req; |
900 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
901 | |
902 | jz_udc_set_index(dev, ep_index(ep)); |
903 | |
904 | csr = usb_readb(dev, ep->csr); |
905 | DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr); |
906 | |
907 | if (csr & USB_INCSR_SENTSTALL) { |
908 | DEBUG("USB_INCSR_SENTSTALL\n"); |
909 | usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL); |
910 | return; |
911 | } |
912 | |
913 | if (!ep->desc) { |
914 | DEBUG("%s: NO EP DESC\n", __FUNCTION__); |
915 | return; |
916 | } |
917 | |
918 | if (!list_empty(&ep->queue)) { |
919 | req = list_first_entry(&ep->queue, struct jz4740_request, queue); |
920 | write_fifo(ep, req); |
921 | } |
922 | } |
923 | |
924 | /* |
925 | * Bulk OUT (recv) |
926 | */ |
927 | static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
928 | { |
929 | struct jz4740_ep *ep = &dev->ep[ep_idx]; |
930 | struct jz4740_request *req; |
931 | |
932 | DEBUG("%s: %d\n", __FUNCTION__, ep_idx); |
933 | |
934 | jz_udc_select_ep(ep); |
935 | if (ep->desc) { |
936 | uint32_t csr; |
937 | |
938 | if (use_dma) { |
939 | /* DMA starts here ... */ |
940 | if (!list_empty(&ep->queue)) { |
941 | req = list_first_entry(&ep->queue, struct jz4740_request, queue); |
942 | read_fifo(ep, req); |
943 | } |
944 | return; |
945 | } |
946 | |
947 | /* |
948 | * PIO mode starts here ... |
949 | */ |
950 | |
951 | while ((csr = usb_readb(dev, ep->csr)) & |
952 | (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) { |
953 | DEBUG("%s: %x\n", __FUNCTION__, csr); |
954 | |
955 | if (csr & USB_OUTCSR_SENTSTALL) { |
956 | DEBUG("%s: stall sent, flush fifo\n", |
957 | __FUNCTION__); |
958 | /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */ |
959 | flush(ep); |
960 | } else if (csr & USB_OUTCSR_OUTPKTRDY) { |
961 | if (list_empty(&ep->queue)) |
962 | req = 0; |
963 | else |
964 | req = |
965 | list_entry(ep->queue.next, |
966 | struct jz4740_request, |
967 | queue); |
968 | |
969 | if (!req) { |
970 | DEBUG("%s: NULL REQ %d\n", |
971 | __FUNCTION__, ep_idx); |
972 | break; |
973 | } else { |
974 | read_fifo(ep, req); |
975 | } |
976 | } |
977 | } |
978 | } else { |
979 | /* Throw packet away.. */ |
980 | DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx); |
981 | flush(ep); |
982 | } |
983 | } |
984 | |
985 | /** Halt specific EP |
986 | * Return 0 if success |
987 | * NOTE: Sets INDEX register to EP ! |
988 | */ |
989 | static int jz4740_set_halt(struct usb_ep *_ep, int value) |
990 | { |
991 | struct jz4740_udc *dev; |
992 | struct jz4740_ep *ep; |
993 | unsigned long flags; |
994 | |
995 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
996 | |
997 | ep = container_of(_ep, struct jz4740_ep, ep); |
998 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
999 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1000 | return -EINVAL; |
1001 | } |
1002 | |
1003 | dev = ep->dev; |
1004 | |
1005 | spin_lock_irqsave(&dev->lock, flags); |
1006 | |
1007 | jz_udc_select_ep(ep); |
1008 | |
1009 | DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value); |
1010 | |
1011 | if (ep_index(ep) == 0) { |
1012 | /* EP0 */ |
1013 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL); |
1014 | } else if (ep_is_in(ep)) { |
1015 | uint32_t csr = usb_readb(dev, ep->csr); |
1016 | if (value && ((csr & USB_INCSR_FFNOTEMPT) |
1017 | || !list_empty(&ep->queue))) { |
1018 | /* |
1019 | * Attempts to halt IN endpoints will fail (returning -EAGAIN) |
1020 | * if any transfer requests are still queued, or if the controller |
1021 | * FIFO still holds bytes that the host hasnÂ’t collected. |
1022 | */ |
1023 | spin_unlock_irqrestore(&dev->lock, flags); |
1024 | DEBUG |
1025 | ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n", |
1026 | (csr & USB_INCSR_FFNOTEMPT), |
1027 | !list_empty(&ep->queue)); |
1028 | return -EAGAIN; |
1029 | } |
1030 | flush(ep); |
1031 | if (value) { |
1032 | usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL); |
1033 | } else { |
1034 | usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL); |
1035 | usb_setb(dev, ep->csr, USB_INCSR_CDT); |
1036 | } |
1037 | } else { |
1038 | |
1039 | flush(ep); |
1040 | if (value) { |
1041 | usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
1042 | } else { |
1043 | usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
1044 | usb_setb(dev, ep->csr, USB_OUTCSR_CDT); |
1045 | } |
1046 | } |
1047 | |
1048 | ep->stopped = value; |
1049 | |
1050 | spin_unlock_irqrestore(&dev->lock, flags); |
1051 | |
1052 | DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS"); |
1053 | |
1054 | return 0; |
1055 | } |
1056 | |
1057 | |
1058 | static int jz4740_ep_enable(struct usb_ep *_ep, |
1059 | const struct usb_endpoint_descriptor *desc) |
1060 | { |
1061 | struct jz4740_ep *ep; |
1062 | struct jz4740_udc *dev; |
1063 | unsigned long flags; |
1064 | uint32_t max, csrh = 0; |
1065 | |
1066 | DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name); |
1067 | |
1068 | if (!_ep || !desc) |
1069 | return -EINVAL; |
1070 | |
1071 | ep = container_of(_ep, struct jz4740_ep, ep); |
1072 | if (ep->desc || ep->type == ep_control |
1073 | || desc->bDescriptorType != USB_DT_ENDPOINT |
1074 | || ep->bEndpointAddress != desc->bEndpointAddress) { |
1075 | DEBUG("%s, bad ep or descriptor\n", __FUNCTION__); |
1076 | return -EINVAL; |
1077 | } |
1078 | |
1079 | /* xfer types must match, except that interrupt ~= bulk */ |
1080 | if (ep->bmAttributes != desc->bmAttributes |
1081 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK |
1082 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { |
1083 | DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); |
1084 | return -EINVAL; |
1085 | } |
1086 | |
1087 | dev = ep->dev; |
1088 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { |
1089 | DEBUG("%s, bogus device state\n", __FUNCTION__); |
1090 | return -ESHUTDOWN; |
1091 | } |
1092 | |
1093 | max = le16_to_cpu(desc->wMaxPacketSize); |
1094 | |
1095 | spin_lock_irqsave(&ep->dev->lock, flags); |
1096 | |
1097 | /* Configure the endpoint */ |
1098 | jz_udc_select_ep(ep); |
1099 | if (ep_is_in(ep)) { |
1100 | usb_writew(dev, JZ_REG_UDC_INMAXP, max); |
1101 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
1102 | case USB_ENDPOINT_XFER_BULK: |
1103 | case USB_ENDPOINT_XFER_INT: |
1104 | csrh &= ~USB_INCSRH_ISO; |
1105 | break; |
1106 | case USB_ENDPOINT_XFER_ISOC: |
1107 | csrh |= USB_INCSRH_ISO; |
1108 | break; |
1109 | } |
1110 | usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh); |
1111 | } |
1112 | else { |
1113 | usb_writew(dev, JZ_REG_UDC_OUTMAXP, max); |
1114 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
1115 | case USB_ENDPOINT_XFER_BULK: |
1116 | csrh &= ~USB_OUTCSRH_ISO; |
1117 | break; |
1118 | case USB_ENDPOINT_XFER_INT: |
1119 | csrh &= ~USB_OUTCSRH_ISO; |
1120 | csrh |= USB_OUTCSRH_DNYT; |
1121 | break; |
1122 | case USB_ENDPOINT_XFER_ISOC: |
1123 | csrh |= USB_OUTCSRH_ISO; |
1124 | break; |
1125 | } |
1126 | usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh); |
1127 | } |
1128 | |
1129 | |
1130 | ep->stopped = 0; |
1131 | ep->desc = desc; |
1132 | ep->ep.maxpacket = max; |
1133 | |
1134 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1135 | |
1136 | /* Reset halt state (does flush) */ |
1137 | jz4740_set_halt(_ep, 0); |
1138 | |
1139 | DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name); |
1140 | |
1141 | return 0; |
1142 | } |
1143 | |
1144 | /** Disable EP |
1145 | * NOTE: Sets INDEX register |
1146 | */ |
1147 | static int jz4740_ep_disable(struct usb_ep *_ep) |
1148 | { |
1149 | struct jz4740_ep *ep; |
1150 | unsigned long flags; |
1151 | |
1152 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1153 | |
1154 | ep = container_of(_ep, struct jz4740_ep, ep); |
1155 | if (!_ep || !ep->desc) { |
1156 | DEBUG("%s, %s not enabled\n", __FUNCTION__, |
1157 | _ep ? ep->ep.name : NULL); |
1158 | return -EINVAL; |
1159 | } |
1160 | |
1161 | spin_lock_irqsave(&ep->dev->lock, flags); |
1162 | |
1163 | jz_udc_select_ep(ep); |
1164 | |
1165 | /* Nuke all pending requests (does flush) */ |
1166 | nuke(ep, -ESHUTDOWN); |
1167 | |
1168 | /* Disable ep IRQ */ |
1169 | pio_irq_disable(ep); |
1170 | |
1171 | ep->desc = 0; |
1172 | ep->stopped = 1; |
1173 | |
1174 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1175 | |
1176 | DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name); |
1177 | return 0; |
1178 | } |
1179 | |
1180 | static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
1181 | { |
1182 | struct jz4740_request *req; |
1183 | |
1184 | req = kzalloc(sizeof(*req), gfp_flags); |
1185 | if (!req) |
1186 | return NULL; |
1187 | |
1188 | INIT_LIST_HEAD(&req->queue); |
1189 | |
1190 | return &req->req; |
1191 | } |
1192 | |
1193 | static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req) |
1194 | { |
1195 | struct jz4740_request *req; |
1196 | |
1197 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
1198 | |
1199 | req = container_of(_req, struct jz4740_request, req); |
1200 | WARN_ON(!list_empty(&req->queue)); |
1201 | kfree(req); |
1202 | } |
1203 | |
1204 | /*--------------------------------------------------------------------*/ |
1205 | |
1206 | /** Queue one request |
1207 | * Kickstart transfer if needed |
1208 | * NOTE: Sets INDEX register |
1209 | */ |
1210 | static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req, |
1211 | gfp_t gfp_flags) |
1212 | { |
1213 | struct jz4740_request *req; |
1214 | struct jz4740_ep *ep; |
1215 | struct jz4740_udc *dev; |
1216 | |
1217 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1218 | |
1219 | req = container_of(_req, struct jz4740_request, req); |
1220 | if (unlikely |
1221 | (!_req || !_req->complete || !_req->buf |
1222 | || !list_empty(&req->queue))) { |
1223 | DEBUG("%s, bad params\n", __FUNCTION__); |
1224 | return -EINVAL; |
1225 | } |
1226 | |
1227 | ep = container_of(_ep, struct jz4740_ep, ep); |
1228 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
1229 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1230 | return -EINVAL; |
1231 | } |
1232 | |
1233 | dev = ep->dev; |
1234 | if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { |
1235 | DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver); |
1236 | return -ESHUTDOWN; |
1237 | } |
1238 | |
1239 | DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length, |
1240 | _req->buf); |
1241 | |
1242 | spin_lock_irqsave(&dev->lock, dev->lock_flags); |
1243 | |
1244 | _req->status = -EINPROGRESS; |
1245 | _req->actual = 0; |
1246 | |
1247 | /* kickstart this i/o queue? */ |
1248 | DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue), |
1249 | ep->stopped); |
1250 | if (list_empty(&ep->queue) && likely(!ep->stopped)) { |
1251 | uint32_t csr; |
1252 | |
1253 | if (unlikely(ep_index(ep) == 0)) { |
1254 | /* EP0 */ |
1255 | list_add_tail(&req->queue, &ep->queue); |
1256 | jz4740_ep0_kick(dev, ep); |
1257 | req = 0; |
1258 | } else if (use_dma) { |
1259 | /* DMA */ |
1260 | kick_dma(ep, req); |
1261 | } |
1262 | /* PIO */ |
1263 | else if (ep_is_in(ep)) { |
1264 | /* EP1 & EP2 */ |
1265 | jz_udc_select_ep(ep); |
1266 | csr = usb_readb(dev, ep->csr); |
1267 | pio_irq_enable(ep); |
1268 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
1269 | if (write_fifo(ep, req) == 1) |
1270 | req = 0; |
1271 | } |
1272 | } else { |
1273 | /* EP1 */ |
1274 | jz_udc_select_ep(ep); |
1275 | csr = usb_readb(dev, ep->csr); |
1276 | pio_irq_enable(ep); |
1277 | if (csr & USB_OUTCSR_OUTPKTRDY) { |
1278 | if (read_fifo(ep, req) == 1) |
1279 | req = 0; |
1280 | } |
1281 | } |
1282 | } |
1283 | |
1284 | /* pio or dma irq handler advances the queue. */ |
1285 | if (likely(req != 0)) |
1286 | list_add_tail(&req->queue, &ep->queue); |
1287 | |
1288 | spin_unlock_irqrestore(&dev->lock, dev->lock_flags); |
1289 | |
1290 | return 0; |
1291 | } |
1292 | |
1293 | /* dequeue JUST ONE request */ |
1294 | static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
1295 | { |
1296 | struct jz4740_ep *ep; |
1297 | struct jz4740_request *req; |
1298 | unsigned long flags; |
1299 | |
1300 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1301 | |
1302 | ep = container_of(_ep, struct jz4740_ep, ep); |
1303 | if (!_ep || ep->type == ep_control) |
1304 | return -EINVAL; |
1305 | |
1306 | spin_lock_irqsave(&ep->dev->lock, flags); |
1307 | |
1308 | /* make sure it's actually queued on this endpoint */ |
1309 | list_for_each_entry(req, &ep->queue, queue) { |
1310 | if (&req->req == _req) |
1311 | break; |
1312 | } |
1313 | if (&req->req != _req) { |
1314 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1315 | return -EINVAL; |
1316 | } |
1317 | done(ep, req, -ECONNRESET); |
1318 | |
1319 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1320 | return 0; |
1321 | } |
1322 | |
1323 | /** Return bytes in EP FIFO |
1324 | * NOTE: Sets INDEX register to EP |
1325 | */ |
1326 | static int jz4740_fifo_status(struct usb_ep *_ep) |
1327 | { |
1328 | uint32_t csr; |
1329 | int count = 0; |
1330 | struct jz4740_ep *ep; |
1331 | unsigned long flags; |
1332 | |
1333 | ep = container_of(_ep, struct jz4740_ep, ep); |
1334 | if (!_ep) { |
1335 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1336 | return -ENODEV; |
1337 | } |
1338 | |
1339 | DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep)); |
1340 | |
1341 | /* LPD can't report unclaimed bytes from IN fifos */ |
1342 | if (ep_is_in(ep)) |
1343 | return -EOPNOTSUPP; |
1344 | |
1345 | spin_lock_irqsave(&ep->dev->lock, flags); |
1346 | jz_udc_select_ep(ep); |
1347 | |
1348 | csr = usb_readb(ep->dev, ep->csr); |
1349 | if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN || |
1350 | csr & 0x1) { |
1351 | count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1352 | } |
1353 | |
1354 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1355 | |
1356 | return count; |
1357 | } |
1358 | |
1359 | /** Flush EP FIFO |
1360 | * NOTE: Sets INDEX register to EP |
1361 | */ |
1362 | static void jz4740_fifo_flush(struct usb_ep *_ep) |
1363 | { |
1364 | struct jz4740_ep *ep; |
1365 | unsigned long flags; |
1366 | |
1367 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1368 | |
1369 | ep = container_of(_ep, struct jz4740_ep, ep); |
1370 | if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) { |
1371 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1372 | return; |
1373 | } |
1374 | |
1375 | spin_lock_irqsave(&ep->dev->lock, flags); |
1376 | |
1377 | jz_udc_select_ep(ep); |
1378 | flush(ep); |
1379 | |
1380 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1381 | } |
1382 | |
1383 | /****************************************************************/ |
1384 | /* End Point 0 related functions */ |
1385 | /****************************************************************/ |
1386 | |
1387 | /* return: 0 = still running, 1 = completed, negative = errno */ |
1388 | static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1389 | { |
1390 | uint32_t max; |
1391 | unsigned count; |
1392 | int is_last; |
1393 | |
1394 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1395 | max = ep_maxpacket(ep); |
1396 | |
1397 | count = write_packet(ep, req, max); |
1398 | |
1399 | /* last packet is usually short (or a zlp) */ |
1400 | if (unlikely(count != max)) |
1401 | is_last = 1; |
1402 | else { |
1403 | if (likely(req->req.length != req->req.actual) || req->req.zero) |
1404 | is_last = 0; |
1405 | else |
1406 | is_last = 1; |
1407 | } |
1408 | |
1409 | DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__, |
1410 | ep->ep.name, count, |
1411 | is_last ? "/L" : "", req->req.length - req->req.actual, req); |
1412 | |
1413 | /* requests complete when all IN data is in the FIFO */ |
1414 | if (is_last) { |
1415 | done(ep, req, 0); |
1416 | return 1; |
1417 | } |
1418 | |
1419 | return 0; |
1420 | } |
1421 | |
1422 | static inline int jz4740_fifo_read(struct jz4740_ep *ep, |
1423 | unsigned char *cp, int max) |
1424 | { |
1425 | int bytes; |
1426 | int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1427 | |
1428 | if (count > max) |
1429 | count = max; |
1430 | bytes = count; |
1431 | while (count--) |
1432 | *cp++ = usb_readb(ep->dev, ep->fifo); |
1433 | |
1434 | return bytes; |
1435 | } |
1436 | |
1437 | static inline void jz4740_fifo_write(struct jz4740_ep *ep, |
1438 | unsigned char *cp, int count) |
1439 | { |
1440 | DEBUG("fifo_write: %d %d\n", ep_index(ep), count); |
1441 | while (count--) |
1442 | usb_writeb(ep->dev, ep->fifo, *cp++); |
1443 | } |
1444 | |
1445 | static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1446 | { |
1447 | struct jz4740_udc *dev = ep->dev; |
1448 | uint32_t csr; |
1449 | uint8_t *buf; |
1450 | unsigned bufferspace, count, is_short; |
1451 | |
1452 | DEBUG_EP0("%s\n", __FUNCTION__); |
1453 | |
1454 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1455 | if (!(csr & USB_CSR0_OUTPKTRDY)) |
1456 | return 0; |
1457 | |
1458 | buf = req->req.buf + req->req.actual; |
1459 | prefetchw(buf); |
1460 | bufferspace = req->req.length - req->req.actual; |
1461 | |
1462 | /* read all bytes from this packet */ |
1463 | if (likely(csr & USB_CSR0_OUTPKTRDY)) { |
1464 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
1465 | req->req.actual += min(count, bufferspace); |
1466 | } else /* zlp */ |
1467 | count = 0; |
1468 | |
1469 | is_short = (count < ep->ep.maxpacket); |
1470 | DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n", |
1471 | ep->ep.name, csr, count, |
1472 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
1473 | |
1474 | while (likely(count-- != 0)) { |
1475 | uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo); |
1476 | |
1477 | if (unlikely(bufferspace == 0)) { |
1478 | /* this happens when the driver's buffer |
1479 | * is smaller than what the host sent. |
1480 | * discard the extra data. |
1481 | */ |
1482 | if (req->req.status != -EOVERFLOW) |
1483 | DEBUG_EP0("%s overflow %d\n", ep->ep.name, |
1484 | count); |
1485 | req->req.status = -EOVERFLOW; |
1486 | } else { |
1487 | *buf++ = byte; |
1488 | bufferspace--; |
1489 | } |
1490 | } |
1491 | |
1492 | /* completion */ |
1493 | if (is_short || req->req.actual == req->req.length) { |
1494 | done(ep, req, 0); |
1495 | return 1; |
1496 | } |
1497 | |
1498 | /* finished that packet. the next one may be waiting... */ |
1499 | return 0; |
1500 | } |
1501 | |
1502 | /** |
1503 | * udc_set_address - set the USB address for this device |
1504 | * @address: |
1505 | * |
1506 | * Called from control endpoint function after it decodes a set address setup packet. |
1507 | */ |
1508 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address) |
1509 | { |
1510 | DEBUG_EP0("%s: %d\n", __FUNCTION__, address); |
1511 | |
1512 | usb_writeb(dev, JZ_REG_UDC_FADDR, address); |
1513 | } |
1514 | |
1515 | /* |
1516 | * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY) |
1517 | * - if error |
1518 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1519 | * - else |
1520 | * set USB_CSR0_SVDOUTPKTRDY bit |
1521 | if last set USB_CSR0_DATAEND bit |
1522 | */ |
1523 | static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart) |
1524 | { |
1525 | struct jz4740_request *req; |
1526 | struct jz4740_ep *ep = &dev->ep[0]; |
1527 | int ret; |
1528 | |
1529 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1530 | |
1531 | if (list_empty(&ep->queue)) |
1532 | req = 0; |
1533 | else |
1534 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1535 | |
1536 | if (req) { |
1537 | if (req->req.length == 0) { |
1538 | DEBUG_EP0("ZERO LENGTH OUT!\n"); |
1539 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1540 | dev->ep0state = WAIT_FOR_SETUP; |
1541 | return; |
1542 | } else if (kickstart) { |
1543 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY)); |
1544 | return; |
1545 | } |
1546 | ret = read_fifo_ep0(ep, req); |
1547 | if (ret) { |
1548 | /* Done! */ |
1549 | DEBUG_EP0("%s: finished, waiting for status\n", |
1550 | __FUNCTION__); |
1551 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1552 | dev->ep0state = WAIT_FOR_SETUP; |
1553 | } else { |
1554 | /* Not done yet.. */ |
1555 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1556 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1557 | } |
1558 | } else { |
1559 | DEBUG_EP0("NO REQ??!\n"); |
1560 | } |
1561 | } |
1562 | |
1563 | /* |
1564 | * DATA_STATE_XMIT |
1565 | */ |
1566 | static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr) |
1567 | { |
1568 | struct jz4740_request *req; |
1569 | struct jz4740_ep *ep = &dev->ep[0]; |
1570 | int ret, need_zlp = 0; |
1571 | |
1572 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1573 | |
1574 | if (list_empty(&ep->queue)) |
1575 | req = 0; |
1576 | else |
1577 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1578 | |
1579 | if (!req) { |
1580 | DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__); |
1581 | return 0; |
1582 | } |
1583 | |
1584 | if (req->req.length == 0) { |
1585 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1586 | dev->ep0state = WAIT_FOR_SETUP; |
1587 | return 1; |
1588 | } |
1589 | |
1590 | if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) { |
1591 | /* Next write will end with the packet size, */ |
1592 | /* so we need zero-length-packet */ |
1593 | need_zlp = 1; |
1594 | } |
1595 | |
1596 | ret = write_fifo_ep0(ep, req); |
1597 | |
1598 | if (ret == 1 && !need_zlp) { |
1599 | /* Last packet */ |
1600 | DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__); |
1601 | |
1602 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1603 | dev->ep0state = WAIT_FOR_SETUP; |
1604 | } else { |
1605 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1606 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1607 | } |
1608 | |
1609 | if (need_zlp) { |
1610 | DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__); |
1611 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1612 | dev->ep0state = DATA_STATE_NEED_ZLP; |
1613 | } |
1614 | |
1615 | return 1; |
1616 | } |
1617 | |
1618 | static int jz4740_handle_get_status(struct jz4740_udc *dev, |
1619 | struct usb_ctrlrequest *ctrl) |
1620 | { |
1621 | struct jz4740_ep *ep0 = &dev->ep[0]; |
1622 | struct jz4740_ep *qep; |
1623 | int reqtype = (ctrl->bRequestType & USB_RECIP_MASK); |
1624 | uint16_t val = 0; |
1625 | |
1626 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1627 | |
1628 | if (reqtype == USB_RECIP_INTERFACE) { |
1629 | /* This is not supported. |
1630 | * And according to the USB spec, this one does nothing.. |
1631 | * Just return 0 |
1632 | */ |
1633 | DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n"); |
1634 | } else if (reqtype == USB_RECIP_DEVICE) { |
1635 | DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n"); |
1636 | val |= (1 << 0); /* Self powered */ |
1637 | /*val |= (1<<1); *//* Remote wakeup */ |
1638 | } else if (reqtype == USB_RECIP_ENDPOINT) { |
1639 | int ep_num = (ctrl->wIndex & ~USB_DIR_IN); |
1640 | |
1641 | DEBUG_SETUP |
1642 | ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n", |
1643 | ep_num, ctrl->wLength); |
1644 | |
1645 | if (ctrl->wLength > 2 || ep_num > 3) |
1646 | return -EOPNOTSUPP; |
1647 | |
1648 | qep = &dev->ep[ep_num]; |
1649 | if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0) |
1650 | && ep_index(qep) != 0) { |
1651 | return -EOPNOTSUPP; |
1652 | } |
1653 | |
1654 | jz_udc_set_index(dev, ep_index(qep)); |
1655 | |
1656 | /* Return status on next IN token */ |
1657 | switch (qep->type) { |
1658 | case ep_control: |
1659 | val = |
1660 | (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) == |
1661 | USB_CSR0_SENDSTALL; |
1662 | break; |
1663 | case ep_bulk_in: |
1664 | case ep_interrupt: |
1665 | val = |
1666 | (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) == |
1667 | USB_INCSR_SENDSTALL; |
1668 | break; |
1669 | case ep_bulk_out: |
1670 | val = |
1671 | (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) == |
1672 | USB_OUTCSR_SENDSTALL; |
1673 | break; |
1674 | } |
1675 | |
1676 | /* Back to EP0 index */ |
1677 | jz_udc_set_index(dev, 0); |
1678 | |
1679 | DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num, |
1680 | ctrl->wIndex, val); |
1681 | } else { |
1682 | DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype); |
1683 | return -EOPNOTSUPP; |
1684 | } |
1685 | |
1686 | /* Clear "out packet ready" */ |
1687 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1688 | /* Put status to FIFO */ |
1689 | jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val)); |
1690 | /* Issue "In packet ready" */ |
1691 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1692 | |
1693 | return 0; |
1694 | } |
1695 | |
1696 | /* |
1697 | * WAIT_FOR_SETUP (OUTPKTRDY) |
1698 | * - read data packet from EP0 FIFO |
1699 | * - decode command |
1700 | * - if error |
1701 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1702 | * - else |
1703 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits |
1704 | */ |
1705 | static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr) |
1706 | { |
1707 | struct jz4740_ep *ep = &dev->ep[0]; |
1708 | struct usb_ctrlrequest ctrl; |
1709 | int i; |
1710 | |
1711 | DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr); |
1712 | |
1713 | /* Nuke all previous transfers */ |
1714 | nuke(ep, -EPROTO); |
1715 | |
1716 | /* read control req from fifo (8 bytes) */ |
1717 | jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8); |
1718 | |
1719 | DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n", |
1720 | ctrl.bRequestType, ctrl.bRequest, |
1721 | ctrl.wValue, ctrl.wIndex, ctrl.wLength); |
1722 | |
1723 | /* Set direction of EP0 */ |
1724 | if (likely(ctrl.bRequestType & USB_DIR_IN)) { |
1725 | ep->bEndpointAddress |= USB_DIR_IN; |
1726 | } else { |
1727 | ep->bEndpointAddress &= ~USB_DIR_IN; |
1728 | } |
1729 | |
1730 | /* Handle some SETUP packets ourselves */ |
1731 | switch (ctrl.bRequest) { |
1732 | case USB_REQ_SET_ADDRESS: |
1733 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1734 | break; |
1735 | |
1736 | DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue); |
1737 | udc_set_address(dev, ctrl.wValue); |
1738 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1739 | return; |
1740 | |
1741 | case USB_REQ_SET_CONFIGURATION: |
1742 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1743 | break; |
1744 | |
1745 | DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue); |
1746 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1747 | |
1748 | /* Enable RESUME and SUSPEND interrupts */ |
1749 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND)); |
1750 | break; |
1751 | |
1752 | case USB_REQ_SET_INTERFACE: |
1753 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1754 | break; |
1755 | |
1756 | DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue); |
1757 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1758 | break; |
1759 | |
1760 | case USB_REQ_GET_STATUS: |
1761 | if (jz4740_handle_get_status(dev, &ctrl) == 0) |
1762 | return; |
1763 | |
1764 | case USB_REQ_CLEAR_FEATURE: |
1765 | case USB_REQ_SET_FEATURE: |
1766 | if (ctrl.bRequestType == USB_RECIP_ENDPOINT) { |
1767 | struct jz4740_ep *qep; |
1768 | int ep_num = (ctrl.wIndex & 0x0f); |
1769 | |
1770 | /* Support only HALT feature */ |
1771 | if (ctrl.wValue != 0 || ctrl.wLength != 0 |
1772 | || ep_num > 3 || ep_num < 1) |
1773 | break; |
1774 | |
1775 | qep = &dev->ep[ep_num]; |
1776 | spin_unlock(&dev->lock); |
1777 | if (ctrl.bRequest == USB_REQ_SET_FEATURE) { |
1778 | DEBUG_SETUP("SET_FEATURE (%d)\n", |
1779 | ep_num); |
1780 | jz4740_set_halt(&qep->ep, 1); |
1781 | } else { |
1782 | DEBUG_SETUP("CLR_FEATURE (%d)\n", |
1783 | ep_num); |
1784 | jz4740_set_halt(&qep->ep, 0); |
1785 | } |
1786 | spin_lock(&dev->lock); |
1787 | |
1788 | jz_udc_set_index(dev, 0); |
1789 | |
1790 | /* Reply with a ZLP on next IN token */ |
1791 | usb_setb(dev, JZ_REG_UDC_CSR0, |
1792 | (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1793 | return; |
1794 | } |
1795 | break; |
1796 | |
1797 | default: |
1798 | break; |
1799 | } |
1800 | |
1801 | /* gadget drivers see class/vendor specific requests, |
1802 | * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, |
1803 | * and more. |
1804 | */ |
1805 | if (dev->driver) { |
1806 | /* device-2-host (IN) or no data setup command, process immediately */ |
1807 | spin_unlock(&dev->lock); |
1808 | |
1809 | i = dev->driver->setup(&dev->gadget, &ctrl); |
1810 | spin_lock(&dev->lock); |
1811 | |
1812 | if (unlikely(i < 0)) { |
1813 | /* setup processing failed, force stall */ |
1814 | DEBUG_SETUP |
1815 | (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n", |
1816 | i); |
1817 | jz_udc_set_index(dev, 0); |
1818 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL)); |
1819 | |
1820 | /* ep->stopped = 1; */ |
1821 | dev->ep0state = WAIT_FOR_SETUP; |
1822 | } |
1823 | else { |
1824 | DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength); |
1825 | /* if (!ctrl.wLength) { |
1826 | usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1827 | }*/ |
1828 | } |
1829 | } |
1830 | } |
1831 | |
1832 | /* |
1833 | * DATA_STATE_NEED_ZLP |
1834 | */ |
1835 | static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr) |
1836 | { |
1837 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1838 | |
1839 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1840 | dev->ep0state = WAIT_FOR_SETUP; |
1841 | } |
1842 | |
1843 | /* |
1844 | * handle ep0 interrupt |
1845 | */ |
1846 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr) |
1847 | { |
1848 | struct jz4740_ep *ep = &dev->ep[0]; |
1849 | uint32_t csr; |
1850 | |
1851 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1852 | /* Set index 0 */ |
1853 | jz_udc_set_index(dev, 0); |
1854 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1855 | |
1856 | DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]); |
1857 | |
1858 | /* |
1859 | * if SENT_STALL is set |
1860 | * - clear the SENT_STALL bit |
1861 | */ |
1862 | if (csr & USB_CSR0_SENTSTALL) { |
1863 | DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr); |
1864 | usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL); |
1865 | nuke(ep, -ECONNABORTED); |
1866 | dev->ep0state = WAIT_FOR_SETUP; |
1867 | return; |
1868 | } |
1869 | |
1870 | /* |
1871 | * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear |
1872 | * - fill EP0 FIFO |
1873 | * - if last packet |
1874 | * - set IN_PKT_RDY | DATA_END |
1875 | * - else |
1876 | * set IN_PKT_RDY |
1877 | */ |
1878 | if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) { |
1879 | DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n", |
1880 | __FUNCTION__); |
1881 | |
1882 | switch (dev->ep0state) { |
1883 | case DATA_STATE_XMIT: |
1884 | DEBUG_EP0("continue with DATA_STATE_XMIT\n"); |
1885 | jz4740_ep0_in(dev, csr); |
1886 | return; |
1887 | case DATA_STATE_NEED_ZLP: |
1888 | DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n"); |
1889 | jz4740_ep0_in_zlp(dev, csr); |
1890 | return; |
1891 | default: |
1892 | /* Stall? */ |
1893 | // DEBUG_EP0("Odd state!! state = %s\n", |
1894 | // state_names[dev->ep0state]); |
1895 | dev->ep0state = WAIT_FOR_SETUP; |
1896 | /* nuke(ep, 0); */ |
1897 | /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */ |
1898 | // break; |
1899 | return; |
1900 | } |
1901 | } |
1902 | |
1903 | /* |
1904 | * if SETUPEND is set |
1905 | * - abort the last transfer |
1906 | * - set SERVICED_SETUP_END_BIT |
1907 | */ |
1908 | if (csr & USB_CSR0_SETUPEND) { |
1909 | DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr); |
1910 | |
1911 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND); |
1912 | nuke(ep, 0); |
1913 | dev->ep0state = WAIT_FOR_SETUP; |
1914 | } |
1915 | |
1916 | /* |
1917 | * if USB_CSR0_OUTPKTRDY is set |
1918 | * - read data packet from EP0 FIFO |
1919 | * - decode command |
1920 | * - if error |
1921 | * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits |
1922 | * - else |
1923 | * set SVDOUTPKTRDY | DATAEND bits |
1924 | */ |
1925 | if (csr & USB_CSR0_OUTPKTRDY) { |
1926 | |
1927 | DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__, |
1928 | csr); |
1929 | |
1930 | switch (dev->ep0state) { |
1931 | case WAIT_FOR_SETUP: |
1932 | DEBUG_EP0("WAIT_FOR_SETUP\n"); |
1933 | jz4740_ep0_setup(dev, csr); |
1934 | break; |
1935 | |
1936 | case DATA_STATE_RECV: |
1937 | DEBUG_EP0("DATA_STATE_RECV\n"); |
1938 | jz4740_ep0_out(dev, csr, 0); |
1939 | break; |
1940 | |
1941 | default: |
1942 | /* send stall? */ |
1943 | DEBUG_EP0("strange state!! 2. send stall? state = %d\n", |
1944 | dev->ep0state); |
1945 | break; |
1946 | } |
1947 | } |
1948 | } |
1949 | |
1950 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep) |
1951 | { |
1952 | uint32_t csr; |
1953 | |
1954 | jz_udc_set_index(dev, 0); |
1955 | |
1956 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1957 | |
1958 | /* Clear "out packet ready" */ |
1959 | |
1960 | if (ep_is_in(ep)) { |
1961 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1962 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1963 | dev->ep0state = DATA_STATE_XMIT; |
1964 | jz4740_ep0_in(dev, csr); |
1965 | } else { |
1966 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1967 | dev->ep0state = DATA_STATE_RECV; |
1968 | jz4740_ep0_out(dev, csr, 1); |
1969 | } |
1970 | } |
1971 | |
1972 | /** Handle USB RESET interrupt |
1973 | */ |
1974 | static void jz4740_reset_irq(struct jz4740_udc *dev) |
1975 | { |
1976 | dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ? |
1977 | USB_SPEED_HIGH : USB_SPEED_FULL; |
1978 | |
1979 | DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0, |
1980 | (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" ); |
1981 | } |
1982 | |
1983 | /* |
1984 | * jz4740 usb device interrupt handler. |
1985 | */ |
1986 | static irqreturn_t jz4740_udc_irq(int irq, void *devid) |
1987 | { |
1988 | struct jz4740_udc *jz4740_udc = devid; |
1989 | uint8_t index; |
1990 | |
1991 | uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */ |
1992 | uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN); |
1993 | uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT); |
1994 | uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR); |
1995 | |
1996 | if (!intr_usb && !intr_in && !intr_out && !intr_dma) |
1997 | return IRQ_HANDLED; |
1998 | |
1999 | |
2000 | DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n", |
2001 | intr_out, intr_in, intr_usb); |
2002 | |
2003 | spin_lock(&jz4740_udc->lock); |
2004 | index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX); |
2005 | |
2006 | /* Check for resume from suspend mode */ |
2007 | if ((intr_usb & USB_INTR_RESUME) && |
2008 | (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) { |
2009 | DEBUG("USB resume\n"); |
2010 | jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */ |
2011 | } |
2012 | |
2013 | /* Check for system interrupts */ |
2014 | if (intr_usb & USB_INTR_RESET) { |
2015 | DEBUG("USB reset\n"); |
2016 | jz4740_reset_irq(jz4740_udc); |
2017 | } |
2018 | |
2019 | /* Check for endpoint 0 interrupt */ |
2020 | if (intr_in & USB_INTR_EP0) { |
2021 | DEBUG("USB_INTR_EP0 (control)\n"); |
2022 | jz4740_handle_ep0(jz4740_udc, intr_in); |
2023 | } |
2024 | |
2025 | /* Check for Bulk-IN DMA interrupt */ |
2026 | if (intr_dma & 0x1) { |
2027 | int ep_num; |
2028 | struct jz4740_ep *ep; |
2029 | ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf; |
2030 | ep = &jz4740_udc->ep[ep_num + 1]; |
2031 | jz_udc_set_index(jz4740_udc, ep_num); |
2032 | usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY); |
2033 | /* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/ |
2034 | } |
2035 | |
2036 | /* Check for Bulk-OUT DMA interrupt */ |
2037 | if (intr_dma & 0x2) { |
2038 | int ep_num; |
2039 | ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf; |
2040 | jz4740_out_epn(jz4740_udc, ep_num, intr_out); |
2041 | } |
2042 | |
2043 | /* Check for each configured endpoint interrupt */ |
2044 | if (intr_in & USB_INTR_INEP1) { |
2045 | DEBUG("USB_INTR_INEP1\n"); |
2046 | jz4740_in_epn(jz4740_udc, 1, intr_in); |
2047 | } |
2048 | |
2049 | if (intr_in & USB_INTR_INEP2) { |
2050 | DEBUG("USB_INTR_INEP2\n"); |
2051 | jz4740_in_epn(jz4740_udc, 2, intr_in); |
2052 | } |
2053 | |
2054 | if (intr_out & USB_INTR_OUTEP1) { |
2055 | DEBUG("USB_INTR_OUTEP1\n"); |
2056 | jz4740_out_epn(jz4740_udc, 1, intr_out); |
2057 | } |
2058 | |
2059 | /* Check for suspend mode */ |
2060 | if ((intr_usb & USB_INTR_SUSPEND) && |
2061 | (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) { |
2062 | DEBUG("USB suspend\n"); |
2063 | jz4740_udc->driver->suspend(&jz4740_udc->gadget); |
2064 | /* Host unloaded from us, can do something, such as flushing |
2065 | the NAND block cache etc. */ |
2066 | } |
2067 | |
2068 | jz_udc_set_index(jz4740_udc, index); |
2069 | |
2070 | spin_unlock(&jz4740_udc->lock); |
2071 | |
2072 | return IRQ_HANDLED; |
2073 | } |
2074 | |
2075 | |
2076 | |
2077 | /*-------------------------------------------------------------------------*/ |
2078 | |
2079 | |
2080 | static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget) |
2081 | { |
2082 | return container_of(gadget, struct jz4740_udc, gadget); |
2083 | } |
2084 | |
2085 | static int jz4740_udc_get_frame(struct usb_gadget *_gadget) |
2086 | { |
2087 | DEBUG("%s, %p\n", __FUNCTION__, _gadget); |
2088 | return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME); |
2089 | } |
2090 | |
2091 | static int jz4740_udc_wakeup(struct usb_gadget *_gadget) |
2092 | { |
2093 | /* host may not have enabled remote wakeup */ |
2094 | /*if ((UDCCS0 & UDCCS0_DRWF) == 0) |
2095 | return -EHOSTUNREACH; |
2096 | udc_set_mask_UDCCR(UDCCR_RSM); */ |
2097 | return -ENOTSUPP; |
2098 | } |
2099 | |
2100 | static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on) |
2101 | { |
2102 | struct jz4740_udc *udc = gadget_to_udc(_gadget); |
2103 | unsigned long flags; |
2104 | |
2105 | local_irq_save(flags); |
2106 | |
2107 | if (on) { |
2108 | udc->state = UDC_STATE_ENABLE; |
2109 | udc_enable(udc); |
2110 | } else { |
2111 | udc->state = UDC_STATE_DISABLE; |
2112 | udc_disable(udc); |
2113 | } |
2114 | |
2115 | local_irq_restore(flags); |
2116 | |
2117 | return 0; |
2118 | } |
2119 | |
2120 | |
2121 | static const struct usb_gadget_ops jz4740_udc_ops = { |
2122 | .get_frame = jz4740_udc_get_frame, |
2123 | .wakeup = jz4740_udc_wakeup, |
2124 | .pullup = jz4740_udc_pullup, |
2125 | }; |
2126 | |
2127 | static struct usb_ep_ops jz4740_ep_ops = { |
2128 | .enable = jz4740_ep_enable, |
2129 | .disable = jz4740_ep_disable, |
2130 | |
2131 | .alloc_request = jz4740_alloc_request, |
2132 | .free_request = jz4740_free_request, |
2133 | |
2134 | .queue = jz4740_queue, |
2135 | .dequeue = jz4740_dequeue, |
2136 | |
2137 | .set_halt = jz4740_set_halt, |
2138 | .fifo_status = jz4740_fifo_status, |
2139 | .fifo_flush = jz4740_fifo_flush, |
2140 | }; |
2141 | |
2142 | |
2143 | /*-------------------------------------------------------------------------*/ |
2144 | |
2145 | static struct jz4740_udc jz4740_udc_controller = { |
2146 | .gadget = { |
2147 | .ops = &jz4740_udc_ops, |
2148 | .ep0 = &jz4740_udc_controller.ep[0].ep, |
2149 | .name = "jz4740-udc", |
2150 | .dev = { |
2151 | .init_name = "gadget", |
2152 | }, |
2153 | }, |
2154 | |
2155 | /* control endpoint */ |
2156 | .ep[0] = { |
2157 | .ep = { |
2158 | .name = "ep0", |
2159 | .ops = &jz4740_ep_ops, |
2160 | .maxpacket = EP0_MAXPACKETSIZE, |
2161 | }, |
2162 | .dev = &jz4740_udc_controller, |
2163 | |
2164 | .bEndpointAddress = 0, |
2165 | .bmAttributes = 0, |
2166 | |
2167 | .type = ep_control, |
2168 | .fifo = JZ_REG_UDC_EP_FIFO(0), |
2169 | .csr = JZ_REG_UDC_CSR0, |
2170 | }, |
2171 | |
2172 | /* bulk out endpoint */ |
2173 | .ep[1] = { |
2174 | .ep = { |
2175 | .name = "ep1out-bulk", |
2176 | .ops = &jz4740_ep_ops, |
2177 | .maxpacket = EPBULK_MAXPACKETSIZE, |
2178 | }, |
2179 | .dev = &jz4740_udc_controller, |
2180 | |
2181 | .bEndpointAddress = 1, |
2182 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2183 | |
2184 | .type = ep_bulk_out, |
2185 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2186 | .csr = JZ_REG_UDC_OUTCSR, |
2187 | }, |
2188 | |
2189 | /* bulk in endpoint */ |
2190 | .ep[2] = { |
2191 | .ep = { |
2192 | .name = "ep1in-bulk", |
2193 | .ops = &jz4740_ep_ops, |
2194 | .maxpacket = EPBULK_MAXPACKETSIZE, |
2195 | }, |
2196 | .dev = &jz4740_udc_controller, |
2197 | |
2198 | .bEndpointAddress = 1 | USB_DIR_IN, |
2199 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2200 | |
2201 | .type = ep_bulk_in, |
2202 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2203 | .csr = JZ_REG_UDC_INCSR, |
2204 | }, |
2205 | |
2206 | /* interrupt in endpoint */ |
2207 | .ep[3] = { |
2208 | .ep = { |
2209 | .name = "ep2in-int", |
2210 | .ops = &jz4740_ep_ops, |
2211 | .maxpacket = EPINTR_MAXPACKETSIZE, |
2212 | }, |
2213 | .dev = &jz4740_udc_controller, |
2214 | |
2215 | .bEndpointAddress = 2 | USB_DIR_IN, |
2216 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2217 | |
2218 | .type = ep_interrupt, |
2219 | .fifo = JZ_REG_UDC_EP_FIFO(2), |
2220 | .csr = JZ_REG_UDC_INCSR, |
2221 | }, |
2222 | }; |
2223 | |
2224 | static int __devinit jz4740_udc_probe(struct platform_device *pdev) |
2225 | { |
2226 | struct jz4740_udc *jz4740_udc = &jz4740_udc_controller; |
2227 | int ret; |
2228 | |
2229 | spin_lock_init(&jz4740_udc->lock); |
2230 | |
2231 | jz4740_udc->dev = &pdev->dev; |
2232 | jz4740_udc->gadget.dev.parent = &pdev->dev; |
2233 | jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask; |
2234 | |
2235 | ret = device_register(&jz4740_udc->gadget.dev); |
2236 | if (ret) |
2237 | return ret; |
2238 | |
2239 | jz4740_udc->clk = clk_get(&pdev->dev, "udc"); |
2240 | if (IS_ERR(jz4740_udc->clk)) { |
2241 | ret = PTR_ERR(jz4740_udc->clk); |
2242 | dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret); |
2243 | goto err_device_unregister; |
2244 | } |
2245 | |
2246 | platform_set_drvdata(pdev, jz4740_udc); |
2247 | |
2248 | jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2249 | |
2250 | if (!jz4740_udc->mem) { |
2251 | ret = -ENOENT; |
2252 | dev_err(&pdev->dev, "Failed to get mmio memory resource\n"); |
2253 | goto err_clk_put; |
2254 | } |
2255 | |
2256 | jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start, |
2257 | resource_size(jz4740_udc->mem), pdev->name); |
2258 | |
2259 | if (!jz4740_udc->mem) { |
2260 | ret = -EBUSY; |
2261 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
2262 | goto err_device_unregister; |
2263 | } |
2264 | |
2265 | jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem)); |
2266 | |
2267 | if (!jz4740_udc->base) { |
2268 | ret = -EBUSY; |
2269 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
2270 | goto err_release_mem_region; |
2271 | } |
2272 | |
2273 | jz4740_udc->irq = platform_get_irq(pdev, 0); |
2274 | ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name, |
2275 | jz4740_udc); |
2276 | if (ret) { |
2277 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
2278 | goto err_iounmap; |
2279 | } |
2280 | |
2281 | udc_disable(jz4740_udc); |
2282 | udc_reinit(jz4740_udc); |
2283 | |
2284 | return 0; |
2285 | |
2286 | err_iounmap: |
2287 | iounmap(jz4740_udc->base); |
2288 | err_release_mem_region: |
2289 | release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem)); |
2290 | err_clk_put: |
2291 | clk_put(jz4740_udc->clk); |
2292 | err_device_unregister: |
2293 | device_unregister(&jz4740_udc->gadget.dev); |
2294 | platform_set_drvdata(pdev, NULL); |
2295 | |
2296 | return ret; |
2297 | } |
2298 | |
2299 | static int __devexit jz4740_udc_remove(struct platform_device *pdev) |
2300 | { |
2301 | struct jz4740_udc *dev = platform_get_drvdata(pdev); |
2302 | |
2303 | if (dev->driver) |
2304 | return -EBUSY; |
2305 | |
2306 | udc_disable(dev); |
2307 | |
2308 | free_irq(dev->irq, dev); |
2309 | iounmap(dev->base); |
2310 | release_mem_region(dev->mem->start, resource_size(dev->mem)); |
2311 | clk_put(dev->clk); |
2312 | |
2313 | platform_set_drvdata(pdev, NULL); |
2314 | device_unregister(&dev->gadget.dev); |
2315 | |
2316 | return 0; |
2317 | } |
2318 | |
2319 | #ifdef CONFIG_PM |
2320 | |
2321 | static int jz4740_udc_suspend(struct device *dev) |
2322 | { |
2323 | struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev); |
2324 | |
2325 | if (jz4740_udc->state == UDC_STATE_ENABLE) |
2326 | udc_disable(jz4740_udc); |
2327 | |
2328 | return 0; |
2329 | } |
2330 | |
2331 | static int jz4740_udc_resume(struct device *dev) |
2332 | { |
2333 | struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev); |
2334 | |
2335 | if (jz4740_udc->state == UDC_STATE_ENABLE) |
2336 | udc_enable(jz4740_udc); |
2337 | |
2338 | return 0; |
2339 | } |
2340 | |
2341 | static const struct dev_pm_ops jz4740_udc_pm_ops = { |
2342 | .suspend = jz4740_udc_suspend, |
2343 | .resume = jz4740_udc_resume, |
2344 | }; |
2345 | |
2346 | #define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops) |
2347 | |
2348 | #else |
2349 | #define JZ4740_UDC_PM_OPS NULL |
2350 | #endif |
2351 | |
2352 | static struct platform_driver udc_driver = { |
2353 | .probe = jz4740_udc_probe, |
2354 | .remove = __devexit_p(jz4740_udc_remove), |
2355 | .driver = { |
2356 | .name = "jz-udc", |
2357 | .owner = THIS_MODULE, |
2358 | .pm = JZ4740_UDC_PM_OPS, |
2359 | }, |
2360 | }; |
2361 | |
2362 | /*-------------------------------------------------------------------------*/ |
2363 | |
2364 | static int __init udc_init (void) |
2365 | { |
2366 | return platform_driver_register(&udc_driver); |
2367 | } |
2368 | module_init(udc_init); |
2369 | |
2370 | static void __exit udc_exit (void) |
2371 | { |
2372 | platform_driver_unregister(&udc_driver); |
2373 | } |
2374 | module_exit(udc_exit); |
2375 | |
2376 | MODULE_DESCRIPTION("JZ4740 USB Device Controller"); |
2377 | MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>"); |
2378 | MODULE_LICENSE("GPL"); |
2379 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9