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Source at commit fc705e74b51166f3b0fefc5e28776a430609b80a created 13 years 23 days ago. By Peter Zotov, MIPS: JZ47xx: Generalize clock framework. | |
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1 | /* |
2 | * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 SoC clock support |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | */ |
15 | |
16 | #include <linux/kernel.h> |
17 | #include <linux/errno.h> |
18 | #include <linux/clk.h> |
19 | #include <linux/spinlock.h> |
20 | #include <linux/io.h> |
21 | #include <linux/module.h> |
22 | #include <linux/list.h> |
23 | #include <linux/err.h> |
24 | |
25 | #include <asm/mach-jz47xx/clock.h> |
26 | #include <asm/mach-jz47xx/base.h> |
27 | |
28 | #include "../clock.h" |
29 | |
30 | #define JZ_REG_CLOCK_CTRL 0x00 |
31 | #define JZ_REG_CLOCK_LOW_POWER 0x04 |
32 | #define JZ_REG_CLOCK_PLL 0x10 |
33 | #define JZ_REG_CLOCK_GATE 0x20 |
34 | #define JZ_REG_CLOCK_SLEEP_CTRL 0x24 |
35 | #define JZ_REG_CLOCK_I2S 0x60 |
36 | #define JZ_REG_CLOCK_LCD 0x64 |
37 | #define JZ_REG_CLOCK_MMC 0x68 |
38 | #define JZ_REG_CLOCK_UHC 0x6C |
39 | #define JZ_REG_CLOCK_SPI 0x74 |
40 | |
41 | #define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31) |
42 | #define JZ_CLOCK_CTRL_KO_ENABLE BIT(30) |
43 | #define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29) |
44 | #define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000 |
45 | #define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22) |
46 | #define JZ_CLOCK_CTRL_PLL_HALF BIT(21) |
47 | #define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000 |
48 | #define JZ_CLOCK_CTRL_UDIV_OFFSET 23 |
49 | #define JZ_CLOCK_CTRL_LDIV_OFFSET 16 |
50 | #define JZ_CLOCK_CTRL_MDIV_OFFSET 12 |
51 | #define JZ_CLOCK_CTRL_PDIV_OFFSET 8 |
52 | #define JZ_CLOCK_CTRL_HDIV_OFFSET 4 |
53 | #define JZ_CLOCK_CTRL_CDIV_OFFSET 0 |
54 | |
55 | #define JZ_CLOCK_GATE_UART0 BIT(0) |
56 | #define JZ_CLOCK_GATE_TCU BIT(1) |
57 | #define JZ_CLOCK_GATE_RTC BIT(2) |
58 | #define JZ_CLOCK_GATE_I2C BIT(3) |
59 | #define JZ_CLOCK_GATE_SPI BIT(4) |
60 | #define JZ_CLOCK_GATE_AIC BIT(5) |
61 | #define JZ_CLOCK_GATE_I2S BIT(6) |
62 | #define JZ_CLOCK_GATE_MMC BIT(7) |
63 | #define JZ_CLOCK_GATE_ADC BIT(8) |
64 | #define JZ_CLOCK_GATE_CIM BIT(9) |
65 | #define JZ_CLOCK_GATE_LCD BIT(10) |
66 | #define JZ_CLOCK_GATE_UDC BIT(11) |
67 | #define JZ_CLOCK_GATE_DMAC BIT(12) |
68 | #define JZ_CLOCK_GATE_IPU BIT(13) |
69 | #define JZ_CLOCK_GATE_UHC BIT(14) |
70 | #define JZ_CLOCK_GATE_UART1 BIT(15) |
71 | |
72 | #define JZ_CLOCK_I2S_DIV_MASK 0x01ff |
73 | |
74 | #define JZ_CLOCK_LCD_DIV_MASK 0x01ff |
75 | |
76 | #define JZ_CLOCK_MMC_DIV_MASK 0x001f |
77 | |
78 | #define JZ_CLOCK_UHC_DIV_MASK 0x000f |
79 | |
80 | #define JZ_CLOCK_SPI_SRC_PLL BIT(31) |
81 | #define JZ_CLOCK_SPI_DIV_MASK 0x000f |
82 | |
83 | #define JZ_CLOCK_PLL_M_MASK 0x01ff |
84 | #define JZ_CLOCK_PLL_N_MASK 0x001f |
85 | #define JZ_CLOCK_PLL_OD_MASK 0x0003 |
86 | #define JZ_CLOCK_PLL_STABLE BIT(10) |
87 | #define JZ_CLOCK_PLL_BYPASS BIT(9) |
88 | #define JZ_CLOCK_PLL_ENABLED BIT(8) |
89 | #define JZ_CLOCK_PLL_STABLIZE_MASK 0x000f |
90 | #define JZ_CLOCK_PLL_M_OFFSET 23 |
91 | #define JZ_CLOCK_PLL_N_OFFSET 18 |
92 | #define JZ_CLOCK_PLL_OD_OFFSET 16 |
93 | |
94 | #define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2) |
95 | #define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0) |
96 | |
97 | #define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7) |
98 | #define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6) |
99 | |
100 | static void __iomem *jz_clock_base; |
101 | static spinlock_t jz_clock_lock; |
102 | static LIST_HEAD(jz_clocks); |
103 | |
104 | struct main_clk { |
105 | struct clk clk; |
106 | uint32_t div_offset; |
107 | }; |
108 | |
109 | struct divided_clk { |
110 | struct clk clk; |
111 | uint32_t reg; |
112 | uint32_t mask; |
113 | }; |
114 | |
115 | struct static_clk { |
116 | struct clk clk; |
117 | unsigned long rate; |
118 | }; |
119 | |
120 | static uint32_t jz_clk_reg_read(int reg) |
121 | { |
122 | return readl(jz_clock_base + reg); |
123 | } |
124 | |
125 | static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask) |
126 | { |
127 | uint32_t val2; |
128 | |
129 | spin_lock(&jz_clock_lock); |
130 | val2 = readl(jz_clock_base + reg); |
131 | val2 &= ~mask; |
132 | val2 |= val; |
133 | writel(val2, jz_clock_base + reg); |
134 | spin_unlock(&jz_clock_lock); |
135 | } |
136 | |
137 | static void jz_clk_reg_set_bits(int reg, uint32_t mask) |
138 | { |
139 | uint32_t val; |
140 | |
141 | spin_lock(&jz_clock_lock); |
142 | val = readl(jz_clock_base + reg); |
143 | val |= mask; |
144 | writel(val, jz_clock_base + reg); |
145 | spin_unlock(&jz_clock_lock); |
146 | } |
147 | |
148 | static void jz_clk_reg_clear_bits(int reg, uint32_t mask) |
149 | { |
150 | uint32_t val; |
151 | |
152 | spin_lock(&jz_clock_lock); |
153 | val = readl(jz_clock_base + reg); |
154 | val &= ~mask; |
155 | writel(val, jz_clock_base + reg); |
156 | spin_unlock(&jz_clock_lock); |
157 | } |
158 | |
159 | static int jz_clk_enable_gating(struct clk *clk) |
160 | { |
161 | if (clk->gate_bit == JZ47XX_CLK_NOT_GATED) |
162 | return -EINVAL; |
163 | |
164 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); |
165 | return 0; |
166 | } |
167 | |
168 | static int jz_clk_disable_gating(struct clk *clk) |
169 | { |
170 | if (clk->gate_bit == JZ47XX_CLK_NOT_GATED) |
171 | return -EINVAL; |
172 | |
173 | jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); |
174 | return 0; |
175 | } |
176 | |
177 | static int jz_clk_is_enabled_gating(struct clk *clk) |
178 | { |
179 | if (clk->gate_bit == JZ47XX_CLK_NOT_GATED) |
180 | return 1; |
181 | |
182 | return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit); |
183 | } |
184 | |
185 | static unsigned long jz_clk_static_get_rate(struct clk *clk) |
186 | { |
187 | return ((struct static_clk *)clk)->rate; |
188 | } |
189 | |
190 | static int jz_clk_ko_enable(struct clk *clk) |
191 | { |
192 | jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE); |
193 | return 0; |
194 | } |
195 | |
196 | static int jz_clk_ko_disable(struct clk *clk) |
197 | { |
198 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE); |
199 | return 0; |
200 | } |
201 | |
202 | static int jz_clk_ko_is_enabled(struct clk *clk) |
203 | { |
204 | return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE); |
205 | } |
206 | |
207 | static const int pllno[] = {1, 2, 2, 4}; |
208 | |
209 | static unsigned long jz_clk_pll_get_rate(struct clk *clk) |
210 | { |
211 | uint32_t val; |
212 | int m; |
213 | int n; |
214 | int od; |
215 | |
216 | val = jz_clk_reg_read(JZ_REG_CLOCK_PLL); |
217 | |
218 | if (val & JZ_CLOCK_PLL_BYPASS) |
219 | return clk_get_rate(clk->parent); |
220 | |
221 | m = ((val >> 23) & 0x1ff) + 2; |
222 | n = ((val >> 18) & 0x1f) + 2; |
223 | od = (val >> 16) & 0x3; |
224 | |
225 | return ((clk_get_rate(clk->parent) / n) * m) / pllno[od]; |
226 | } |
227 | |
228 | static unsigned long jz_clk_pll_half_get_rate(struct clk *clk) |
229 | { |
230 | uint32_t reg; |
231 | |
232 | reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); |
233 | if (reg & JZ_CLOCK_CTRL_PLL_HALF) |
234 | return jz_clk_pll_get_rate(clk->parent); |
235 | return jz_clk_pll_get_rate(clk->parent) >> 1; |
236 | } |
237 | |
238 | static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
239 | |
240 | static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate) |
241 | { |
242 | unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); |
243 | int div; |
244 | |
245 | div = parent_rate / rate; |
246 | if (div > 32) |
247 | return parent_rate / 32; |
248 | else if (div < 1) |
249 | return parent_rate; |
250 | |
251 | div &= (0x3 << (ffs(div) - 1)); |
252 | |
253 | return parent_rate / div; |
254 | } |
255 | |
256 | static unsigned long jz_clk_main_get_rate(struct clk *clk) |
257 | { |
258 | struct main_clk *mclk = (struct main_clk *)clk; |
259 | uint32_t div; |
260 | |
261 | div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); |
262 | |
263 | div >>= mclk->div_offset; |
264 | div &= 0xf; |
265 | |
266 | if (div >= ARRAY_SIZE(jz_clk_main_divs)) |
267 | div = ARRAY_SIZE(jz_clk_main_divs) - 1; |
268 | |
269 | return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div]; |
270 | } |
271 | |
272 | static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate) |
273 | { |
274 | struct main_clk *mclk = (struct main_clk *)clk; |
275 | int i; |
276 | int div; |
277 | unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); |
278 | |
279 | rate = jz_clk_main_round_rate(clk, rate); |
280 | |
281 | div = parent_rate / rate; |
282 | |
283 | i = (ffs(div) - 1) << 1; |
284 | if (i > 0 && !(div & BIT(i-1))) |
285 | i -= 1; |
286 | |
287 | jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset, |
288 | 0xf << mclk->div_offset); |
289 | |
290 | return 0; |
291 | } |
292 | |
293 | static struct clk_ops jz_clk_static_ops = { |
294 | .get_rate = jz_clk_static_get_rate, |
295 | .enable = jz_clk_enable_gating, |
296 | .disable = jz_clk_disable_gating, |
297 | .is_enabled = jz_clk_is_enabled_gating, |
298 | }; |
299 | |
300 | static struct static_clk jz_clk_ext = { |
301 | .clk = { |
302 | .name = "ext", |
303 | .gate_bit = JZ47XX_CLK_NOT_GATED, |
304 | .ops = &jz_clk_static_ops, |
305 | }, |
306 | }; |
307 | |
308 | static struct clk_ops jz_clk_pll_ops = { |
309 | .get_rate = jz_clk_pll_get_rate, |
310 | }; |
311 | |
312 | static struct clk jz_clk_pll = { |
313 | .name = "pll", |
314 | .parent = &jz_clk_ext.clk, |
315 | .ops = &jz_clk_pll_ops, |
316 | }; |
317 | |
318 | static struct clk_ops jz_clk_pll_half_ops = { |
319 | .get_rate = jz_clk_pll_half_get_rate, |
320 | }; |
321 | |
322 | static struct clk jz_clk_pll_half = { |
323 | .name = "pll half", |
324 | .parent = &jz_clk_pll, |
325 | .ops = &jz_clk_pll_half_ops, |
326 | }; |
327 | |
328 | static const struct clk_ops jz_clk_main_ops = { |
329 | .get_rate = jz_clk_main_get_rate, |
330 | .set_rate = jz_clk_main_set_rate, |
331 | .round_rate = jz_clk_main_round_rate, |
332 | }; |
333 | |
334 | static struct main_clk jz_clk_cpu = { |
335 | .clk = { |
336 | .name = "cclk", |
337 | .parent = &jz_clk_pll, |
338 | .ops = &jz_clk_main_ops, |
339 | }, |
340 | .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET, |
341 | }; |
342 | |
343 | static struct main_clk jz_clk_memory = { |
344 | .clk = { |
345 | .name = "mclk", |
346 | .parent = &jz_clk_pll, |
347 | .ops = &jz_clk_main_ops, |
348 | }, |
349 | .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET, |
350 | }; |
351 | |
352 | static struct main_clk jz_clk_high_speed_peripheral = { |
353 | .clk = { |
354 | .name = "hclk", |
355 | .parent = &jz_clk_pll, |
356 | .ops = &jz_clk_main_ops, |
357 | }, |
358 | .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET, |
359 | }; |
360 | |
361 | |
362 | static struct main_clk jz_clk_low_speed_peripheral = { |
363 | .clk = { |
364 | .name = "pclk", |
365 | .parent = &jz_clk_pll, |
366 | .ops = &jz_clk_main_ops, |
367 | }, |
368 | .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET, |
369 | }; |
370 | |
371 | static const struct clk_ops jz_clk_ko_ops = { |
372 | .enable = jz_clk_ko_enable, |
373 | .disable = jz_clk_ko_disable, |
374 | .is_enabled = jz_clk_ko_is_enabled, |
375 | }; |
376 | |
377 | static struct clk jz_clk_ko = { |
378 | .name = "cko", |
379 | .parent = &jz_clk_memory.clk, |
380 | .ops = &jz_clk_ko_ops, |
381 | }; |
382 | |
383 | static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent) |
384 | { |
385 | if (parent == &jz_clk_pll) |
386 | jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI); |
387 | else if (parent == &jz_clk_ext.clk) |
388 | jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI); |
389 | else |
390 | return -EINVAL; |
391 | |
392 | clk->parent = parent; |
393 | |
394 | return 0; |
395 | } |
396 | |
397 | static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent) |
398 | { |
399 | if (parent == &jz_clk_pll_half) |
400 | jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL); |
401 | else if (parent == &jz_clk_ext.clk) |
402 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL); |
403 | else |
404 | return -EINVAL; |
405 | |
406 | clk->parent = parent; |
407 | |
408 | return 0; |
409 | } |
410 | |
411 | static int jz_clk_udc_phy_enable(struct clk *clk) |
412 | { |
413 | jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL, |
414 | JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); |
415 | |
416 | return 0; |
417 | } |
418 | |
419 | static int jz_clk_udc_phy_disable(struct clk *clk) |
420 | { |
421 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL, |
422 | JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); |
423 | |
424 | return 0; |
425 | } |
426 | |
427 | static int jz_clk_udc_phy_is_enabled(struct clk *clk) |
428 | { |
429 | return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) & |
430 | JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); |
431 | } |
432 | |
433 | static int jz_clk_udc_enable(struct clk *clk) |
434 | { |
435 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); |
436 | |
437 | return 0; |
438 | } |
439 | |
440 | static int jz_clk_udc_disable(struct clk *clk) |
441 | { |
442 | jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); |
443 | |
444 | return 0; |
445 | } |
446 | |
447 | static int jz_clk_udc_is_enabled(struct clk *clk) |
448 | { |
449 | return !!(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & JZ_CLOCK_GATE_UDC); |
450 | } |
451 | |
452 | static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent) |
453 | { |
454 | if (parent == &jz_clk_pll_half) |
455 | jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL); |
456 | else if (parent == &jz_clk_ext.clk) |
457 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL); |
458 | else |
459 | return -EINVAL; |
460 | |
461 | clk->parent = parent; |
462 | |
463 | return 0; |
464 | } |
465 | |
466 | static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate) |
467 | { |
468 | int div; |
469 | |
470 | if (clk->parent == &jz_clk_ext.clk) |
471 | return -EINVAL; |
472 | |
473 | div = clk_get_rate(clk->parent) / rate - 1; |
474 | |
475 | if (div < 0) |
476 | div = 0; |
477 | else if (div > 63) |
478 | div = 63; |
479 | |
480 | jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET, |
481 | JZ_CLOCK_CTRL_UDIV_MASK); |
482 | return 0; |
483 | } |
484 | |
485 | static unsigned long jz_clk_udc_get_rate(struct clk *clk) |
486 | { |
487 | int div; |
488 | |
489 | if (clk->parent == &jz_clk_ext.clk) |
490 | return clk_get_rate(clk->parent); |
491 | |
492 | div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK); |
493 | div >>= JZ_CLOCK_CTRL_UDIV_OFFSET; |
494 | div += 1; |
495 | |
496 | return clk_get_rate(clk->parent) / div; |
497 | } |
498 | |
499 | static unsigned long jz_clk_divided_get_rate(struct clk *clk) |
500 | { |
501 | struct divided_clk *dclk = (struct divided_clk *)clk; |
502 | int div; |
503 | |
504 | if (clk->parent == &jz_clk_ext.clk) |
505 | return clk_get_rate(clk->parent); |
506 | |
507 | div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1; |
508 | |
509 | return clk_get_rate(clk->parent) / div; |
510 | } |
511 | |
512 | static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate) |
513 | { |
514 | struct divided_clk *dclk = (struct divided_clk *)clk; |
515 | int div; |
516 | |
517 | if (clk->parent == &jz_clk_ext.clk) |
518 | return -EINVAL; |
519 | |
520 | div = clk_get_rate(clk->parent) / rate - 1; |
521 | |
522 | if (div < 0) |
523 | div = 0; |
524 | else if (div > dclk->mask) |
525 | div = dclk->mask; |
526 | |
527 | jz_clk_reg_write_mask(dclk->reg, div, dclk->mask); |
528 | |
529 | return 0; |
530 | } |
531 | |
532 | static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate) |
533 | { |
534 | int div; |
535 | unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent); |
536 | |
537 | if (rate > 150000000) |
538 | return 150000000; |
539 | |
540 | div = parent_rate / rate; |
541 | if (div < 1) |
542 | div = 1; |
543 | else if (div > 32) |
544 | div = 32; |
545 | |
546 | return parent_rate / div; |
547 | } |
548 | |
549 | static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate) |
550 | { |
551 | int div; |
552 | |
553 | if (rate > 150000000) |
554 | return -EINVAL; |
555 | |
556 | div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1; |
557 | if (div < 0) |
558 | div = 0; |
559 | else if (div > 31) |
560 | div = 31; |
561 | |
562 | jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET, |
563 | JZ_CLOCK_CTRL_LDIV_MASK); |
564 | |
565 | return 0; |
566 | } |
567 | |
568 | static unsigned long jz_clk_ldclk_get_rate(struct clk *clk) |
569 | { |
570 | int div; |
571 | |
572 | div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK; |
573 | div >>= JZ_CLOCK_CTRL_LDIV_OFFSET; |
574 | |
575 | return jz_clk_pll_half_get_rate(clk->parent) / (div + 1); |
576 | } |
577 | |
578 | static const struct clk_ops jz_clk_ops_ld = { |
579 | .set_rate = jz_clk_ldclk_set_rate, |
580 | .get_rate = jz_clk_ldclk_get_rate, |
581 | .round_rate = jz_clk_ldclk_round_rate, |
582 | .enable = jz_clk_enable_gating, |
583 | .disable = jz_clk_disable_gating, |
584 | .is_enabled = jz_clk_is_enabled_gating, |
585 | }; |
586 | |
587 | static struct clk jz_clk_ld = { |
588 | .name = "lcd", |
589 | .gate_bit = JZ_CLOCK_GATE_LCD, |
590 | .parent = &jz_clk_pll_half, |
591 | .ops = &jz_clk_ops_ld, |
592 | }; |
593 | |
594 | static const struct clk_ops jz_clk_i2s_ops = { |
595 | .set_rate = jz_clk_divided_set_rate, |
596 | .get_rate = jz_clk_divided_get_rate, |
597 | .enable = jz_clk_enable_gating, |
598 | .disable = jz_clk_disable_gating, |
599 | .is_enabled = jz_clk_is_enabled_gating, |
600 | .set_parent = jz_clk_i2s_set_parent, |
601 | }; |
602 | |
603 | static const struct clk_ops jz_clk_spi_ops = { |
604 | .set_rate = jz_clk_divided_set_rate, |
605 | .get_rate = jz_clk_divided_get_rate, |
606 | .enable = jz_clk_enable_gating, |
607 | .disable = jz_clk_disable_gating, |
608 | .is_enabled = jz_clk_is_enabled_gating, |
609 | .set_parent = jz_clk_spi_set_parent, |
610 | }; |
611 | |
612 | static const struct clk_ops jz_clk_divided_ops = { |
613 | .set_rate = jz_clk_divided_set_rate, |
614 | .get_rate = jz_clk_divided_get_rate, |
615 | .enable = jz_clk_enable_gating, |
616 | .disable = jz_clk_disable_gating, |
617 | .is_enabled = jz_clk_is_enabled_gating, |
618 | }; |
619 | |
620 | static struct divided_clk jz4740_clock_divided_clks[] = { |
621 | [0] = { |
622 | .clk = { |
623 | .name = "i2s", |
624 | .parent = &jz_clk_ext.clk, |
625 | .gate_bit = JZ_CLOCK_GATE_I2S, |
626 | .ops = &jz_clk_i2s_ops, |
627 | }, |
628 | .reg = JZ_REG_CLOCK_I2S, |
629 | .mask = JZ_CLOCK_I2S_DIV_MASK, |
630 | }, |
631 | [1] = { |
632 | .clk = { |
633 | .name = "spi", |
634 | .parent = &jz_clk_ext.clk, |
635 | .gate_bit = JZ_CLOCK_GATE_SPI, |
636 | .ops = &jz_clk_spi_ops, |
637 | }, |
638 | .reg = JZ_REG_CLOCK_SPI, |
639 | .mask = JZ_CLOCK_SPI_DIV_MASK, |
640 | }, |
641 | [2] = { |
642 | .clk = { |
643 | .name = "lcd_pclk", |
644 | .parent = &jz_clk_pll_half, |
645 | .gate_bit = JZ47XX_CLK_NOT_GATED, |
646 | .ops = &jz_clk_divided_ops, |
647 | }, |
648 | .reg = JZ_REG_CLOCK_LCD, |
649 | .mask = JZ_CLOCK_LCD_DIV_MASK, |
650 | }, |
651 | [3] = { |
652 | .clk = { |
653 | .name = "mmc", |
654 | .parent = &jz_clk_pll_half, |
655 | .gate_bit = JZ_CLOCK_GATE_MMC, |
656 | .ops = &jz_clk_divided_ops, |
657 | }, |
658 | .reg = JZ_REG_CLOCK_MMC, |
659 | .mask = JZ_CLOCK_MMC_DIV_MASK, |
660 | }, |
661 | [4] = { |
662 | .clk = { |
663 | .name = "uhc", |
664 | .parent = &jz_clk_pll_half, |
665 | .gate_bit = JZ_CLOCK_GATE_UHC, |
666 | .ops = &jz_clk_divided_ops, |
667 | }, |
668 | .reg = JZ_REG_CLOCK_UHC, |
669 | .mask = JZ_CLOCK_UHC_DIV_MASK, |
670 | }, |
671 | }; |
672 | |
673 | static const struct clk_ops jz_clk_udc_phy_ops = { |
674 | .enable = jz_clk_udc_phy_enable, |
675 | .disable = jz_clk_udc_phy_disable, |
676 | .is_enabled = jz_clk_udc_phy_is_enabled, |
677 | }; |
678 | |
679 | static const struct clk_ops jz_clk_udc_ops = { |
680 | .set_parent = jz_clk_udc_set_parent, |
681 | .set_rate = jz_clk_udc_set_rate, |
682 | .get_rate = jz_clk_udc_get_rate, |
683 | .enable = jz_clk_udc_enable, |
684 | .disable = jz_clk_udc_disable, |
685 | .is_enabled = jz_clk_udc_is_enabled, |
686 | }; |
687 | |
688 | static const struct clk_ops jz_clk_simple_ops = { |
689 | .enable = jz_clk_enable_gating, |
690 | .disable = jz_clk_disable_gating, |
691 | .is_enabled = jz_clk_is_enabled_gating, |
692 | }; |
693 | |
694 | static struct clk jz4740_clock_simple_clks[] = { |
695 | [0] = { |
696 | .name = "udc", |
697 | .parent = &jz_clk_ext.clk, |
698 | .ops = &jz_clk_udc_ops, |
699 | }, |
700 | [1] = { |
701 | .name = "uart0", |
702 | .parent = &jz_clk_ext.clk, |
703 | .gate_bit = JZ_CLOCK_GATE_UART0, |
704 | .ops = &jz_clk_simple_ops, |
705 | }, |
706 | [2] = { |
707 | .name = "uart1", |
708 | .parent = &jz_clk_ext.clk, |
709 | .gate_bit = JZ_CLOCK_GATE_UART1, |
710 | .ops = &jz_clk_simple_ops, |
711 | }, |
712 | [3] = { |
713 | .name = "dma", |
714 | .parent = &jz_clk_high_speed_peripheral.clk, |
715 | .gate_bit = JZ_CLOCK_GATE_UART0, |
716 | .ops = &jz_clk_simple_ops, |
717 | }, |
718 | [4] = { |
719 | .name = "ipu", |
720 | .parent = &jz_clk_high_speed_peripheral.clk, |
721 | .gate_bit = JZ_CLOCK_GATE_IPU, |
722 | .ops = &jz_clk_simple_ops, |
723 | }, |
724 | [5] = { |
725 | .name = "adc", |
726 | .parent = &jz_clk_ext.clk, |
727 | .gate_bit = JZ_CLOCK_GATE_ADC, |
728 | .ops = &jz_clk_simple_ops, |
729 | }, |
730 | [6] = { |
731 | .name = "i2c", |
732 | .parent = &jz_clk_ext.clk, |
733 | .gate_bit = JZ_CLOCK_GATE_I2C, |
734 | .ops = &jz_clk_simple_ops, |
735 | }, |
736 | [7] = { |
737 | .name = "aic", |
738 | .parent = &jz_clk_ext.clk, |
739 | .gate_bit = JZ_CLOCK_GATE_AIC, |
740 | .ops = &jz_clk_simple_ops, |
741 | }, |
742 | [8] = { |
743 | .name = "udc-phy", |
744 | .parent = &jz4740_clock_simple_clks[0], /* udc */ |
745 | .ops = &jz_clk_udc_phy_ops, |
746 | }, |
747 | }; |
748 | |
749 | static struct static_clk jz_clk_rtc = { |
750 | .clk = { |
751 | .name = "rtc", |
752 | .gate_bit = JZ_CLOCK_GATE_RTC, |
753 | .ops = &jz_clk_static_ops, |
754 | }, |
755 | .rate = 32768, |
756 | }; |
757 | |
758 | int clk_enable(struct clk *clk) |
759 | { |
760 | if (!clk->ops->enable) |
761 | return -EINVAL; |
762 | |
763 | return clk->ops->enable(clk); |
764 | } |
765 | EXPORT_SYMBOL_GPL(clk_enable); |
766 | |
767 | void clk_disable(struct clk *clk) |
768 | { |
769 | if (clk->ops->disable) |
770 | clk->ops->disable(clk); |
771 | } |
772 | EXPORT_SYMBOL_GPL(clk_disable); |
773 | |
774 | int clk_is_enabled(struct clk *clk) |
775 | { |
776 | if (clk->ops->is_enabled) |
777 | return clk->ops->is_enabled(clk); |
778 | |
779 | return 1; |
780 | } |
781 | |
782 | unsigned long clk_get_rate(struct clk *clk) |
783 | { |
784 | if (clk->ops->get_rate) |
785 | return clk->ops->get_rate(clk); |
786 | if (clk->parent) |
787 | return clk_get_rate(clk->parent); |
788 | |
789 | return -EINVAL; |
790 | } |
791 | EXPORT_SYMBOL_GPL(clk_get_rate); |
792 | |
793 | int clk_set_rate(struct clk *clk, unsigned long rate) |
794 | { |
795 | if (!clk->ops->set_rate) |
796 | return -EINVAL; |
797 | return clk->ops->set_rate(clk, rate); |
798 | } |
799 | EXPORT_SYMBOL_GPL(clk_set_rate); |
800 | |
801 | long clk_round_rate(struct clk *clk, unsigned long rate) |
802 | { |
803 | if (clk->ops->round_rate) |
804 | return clk->ops->round_rate(clk, rate); |
805 | |
806 | return -EINVAL; |
807 | } |
808 | EXPORT_SYMBOL_GPL(clk_round_rate); |
809 | |
810 | int clk_set_parent(struct clk *clk, struct clk *parent) |
811 | { |
812 | int ret; |
813 | int enabled; |
814 | |
815 | if (!clk->ops->set_parent) |
816 | return -EINVAL; |
817 | |
818 | enabled = clk_is_enabled(clk); |
819 | if (enabled) |
820 | clk_disable(clk); |
821 | ret = clk->ops->set_parent(clk, parent); |
822 | if (enabled) |
823 | clk_enable(clk); |
824 | |
825 | jz4740_clock_debugfs_update_parent(clk); |
826 | |
827 | return ret; |
828 | } |
829 | EXPORT_SYMBOL_GPL(clk_set_parent); |
830 | |
831 | struct clk *clk_get(struct device *dev, const char *name) |
832 | { |
833 | struct clk *clk; |
834 | |
835 | list_for_each_entry(clk, &jz_clocks, list) { |
836 | if (strcmp(clk->name, name) == 0) |
837 | return clk; |
838 | } |
839 | return ERR_PTR(-ENXIO); |
840 | } |
841 | EXPORT_SYMBOL_GPL(clk_get); |
842 | |
843 | void clk_put(struct clk *clk) |
844 | { |
845 | } |
846 | EXPORT_SYMBOL_GPL(clk_put); |
847 | |
848 | static inline void clk_add(struct clk *clk) |
849 | { |
850 | list_add_tail(&clk->list, &jz_clocks); |
851 | |
852 | jz4740_clock_debugfs_add_clk(clk); |
853 | } |
854 | |
855 | static void clk_register_clks(void) |
856 | { |
857 | size_t i; |
858 | |
859 | clk_add(&jz_clk_ext.clk); |
860 | clk_add(&jz_clk_pll); |
861 | clk_add(&jz_clk_pll_half); |
862 | clk_add(&jz_clk_cpu.clk); |
863 | clk_add(&jz_clk_high_speed_peripheral.clk); |
864 | clk_add(&jz_clk_low_speed_peripheral.clk); |
865 | clk_add(&jz_clk_ko); |
866 | clk_add(&jz_clk_ld); |
867 | clk_add(&jz_clk_rtc.clk); |
868 | |
869 | for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i) |
870 | clk_add(&jz4740_clock_divided_clks[i].clk); |
871 | |
872 | for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i) |
873 | clk_add(&jz4740_clock_simple_clks[i]); |
874 | } |
875 | |
876 | void jz47xx_clock_set_wait_mode(enum jz47xx_wait_mode mode) |
877 | { |
878 | switch (mode) { |
879 | case JZ47XX_WAIT_MODE_IDLE: |
880 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP); |
881 | break; |
882 | case JZ47XX_WAIT_MODE_SLEEP: |
883 | jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP); |
884 | break; |
885 | } |
886 | } |
887 | |
888 | void jz47xx_clock_suspend(void) |
889 | { |
890 | jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, |
891 | JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0); |
892 | |
893 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED); |
894 | } |
895 | |
896 | void jz47xx_clock_resume(void) |
897 | { |
898 | uint32_t pll; |
899 | |
900 | jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED); |
901 | |
902 | do { |
903 | pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL); |
904 | } while (!(pll & JZ_CLOCK_PLL_STABLE)); |
905 | |
906 | jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, |
907 | JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0); |
908 | } |
909 | |
910 | static int jz4740_clock_init(void) |
911 | { |
912 | uint32_t val; |
913 | |
914 | jz_clock_base = ioremap(JZ47XX_CPM_BASE_ADDR, 0x100); |
915 | if (!jz_clock_base) |
916 | return -EBUSY; |
917 | |
918 | spin_lock_init(&jz_clock_lock); |
919 | |
920 | jz_clk_ext.rate = jz47xx_clock_bdata.ext_rate; |
921 | jz_clk_rtc.rate = jz47xx_clock_bdata.rtc_rate; |
922 | |
923 | val = jz_clk_reg_read(JZ_REG_CLOCK_SPI); |
924 | |
925 | if (val & JZ_CLOCK_SPI_SRC_PLL) |
926 | jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half; |
927 | |
928 | val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); |
929 | |
930 | if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL) |
931 | jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half; |
932 | |
933 | if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL) |
934 | jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half; |
935 | |
936 | jz4740_clock_debugfs_init(); |
937 | |
938 | clk_register_clks(); |
939 | |
940 | return 0; |
941 | } |
942 | arch_initcall(jz4740_clock_init); |
943 |
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
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