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1 | #include <linux/types.h> |
2 | #include <linux/mm.h> |
3 | #include <linux/slab.h> |
4 | #include <linux/blkdev.h> |
5 | #include <linux/init.h> |
6 | #include <linux/interrupt.h> |
7 | |
8 | #include <asm/setup.h> |
9 | #include <asm/page.h> |
10 | #include <asm/pgtable.h> |
11 | #include <asm/amigaints.h> |
12 | #include <asm/amigahw.h> |
13 | #include <linux/zorro.h> |
14 | #include <asm/irq.h> |
15 | #include <linux/spinlock.h> |
16 | |
17 | #include "scsi.h" |
18 | #include <scsi/scsi_host.h> |
19 | #include "wd33c93.h" |
20 | #include "gvp11.h" |
21 | |
22 | #include<linux/stat.h> |
23 | |
24 | #define DMA(ptr) ((gvp11_scsiregs *)((ptr)->base)) |
25 | #define HDATA(ptr) ((struct WD33C93_hostdata *)((ptr)->hostdata)) |
26 | |
27 | static irqreturn_t gvp11_intr (int irq, void *_instance) |
28 | { |
29 | unsigned long flags; |
30 | unsigned int status; |
31 | struct Scsi_Host *instance = (struct Scsi_Host *)_instance; |
32 | |
33 | status = DMA(instance)->CNTR; |
34 | if (!(status & GVP11_DMAC_INT_PENDING)) |
35 | return IRQ_NONE; |
36 | |
37 | spin_lock_irqsave(instance->host_lock, flags); |
38 | wd33c93_intr(instance); |
39 | spin_unlock_irqrestore(instance->host_lock, flags); |
40 | return IRQ_HANDLED; |
41 | } |
42 | |
43 | static int gvp11_xfer_mask = 0; |
44 | |
45 | void gvp11_setup (char *str, int *ints) |
46 | { |
47 | gvp11_xfer_mask = ints[1]; |
48 | } |
49 | |
50 | static int dma_setup(struct scsi_cmnd *cmd, int dir_in) |
51 | { |
52 | unsigned short cntr = GVP11_DMAC_INT_ENABLE; |
53 | unsigned long addr = virt_to_bus(cmd->SCp.ptr); |
54 | int bank_mask; |
55 | static int scsi_alloc_out_of_range = 0; |
56 | |
57 | /* use bounce buffer if the physical address is bad */ |
58 | if (addr & HDATA(cmd->device->host)->dma_xfer_mask) |
59 | { |
60 | HDATA(cmd->device->host)->dma_bounce_len = (cmd->SCp.this_residual + 511) |
61 | & ~0x1ff; |
62 | |
63 | if( !scsi_alloc_out_of_range ) { |
64 | HDATA(cmd->device->host)->dma_bounce_buffer = |
65 | kmalloc (HDATA(cmd->device->host)->dma_bounce_len, GFP_KERNEL); |
66 | HDATA(cmd->device->host)->dma_buffer_pool = BUF_SCSI_ALLOCED; |
67 | } |
68 | |
69 | if (scsi_alloc_out_of_range || |
70 | !HDATA(cmd->device->host)->dma_bounce_buffer) { |
71 | HDATA(cmd->device->host)->dma_bounce_buffer = |
72 | amiga_chip_alloc(HDATA(cmd->device->host)->dma_bounce_len, |
73 | "GVP II SCSI Bounce Buffer"); |
74 | |
75 | if(!HDATA(cmd->device->host)->dma_bounce_buffer) |
76 | { |
77 | HDATA(cmd->device->host)->dma_bounce_len = 0; |
78 | return 1; |
79 | } |
80 | |
81 | HDATA(cmd->device->host)->dma_buffer_pool = BUF_CHIP_ALLOCED; |
82 | } |
83 | |
84 | /* check if the address of the bounce buffer is OK */ |
85 | addr = virt_to_bus(HDATA(cmd->device->host)->dma_bounce_buffer); |
86 | |
87 | if (addr & HDATA(cmd->device->host)->dma_xfer_mask) { |
88 | /* fall back to Chip RAM if address out of range */ |
89 | if( HDATA(cmd->device->host)->dma_buffer_pool == BUF_SCSI_ALLOCED) { |
90 | kfree (HDATA(cmd->device->host)->dma_bounce_buffer); |
91 | scsi_alloc_out_of_range = 1; |
92 | } else { |
93 | amiga_chip_free (HDATA(cmd->device->host)->dma_bounce_buffer); |
94 | } |
95 | |
96 | HDATA(cmd->device->host)->dma_bounce_buffer = |
97 | amiga_chip_alloc(HDATA(cmd->device->host)->dma_bounce_len, |
98 | "GVP II SCSI Bounce Buffer"); |
99 | |
100 | if(!HDATA(cmd->device->host)->dma_bounce_buffer) |
101 | { |
102 | HDATA(cmd->device->host)->dma_bounce_len = 0; |
103 | return 1; |
104 | } |
105 | |
106 | addr = virt_to_bus(HDATA(cmd->device->host)->dma_bounce_buffer); |
107 | HDATA(cmd->device->host)->dma_buffer_pool = BUF_CHIP_ALLOCED; |
108 | } |
109 | |
110 | if (!dir_in) { |
111 | /* copy to bounce buffer for a write */ |
112 | memcpy (HDATA(cmd->device->host)->dma_bounce_buffer, |
113 | cmd->SCp.ptr, cmd->SCp.this_residual); |
114 | } |
115 | } |
116 | |
117 | /* setup dma direction */ |
118 | if (!dir_in) |
119 | cntr |= GVP11_DMAC_DIR_WRITE; |
120 | |
121 | HDATA(cmd->device->host)->dma_dir = dir_in; |
122 | DMA(cmd->device->host)->CNTR = cntr; |
123 | |
124 | /* setup DMA *physical* address */ |
125 | DMA(cmd->device->host)->ACR = addr; |
126 | |
127 | if (dir_in) |
128 | /* invalidate any cache */ |
129 | cache_clear (addr, cmd->SCp.this_residual); |
130 | else |
131 | /* push any dirty cache */ |
132 | cache_push (addr, cmd->SCp.this_residual); |
133 | |
134 | if ((bank_mask = (~HDATA(cmd->device->host)->dma_xfer_mask >> 18) & 0x01c0)) |
135 | DMA(cmd->device->host)->BANK = bank_mask & (addr >> 18); |
136 | |
137 | /* start DMA */ |
138 | DMA(cmd->device->host)->ST_DMA = 1; |
139 | |
140 | /* return success */ |
141 | return 0; |
142 | } |
143 | |
144 | static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt, |
145 | int status) |
146 | { |
147 | /* stop DMA */ |
148 | DMA(instance)->SP_DMA = 1; |
149 | /* remove write bit from CONTROL bits */ |
150 | DMA(instance)->CNTR = GVP11_DMAC_INT_ENABLE; |
151 | |
152 | /* copy from a bounce buffer, if necessary */ |
153 | if (status && HDATA(instance)->dma_bounce_buffer) { |
154 | if (HDATA(instance)->dma_dir && SCpnt) |
155 | memcpy (SCpnt->SCp.ptr, |
156 | HDATA(instance)->dma_bounce_buffer, |
157 | SCpnt->SCp.this_residual); |
158 | |
159 | if (HDATA(instance)->dma_buffer_pool == BUF_SCSI_ALLOCED) |
160 | kfree (HDATA(instance)->dma_bounce_buffer); |
161 | else |
162 | amiga_chip_free(HDATA(instance)->dma_bounce_buffer); |
163 | |
164 | HDATA(instance)->dma_bounce_buffer = NULL; |
165 | HDATA(instance)->dma_bounce_len = 0; |
166 | } |
167 | } |
168 | |
169 | #define CHECK_WD33C93 |
170 | |
171 | int __init gvp11_detect(struct scsi_host_template *tpnt) |
172 | { |
173 | static unsigned char called = 0; |
174 | struct Scsi_Host *instance; |
175 | unsigned long address; |
176 | unsigned int epc; |
177 | struct zorro_dev *z = NULL; |
178 | unsigned int default_dma_xfer_mask; |
179 | wd33c93_regs regs; |
180 | int num_gvp11 = 0; |
181 | #ifdef CHECK_WD33C93 |
182 | volatile unsigned char *sasr_3393, *scmd_3393; |
183 | unsigned char save_sasr; |
184 | unsigned char q, qq; |
185 | #endif |
186 | |
187 | if (!MACH_IS_AMIGA || called) |
188 | return 0; |
189 | called = 1; |
190 | |
191 | tpnt->proc_name = "GVP11"; |
192 | tpnt->proc_info = &wd33c93_proc_info; |
193 | |
194 | while ((z = zorro_find_device(ZORRO_WILDCARD, z))) { |
195 | /* |
196 | * This should (hopefully) be the correct way to identify |
197 | * all the different GVP SCSI controllers (except for the |
198 | * SERIES I though). |
199 | */ |
200 | |
201 | if (z->id == ZORRO_PROD_GVP_COMBO_030_R3_SCSI || |
202 | z->id == ZORRO_PROD_GVP_SERIES_II) |
203 | default_dma_xfer_mask = ~0x00ffffff; |
204 | else if (z->id == ZORRO_PROD_GVP_GFORCE_030_SCSI || |
205 | z->id == ZORRO_PROD_GVP_A530_SCSI || |
206 | z->id == ZORRO_PROD_GVP_COMBO_030_R4_SCSI) |
207 | default_dma_xfer_mask = ~0x01ffffff; |
208 | else if (z->id == ZORRO_PROD_GVP_A1291 || |
209 | z->id == ZORRO_PROD_GVP_GFORCE_040_SCSI_1) |
210 | default_dma_xfer_mask = ~0x07ffffff; |
211 | else |
212 | continue; |
213 | |
214 | /* |
215 | * Rumors state that some GVP ram boards use the same product |
216 | * code as the SCSI controllers. Therefore if the board-size |
217 | * is not 64KB we asume it is a ram board and bail out. |
218 | */ |
219 | if (z->resource.end-z->resource.start != 0xffff) |
220 | continue; |
221 | |
222 | address = z->resource.start; |
223 | if (!request_mem_region(address, 256, "wd33c93")) |
224 | continue; |
225 | |
226 | #ifdef CHECK_WD33C93 |
227 | |
228 | /* |
229 | * These darn GVP boards are a problem - it can be tough to tell |
230 | * whether or not they include a SCSI controller. This is the |
231 | * ultimate Yet-Another-GVP-Detection-Hack in that it actually |
232 | * probes for a WD33c93 chip: If we find one, it's extremely |
233 | * likely that this card supports SCSI, regardless of Product_ |
234 | * Code, Board_Size, etc. |
235 | */ |
236 | |
237 | /* Get pointers to the presumed register locations and save contents */ |
238 | |
239 | sasr_3393 = &(((gvp11_scsiregs *)(ZTWO_VADDR(address)))->SASR); |
240 | scmd_3393 = &(((gvp11_scsiregs *)(ZTWO_VADDR(address)))->SCMD); |
241 | save_sasr = *sasr_3393; |
242 | |
243 | /* First test the AuxStatus Reg */ |
244 | |
245 | q = *sasr_3393; /* read it */ |
246 | if (q & 0x08) /* bit 3 should always be clear */ |
247 | goto release; |
248 | *sasr_3393 = WD_AUXILIARY_STATUS; /* setup indirect address */ |
249 | if (*sasr_3393 == WD_AUXILIARY_STATUS) { /* shouldn't retain the write */ |
250 | *sasr_3393 = save_sasr; /* Oops - restore this byte */ |
251 | goto release; |
252 | } |
253 | if (*sasr_3393 != q) { /* should still read the same */ |
254 | *sasr_3393 = save_sasr; /* Oops - restore this byte */ |
255 | goto release; |
256 | } |
257 | if (*scmd_3393 != q) /* and so should the image at 0x1f */ |
258 | goto release; |
259 | |
260 | |
261 | /* Ok, we probably have a wd33c93, but let's check a few other places |
262 | * for good measure. Make sure that this works for both 'A and 'B |
263 | * chip versions. |
264 | */ |
265 | |
266 | *sasr_3393 = WD_SCSI_STATUS; |
267 | q = *scmd_3393; |
268 | *sasr_3393 = WD_SCSI_STATUS; |
269 | *scmd_3393 = ~q; |
270 | *sasr_3393 = WD_SCSI_STATUS; |
271 | qq = *scmd_3393; |
272 | *sasr_3393 = WD_SCSI_STATUS; |
273 | *scmd_3393 = q; |
274 | if (qq != q) /* should be read only */ |
275 | goto release; |
276 | *sasr_3393 = 0x1e; /* this register is unimplemented */ |
277 | q = *scmd_3393; |
278 | *sasr_3393 = 0x1e; |
279 | *scmd_3393 = ~q; |
280 | *sasr_3393 = 0x1e; |
281 | qq = *scmd_3393; |
282 | *sasr_3393 = 0x1e; |
283 | *scmd_3393 = q; |
284 | if (qq != q || qq != 0xff) /* should be read only, all 1's */ |
285 | goto release; |
286 | *sasr_3393 = WD_TIMEOUT_PERIOD; |
287 | q = *scmd_3393; |
288 | *sasr_3393 = WD_TIMEOUT_PERIOD; |
289 | *scmd_3393 = ~q; |
290 | *sasr_3393 = WD_TIMEOUT_PERIOD; |
291 | qq = *scmd_3393; |
292 | *sasr_3393 = WD_TIMEOUT_PERIOD; |
293 | *scmd_3393 = q; |
294 | if (qq != (~q & 0xff)) /* should be read/write */ |
295 | goto release; |
296 | #endif |
297 | |
298 | instance = scsi_register (tpnt, sizeof (struct WD33C93_hostdata)); |
299 | if(instance == NULL) |
300 | goto release; |
301 | instance->base = ZTWO_VADDR(address); |
302 | instance->irq = IRQ_AMIGA_PORTS; |
303 | instance->unique_id = z->slotaddr; |
304 | |
305 | if (gvp11_xfer_mask) |
306 | HDATA(instance)->dma_xfer_mask = gvp11_xfer_mask; |
307 | else |
308 | HDATA(instance)->dma_xfer_mask = default_dma_xfer_mask; |
309 | |
310 | |
311 | DMA(instance)->secret2 = 1; |
312 | DMA(instance)->secret1 = 0; |
313 | DMA(instance)->secret3 = 15; |
314 | while (DMA(instance)->CNTR & GVP11_DMAC_BUSY) ; |
315 | DMA(instance)->CNTR = 0; |
316 | |
317 | DMA(instance)->BANK = 0; |
318 | |
319 | epc = *(unsigned short *)(ZTWO_VADDR(address) + 0x8000); |
320 | |
321 | /* |
322 | * Check for 14MHz SCSI clock |
323 | */ |
324 | regs.SASR = &(DMA(instance)->SASR); |
325 | regs.SCMD = &(DMA(instance)->SCMD); |
326 | HDATA(instance)->no_sync = 0xff; |
327 | HDATA(instance)->fast = 0; |
328 | HDATA(instance)->dma_mode = CTRL_DMA; |
329 | wd33c93_init(instance, regs, dma_setup, dma_stop, |
330 | (epc & GVP_SCSICLKMASK) ? WD33C93_FS_8_10 |
331 | : WD33C93_FS_12_15); |
332 | |
333 | if (request_irq(IRQ_AMIGA_PORTS, gvp11_intr, IRQF_SHARED, "GVP11 SCSI", |
334 | instance)) |
335 | goto unregister; |
336 | DMA(instance)->CNTR = GVP11_DMAC_INT_ENABLE; |
337 | num_gvp11++; |
338 | continue; |
339 | |
340 | unregister: |
341 | scsi_unregister(instance); |
342 | wd33c93_release(); |
343 | release: |
344 | release_mem_region(address, 256); |
345 | } |
346 | |
347 | return num_gvp11; |
348 | } |
349 | |
350 | static int gvp11_bus_reset(struct scsi_cmnd *cmd) |
351 | { |
352 | /* FIXME perform bus-specific reset */ |
353 | |
354 | /* FIXME 2: shouldn't we no-op this function (return |
355 | FAILED), and fall back to host reset function, |
356 | wd33c93_host_reset ? */ |
357 | |
358 | spin_lock_irq(cmd->device->host->host_lock); |
359 | wd33c93_host_reset(cmd); |
360 | spin_unlock_irq(cmd->device->host->host_lock); |
361 | |
362 | return SUCCESS; |
363 | } |
364 | |
365 | |
366 | #define HOSTS_C |
367 | |
368 | #include "gvp11.h" |
369 | |
370 | static struct scsi_host_template driver_template = { |
371 | .proc_name = "GVP11", |
372 | .name = "GVP Series II SCSI", |
373 | .detect = gvp11_detect, |
374 | .release = gvp11_release, |
375 | .queuecommand = wd33c93_queuecommand, |
376 | .eh_abort_handler = wd33c93_abort, |
377 | .eh_bus_reset_handler = gvp11_bus_reset, |
378 | .eh_host_reset_handler = wd33c93_host_reset, |
379 | .can_queue = CAN_QUEUE, |
380 | .this_id = 7, |
381 | .sg_tablesize = SG_ALL, |
382 | .cmd_per_lun = CMD_PER_LUN, |
383 | .use_clustering = DISABLE_CLUSTERING |
384 | }; |
385 | |
386 | |
387 | #include "scsi_module.c" |
388 | |
389 | int gvp11_release(struct Scsi_Host *instance) |
390 | { |
391 | #ifdef MODULE |
392 | DMA(instance)->CNTR = 0; |
393 | release_mem_region(ZTWO_PADDR(instance->base), 256); |
394 | free_irq(IRQ_AMIGA_PORTS, instance); |
395 | wd33c93_release(); |
396 | #endif |
397 | return 1; |
398 | } |
399 | |
400 | MODULE_LICENSE("GPL"); |
401 |
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