Root/
1 | /* |
2 | * linux/drivers/char/amba.c |
3 | * |
4 | * Driver for AMBA serial ports |
5 | * |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
7 | * |
8 | * Copyright 1999 ARM Limited |
9 | * Copyright (C) 2000 Deep Blue Solutions Ltd. |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by |
13 | * the Free Software Foundation; either version 2 of the License, or |
14 | * (at your option) any later version. |
15 | * |
16 | * This program is distributed in the hope that it will be useful, |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
19 | * GNU General Public License for more details. |
20 | * |
21 | * You should have received a copy of the GNU General Public License |
22 | * along with this program; if not, write to the Free Software |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
24 | * |
25 | * This is a generic driver for ARM AMBA-type serial ports. They |
26 | * have a lot of 16550-like features, but are not register compatible. |
27 | * Note that although they do have CTS, DCD and DSR inputs, they do |
28 | * not have an RI input, nor do they have DTR or RTS outputs. If |
29 | * required, these have to be supplied via some other means (eg, GPIO) |
30 | * and hooked into this driver. |
31 | */ |
32 | |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ |
35 | #endif |
36 | |
37 | #include <linux/module.h> |
38 | #include <linux/ioport.h> |
39 | #include <linux/init.h> |
40 | #include <linux/console.h> |
41 | #include <linux/sysrq.h> |
42 | #include <linux/device.h> |
43 | #include <linux/tty.h> |
44 | #include <linux/tty_flip.h> |
45 | #include <linux/serial_core.h> |
46 | #include <linux/serial.h> |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> |
49 | #include <linux/clk.h> |
50 | #include <linux/slab.h> |
51 | |
52 | #include <asm/io.h> |
53 | #include <asm/sizes.h> |
54 | |
55 | #define UART_NR 14 |
56 | |
57 | #define SERIAL_AMBA_MAJOR 204 |
58 | #define SERIAL_AMBA_MINOR 64 |
59 | #define SERIAL_AMBA_NR UART_NR |
60 | |
61 | #define AMBA_ISR_PASS_LIMIT 256 |
62 | |
63 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
64 | #define UART_DUMMY_DR_RX (1 << 16) |
65 | |
66 | /* |
67 | * We wrap our port structure around the generic uart_port. |
68 | */ |
69 | struct uart_amba_port { |
70 | struct uart_port port; |
71 | struct clk *clk; |
72 | unsigned int im; /* interrupt mask */ |
73 | unsigned int old_status; |
74 | unsigned int ifls; /* vendor-specific */ |
75 | bool autorts; |
76 | }; |
77 | |
78 | /* There is by now at least one vendor with differing details, so handle it */ |
79 | struct vendor_data { |
80 | unsigned int ifls; |
81 | unsigned int fifosize; |
82 | }; |
83 | |
84 | static struct vendor_data vendor_arm = { |
85 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, |
86 | .fifosize = 16, |
87 | }; |
88 | |
89 | static struct vendor_data vendor_st = { |
90 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, |
91 | .fifosize = 64, |
92 | }; |
93 | |
94 | static void pl011_stop_tx(struct uart_port *port) |
95 | { |
96 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
97 | |
98 | uap->im &= ~UART011_TXIM; |
99 | writew(uap->im, uap->port.membase + UART011_IMSC); |
100 | } |
101 | |
102 | static void pl011_start_tx(struct uart_port *port) |
103 | { |
104 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
105 | |
106 | uap->im |= UART011_TXIM; |
107 | writew(uap->im, uap->port.membase + UART011_IMSC); |
108 | } |
109 | |
110 | static void pl011_stop_rx(struct uart_port *port) |
111 | { |
112 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
113 | |
114 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| |
115 | UART011_PEIM|UART011_BEIM|UART011_OEIM); |
116 | writew(uap->im, uap->port.membase + UART011_IMSC); |
117 | } |
118 | |
119 | static void pl011_enable_ms(struct uart_port *port) |
120 | { |
121 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
122 | |
123 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; |
124 | writew(uap->im, uap->port.membase + UART011_IMSC); |
125 | } |
126 | |
127 | static void pl011_rx_chars(struct uart_amba_port *uap) |
128 | { |
129 | struct tty_struct *tty = uap->port.state->port.tty; |
130 | unsigned int status, ch, flag, max_count = 256; |
131 | |
132 | status = readw(uap->port.membase + UART01x_FR); |
133 | while ((status & UART01x_FR_RXFE) == 0 && max_count--) { |
134 | ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX; |
135 | flag = TTY_NORMAL; |
136 | uap->port.icount.rx++; |
137 | |
138 | /* |
139 | * Note that the error handling code is |
140 | * out of the main execution path |
141 | */ |
142 | if (unlikely(ch & UART_DR_ERROR)) { |
143 | if (ch & UART011_DR_BE) { |
144 | ch &= ~(UART011_DR_FE | UART011_DR_PE); |
145 | uap->port.icount.brk++; |
146 | if (uart_handle_break(&uap->port)) |
147 | goto ignore_char; |
148 | } else if (ch & UART011_DR_PE) |
149 | uap->port.icount.parity++; |
150 | else if (ch & UART011_DR_FE) |
151 | uap->port.icount.frame++; |
152 | if (ch & UART011_DR_OE) |
153 | uap->port.icount.overrun++; |
154 | |
155 | ch &= uap->port.read_status_mask; |
156 | |
157 | if (ch & UART011_DR_BE) |
158 | flag = TTY_BREAK; |
159 | else if (ch & UART011_DR_PE) |
160 | flag = TTY_PARITY; |
161 | else if (ch & UART011_DR_FE) |
162 | flag = TTY_FRAME; |
163 | } |
164 | |
165 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) |
166 | goto ignore_char; |
167 | |
168 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); |
169 | |
170 | ignore_char: |
171 | status = readw(uap->port.membase + UART01x_FR); |
172 | } |
173 | spin_unlock(&uap->port.lock); |
174 | tty_flip_buffer_push(tty); |
175 | spin_lock(&uap->port.lock); |
176 | } |
177 | |
178 | static void pl011_tx_chars(struct uart_amba_port *uap) |
179 | { |
180 | struct circ_buf *xmit = &uap->port.state->xmit; |
181 | int count; |
182 | |
183 | if (uap->port.x_char) { |
184 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); |
185 | uap->port.icount.tx++; |
186 | uap->port.x_char = 0; |
187 | return; |
188 | } |
189 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { |
190 | pl011_stop_tx(&uap->port); |
191 | return; |
192 | } |
193 | |
194 | count = uap->port.fifosize >> 1; |
195 | do { |
196 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); |
197 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
198 | uap->port.icount.tx++; |
199 | if (uart_circ_empty(xmit)) |
200 | break; |
201 | } while (--count > 0); |
202 | |
203 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
204 | uart_write_wakeup(&uap->port); |
205 | |
206 | if (uart_circ_empty(xmit)) |
207 | pl011_stop_tx(&uap->port); |
208 | } |
209 | |
210 | static void pl011_modem_status(struct uart_amba_port *uap) |
211 | { |
212 | unsigned int status, delta; |
213 | |
214 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
215 | |
216 | delta = status ^ uap->old_status; |
217 | uap->old_status = status; |
218 | |
219 | if (!delta) |
220 | return; |
221 | |
222 | if (delta & UART01x_FR_DCD) |
223 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); |
224 | |
225 | if (delta & UART01x_FR_DSR) |
226 | uap->port.icount.dsr++; |
227 | |
228 | if (delta & UART01x_FR_CTS) |
229 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); |
230 | |
231 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
232 | } |
233 | |
234 | static irqreturn_t pl011_int(int irq, void *dev_id) |
235 | { |
236 | struct uart_amba_port *uap = dev_id; |
237 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
238 | int handled = 0; |
239 | |
240 | spin_lock(&uap->port.lock); |
241 | |
242 | status = readw(uap->port.membase + UART011_MIS); |
243 | if (status) { |
244 | do { |
245 | writew(status & ~(UART011_TXIS|UART011_RTIS| |
246 | UART011_RXIS), |
247 | uap->port.membase + UART011_ICR); |
248 | |
249 | if (status & (UART011_RTIS|UART011_RXIS)) |
250 | pl011_rx_chars(uap); |
251 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
252 | UART011_CTSMIS|UART011_RIMIS)) |
253 | pl011_modem_status(uap); |
254 | if (status & UART011_TXIS) |
255 | pl011_tx_chars(uap); |
256 | |
257 | if (pass_counter-- == 0) |
258 | break; |
259 | |
260 | status = readw(uap->port.membase + UART011_MIS); |
261 | } while (status != 0); |
262 | handled = 1; |
263 | } |
264 | |
265 | spin_unlock(&uap->port.lock); |
266 | |
267 | return IRQ_RETVAL(handled); |
268 | } |
269 | |
270 | static unsigned int pl01x_tx_empty(struct uart_port *port) |
271 | { |
272 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
273 | unsigned int status = readw(uap->port.membase + UART01x_FR); |
274 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; |
275 | } |
276 | |
277 | static unsigned int pl01x_get_mctrl(struct uart_port *port) |
278 | { |
279 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
280 | unsigned int result = 0; |
281 | unsigned int status = readw(uap->port.membase + UART01x_FR); |
282 | |
283 | #define TIOCMBIT(uartbit, tiocmbit) \ |
284 | if (status & uartbit) \ |
285 | result |= tiocmbit |
286 | |
287 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
288 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); |
289 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); |
290 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); |
291 | #undef TIOCMBIT |
292 | return result; |
293 | } |
294 | |
295 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) |
296 | { |
297 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
298 | unsigned int cr; |
299 | |
300 | cr = readw(uap->port.membase + UART011_CR); |
301 | |
302 | #define TIOCMBIT(tiocmbit, uartbit) \ |
303 | if (mctrl & tiocmbit) \ |
304 | cr |= uartbit; \ |
305 | else \ |
306 | cr &= ~uartbit |
307 | |
308 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
309 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); |
310 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); |
311 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); |
312 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); |
313 | |
314 | if (uap->autorts) { |
315 | /* We need to disable auto-RTS if we want to turn RTS off */ |
316 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); |
317 | } |
318 | #undef TIOCMBIT |
319 | |
320 | writew(cr, uap->port.membase + UART011_CR); |
321 | } |
322 | |
323 | static void pl011_break_ctl(struct uart_port *port, int break_state) |
324 | { |
325 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
326 | unsigned long flags; |
327 | unsigned int lcr_h; |
328 | |
329 | spin_lock_irqsave(&uap->port.lock, flags); |
330 | lcr_h = readw(uap->port.membase + UART011_LCRH); |
331 | if (break_state == -1) |
332 | lcr_h |= UART01x_LCRH_BRK; |
333 | else |
334 | lcr_h &= ~UART01x_LCRH_BRK; |
335 | writew(lcr_h, uap->port.membase + UART011_LCRH); |
336 | spin_unlock_irqrestore(&uap->port.lock, flags); |
337 | } |
338 | |
339 | #ifdef CONFIG_CONSOLE_POLL |
340 | static int pl010_get_poll_char(struct uart_port *port) |
341 | { |
342 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
343 | unsigned int status; |
344 | |
345 | do { |
346 | status = readw(uap->port.membase + UART01x_FR); |
347 | } while (status & UART01x_FR_RXFE); |
348 | |
349 | return readw(uap->port.membase + UART01x_DR); |
350 | } |
351 | |
352 | static void pl010_put_poll_char(struct uart_port *port, |
353 | unsigned char ch) |
354 | { |
355 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
356 | |
357 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
358 | barrier(); |
359 | |
360 | writew(ch, uap->port.membase + UART01x_DR); |
361 | } |
362 | |
363 | #endif /* CONFIG_CONSOLE_POLL */ |
364 | |
365 | static int pl011_startup(struct uart_port *port) |
366 | { |
367 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
368 | unsigned int cr; |
369 | int retval; |
370 | |
371 | /* |
372 | * Try to enable the clock producer. |
373 | */ |
374 | retval = clk_enable(uap->clk); |
375 | if (retval) |
376 | goto out; |
377 | |
378 | uap->port.uartclk = clk_get_rate(uap->clk); |
379 | |
380 | /* |
381 | * Allocate the IRQ |
382 | */ |
383 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); |
384 | if (retval) |
385 | goto clk_dis; |
386 | |
387 | writew(uap->ifls, uap->port.membase + UART011_IFLS); |
388 | |
389 | /* |
390 | * Provoke TX FIFO interrupt into asserting. |
391 | */ |
392 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; |
393 | writew(cr, uap->port.membase + UART011_CR); |
394 | writew(0, uap->port.membase + UART011_FBRD); |
395 | writew(1, uap->port.membase + UART011_IBRD); |
396 | writew(0, uap->port.membase + UART011_LCRH); |
397 | writew(0, uap->port.membase + UART01x_DR); |
398 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) |
399 | barrier(); |
400 | |
401 | cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; |
402 | writew(cr, uap->port.membase + UART011_CR); |
403 | |
404 | /* |
405 | * initialise the old status of the modem signals |
406 | */ |
407 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
408 | |
409 | /* |
410 | * Finally, enable interrupts |
411 | */ |
412 | spin_lock_irq(&uap->port.lock); |
413 | uap->im = UART011_RXIM | UART011_RTIM; |
414 | writew(uap->im, uap->port.membase + UART011_IMSC); |
415 | spin_unlock_irq(&uap->port.lock); |
416 | |
417 | return 0; |
418 | |
419 | clk_dis: |
420 | clk_disable(uap->clk); |
421 | out: |
422 | return retval; |
423 | } |
424 | |
425 | static void pl011_shutdown(struct uart_port *port) |
426 | { |
427 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
428 | unsigned long val; |
429 | |
430 | /* |
431 | * disable all interrupts |
432 | */ |
433 | spin_lock_irq(&uap->port.lock); |
434 | uap->im = 0; |
435 | writew(uap->im, uap->port.membase + UART011_IMSC); |
436 | writew(0xffff, uap->port.membase + UART011_ICR); |
437 | spin_unlock_irq(&uap->port.lock); |
438 | |
439 | /* |
440 | * Free the interrupt |
441 | */ |
442 | free_irq(uap->port.irq, uap); |
443 | |
444 | /* |
445 | * disable the port |
446 | */ |
447 | uap->autorts = false; |
448 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); |
449 | |
450 | /* |
451 | * disable break condition and fifos |
452 | */ |
453 | val = readw(uap->port.membase + UART011_LCRH); |
454 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); |
455 | writew(val, uap->port.membase + UART011_LCRH); |
456 | |
457 | /* |
458 | * Shut down the clock producer |
459 | */ |
460 | clk_disable(uap->clk); |
461 | } |
462 | |
463 | static void |
464 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
465 | struct ktermios *old) |
466 | { |
467 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
468 | unsigned int lcr_h, old_cr; |
469 | unsigned long flags; |
470 | unsigned int baud, quot; |
471 | |
472 | /* |
473 | * Ask the core to calculate the divisor for us. |
474 | */ |
475 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); |
476 | quot = port->uartclk * 4 / baud; |
477 | |
478 | switch (termios->c_cflag & CSIZE) { |
479 | case CS5: |
480 | lcr_h = UART01x_LCRH_WLEN_5; |
481 | break; |
482 | case CS6: |
483 | lcr_h = UART01x_LCRH_WLEN_6; |
484 | break; |
485 | case CS7: |
486 | lcr_h = UART01x_LCRH_WLEN_7; |
487 | break; |
488 | default: // CS8 |
489 | lcr_h = UART01x_LCRH_WLEN_8; |
490 | break; |
491 | } |
492 | if (termios->c_cflag & CSTOPB) |
493 | lcr_h |= UART01x_LCRH_STP2; |
494 | if (termios->c_cflag & PARENB) { |
495 | lcr_h |= UART01x_LCRH_PEN; |
496 | if (!(termios->c_cflag & PARODD)) |
497 | lcr_h |= UART01x_LCRH_EPS; |
498 | } |
499 | if (port->fifosize > 1) |
500 | lcr_h |= UART01x_LCRH_FEN; |
501 | |
502 | spin_lock_irqsave(&port->lock, flags); |
503 | |
504 | /* |
505 | * Update the per-port timeout. |
506 | */ |
507 | uart_update_timeout(port, termios->c_cflag, baud); |
508 | |
509 | port->read_status_mask = UART011_DR_OE | 255; |
510 | if (termios->c_iflag & INPCK) |
511 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
512 | if (termios->c_iflag & (BRKINT | PARMRK)) |
513 | port->read_status_mask |= UART011_DR_BE; |
514 | |
515 | /* |
516 | * Characters to ignore |
517 | */ |
518 | port->ignore_status_mask = 0; |
519 | if (termios->c_iflag & IGNPAR) |
520 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
521 | if (termios->c_iflag & IGNBRK) { |
522 | port->ignore_status_mask |= UART011_DR_BE; |
523 | /* |
524 | * If we're ignoring parity and break indicators, |
525 | * ignore overruns too (for real raw support). |
526 | */ |
527 | if (termios->c_iflag & IGNPAR) |
528 | port->ignore_status_mask |= UART011_DR_OE; |
529 | } |
530 | |
531 | /* |
532 | * Ignore all characters if CREAD is not set. |
533 | */ |
534 | if ((termios->c_cflag & CREAD) == 0) |
535 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
536 | |
537 | if (UART_ENABLE_MS(port, termios->c_cflag)) |
538 | pl011_enable_ms(port); |
539 | |
540 | /* first, disable everything */ |
541 | old_cr = readw(port->membase + UART011_CR); |
542 | writew(0, port->membase + UART011_CR); |
543 | |
544 | if (termios->c_cflag & CRTSCTS) { |
545 | if (old_cr & UART011_CR_RTS) |
546 | old_cr |= UART011_CR_RTSEN; |
547 | |
548 | old_cr |= UART011_CR_CTSEN; |
549 | uap->autorts = true; |
550 | } else { |
551 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); |
552 | uap->autorts = false; |
553 | } |
554 | |
555 | /* Set baud rate */ |
556 | writew(quot & 0x3f, port->membase + UART011_FBRD); |
557 | writew(quot >> 6, port->membase + UART011_IBRD); |
558 | |
559 | /* |
560 | * ----------v----------v----------v----------v----- |
561 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L |
562 | * ----------^----------^----------^----------^----- |
563 | */ |
564 | writew(lcr_h, port->membase + UART011_LCRH); |
565 | writew(old_cr, port->membase + UART011_CR); |
566 | |
567 | spin_unlock_irqrestore(&port->lock, flags); |
568 | } |
569 | |
570 | static const char *pl011_type(struct uart_port *port) |
571 | { |
572 | return port->type == PORT_AMBA ? "AMBA/PL011" : NULL; |
573 | } |
574 | |
575 | /* |
576 | * Release the memory region(s) being used by 'port' |
577 | */ |
578 | static void pl010_release_port(struct uart_port *port) |
579 | { |
580 | release_mem_region(port->mapbase, SZ_4K); |
581 | } |
582 | |
583 | /* |
584 | * Request the memory region(s) being used by 'port' |
585 | */ |
586 | static int pl010_request_port(struct uart_port *port) |
587 | { |
588 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") |
589 | != NULL ? 0 : -EBUSY; |
590 | } |
591 | |
592 | /* |
593 | * Configure/autoconfigure the port. |
594 | */ |
595 | static void pl010_config_port(struct uart_port *port, int flags) |
596 | { |
597 | if (flags & UART_CONFIG_TYPE) { |
598 | port->type = PORT_AMBA; |
599 | pl010_request_port(port); |
600 | } |
601 | } |
602 | |
603 | /* |
604 | * verify the new serial_struct (for TIOCSSERIAL). |
605 | */ |
606 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) |
607 | { |
608 | int ret = 0; |
609 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) |
610 | ret = -EINVAL; |
611 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
612 | ret = -EINVAL; |
613 | if (ser->baud_base < 9600) |
614 | ret = -EINVAL; |
615 | return ret; |
616 | } |
617 | |
618 | static struct uart_ops amba_pl011_pops = { |
619 | .tx_empty = pl01x_tx_empty, |
620 | .set_mctrl = pl011_set_mctrl, |
621 | .get_mctrl = pl01x_get_mctrl, |
622 | .stop_tx = pl011_stop_tx, |
623 | .start_tx = pl011_start_tx, |
624 | .stop_rx = pl011_stop_rx, |
625 | .enable_ms = pl011_enable_ms, |
626 | .break_ctl = pl011_break_ctl, |
627 | .startup = pl011_startup, |
628 | .shutdown = pl011_shutdown, |
629 | .set_termios = pl011_set_termios, |
630 | .type = pl011_type, |
631 | .release_port = pl010_release_port, |
632 | .request_port = pl010_request_port, |
633 | .config_port = pl010_config_port, |
634 | .verify_port = pl010_verify_port, |
635 | #ifdef CONFIG_CONSOLE_POLL |
636 | .poll_get_char = pl010_get_poll_char, |
637 | .poll_put_char = pl010_put_poll_char, |
638 | #endif |
639 | }; |
640 | |
641 | static struct uart_amba_port *amba_ports[UART_NR]; |
642 | |
643 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE |
644 | |
645 | static void pl011_console_putchar(struct uart_port *port, int ch) |
646 | { |
647 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
648 | |
649 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
650 | barrier(); |
651 | writew(ch, uap->port.membase + UART01x_DR); |
652 | } |
653 | |
654 | static void |
655 | pl011_console_write(struct console *co, const char *s, unsigned int count) |
656 | { |
657 | struct uart_amba_port *uap = amba_ports[co->index]; |
658 | unsigned int status, old_cr, new_cr; |
659 | |
660 | clk_enable(uap->clk); |
661 | |
662 | /* |
663 | * First save the CR then disable the interrupts |
664 | */ |
665 | old_cr = readw(uap->port.membase + UART011_CR); |
666 | new_cr = old_cr & ~UART011_CR_CTSEN; |
667 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; |
668 | writew(new_cr, uap->port.membase + UART011_CR); |
669 | |
670 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
671 | |
672 | /* |
673 | * Finally, wait for transmitter to become empty |
674 | * and restore the TCR |
675 | */ |
676 | do { |
677 | status = readw(uap->port.membase + UART01x_FR); |
678 | } while (status & UART01x_FR_BUSY); |
679 | writew(old_cr, uap->port.membase + UART011_CR); |
680 | |
681 | clk_disable(uap->clk); |
682 | } |
683 | |
684 | static void __init |
685 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, |
686 | int *parity, int *bits) |
687 | { |
688 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { |
689 | unsigned int lcr_h, ibrd, fbrd; |
690 | |
691 | lcr_h = readw(uap->port.membase + UART011_LCRH); |
692 | |
693 | *parity = 'n'; |
694 | if (lcr_h & UART01x_LCRH_PEN) { |
695 | if (lcr_h & UART01x_LCRH_EPS) |
696 | *parity = 'e'; |
697 | else |
698 | *parity = 'o'; |
699 | } |
700 | |
701 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) |
702 | *bits = 7; |
703 | else |
704 | *bits = 8; |
705 | |
706 | ibrd = readw(uap->port.membase + UART011_IBRD); |
707 | fbrd = readw(uap->port.membase + UART011_FBRD); |
708 | |
709 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); |
710 | } |
711 | } |
712 | |
713 | static int __init pl011_console_setup(struct console *co, char *options) |
714 | { |
715 | struct uart_amba_port *uap; |
716 | int baud = 38400; |
717 | int bits = 8; |
718 | int parity = 'n'; |
719 | int flow = 'n'; |
720 | |
721 | /* |
722 | * Check whether an invalid uart number has been specified, and |
723 | * if so, search for the first available port that does have |
724 | * console support. |
725 | */ |
726 | if (co->index >= UART_NR) |
727 | co->index = 0; |
728 | uap = amba_ports[co->index]; |
729 | if (!uap) |
730 | return -ENODEV; |
731 | |
732 | uap->port.uartclk = clk_get_rate(uap->clk); |
733 | |
734 | if (options) |
735 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
736 | else |
737 | pl011_console_get_options(uap, &baud, &parity, &bits); |
738 | |
739 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); |
740 | } |
741 | |
742 | static struct uart_driver amba_reg; |
743 | static struct console amba_console = { |
744 | .name = "ttyAMA", |
745 | .write = pl011_console_write, |
746 | .device = uart_console_device, |
747 | .setup = pl011_console_setup, |
748 | .flags = CON_PRINTBUFFER, |
749 | .index = -1, |
750 | .data = &amba_reg, |
751 | }; |
752 | |
753 | #define AMBA_CONSOLE (&amba_console) |
754 | #else |
755 | #define AMBA_CONSOLE NULL |
756 | #endif |
757 | |
758 | static struct uart_driver amba_reg = { |
759 | .owner = THIS_MODULE, |
760 | .driver_name = "ttyAMA", |
761 | .dev_name = "ttyAMA", |
762 | .major = SERIAL_AMBA_MAJOR, |
763 | .minor = SERIAL_AMBA_MINOR, |
764 | .nr = UART_NR, |
765 | .cons = AMBA_CONSOLE, |
766 | }; |
767 | |
768 | static int pl011_probe(struct amba_device *dev, struct amba_id *id) |
769 | { |
770 | struct uart_amba_port *uap; |
771 | struct vendor_data *vendor = id->data; |
772 | void __iomem *base; |
773 | int i, ret; |
774 | |
775 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) |
776 | if (amba_ports[i] == NULL) |
777 | break; |
778 | |
779 | if (i == ARRAY_SIZE(amba_ports)) { |
780 | ret = -EBUSY; |
781 | goto out; |
782 | } |
783 | |
784 | uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); |
785 | if (uap == NULL) { |
786 | ret = -ENOMEM; |
787 | goto out; |
788 | } |
789 | |
790 | base = ioremap(dev->res.start, resource_size(&dev->res)); |
791 | if (!base) { |
792 | ret = -ENOMEM; |
793 | goto free; |
794 | } |
795 | |
796 | uap->clk = clk_get(&dev->dev, NULL); |
797 | if (IS_ERR(uap->clk)) { |
798 | ret = PTR_ERR(uap->clk); |
799 | goto unmap; |
800 | } |
801 | |
802 | uap->ifls = vendor->ifls; |
803 | uap->port.dev = &dev->dev; |
804 | uap->port.mapbase = dev->res.start; |
805 | uap->port.membase = base; |
806 | uap->port.iotype = UPIO_MEM; |
807 | uap->port.irq = dev->irq[0]; |
808 | uap->port.fifosize = vendor->fifosize; |
809 | uap->port.ops = &amba_pl011_pops; |
810 | uap->port.flags = UPF_BOOT_AUTOCONF; |
811 | uap->port.line = i; |
812 | |
813 | amba_ports[i] = uap; |
814 | |
815 | amba_set_drvdata(dev, uap); |
816 | ret = uart_add_one_port(&amba_reg, &uap->port); |
817 | if (ret) { |
818 | amba_set_drvdata(dev, NULL); |
819 | amba_ports[i] = NULL; |
820 | clk_put(uap->clk); |
821 | unmap: |
822 | iounmap(base); |
823 | free: |
824 | kfree(uap); |
825 | } |
826 | out: |
827 | return ret; |
828 | } |
829 | |
830 | static int pl011_remove(struct amba_device *dev) |
831 | { |
832 | struct uart_amba_port *uap = amba_get_drvdata(dev); |
833 | int i; |
834 | |
835 | amba_set_drvdata(dev, NULL); |
836 | |
837 | uart_remove_one_port(&amba_reg, &uap->port); |
838 | |
839 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) |
840 | if (amba_ports[i] == uap) |
841 | amba_ports[i] = NULL; |
842 | |
843 | iounmap(uap->port.membase); |
844 | clk_put(uap->clk); |
845 | kfree(uap); |
846 | return 0; |
847 | } |
848 | |
849 | #ifdef CONFIG_PM |
850 | static int pl011_suspend(struct amba_device *dev, pm_message_t state) |
851 | { |
852 | struct uart_amba_port *uap = amba_get_drvdata(dev); |
853 | |
854 | if (!uap) |
855 | return -EINVAL; |
856 | |
857 | return uart_suspend_port(&amba_reg, &uap->port); |
858 | } |
859 | |
860 | static int pl011_resume(struct amba_device *dev) |
861 | { |
862 | struct uart_amba_port *uap = amba_get_drvdata(dev); |
863 | |
864 | if (!uap) |
865 | return -EINVAL; |
866 | |
867 | return uart_resume_port(&amba_reg, &uap->port); |
868 | } |
869 | #endif |
870 | |
871 | static struct amba_id pl011_ids[] __initdata = { |
872 | { |
873 | .id = 0x00041011, |
874 | .mask = 0x000fffff, |
875 | .data = &vendor_arm, |
876 | }, |
877 | { |
878 | .id = 0x00380802, |
879 | .mask = 0x00ffffff, |
880 | .data = &vendor_st, |
881 | }, |
882 | { 0, 0 }, |
883 | }; |
884 | |
885 | static struct amba_driver pl011_driver = { |
886 | .drv = { |
887 | .name = "uart-pl011", |
888 | }, |
889 | .id_table = pl011_ids, |
890 | .probe = pl011_probe, |
891 | .remove = pl011_remove, |
892 | #ifdef CONFIG_PM |
893 | .suspend = pl011_suspend, |
894 | .resume = pl011_resume, |
895 | #endif |
896 | }; |
897 | |
898 | static int __init pl011_init(void) |
899 | { |
900 | int ret; |
901 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
902 | |
903 | ret = uart_register_driver(&amba_reg); |
904 | if (ret == 0) { |
905 | ret = amba_driver_register(&pl011_driver); |
906 | if (ret) |
907 | uart_unregister_driver(&amba_reg); |
908 | } |
909 | return ret; |
910 | } |
911 | |
912 | static void __exit pl011_exit(void) |
913 | { |
914 | amba_driver_unregister(&pl011_driver); |
915 | uart_unregister_driver(&amba_reg); |
916 | } |
917 | |
918 | /* |
919 | * While this can be a module, if builtin it's most likely the console |
920 | * So let's leave module_exit but move module_init to an earlier place |
921 | */ |
922 | arch_initcall(pl011_init); |
923 | module_exit(pl011_exit); |
924 | |
925 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); |
926 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); |
927 | MODULE_LICENSE("GPL"); |
928 |
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