Root/
1 | /* Analog Devices 1889 audio driver |
2 | * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org> |
3 | */ |
4 | |
5 | #ifndef __AD1889_H__ |
6 | #define __AD1889_H__ |
7 | |
8 | #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */ |
9 | #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */ |
10 | #define AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */ |
11 | #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */ |
12 | #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */ |
13 | #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */ |
14 | #define AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */ |
15 | |
16 | #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */ |
17 | #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */ |
18 | #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */ |
19 | #define AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */ |
20 | #define AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo request point */ |
21 | #define AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */ |
22 | #define AD_DS_RAMC_RERQ 0x3000 /* res. fifo request point */ |
23 | |
24 | #define AD_DS_WADA 0x04 /* wave channel mix attenuation */ |
25 | #define AD_DS_WADA_RWAM 0x0080 /* right wave mute */ |
26 | #define AD_DS_WADA_RWAA 0x001f /* right wave attenuation */ |
27 | #define AD_DS_WADA_LWAM 0x8000 /* left wave mute */ |
28 | #define AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */ |
29 | |
30 | #define AD_DS_SYDA 0x06 /* synthesis channel mix attenuation */ |
31 | #define AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */ |
32 | #define AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */ |
33 | #define AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */ |
34 | #define AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */ |
35 | |
36 | #define AD_DS_WAS 0x08 /* wave channel sample rate */ |
37 | #define AD_DS_WAS_WAS 0xffff /* sample rate mask */ |
38 | |
39 | #define AD_DS_RES 0x0a /* resampler channel sample rate */ |
40 | #define AD_DS_RES_RES 0xffff /* sample rate mask */ |
41 | |
42 | #define AD_DS_CCS 0x0c /* chip control/status */ |
43 | #define AD_DS_CCS_ADO 0x0001 /* ADC channel overflow */ |
44 | #define AD_DS_CCS_REO 0x0002 /* resampler channel overflow */ |
45 | #define AD_DS_CCS_SYU 0x0004 /* synthesis channel underflow */ |
46 | #define AD_DS_CCS_WAU 0x0008 /* wave channel underflow */ |
47 | /* bits 4 -> 7, 9, 11 -> 14 reserved */ |
48 | #define AD_DS_CCS_XTD 0x0100 /* xtd delay control (4096 clock cycles) */ |
49 | #define AD_DS_CCS_PDALL 0x0400 /* power */ |
50 | #define AD_DS_CCS_CLKEN 0x8000 /* clock */ |
51 | |
52 | #define AD_DMA_RESBA 0x40 /* RES base address */ |
53 | #define AD_DMA_RESCA 0x44 /* RES current address */ |
54 | #define AD_DMA_RESBC 0x48 /* RES base count */ |
55 | #define AD_DMA_RESCC 0x4c /* RES current count */ |
56 | |
57 | #define AD_DMA_ADCBA 0x50 /* ADC base address */ |
58 | #define AD_DMA_ADCCA 0x54 /* ADC current address */ |
59 | #define AD_DMA_ADCBC 0x58 /* ADC base count */ |
60 | #define AD_DMA_ADCCC 0x5c /* ADC current count */ |
61 | |
62 | #define AD_DMA_SYNBA 0x60 /* synth base address */ |
63 | #define AD_DMA_SYNCA 0x64 /* synth current address */ |
64 | #define AD_DMA_SYNBC 0x68 /* synth base count */ |
65 | #define AD_DMA_SYNCC 0x6c /* synth current count */ |
66 | |
67 | #define AD_DMA_WAVBA 0x70 /* wave base address */ |
68 | #define AD_DMA_WAVCA 0x74 /* wave current address */ |
69 | #define AD_DMA_WAVBC 0x78 /* wave base count */ |
70 | #define AD_DMA_WAVCC 0x7c /* wave current count */ |
71 | |
72 | #define AD_DMA_RESIC 0x80 /* RES dma interrupt current byte count */ |
73 | #define AD_DMA_RESIB 0x84 /* RES dma interrupt base byte count */ |
74 | |
75 | #define AD_DMA_ADCIC 0x88 /* ADC dma interrupt current byte count */ |
76 | #define AD_DMA_ADCIB 0x8c /* ADC dma interrupt base byte count */ |
77 | |
78 | #define AD_DMA_SYNIC 0x90 /* synth dma interrupt current byte count */ |
79 | #define AD_DMA_SYNIB 0x94 /* synth dma interrupt base byte count */ |
80 | |
81 | #define AD_DMA_WAVIC 0x98 /* wave dma interrupt current byte count */ |
82 | #define AD_DMA_WAVIB 0x9c /* wave dma interrupt base byte count */ |
83 | |
84 | #define AD_DMA_ICC 0xffffff /* current byte count mask */ |
85 | #define AD_DMA_IBC 0xffffff /* base byte count mask */ |
86 | /* bits 24 -> 31 reserved */ |
87 | |
88 | /* 4 bytes pad */ |
89 | #define AD_DMA_ADC 0xa8 /* ADC dma control and status */ |
90 | #define AD_DMA_SYNTH 0xb0 /* Synth dma control and status */ |
91 | #define AD_DMA_WAV 0xb8 /* wave dma control and status */ |
92 | #define AD_DMA_RES 0xa0 /* Resample dma control and status */ |
93 | |
94 | #define AD_DMA_SGDE 0x0001 /* SGD mode enable */ |
95 | #define AD_DMA_LOOP 0x0002 /* loop enable */ |
96 | #define AD_DMA_IM 0x000c /* interrupt mode mask */ |
97 | #define AD_DMA_IM_DIS (~AD_DMA_IM) /* disable */ |
98 | #define AD_DMA_IM_CNT 0x0004 /* interrupt on count */ |
99 | #define AD_DMA_IM_SGD 0x0008 /* interrupt on SGD flag */ |
100 | #define AD_DMA_IM_EOL 0x000c /* interrupt on End of Linked List */ |
101 | #define AD_DMA_SGDS 0x0030 /* SGD status */ |
102 | #define AD_DMA_SFLG 0x0040 /* SGD flag */ |
103 | #define AD_DMA_EOL 0x0080 /* SGD end of list */ |
104 | /* bits 8 -> 15 reserved */ |
105 | |
106 | #define AD_DMA_DISR 0xc0 /* dma interrupt status */ |
107 | #define AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */ |
108 | #define AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */ |
109 | #define AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */ |
110 | #define AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */ |
111 | /* bits 4, 5 reserved */ |
112 | #define AD_DMA_DISR_SEPS 0x000040 /* serial eeprom status */ |
113 | /* bits 7 -> 13 reserved */ |
114 | #define AD_DMA_DISR_PMAI 0x004000 /* pci master abort interrupt */ |
115 | #define AD_DMA_DISR_PTAI 0x008000 /* pci target abort interrupt */ |
116 | #define AD_DMA_DISR_PTAE 0x010000 /* pci target abort interrupt enable */ |
117 | #define AD_DMA_DISR_PMAE 0x020000 /* pci master abort interrupt enable */ |
118 | /* bits 19 -> 31 reserved */ |
119 | |
120 | /* interrupt mask */ |
121 | #define AD_INTR_MASK (AD_DMA_DISR_RESI|AD_DMA_DISR_ADCI| \ |
122 | AD_DMA_DISR_WAVI|AD_DMA_DISR_SYNI| \ |
123 | AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI) |
124 | |
125 | #define AD_DMA_CHSS 0xc4 /* dma channel stop status */ |
126 | #define AD_DMA_CHSS_RESS 0x000001 /* resampler channel stopped */ |
127 | #define AD_DMA_CHSS_ADCS 0x000002 /* ADC channel stopped */ |
128 | #define AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */ |
129 | #define AD_DMA_CHSS_WAVS 0x000008 /* wave channel stopped */ |
130 | |
131 | #define AD_GPIO_IPC 0xc8 /* gpio port control */ |
132 | #define AD_GPIO_OP 0xca /* gpio output port status */ |
133 | #define AD_GPIO_IP 0xcc /* gpio input port status */ |
134 | |
135 | #define AD_AC97_BASE 0x100 /* ac97 base register */ |
136 | |
137 | #define AD_AC97_RESET 0x100 /* reset */ |
138 | |
139 | #define AD_AC97_PWR_CTL 0x126 /* == AC97_POWERDOWN */ |
140 | #define AD_AC97_PWR_ADC 0x0001 /* ADC ready status */ |
141 | #define AD_AC97_PWR_DAC 0x0002 /* DAC ready status */ |
142 | #define AD_AC97_PWR_PR0 0x0100 /* PR0 (ADC) powerdown */ |
143 | #define AD_AC97_PWR_PR1 0x0200 /* PR1 (DAC) powerdown */ |
144 | |
145 | #define AD_MISC_CTL 0x176 /* misc control */ |
146 | #define AD_MISC_CTL_DACZ 0x8000 /* set for zero fill, unset for repeat */ |
147 | #define AD_MISC_CTL_ARSR 0x0001 /* set for SR1, unset for SR0 */ |
148 | #define AD_MISC_CTL_ALSR 0x0100 |
149 | #define AD_MISC_CTL_DLSR 0x0400 |
150 | #define AD_MISC_CTL_DRSR 0x0004 |
151 | |
152 | #define AD_AC97_SR0 0x178 /* sample rate 0, 0xbb80 == 48K */ |
153 | #define AD_AC97_SR0_48K 0xbb80 /* 48KHz */ |
154 | #define AD_AC97_SR1 0x17a /* sample rate 1 */ |
155 | |
156 | #define AD_AC97_ACIC 0x180 /* ac97 codec interface control */ |
157 | #define AD_AC97_ACIC_ACIE 0x0001 /* analog codec interface enable */ |
158 | #define AD_AC97_ACIC_ACRD 0x0002 /* analog codec reset disable */ |
159 | #define AD_AC97_ACIC_ASOE 0x0004 /* audio stream output enable */ |
160 | #define AD_AC97_ACIC_VSRM 0x0008 /* variable sample rate mode */ |
161 | #define AD_AC97_ACIC_FSDH 0x0100 /* force SDATA_OUT high */ |
162 | #define AD_AC97_ACIC_FSYH 0x0200 /* force sync high */ |
163 | #define AD_AC97_ACIC_ACRDY 0x8000 /* analog codec ready status */ |
164 | /* bits 10 -> 14 reserved */ |
165 | |
166 | |
167 | #define AD_DS_MEMSIZE 512 |
168 | #define AD_OPL_MEMSIZE 16 |
169 | #define AD_MIDI_MEMSIZE 16 |
170 | |
171 | #define AD_WAV_STATE 0 |
172 | #define AD_ADC_STATE 1 |
173 | #define AD_MAX_STATES 2 |
174 | |
175 | #define AD_CHAN_WAV 0x0001 |
176 | #define AD_CHAN_ADC 0x0002 |
177 | #define AD_CHAN_RES 0x0004 |
178 | #define AD_CHAN_SYN 0x0008 |
179 | |
180 | |
181 | /* The chip would support 4 GB buffers and 16 MB periods, |
182 | * but let's not overdo it ... */ |
183 | #define BUFFER_BYTES_MAX (256 * 1024) |
184 | #define PERIOD_BYTES_MIN 32 |
185 | #define PERIOD_BYTES_MAX (BUFFER_BYTES_MAX / 2) |
186 | #define PERIODS_MIN 2 |
187 | #define PERIODS_MAX (BUFFER_BYTES_MAX / PERIOD_BYTES_MIN) |
188 | |
189 | #endif /* __AD1889_H__ */ |
190 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9