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1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> |
6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
13 | * |
14 | * This program is free software; you can redistribute it and/or modify |
15 | * it under the terms of the GNU General Public License as published by |
16 | * the Free Software Foundation; either version 2 of the License, or (at |
17 | * your option) any later version. |
18 | * |
19 | * This program is distributed in the hope that it will be useful, but |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
22 | * General Public License for more details. |
23 | * |
24 | * You should have received a copy of the GNU General Public License along |
25 | * with this program; if not, write to the Free Software Foundation, Inc., |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
27 | * |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
29 | */ |
30 | |
31 | #include <linux/kernel.h> |
32 | #include <linux/module.h> |
33 | #include <linux/init.h> |
34 | #include <linux/cpufreq.h> |
35 | #include <linux/slab.h> |
36 | #include <linux/proc_fs.h> |
37 | #include <linux/seq_file.h> |
38 | #include <linux/acpi.h> |
39 | #include <linux/dmi.h> |
40 | #include <linux/moduleparam.h> |
41 | #include <linux/sched.h> /* need_resched() */ |
42 | #include <linux/pm_qos_params.h> |
43 | #include <linux/clockchips.h> |
44 | #include <linux/cpuidle.h> |
45 | #include <linux/irqflags.h> |
46 | |
47 | /* |
48 | * Include the apic definitions for x86 to have the APIC timer related defines |
49 | * available also for UP (on SMP it gets magically included via linux/smp.h). |
50 | * asm/acpi.h is not an option, as it would require more include magic. Also |
51 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. |
52 | */ |
53 | #ifdef CONFIG_X86 |
54 | #include <asm/apic.h> |
55 | #endif |
56 | |
57 | #include <asm/io.h> |
58 | #include <asm/uaccess.h> |
59 | |
60 | #include <acpi/acpi_bus.h> |
61 | #include <acpi/processor.h> |
62 | #include <asm/processor.h> |
63 | |
64 | #define PREFIX "ACPI: " |
65 | |
66 | #define ACPI_PROCESSOR_CLASS "processor" |
67 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
68 | ACPI_MODULE_NAME("processor_idle"); |
69 | #define ACPI_PROCESSOR_FILE_POWER "power" |
70 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
71 | #define C2_OVERHEAD 1 /* 1us */ |
72 | #define C3_OVERHEAD 1 /* 1us */ |
73 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) |
74 | |
75 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
76 | module_param(max_cstate, uint, 0000); |
77 | static unsigned int nocst __read_mostly; |
78 | module_param(nocst, uint, 0000); |
79 | |
80 | static unsigned int latency_factor __read_mostly = 2; |
81 | module_param(latency_factor, uint, 0644); |
82 | |
83 | static s64 us_to_pm_timer_ticks(s64 t) |
84 | { |
85 | return div64_u64(t * PM_TIMER_FREQUENCY, 1000000); |
86 | } |
87 | /* |
88 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. |
89 | * For now disable this. Probably a bug somewhere else. |
90 | * |
91 | * To skip this limit, boot/load with a large max_cstate limit. |
92 | */ |
93 | static int set_max_cstate(const struct dmi_system_id *id) |
94 | { |
95 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) |
96 | return 0; |
97 | |
98 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
99 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
100 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); |
101 | |
102 | max_cstate = (long)id->driver_data; |
103 | |
104 | return 0; |
105 | } |
106 | |
107 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
108 | callers to only run once -AK */ |
109 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { |
110 | { set_max_cstate, "Clevo 5600D", { |
111 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), |
112 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, |
113 | (void *)2}, |
114 | { set_max_cstate, "Pavilion zv5000", { |
115 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), |
116 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, |
117 | (void *)1}, |
118 | { set_max_cstate, "Asus L8400B", { |
119 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), |
120 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, |
121 | (void *)1}, |
122 | {}, |
123 | }; |
124 | |
125 | |
126 | /* |
127 | * Callers should disable interrupts before the call and enable |
128 | * interrupts after return. |
129 | */ |
130 | static void acpi_safe_halt(void) |
131 | { |
132 | current_thread_info()->status &= ~TS_POLLING; |
133 | /* |
134 | * TS_POLLING-cleared state must be visible before we |
135 | * test NEED_RESCHED: |
136 | */ |
137 | smp_mb(); |
138 | if (!need_resched()) { |
139 | safe_halt(); |
140 | local_irq_disable(); |
141 | } |
142 | current_thread_info()->status |= TS_POLLING; |
143 | } |
144 | |
145 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
146 | |
147 | /* |
148 | * Some BIOS implementations switch to C3 in the published C2 state. |
149 | * This seems to be a common problem on AMD boxen, but other vendors |
150 | * are affected too. We pick the most conservative approach: we assume |
151 | * that the local APIC stops in both C2 and C3. |
152 | */ |
153 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
154 | struct acpi_processor_cx *cx) |
155 | { |
156 | struct acpi_processor_power *pwr = &pr->power; |
157 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
158 | |
159 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
160 | return; |
161 | |
162 | if (boot_cpu_has(X86_FEATURE_AMDC1E)) |
163 | type = ACPI_STATE_C1; |
164 | |
165 | /* |
166 | * Check, if one of the previous states already marked the lapic |
167 | * unstable |
168 | */ |
169 | if (pwr->timer_broadcast_on_state < state) |
170 | return; |
171 | |
172 | if (cx->type >= type) |
173 | pr->power.timer_broadcast_on_state = state; |
174 | } |
175 | |
176 | static void __lapic_timer_propagate_broadcast(void *arg) |
177 | { |
178 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
179 | unsigned long reason; |
180 | |
181 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? |
182 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; |
183 | |
184 | clockevents_notify(reason, &pr->id); |
185 | } |
186 | |
187 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
188 | { |
189 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, |
190 | (void *)pr, 1); |
191 | } |
192 | |
193 | /* Power(C) State timer broadcast control */ |
194 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
195 | struct acpi_processor_cx *cx, |
196 | int broadcast) |
197 | { |
198 | int state = cx - pr->power.states; |
199 | |
200 | if (state >= pr->power.timer_broadcast_on_state) { |
201 | unsigned long reason; |
202 | |
203 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : |
204 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; |
205 | clockevents_notify(reason, &pr->id); |
206 | } |
207 | } |
208 | |
209 | #else |
210 | |
211 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
212 | struct acpi_processor_cx *cstate) { } |
213 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
214 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
215 | struct acpi_processor_cx *cx, |
216 | int broadcast) |
217 | { |
218 | } |
219 | |
220 | #endif |
221 | |
222 | /* |
223 | * Suspend / resume control |
224 | */ |
225 | static int acpi_idle_suspend; |
226 | static u32 saved_bm_rld; |
227 | |
228 | static void acpi_idle_bm_rld_save(void) |
229 | { |
230 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); |
231 | } |
232 | static void acpi_idle_bm_rld_restore(void) |
233 | { |
234 | u32 resumed_bm_rld; |
235 | |
236 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); |
237 | |
238 | if (resumed_bm_rld != saved_bm_rld) |
239 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); |
240 | } |
241 | |
242 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) |
243 | { |
244 | if (acpi_idle_suspend == 1) |
245 | return 0; |
246 | |
247 | acpi_idle_bm_rld_save(); |
248 | acpi_idle_suspend = 1; |
249 | return 0; |
250 | } |
251 | |
252 | int acpi_processor_resume(struct acpi_device * device) |
253 | { |
254 | if (acpi_idle_suspend == 0) |
255 | return 0; |
256 | |
257 | acpi_idle_bm_rld_restore(); |
258 | acpi_idle_suspend = 0; |
259 | return 0; |
260 | } |
261 | |
262 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
263 | static void tsc_check_state(int state) |
264 | { |
265 | switch (boot_cpu_data.x86_vendor) { |
266 | case X86_VENDOR_AMD: |
267 | case X86_VENDOR_INTEL: |
268 | /* |
269 | * AMD Fam10h TSC will tick in all |
270 | * C/P/S0/S1 states when this bit is set. |
271 | */ |
272 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
273 | return; |
274 | |
275 | /*FALL THROUGH*/ |
276 | default: |
277 | /* TSC could halt in idle, so notify users */ |
278 | if (state > ACPI_STATE_C1) |
279 | mark_tsc_unstable("TSC halts in idle"); |
280 | } |
281 | } |
282 | #else |
283 | static void tsc_check_state(int state) { return; } |
284 | #endif |
285 | |
286 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
287 | { |
288 | |
289 | if (!pr) |
290 | return -EINVAL; |
291 | |
292 | if (!pr->pblk) |
293 | return -ENODEV; |
294 | |
295 | /* if info is obtained from pblk/fadt, type equals state */ |
296 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
297 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; |
298 | |
299 | #ifndef CONFIG_HOTPLUG_CPU |
300 | /* |
301 | * Check for P_LVL2_UP flag before entering C2 and above on |
302 | * an SMP system. |
303 | */ |
304 | if ((num_online_cpus() > 1) && |
305 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
306 | return -ENODEV; |
307 | #endif |
308 | |
309 | /* determine C2 and C3 address from pblk */ |
310 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; |
311 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; |
312 | |
313 | /* determine latencies from FADT */ |
314 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
315 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; |
316 | |
317 | /* |
318 | * FADT specified C2 latency must be less than or equal to |
319 | * 100 microseconds. |
320 | */ |
321 | if (acpi_gbl_FADT.C2latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { |
322 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
323 | "C2 latency too large [%d]\n", acpi_gbl_FADT.C2latency)); |
324 | /* invalidate C2 */ |
325 | pr->power.states[ACPI_STATE_C2].address = 0; |
326 | } |
327 | |
328 | /* |
329 | * FADT supplied C3 latency must be less than or equal to |
330 | * 1000 microseconds. |
331 | */ |
332 | if (acpi_gbl_FADT.C3latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { |
333 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
334 | "C3 latency too large [%d]\n", acpi_gbl_FADT.C3latency)); |
335 | /* invalidate C3 */ |
336 | pr->power.states[ACPI_STATE_C3].address = 0; |
337 | } |
338 | |
339 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
340 | "lvl2[0x%08x] lvl3[0x%08x]\n", |
341 | pr->power.states[ACPI_STATE_C2].address, |
342 | pr->power.states[ACPI_STATE_C3].address)); |
343 | |
344 | return 0; |
345 | } |
346 | |
347 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
348 | { |
349 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
350 | /* set the first C-State to C1 */ |
351 | /* all processors need to support C1 */ |
352 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; |
353 | pr->power.states[ACPI_STATE_C1].valid = 1; |
354 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
355 | } |
356 | /* the C0 state only exists as a filler in our array */ |
357 | pr->power.states[ACPI_STATE_C0].valid = 1; |
358 | return 0; |
359 | } |
360 | |
361 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
362 | { |
363 | acpi_status status = 0; |
364 | u64 count; |
365 | int current_count; |
366 | int i; |
367 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; |
368 | union acpi_object *cst; |
369 | |
370 | |
371 | if (nocst) |
372 | return -ENODEV; |
373 | |
374 | current_count = 0; |
375 | |
376 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); |
377 | if (ACPI_FAILURE(status)) { |
378 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); |
379 | return -ENODEV; |
380 | } |
381 | |
382 | cst = buffer.pointer; |
383 | |
384 | /* There must be at least 2 elements */ |
385 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { |
386 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
387 | status = -EFAULT; |
388 | goto end; |
389 | } |
390 | |
391 | count = cst->package.elements[0].integer.value; |
392 | |
393 | /* Validate number of power states. */ |
394 | if (count < 1 || count != cst->package.count - 1) { |
395 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
396 | status = -EFAULT; |
397 | goto end; |
398 | } |
399 | |
400 | /* Tell driver that at least _CST is supported. */ |
401 | pr->flags.has_cst = 1; |
402 | |
403 | for (i = 1; i <= count; i++) { |
404 | union acpi_object *element; |
405 | union acpi_object *obj; |
406 | struct acpi_power_register *reg; |
407 | struct acpi_processor_cx cx; |
408 | |
409 | memset(&cx, 0, sizeof(cx)); |
410 | |
411 | element = &(cst->package.elements[i]); |
412 | if (element->type != ACPI_TYPE_PACKAGE) |
413 | continue; |
414 | |
415 | if (element->package.count != 4) |
416 | continue; |
417 | |
418 | obj = &(element->package.elements[0]); |
419 | |
420 | if (obj->type != ACPI_TYPE_BUFFER) |
421 | continue; |
422 | |
423 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
424 | |
425 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && |
426 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
427 | continue; |
428 | |
429 | /* There should be an easy way to extract an integer... */ |
430 | obj = &(element->package.elements[1]); |
431 | if (obj->type != ACPI_TYPE_INTEGER) |
432 | continue; |
433 | |
434 | cx.type = obj->integer.value; |
435 | /* |
436 | * Some buggy BIOSes won't list C1 in _CST - |
437 | * Let acpi_processor_get_power_info_default() handle them later |
438 | */ |
439 | if (i == 1 && cx.type != ACPI_STATE_C1) |
440 | current_count++; |
441 | |
442 | cx.address = reg->address; |
443 | cx.index = current_count + 1; |
444 | |
445 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
446 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
447 | if (acpi_processor_ffh_cstate_probe |
448 | (pr->id, &cx, reg) == 0) { |
449 | cx.entry_method = ACPI_CSTATE_FFH; |
450 | } else if (cx.type == ACPI_STATE_C1) { |
451 | /* |
452 | * C1 is a special case where FIXED_HARDWARE |
453 | * can be handled in non-MWAIT way as well. |
454 | * In that case, save this _CST entry info. |
455 | * Otherwise, ignore this info and continue. |
456 | */ |
457 | cx.entry_method = ACPI_CSTATE_HALT; |
458 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
459 | } else { |
460 | continue; |
461 | } |
462 | if (cx.type == ACPI_STATE_C1 && |
463 | (idle_halt || idle_nomwait)) { |
464 | /* |
465 | * In most cases the C1 space_id obtained from |
466 | * _CST object is FIXED_HARDWARE access mode. |
467 | * But when the option of idle=halt is added, |
468 | * the entry_method type should be changed from |
469 | * CSTATE_FFH to CSTATE_HALT. |
470 | * When the option of idle=nomwait is added, |
471 | * the C1 entry_method type should be |
472 | * CSTATE_HALT. |
473 | */ |
474 | cx.entry_method = ACPI_CSTATE_HALT; |
475 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
476 | } |
477 | } else { |
478 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", |
479 | cx.address); |
480 | } |
481 | |
482 | if (cx.type == ACPI_STATE_C1) { |
483 | cx.valid = 1; |
484 | } |
485 | |
486 | obj = &(element->package.elements[2]); |
487 | if (obj->type != ACPI_TYPE_INTEGER) |
488 | continue; |
489 | |
490 | cx.latency = obj->integer.value; |
491 | |
492 | obj = &(element->package.elements[3]); |
493 | if (obj->type != ACPI_TYPE_INTEGER) |
494 | continue; |
495 | |
496 | cx.power = obj->integer.value; |
497 | |
498 | current_count++; |
499 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); |
500 | |
501 | /* |
502 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 |
503 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) |
504 | */ |
505 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { |
506 | printk(KERN_WARNING |
507 | "Limiting number of power states to max (%d)\n", |
508 | ACPI_PROCESSOR_MAX_POWER); |
509 | printk(KERN_WARNING |
510 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); |
511 | break; |
512 | } |
513 | } |
514 | |
515 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
516 | current_count)); |
517 | |
518 | /* Validate number of power states discovered */ |
519 | if (current_count < 2) |
520 | status = -EFAULT; |
521 | |
522 | end: |
523 | kfree(buffer.pointer); |
524 | |
525 | return status; |
526 | } |
527 | |
528 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
529 | struct acpi_processor_cx *cx) |
530 | { |
531 | static int bm_check_flag = -1; |
532 | static int bm_control_flag = -1; |
533 | |
534 | |
535 | if (!cx->address) |
536 | return; |
537 | |
538 | /* |
539 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) |
540 | * DMA transfers are used by any ISA device to avoid livelock. |
541 | * Note that we could disable Type-F DMA (as recommended by |
542 | * the erratum), but this is known to disrupt certain ISA |
543 | * devices thus we take the conservative approach. |
544 | */ |
545 | else if (errata.piix4.fdma) { |
546 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
547 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
548 | return; |
549 | } |
550 | |
551 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
552 | if (bm_check_flag == -1) { |
553 | /* Determine whether bm_check is needed based on CPU */ |
554 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); |
555 | bm_check_flag = pr->flags.bm_check; |
556 | bm_control_flag = pr->flags.bm_control; |
557 | } else { |
558 | pr->flags.bm_check = bm_check_flag; |
559 | pr->flags.bm_control = bm_control_flag; |
560 | } |
561 | |
562 | if (pr->flags.bm_check) { |
563 | if (!pr->flags.bm_control) { |
564 | if (pr->flags.has_cst != 1) { |
565 | /* bus mastering control is necessary */ |
566 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
567 | "C3 support requires BM control\n")); |
568 | return; |
569 | } else { |
570 | /* Here we enter C3 without bus mastering */ |
571 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
572 | "C3 support without BM control\n")); |
573 | } |
574 | } |
575 | } else { |
576 | /* |
577 | * WBINVD should be set in fadt, for C3 state to be |
578 | * supported on when bm_check is not required. |
579 | */ |
580 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
581 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
582 | "Cache invalidation should work properly" |
583 | " for C3 to be enabled on SMP systems\n")); |
584 | return; |
585 | } |
586 | } |
587 | |
588 | /* |
589 | * Otherwise we've met all of our C3 requirements. |
590 | * Normalize the C3 latency to expidite policy. Enable |
591 | * checking of bus mastering status (bm_check) so we can |
592 | * use this in our C3 policy |
593 | */ |
594 | cx->valid = 1; |
595 | |
596 | cx->latency_ticks = cx->latency; |
597 | /* |
598 | * On older chipsets, BM_RLD needs to be set |
599 | * in order for Bus Master activity to wake the |
600 | * system from C3. Newer chipsets handle DMA |
601 | * during C3 automatically and BM_RLD is a NOP. |
602 | * In either case, the proper way to |
603 | * handle BM_RLD is to set it and leave it set. |
604 | */ |
605 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
606 | |
607 | return; |
608 | } |
609 | |
610 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
611 | { |
612 | unsigned int i; |
613 | unsigned int working = 0; |
614 | |
615 | pr->power.timer_broadcast_on_state = INT_MAX; |
616 | |
617 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
618 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
619 | |
620 | switch (cx->type) { |
621 | case ACPI_STATE_C1: |
622 | cx->valid = 1; |
623 | break; |
624 | |
625 | case ACPI_STATE_C2: |
626 | if (!cx->address) |
627 | break; |
628 | cx->valid = 1; |
629 | cx->latency_ticks = cx->latency; /* Normalize latency */ |
630 | break; |
631 | |
632 | case ACPI_STATE_C3: |
633 | acpi_processor_power_verify_c3(pr, cx); |
634 | break; |
635 | } |
636 | if (!cx->valid) |
637 | continue; |
638 | |
639 | lapic_timer_check_state(i, pr, cx); |
640 | tsc_check_state(cx->type); |
641 | working++; |
642 | } |
643 | |
644 | lapic_timer_propagate_broadcast(pr); |
645 | |
646 | return (working); |
647 | } |
648 | |
649 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
650 | { |
651 | unsigned int i; |
652 | int result; |
653 | |
654 | |
655 | /* NOTE: the idle thread may not be running while calling |
656 | * this function */ |
657 | |
658 | /* Zero initialize all the C-states info. */ |
659 | memset(pr->power.states, 0, sizeof(pr->power.states)); |
660 | |
661 | result = acpi_processor_get_power_info_cst(pr); |
662 | if (result == -ENODEV) |
663 | result = acpi_processor_get_power_info_fadt(pr); |
664 | |
665 | if (result) |
666 | return result; |
667 | |
668 | acpi_processor_get_power_info_default(pr); |
669 | |
670 | pr->power.count = acpi_processor_power_verify(pr); |
671 | |
672 | /* |
673 | * if one state of type C2 or C3 is available, mark this |
674 | * CPU as being "idle manageable" |
675 | */ |
676 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
677 | if (pr->power.states[i].valid) { |
678 | pr->power.count = i; |
679 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
680 | pr->flags.power = 1; |
681 | } |
682 | } |
683 | |
684 | return 0; |
685 | } |
686 | |
687 | #ifdef CONFIG_ACPI_PROCFS |
688 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
689 | { |
690 | struct acpi_processor *pr = seq->private; |
691 | unsigned int i; |
692 | |
693 | |
694 | if (!pr) |
695 | goto end; |
696 | |
697 | seq_printf(seq, "active state: C%zd\n" |
698 | "max_cstate: C%d\n" |
699 | "maximum allowed latency: %d usec\n", |
700 | pr->power.state ? pr->power.state - pr->power.states : 0, |
701 | max_cstate, pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); |
702 | |
703 | seq_puts(seq, "states:\n"); |
704 | |
705 | for (i = 1; i <= pr->power.count; i++) { |
706 | seq_printf(seq, " %cC%d: ", |
707 | (&pr->power.states[i] == |
708 | pr->power.state ? '*' : ' '), i); |
709 | |
710 | if (!pr->power.states[i].valid) { |
711 | seq_puts(seq, "<not supported>\n"); |
712 | continue; |
713 | } |
714 | |
715 | switch (pr->power.states[i].type) { |
716 | case ACPI_STATE_C1: |
717 | seq_printf(seq, "type[C1] "); |
718 | break; |
719 | case ACPI_STATE_C2: |
720 | seq_printf(seq, "type[C2] "); |
721 | break; |
722 | case ACPI_STATE_C3: |
723 | seq_printf(seq, "type[C3] "); |
724 | break; |
725 | default: |
726 | seq_printf(seq, "type[--] "); |
727 | break; |
728 | } |
729 | |
730 | if (pr->power.states[i].promotion.state) |
731 | seq_printf(seq, "promotion[C%zd] ", |
732 | (pr->power.states[i].promotion.state - |
733 | pr->power.states)); |
734 | else |
735 | seq_puts(seq, "promotion[--] "); |
736 | |
737 | if (pr->power.states[i].demotion.state) |
738 | seq_printf(seq, "demotion[C%zd] ", |
739 | (pr->power.states[i].demotion.state - |
740 | pr->power.states)); |
741 | else |
742 | seq_puts(seq, "demotion[--] "); |
743 | |
744 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
745 | pr->power.states[i].latency, |
746 | pr->power.states[i].usage, |
747 | (unsigned long long)pr->power.states[i].time); |
748 | } |
749 | |
750 | end: |
751 | return 0; |
752 | } |
753 | |
754 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) |
755 | { |
756 | return single_open(file, acpi_processor_power_seq_show, |
757 | PDE(inode)->data); |
758 | } |
759 | |
760 | static const struct file_operations acpi_processor_power_fops = { |
761 | .owner = THIS_MODULE, |
762 | .open = acpi_processor_power_open_fs, |
763 | .read = seq_read, |
764 | .llseek = seq_lseek, |
765 | .release = single_release, |
766 | }; |
767 | #endif |
768 | |
769 | /** |
770 | * acpi_idle_bm_check - checks if bus master activity was detected |
771 | */ |
772 | static int acpi_idle_bm_check(void) |
773 | { |
774 | u32 bm_status = 0; |
775 | |
776 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
777 | if (bm_status) |
778 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
779 | /* |
780 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect |
781 | * the true state of bus mastering activity; forcing us to |
782 | * manually check the BMIDEA bit of each IDE channel. |
783 | */ |
784 | else if (errata.piix4.bmisx) { |
785 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) |
786 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) |
787 | bm_status = 1; |
788 | } |
789 | return bm_status; |
790 | } |
791 | |
792 | /** |
793 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry |
794 | * @cx: cstate data |
795 | * |
796 | * Caller disables interrupt before call and enables interrupt after return. |
797 | */ |
798 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) |
799 | { |
800 | /* Don't trace irqs off for idle */ |
801 | stop_critical_timings(); |
802 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
803 | /* Call into architectural FFH based C-state */ |
804 | acpi_processor_ffh_cstate_enter(cx); |
805 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
806 | acpi_safe_halt(); |
807 | } else { |
808 | int unused; |
809 | /* IO port based C-state */ |
810 | inb(cx->address); |
811 | /* Dummy wait op - must do something useless after P_LVL2 read |
812 | because chipsets cannot guarantee that STPCLK# signal |
813 | gets asserted in time to freeze execution properly. */ |
814 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); |
815 | } |
816 | start_critical_timings(); |
817 | } |
818 | |
819 | /** |
820 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type |
821 | * @dev: the target CPU |
822 | * @state: the state data |
823 | * |
824 | * This is equivalent to the HALT instruction. |
825 | */ |
826 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, |
827 | struct cpuidle_state *state) |
828 | { |
829 | ktime_t kt1, kt2; |
830 | s64 idle_time; |
831 | struct acpi_processor *pr; |
832 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); |
833 | |
834 | pr = __get_cpu_var(processors); |
835 | |
836 | if (unlikely(!pr)) |
837 | return 0; |
838 | |
839 | local_irq_disable(); |
840 | |
841 | /* Do not access any ACPI IO ports in suspend path */ |
842 | if (acpi_idle_suspend) { |
843 | local_irq_enable(); |
844 | cpu_relax(); |
845 | return 0; |
846 | } |
847 | |
848 | lapic_timer_state_broadcast(pr, cx, 1); |
849 | kt1 = ktime_get_real(); |
850 | acpi_idle_do_entry(cx); |
851 | kt2 = ktime_get_real(); |
852 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); |
853 | |
854 | local_irq_enable(); |
855 | cx->usage++; |
856 | lapic_timer_state_broadcast(pr, cx, 0); |
857 | |
858 | return idle_time; |
859 | } |
860 | |
861 | /** |
862 | * acpi_idle_enter_simple - enters an ACPI state without BM handling |
863 | * @dev: the target CPU |
864 | * @state: the state data |
865 | */ |
866 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, |
867 | struct cpuidle_state *state) |
868 | { |
869 | struct acpi_processor *pr; |
870 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); |
871 | ktime_t kt1, kt2; |
872 | s64 idle_time; |
873 | s64 sleep_ticks = 0; |
874 | |
875 | pr = __get_cpu_var(processors); |
876 | |
877 | if (unlikely(!pr)) |
878 | return 0; |
879 | |
880 | if (acpi_idle_suspend) |
881 | return(acpi_idle_enter_c1(dev, state)); |
882 | |
883 | local_irq_disable(); |
884 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
885 | current_thread_info()->status &= ~TS_POLLING; |
886 | /* |
887 | * TS_POLLING-cleared state must be visible before we test |
888 | * NEED_RESCHED: |
889 | */ |
890 | smp_mb(); |
891 | } |
892 | |
893 | if (unlikely(need_resched())) { |
894 | current_thread_info()->status |= TS_POLLING; |
895 | local_irq_enable(); |
896 | return 0; |
897 | } |
898 | |
899 | /* |
900 | * Must be done before busmaster disable as we might need to |
901 | * access HPET ! |
902 | */ |
903 | lapic_timer_state_broadcast(pr, cx, 1); |
904 | |
905 | if (cx->type == ACPI_STATE_C3) |
906 | ACPI_FLUSH_CPU_CACHE(); |
907 | |
908 | kt1 = ktime_get_real(); |
909 | /* Tell the scheduler that we are going deep-idle: */ |
910 | sched_clock_idle_sleep_event(); |
911 | acpi_idle_do_entry(cx); |
912 | kt2 = ktime_get_real(); |
913 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); |
914 | |
915 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
916 | |
917 | /* Tell the scheduler how much we idled: */ |
918 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); |
919 | |
920 | local_irq_enable(); |
921 | current_thread_info()->status |= TS_POLLING; |
922 | |
923 | cx->usage++; |
924 | |
925 | lapic_timer_state_broadcast(pr, cx, 0); |
926 | cx->time += sleep_ticks; |
927 | return idle_time; |
928 | } |
929 | |
930 | static int c3_cpu_count; |
931 | static DEFINE_SPINLOCK(c3_lock); |
932 | |
933 | /** |
934 | * acpi_idle_enter_bm - enters C3 with proper BM handling |
935 | * @dev: the target CPU |
936 | * @state: the state data |
937 | * |
938 | * If BM is detected, the deepest non-C3 idle state is entered instead. |
939 | */ |
940 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, |
941 | struct cpuidle_state *state) |
942 | { |
943 | struct acpi_processor *pr; |
944 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); |
945 | ktime_t kt1, kt2; |
946 | s64 idle_time; |
947 | s64 sleep_ticks = 0; |
948 | |
949 | |
950 | pr = __get_cpu_var(processors); |
951 | |
952 | if (unlikely(!pr)) |
953 | return 0; |
954 | |
955 | if (acpi_idle_suspend) |
956 | return(acpi_idle_enter_c1(dev, state)); |
957 | |
958 | if (acpi_idle_bm_check()) { |
959 | if (dev->safe_state) { |
960 | dev->last_state = dev->safe_state; |
961 | return dev->safe_state->enter(dev, dev->safe_state); |
962 | } else { |
963 | local_irq_disable(); |
964 | acpi_safe_halt(); |
965 | local_irq_enable(); |
966 | return 0; |
967 | } |
968 | } |
969 | |
970 | local_irq_disable(); |
971 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
972 | current_thread_info()->status &= ~TS_POLLING; |
973 | /* |
974 | * TS_POLLING-cleared state must be visible before we test |
975 | * NEED_RESCHED: |
976 | */ |
977 | smp_mb(); |
978 | } |
979 | |
980 | if (unlikely(need_resched())) { |
981 | current_thread_info()->status |= TS_POLLING; |
982 | local_irq_enable(); |
983 | return 0; |
984 | } |
985 | |
986 | acpi_unlazy_tlb(smp_processor_id()); |
987 | |
988 | /* Tell the scheduler that we are going deep-idle: */ |
989 | sched_clock_idle_sleep_event(); |
990 | /* |
991 | * Must be done before busmaster disable as we might need to |
992 | * access HPET ! |
993 | */ |
994 | lapic_timer_state_broadcast(pr, cx, 1); |
995 | |
996 | kt1 = ktime_get_real(); |
997 | /* |
998 | * disable bus master |
999 | * bm_check implies we need ARB_DIS |
1000 | * !bm_check implies we need cache flush |
1001 | * bm_control implies whether we can do ARB_DIS |
1002 | * |
1003 | * That leaves a case where bm_check is set and bm_control is |
1004 | * not set. In that case we cannot do much, we enter C3 |
1005 | * without doing anything. |
1006 | */ |
1007 | if (pr->flags.bm_check && pr->flags.bm_control) { |
1008 | spin_lock(&c3_lock); |
1009 | c3_cpu_count++; |
1010 | /* Disable bus master arbitration when all CPUs are in C3 */ |
1011 | if (c3_cpu_count == num_online_cpus()) |
1012 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
1013 | spin_unlock(&c3_lock); |
1014 | } else if (!pr->flags.bm_check) { |
1015 | ACPI_FLUSH_CPU_CACHE(); |
1016 | } |
1017 | |
1018 | acpi_idle_do_entry(cx); |
1019 | |
1020 | /* Re-enable bus master arbitration */ |
1021 | if (pr->flags.bm_check && pr->flags.bm_control) { |
1022 | spin_lock(&c3_lock); |
1023 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
1024 | c3_cpu_count--; |
1025 | spin_unlock(&c3_lock); |
1026 | } |
1027 | kt2 = ktime_get_real(); |
1028 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); |
1029 | |
1030 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
1031 | /* Tell the scheduler how much we idled: */ |
1032 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); |
1033 | |
1034 | local_irq_enable(); |
1035 | current_thread_info()->status |= TS_POLLING; |
1036 | |
1037 | cx->usage++; |
1038 | |
1039 | lapic_timer_state_broadcast(pr, cx, 0); |
1040 | cx->time += sleep_ticks; |
1041 | return idle_time; |
1042 | } |
1043 | |
1044 | struct cpuidle_driver acpi_idle_driver = { |
1045 | .name = "acpi_idle", |
1046 | .owner = THIS_MODULE, |
1047 | }; |
1048 | |
1049 | /** |
1050 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE |
1051 | * @pr: the ACPI processor |
1052 | */ |
1053 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) |
1054 | { |
1055 | int i, count = CPUIDLE_DRIVER_STATE_START; |
1056 | struct acpi_processor_cx *cx; |
1057 | struct cpuidle_state *state; |
1058 | struct cpuidle_device *dev = &pr->power.dev; |
1059 | |
1060 | if (!pr->flags.power_setup_done) |
1061 | return -EINVAL; |
1062 | |
1063 | if (pr->flags.power == 0) { |
1064 | return -EINVAL; |
1065 | } |
1066 | |
1067 | dev->cpu = pr->id; |
1068 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
1069 | dev->states[i].name[0] = '\0'; |
1070 | dev->states[i].desc[0] = '\0'; |
1071 | } |
1072 | |
1073 | if (max_cstate == 0) |
1074 | max_cstate = 1; |
1075 | |
1076 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1077 | cx = &pr->power.states[i]; |
1078 | state = &dev->states[count]; |
1079 | |
1080 | if (!cx->valid) |
1081 | continue; |
1082 | |
1083 | #ifdef CONFIG_HOTPLUG_CPU |
1084 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && |
1085 | !pr->flags.has_cst && |
1086 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
1087 | continue; |
1088 | #endif |
1089 | cpuidle_set_statedata(state, cx); |
1090 | |
1091 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); |
1092 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
1093 | state->exit_latency = cx->latency; |
1094 | state->target_residency = cx->latency * latency_factor; |
1095 | state->power_usage = cx->power; |
1096 | |
1097 | state->flags = 0; |
1098 | switch (cx->type) { |
1099 | case ACPI_STATE_C1: |
1100 | state->flags |= CPUIDLE_FLAG_SHALLOW; |
1101 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1102 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
1103 | |
1104 | state->enter = acpi_idle_enter_c1; |
1105 | dev->safe_state = state; |
1106 | break; |
1107 | |
1108 | case ACPI_STATE_C2: |
1109 | state->flags |= CPUIDLE_FLAG_BALANCED; |
1110 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
1111 | state->enter = acpi_idle_enter_simple; |
1112 | dev->safe_state = state; |
1113 | break; |
1114 | |
1115 | case ACPI_STATE_C3: |
1116 | state->flags |= CPUIDLE_FLAG_DEEP; |
1117 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
1118 | state->flags |= CPUIDLE_FLAG_CHECK_BM; |
1119 | state->enter = pr->flags.bm_check ? |
1120 | acpi_idle_enter_bm : |
1121 | acpi_idle_enter_simple; |
1122 | break; |
1123 | } |
1124 | |
1125 | count++; |
1126 | if (count == CPUIDLE_STATE_MAX) |
1127 | break; |
1128 | } |
1129 | |
1130 | dev->state_count = count; |
1131 | |
1132 | if (!count) |
1133 | return -EINVAL; |
1134 | |
1135 | return 0; |
1136 | } |
1137 | |
1138 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) |
1139 | { |
1140 | int ret = 0; |
1141 | |
1142 | if (boot_option_idle_override) |
1143 | return 0; |
1144 | |
1145 | if (!pr) |
1146 | return -EINVAL; |
1147 | |
1148 | if (nocst) { |
1149 | return -ENODEV; |
1150 | } |
1151 | |
1152 | if (!pr->flags.power_setup_done) |
1153 | return -ENODEV; |
1154 | |
1155 | cpuidle_pause_and_lock(); |
1156 | cpuidle_disable_device(&pr->power.dev); |
1157 | acpi_processor_get_power_info(pr); |
1158 | if (pr->flags.power) { |
1159 | acpi_processor_setup_cpuidle(pr); |
1160 | ret = cpuidle_enable_device(&pr->power.dev); |
1161 | } |
1162 | cpuidle_resume_and_unlock(); |
1163 | |
1164 | return ret; |
1165 | } |
1166 | |
1167 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
1168 | struct acpi_device *device) |
1169 | { |
1170 | acpi_status status = 0; |
1171 | static int first_run; |
1172 | #ifdef CONFIG_ACPI_PROCFS |
1173 | struct proc_dir_entry *entry = NULL; |
1174 | #endif |
1175 | |
1176 | if (boot_option_idle_override) |
1177 | return 0; |
1178 | |
1179 | if (!first_run) { |
1180 | if (idle_halt) { |
1181 | /* |
1182 | * When the boot option of "idle=halt" is added, halt |
1183 | * is used for CPU IDLE. |
1184 | * In such case C2/C3 is meaningless. So the max_cstate |
1185 | * is set to one. |
1186 | */ |
1187 | max_cstate = 1; |
1188 | } |
1189 | dmi_check_system(processor_power_dmi_table); |
1190 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1191 | if (max_cstate < ACPI_C_STATES_MAX) |
1192 | printk(KERN_NOTICE |
1193 | "ACPI: processor limited to max C-state %d\n", |
1194 | max_cstate); |
1195 | first_run++; |
1196 | } |
1197 | |
1198 | if (!pr) |
1199 | return -EINVAL; |
1200 | |
1201 | if (acpi_gbl_FADT.cst_control && !nocst) { |
1202 | status = |
1203 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1204 | if (ACPI_FAILURE(status)) { |
1205 | ACPI_EXCEPTION((AE_INFO, status, |
1206 | "Notifying BIOS of _CST ability failed")); |
1207 | } |
1208 | } |
1209 | |
1210 | acpi_processor_get_power_info(pr); |
1211 | pr->flags.power_setup_done = 1; |
1212 | |
1213 | /* |
1214 | * Install the idle handler if processor power management is supported. |
1215 | * Note that we use previously set idle handler will be used on |
1216 | * platforms that only support C1. |
1217 | */ |
1218 | if (pr->flags.power) { |
1219 | acpi_processor_setup_cpuidle(pr); |
1220 | if (cpuidle_register_device(&pr->power.dev)) |
1221 | return -EIO; |
1222 | } |
1223 | #ifdef CONFIG_ACPI_PROCFS |
1224 | /* 'power' [R] */ |
1225 | entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, |
1226 | S_IRUGO, acpi_device_dir(device), |
1227 | &acpi_processor_power_fops, |
1228 | acpi_driver_data(device)); |
1229 | if (!entry) |
1230 | return -EIO; |
1231 | #endif |
1232 | return 0; |
1233 | } |
1234 | |
1235 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1236 | struct acpi_device *device) |
1237 | { |
1238 | if (boot_option_idle_override) |
1239 | return 0; |
1240 | |
1241 | cpuidle_unregister_device(&pr->power.dev); |
1242 | pr->flags.power_setup_done = 0; |
1243 | |
1244 | #ifdef CONFIG_ACPI_PROCFS |
1245 | if (acpi_device_dir(device)) |
1246 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1247 | acpi_device_dir(device)); |
1248 | #endif |
1249 | |
1250 | return 0; |
1251 | } |
1252 |
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9