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1 | /* |
2 | * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers. |
3 | * |
4 | * This driver is heavily based upon: |
5 | * |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 |
7 | * |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. |
10 | * Portions Copyright (C) 2003 Red Hat Inc |
11 | * Portions Copyright (C) 2005-2009 MontaVista Software, Inc. |
12 | * |
13 | * |
14 | * TODO |
15 | * Work out best PLL policy |
16 | */ |
17 | |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> |
20 | #include <linux/pci.h> |
21 | #include <linux/init.h> |
22 | #include <linux/blkdev.h> |
23 | #include <linux/delay.h> |
24 | #include <scsi/scsi_host.h> |
25 | #include <linux/libata.h> |
26 | |
27 | #define DRV_NAME "pata_hpt3x2n" |
28 | #define DRV_VERSION "0.3.10" |
29 | |
30 | enum { |
31 | HPT_PCI_FAST = (1 << 31), |
32 | PCI66 = (1 << 1), |
33 | USE_DPLL = (1 << 0) |
34 | }; |
35 | |
36 | struct hpt_clock { |
37 | u8 xfer_speed; |
38 | u32 timing; |
39 | }; |
40 | |
41 | struct hpt_chip { |
42 | const char *name; |
43 | struct hpt_clock *clocks[3]; |
44 | }; |
45 | |
46 | /* key for bus clock timings |
47 | * bit |
48 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
49 | * cycles = value + 1 |
50 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. |
51 | * cycles = value + 1 |
52 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file |
53 | * register access. |
54 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
55 | * register access. |
56 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
57 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. |
58 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. |
59 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file |
60 | * register access. |
61 | * 28 UDMA enable. |
62 | * 29 DMA enable. |
63 | * 30 PIO_MST enable. If set, the chip is in bus master mode during |
64 | * PIO xfer. |
65 | * 31 FIFO enable. Only for PIO. |
66 | */ |
67 | |
68 | /* 66MHz DPLL clocks */ |
69 | |
70 | static struct hpt_clock hpt3x2n_clocks[] = { |
71 | { XFER_UDMA_7, 0x1c869c62 }, |
72 | { XFER_UDMA_6, 0x1c869c62 }, |
73 | { XFER_UDMA_5, 0x1c8a9c62 }, |
74 | { XFER_UDMA_4, 0x1c8a9c62 }, |
75 | { XFER_UDMA_3, 0x1c8e9c62 }, |
76 | { XFER_UDMA_2, 0x1c929c62 }, |
77 | { XFER_UDMA_1, 0x1c9a9c62 }, |
78 | { XFER_UDMA_0, 0x1c829c62 }, |
79 | |
80 | { XFER_MW_DMA_2, 0x2c829c62 }, |
81 | { XFER_MW_DMA_1, 0x2c829c66 }, |
82 | { XFER_MW_DMA_0, 0x2c829d2e }, |
83 | |
84 | { XFER_PIO_4, 0x0c829c62 }, |
85 | { XFER_PIO_3, 0x0c829c84 }, |
86 | { XFER_PIO_2, 0x0c829ca6 }, |
87 | { XFER_PIO_1, 0x0d029d26 }, |
88 | { XFER_PIO_0, 0x0d029d5e }, |
89 | }; |
90 | |
91 | /** |
92 | * hpt3x2n_find_mode - reset the hpt3x2n bus |
93 | * @ap: ATA port |
94 | * @speed: transfer mode |
95 | * |
96 | * Return the 32bit register programming information for this channel |
97 | * that matches the speed provided. For the moment the clocks table |
98 | * is hard coded but easy to change. This will be needed if we use |
99 | * different DPLLs |
100 | */ |
101 | |
102 | static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) |
103 | { |
104 | struct hpt_clock *clocks = hpt3x2n_clocks; |
105 | |
106 | while(clocks->xfer_speed) { |
107 | if (clocks->xfer_speed == speed) |
108 | return clocks->timing; |
109 | clocks++; |
110 | } |
111 | BUG(); |
112 | return 0xffffffffU; /* silence compiler warning */ |
113 | } |
114 | |
115 | /** |
116 | * hpt3x2n_cable_detect - Detect the cable type |
117 | * @ap: ATA port to detect on |
118 | * |
119 | * Return the cable type attached to this port |
120 | */ |
121 | |
122 | static int hpt3x2n_cable_detect(struct ata_port *ap) |
123 | { |
124 | u8 scr2, ata66; |
125 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
126 | |
127 | pci_read_config_byte(pdev, 0x5B, &scr2); |
128 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); |
129 | |
130 | udelay(10); /* debounce */ |
131 | |
132 | /* Cable register now active */ |
133 | pci_read_config_byte(pdev, 0x5A, &ata66); |
134 | /* Restore state */ |
135 | pci_write_config_byte(pdev, 0x5B, scr2); |
136 | |
137 | if (ata66 & (2 >> ap->port_no)) |
138 | return ATA_CBL_PATA40; |
139 | else |
140 | return ATA_CBL_PATA80; |
141 | } |
142 | |
143 | /** |
144 | * hpt3x2n_pre_reset - reset the hpt3x2n bus |
145 | * @link: ATA link to reset |
146 | * @deadline: deadline jiffies for the operation |
147 | * |
148 | * Perform the initial reset handling for the 3x2n series controllers. |
149 | * Reset the hardware and state machine, |
150 | */ |
151 | |
152 | static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) |
153 | { |
154 | struct ata_port *ap = link->ap; |
155 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
156 | /* Reset the state machine */ |
157 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
158 | udelay(100); |
159 | |
160 | return ata_sff_prereset(link, deadline); |
161 | } |
162 | |
163 | static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, |
164 | u8 mode) |
165 | { |
166 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
167 | u32 addr1, addr2; |
168 | u32 reg, timing, mask; |
169 | u8 fast; |
170 | |
171 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); |
172 | addr2 = 0x51 + 4 * ap->port_no; |
173 | |
174 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
175 | pci_read_config_byte(pdev, addr2, &fast); |
176 | fast &= ~0x07; |
177 | pci_write_config_byte(pdev, addr2, fast); |
178 | |
179 | /* Determine timing mask and find matching mode entry */ |
180 | if (mode < XFER_MW_DMA_0) |
181 | mask = 0xcfc3ffff; |
182 | else if (mode < XFER_UDMA_0) |
183 | mask = 0x31c001ff; |
184 | else |
185 | mask = 0x303c0000; |
186 | |
187 | timing = hpt3x2n_find_mode(ap, mode); |
188 | |
189 | pci_read_config_dword(pdev, addr1, ®); |
190 | reg = (reg & ~mask) | (timing & mask); |
191 | pci_write_config_dword(pdev, addr1, reg); |
192 | } |
193 | |
194 | /** |
195 | * hpt3x2n_set_piomode - PIO setup |
196 | * @ap: ATA interface |
197 | * @adev: device on the interface |
198 | * |
199 | * Perform PIO mode setup. |
200 | */ |
201 | |
202 | static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) |
203 | { |
204 | hpt3x2n_set_mode(ap, adev, adev->pio_mode); |
205 | } |
206 | |
207 | /** |
208 | * hpt3x2n_set_dmamode - DMA timing setup |
209 | * @ap: ATA interface |
210 | * @adev: Device being configured |
211 | * |
212 | * Set up the channel for MWDMA or UDMA modes. |
213 | */ |
214 | |
215 | static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
216 | { |
217 | hpt3x2n_set_mode(ap, adev, adev->dma_mode); |
218 | } |
219 | |
220 | /** |
221 | * hpt3x2n_bmdma_end - DMA engine stop |
222 | * @qc: ATA command |
223 | * |
224 | * Clean up after the HPT3x2n and later DMA engine |
225 | */ |
226 | |
227 | static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) |
228 | { |
229 | struct ata_port *ap = qc->ap; |
230 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
231 | int mscreg = 0x50 + 2 * ap->port_no; |
232 | u8 bwsr_stat, msc_stat; |
233 | |
234 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
235 | pci_read_config_byte(pdev, mscreg, &msc_stat); |
236 | if (bwsr_stat & (1 << ap->port_no)) |
237 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); |
238 | ata_bmdma_stop(qc); |
239 | } |
240 | |
241 | /** |
242 | * hpt3x2n_set_clock - clock control |
243 | * @ap: ATA port |
244 | * @source: 0x21 or 0x23 for PLL or PCI sourced clock |
245 | * |
246 | * Switch the ATA bus clock between the PLL and PCI clock sources |
247 | * while correctly isolating the bus and resetting internal logic |
248 | * |
249 | * We must use the DPLL for |
250 | * - writing |
251 | * - second channel UDMA7 (SATA ports) or higher |
252 | * - 66MHz PCI |
253 | * |
254 | * or we will underclock the device and get reduced performance. |
255 | */ |
256 | |
257 | static void hpt3x2n_set_clock(struct ata_port *ap, int source) |
258 | { |
259 | void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; |
260 | |
261 | /* Tristate the bus */ |
262 | iowrite8(0x80, bmdma+0x73); |
263 | iowrite8(0x80, bmdma+0x77); |
264 | |
265 | /* Switch clock and reset channels */ |
266 | iowrite8(source, bmdma+0x7B); |
267 | iowrite8(0xC0, bmdma+0x79); |
268 | |
269 | /* Reset state machines, avoid enabling the disabled channels */ |
270 | iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); |
271 | iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); |
272 | |
273 | /* Complete reset */ |
274 | iowrite8(0x00, bmdma+0x79); |
275 | |
276 | /* Reconnect channels to bus */ |
277 | iowrite8(0x00, bmdma+0x73); |
278 | iowrite8(0x00, bmdma+0x77); |
279 | } |
280 | |
281 | static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) |
282 | { |
283 | long flags = (long)ap->host->private_data; |
284 | |
285 | /* See if we should use the DPLL */ |
286 | if (writing) |
287 | return USE_DPLL; /* Needed for write */ |
288 | if (flags & PCI66) |
289 | return USE_DPLL; /* Needed at 66Mhz */ |
290 | return 0; |
291 | } |
292 | |
293 | static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) |
294 | { |
295 | struct ata_port *ap = qc->ap; |
296 | struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; |
297 | int rc, flags = (long)ap->host->private_data; |
298 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); |
299 | |
300 | /* First apply the usual rules */ |
301 | rc = ata_std_qc_defer(qc); |
302 | if (rc != 0) |
303 | return rc; |
304 | |
305 | if ((flags & USE_DPLL) != dpll && alt->qc_active) |
306 | return ATA_DEFER_PORT; |
307 | return 0; |
308 | } |
309 | |
310 | static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) |
311 | { |
312 | struct ata_port *ap = qc->ap; |
313 | int flags = (long)ap->host->private_data; |
314 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); |
315 | |
316 | if ((flags & USE_DPLL) != dpll) { |
317 | flags &= ~USE_DPLL; |
318 | flags |= dpll; |
319 | ap->host->private_data = (void *)(long)flags; |
320 | |
321 | hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); |
322 | } |
323 | return ata_sff_qc_issue(qc); |
324 | } |
325 | |
326 | static struct scsi_host_template hpt3x2n_sht = { |
327 | ATA_BMDMA_SHT(DRV_NAME), |
328 | }; |
329 | |
330 | /* |
331 | * Configuration for HPT3x2n. |
332 | */ |
333 | |
334 | static struct ata_port_operations hpt3x2n_port_ops = { |
335 | .inherits = &ata_bmdma_port_ops, |
336 | |
337 | .bmdma_stop = hpt3x2n_bmdma_stop, |
338 | |
339 | .qc_defer = hpt3x2n_qc_defer, |
340 | .qc_issue = hpt3x2n_qc_issue, |
341 | |
342 | .cable_detect = hpt3x2n_cable_detect, |
343 | .set_piomode = hpt3x2n_set_piomode, |
344 | .set_dmamode = hpt3x2n_set_dmamode, |
345 | .prereset = hpt3x2n_pre_reset, |
346 | }; |
347 | |
348 | /** |
349 | * hpt3xn_calibrate_dpll - Calibrate the DPLL loop |
350 | * @dev: PCI device |
351 | * |
352 | * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this |
353 | * succeeds |
354 | */ |
355 | |
356 | static int hpt3xn_calibrate_dpll(struct pci_dev *dev) |
357 | { |
358 | u8 reg5b; |
359 | u32 reg5c; |
360 | int tries; |
361 | |
362 | for(tries = 0; tries < 0x5000; tries++) { |
363 | udelay(50); |
364 | pci_read_config_byte(dev, 0x5b, ®5b); |
365 | if (reg5b & 0x80) { |
366 | /* See if it stays set */ |
367 | for(tries = 0; tries < 0x1000; tries ++) { |
368 | pci_read_config_byte(dev, 0x5b, ®5b); |
369 | /* Failed ? */ |
370 | if ((reg5b & 0x80) == 0) |
371 | return 0; |
372 | } |
373 | /* Turn off tuning, we have the DPLL set */ |
374 | pci_read_config_dword(dev, 0x5c, ®5c); |
375 | pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); |
376 | return 1; |
377 | } |
378 | } |
379 | /* Never went stable */ |
380 | return 0; |
381 | } |
382 | |
383 | static int hpt3x2n_pci_clock(struct pci_dev *pdev) |
384 | { |
385 | unsigned long freq; |
386 | u32 fcnt; |
387 | unsigned long iobase = pci_resource_start(pdev, 4); |
388 | |
389 | fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ |
390 | if ((fcnt >> 12) != 0xABCDE) { |
391 | printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n"); |
392 | return 33; /* Not BIOS set */ |
393 | } |
394 | fcnt &= 0x1FF; |
395 | |
396 | freq = (fcnt * 77) / 192; |
397 | |
398 | /* Clamp to bands */ |
399 | if (freq < 40) |
400 | return 33; |
401 | if (freq < 45) |
402 | return 40; |
403 | if (freq < 55) |
404 | return 50; |
405 | return 66; |
406 | } |
407 | |
408 | /** |
409 | * hpt3x2n_init_one - Initialise an HPT37X/302 |
410 | * @dev: PCI device |
411 | * @id: Entry in match table |
412 | * |
413 | * Initialise an HPT3x2n device. There are some interesting complications |
414 | * here. Firstly the chip may report 366 and be one of several variants. |
415 | * Secondly all the timings depend on the clock for the chip which we must |
416 | * detect and look up |
417 | * |
418 | * This is the known chip mappings. It may be missing a couple of later |
419 | * releases. |
420 | * |
421 | * Chip version PCI Rev Notes |
422 | * HPT372 4 (HPT366) 5 Other driver |
423 | * HPT372N 4 (HPT366) 6 UDMA133 |
424 | * HPT372 5 (HPT372) 1 Other driver |
425 | * HPT372N 5 (HPT372) 2 UDMA133 |
426 | * HPT302 6 (HPT302) * Other driver |
427 | * HPT302N 6 (HPT302) > 1 UDMA133 |
428 | * HPT371 7 (HPT371) * Other driver |
429 | * HPT371N 7 (HPT371) > 1 UDMA133 |
430 | * HPT374 8 (HPT374) * Other driver |
431 | * HPT372N 9 (HPT372N) * UDMA133 |
432 | * |
433 | * (1) UDMA133 support depends on the bus clock |
434 | * |
435 | * To pin down HPT371N |
436 | */ |
437 | |
438 | static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
439 | { |
440 | /* HPT372N and friends - UDMA133 */ |
441 | static const struct ata_port_info info = { |
442 | .flags = ATA_FLAG_SLAVE_POSS, |
443 | .pio_mask = ATA_PIO4, |
444 | .mwdma_mask = ATA_MWDMA2, |
445 | .udma_mask = ATA_UDMA6, |
446 | .port_ops = &hpt3x2n_port_ops |
447 | }; |
448 | const struct ata_port_info *ppi[] = { &info, NULL }; |
449 | u8 rev = dev->revision; |
450 | u8 irqmask; |
451 | unsigned int pci_mhz; |
452 | unsigned int f_low, f_high; |
453 | int adjust; |
454 | unsigned long iobase = pci_resource_start(dev, 4); |
455 | void *hpriv = (void *)USE_DPLL; |
456 | int rc; |
457 | |
458 | rc = pcim_enable_device(dev); |
459 | if (rc) |
460 | return rc; |
461 | |
462 | switch(dev->device) { |
463 | case PCI_DEVICE_ID_TTI_HPT366: |
464 | if (rev < 6) |
465 | return -ENODEV; |
466 | break; |
467 | case PCI_DEVICE_ID_TTI_HPT371: |
468 | if (rev < 2) |
469 | return -ENODEV; |
470 | /* 371N if rev > 1 */ |
471 | break; |
472 | case PCI_DEVICE_ID_TTI_HPT372: |
473 | /* 372N if rev >= 2*/ |
474 | if (rev < 2) |
475 | return -ENODEV; |
476 | break; |
477 | case PCI_DEVICE_ID_TTI_HPT302: |
478 | if (rev < 2) |
479 | return -ENODEV; |
480 | break; |
481 | case PCI_DEVICE_ID_TTI_HPT372N: |
482 | break; |
483 | default: |
484 | printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device); |
485 | return -ENODEV; |
486 | } |
487 | |
488 | /* Ok so this is a chip we support */ |
489 | |
490 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); |
491 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); |
492 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); |
493 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); |
494 | |
495 | pci_read_config_byte(dev, 0x5A, &irqmask); |
496 | irqmask &= ~0x10; |
497 | pci_write_config_byte(dev, 0x5a, irqmask); |
498 | |
499 | /* |
500 | * HPT371 chips physically have only one channel, the secondary one, |
501 | * but the primary channel registers do exist! Go figure... |
502 | * So, we manually disable the non-existing channel here |
503 | * (if the BIOS hasn't done this already). |
504 | */ |
505 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { |
506 | u8 mcr1; |
507 | pci_read_config_byte(dev, 0x50, &mcr1); |
508 | mcr1 &= ~0x04; |
509 | pci_write_config_byte(dev, 0x50, mcr1); |
510 | } |
511 | |
512 | /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or |
513 | 50 for UDMA100. Right now we always use 66 */ |
514 | |
515 | pci_mhz = hpt3x2n_pci_clock(dev); |
516 | |
517 | f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ |
518 | f_high = f_low + 2; /* Tolerance */ |
519 | |
520 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
521 | /* PLL clock */ |
522 | pci_write_config_byte(dev, 0x5B, 0x21); |
523 | |
524 | /* Unlike the 37x we don't try jiggling the frequency */ |
525 | for(adjust = 0; adjust < 8; adjust++) { |
526 | if (hpt3xn_calibrate_dpll(dev)) |
527 | break; |
528 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); |
529 | } |
530 | if (adjust == 8) { |
531 | printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n"); |
532 | return -ENODEV; |
533 | } |
534 | |
535 | printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n", |
536 | pci_mhz); |
537 | /* Set our private data up. We only need a few flags so we use |
538 | it directly */ |
539 | if (pci_mhz > 60) |
540 | hpriv = (void *)(PCI66 | USE_DPLL); |
541 | |
542 | /* |
543 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in |
544 | * the MISC. register to stretch the UltraDMA Tss timing. |
545 | * NOTE: This register is only writeable via I/O space. |
546 | */ |
547 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) |
548 | outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); |
549 | |
550 | /* Now kick off ATA set up */ |
551 | return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0); |
552 | } |
553 | |
554 | static const struct pci_device_id hpt3x2n[] = { |
555 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, |
556 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, |
557 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, |
558 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, |
559 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, |
560 | |
561 | { }, |
562 | }; |
563 | |
564 | static struct pci_driver hpt3x2n_pci_driver = { |
565 | .name = DRV_NAME, |
566 | .id_table = hpt3x2n, |
567 | .probe = hpt3x2n_init_one, |
568 | .remove = ata_pci_remove_one |
569 | }; |
570 | |
571 | static int __init hpt3x2n_init(void) |
572 | { |
573 | return pci_register_driver(&hpt3x2n_pci_driver); |
574 | } |
575 | |
576 | static void __exit hpt3x2n_exit(void) |
577 | { |
578 | pci_unregister_driver(&hpt3x2n_pci_driver); |
579 | } |
580 | |
581 | MODULE_AUTHOR("Alan Cox"); |
582 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x"); |
583 | MODULE_LICENSE("GPL"); |
584 | MODULE_DEVICE_TABLE(pci, hpt3x2n); |
585 | MODULE_VERSION(DRV_VERSION); |
586 | |
587 | module_init(hpt3x2n_init); |
588 | module_exit(hpt3x2n_exit); |
589 |
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
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v3.9