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1 | /* |
2 | * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer |
3 | * (C) 2005 Red Hat Inc |
4 | * Alan Cox <alan@lxorguk.ukuu.org.uk> |
5 | * (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz |
6 | * |
7 | * Based in part on linux/drivers/ide/pci/pdc202xx_old.c |
8 | * |
9 | * First cut with LBA48/ATAPI |
10 | * |
11 | * TODO: |
12 | * Channel interlock/reset on both required ? |
13 | */ |
14 | |
15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> |
17 | #include <linux/pci.h> |
18 | #include <linux/init.h> |
19 | #include <linux/blkdev.h> |
20 | #include <linux/delay.h> |
21 | #include <scsi/scsi_host.h> |
22 | #include <linux/libata.h> |
23 | |
24 | #define DRV_NAME "pata_pdc202xx_old" |
25 | #define DRV_VERSION "0.4.3" |
26 | |
27 | static int pdc2026x_cable_detect(struct ata_port *ap) |
28 | { |
29 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
30 | u16 cis; |
31 | |
32 | pci_read_config_word(pdev, 0x50, &cis); |
33 | if (cis & (1 << (10 + ap->port_no))) |
34 | return ATA_CBL_PATA40; |
35 | return ATA_CBL_PATA80; |
36 | } |
37 | |
38 | static void pdc202xx_exec_command(struct ata_port *ap, |
39 | const struct ata_taskfile *tf) |
40 | { |
41 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); |
42 | |
43 | iowrite8(tf->command, ap->ioaddr.command_addr); |
44 | ndelay(400); |
45 | } |
46 | |
47 | /** |
48 | * pdc202xx_configure_piomode - set chip PIO timing |
49 | * @ap: ATA interface |
50 | * @adev: ATA device |
51 | * @pio: PIO mode |
52 | * |
53 | * Called to do the PIO mode setup. Our timing registers are shared |
54 | * so a configure_dmamode call will undo any work we do here and vice |
55 | * versa |
56 | */ |
57 | |
58 | static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) |
59 | { |
60 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
61 | int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; |
62 | static u16 pio_timing[5] = { |
63 | 0x0913, 0x050C , 0x0308, 0x0206, 0x0104 |
64 | }; |
65 | u8 r_ap, r_bp; |
66 | |
67 | pci_read_config_byte(pdev, port, &r_ap); |
68 | pci_read_config_byte(pdev, port + 1, &r_bp); |
69 | r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */ |
70 | r_bp &= ~0x1F; |
71 | r_ap |= (pio_timing[pio] >> 8); |
72 | r_bp |= (pio_timing[pio] & 0xFF); |
73 | |
74 | if (ata_pio_need_iordy(adev)) |
75 | r_ap |= 0x20; /* IORDY enable */ |
76 | if (adev->class == ATA_DEV_ATA) |
77 | r_ap |= 0x10; /* FIFO enable */ |
78 | pci_write_config_byte(pdev, port, r_ap); |
79 | pci_write_config_byte(pdev, port + 1, r_bp); |
80 | } |
81 | |
82 | /** |
83 | * pdc202xx_set_piomode - set initial PIO mode data |
84 | * @ap: ATA interface |
85 | * @adev: ATA device |
86 | * |
87 | * Called to do the PIO mode setup. Our timing registers are shared |
88 | * but we want to set the PIO timing by default. |
89 | */ |
90 | |
91 | static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev) |
92 | { |
93 | pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); |
94 | } |
95 | |
96 | /** |
97 | * pdc202xx_configure_dmamode - set DMA mode in chip |
98 | * @ap: ATA interface |
99 | * @adev: ATA device |
100 | * |
101 | * Load DMA cycle times into the chip ready for a DMA transfer |
102 | * to occur. |
103 | */ |
104 | |
105 | static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
106 | { |
107 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
108 | int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; |
109 | static u8 udma_timing[6][2] = { |
110 | { 0x60, 0x03 }, /* 33 Mhz Clock */ |
111 | { 0x40, 0x02 }, |
112 | { 0x20, 0x01 }, |
113 | { 0x40, 0x02 }, /* 66 Mhz Clock */ |
114 | { 0x20, 0x01 }, |
115 | { 0x20, 0x01 } |
116 | }; |
117 | static u8 mdma_timing[3][2] = { |
118 | { 0xe0, 0x0f }, |
119 | { 0x60, 0x04 }, |
120 | { 0x60, 0x03 }, |
121 | }; |
122 | u8 r_bp, r_cp; |
123 | |
124 | pci_read_config_byte(pdev, port + 1, &r_bp); |
125 | pci_read_config_byte(pdev, port + 2, &r_cp); |
126 | |
127 | r_bp &= ~0xE0; |
128 | r_cp &= ~0x0F; |
129 | |
130 | if (adev->dma_mode >= XFER_UDMA_0) { |
131 | int speed = adev->dma_mode - XFER_UDMA_0; |
132 | r_bp |= udma_timing[speed][0]; |
133 | r_cp |= udma_timing[speed][1]; |
134 | |
135 | } else { |
136 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
137 | r_bp |= mdma_timing[speed][0]; |
138 | r_cp |= mdma_timing[speed][1]; |
139 | } |
140 | pci_write_config_byte(pdev, port + 1, r_bp); |
141 | pci_write_config_byte(pdev, port + 2, r_cp); |
142 | |
143 | } |
144 | |
145 | /** |
146 | * pdc2026x_bmdma_start - DMA engine begin |
147 | * @qc: ATA command |
148 | * |
149 | * In UDMA3 or higher we have to clock switch for the duration of the |
150 | * DMA transfer sequence. |
151 | * |
152 | * Note: The host lock held by the libata layer protects |
153 | * us from two channels both trying to set DMA bits at once |
154 | */ |
155 | |
156 | static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc) |
157 | { |
158 | struct ata_port *ap = qc->ap; |
159 | struct ata_device *adev = qc->dev; |
160 | struct ata_taskfile *tf = &qc->tf; |
161 | int sel66 = ap->port_no ? 0x08: 0x02; |
162 | |
163 | void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; |
164 | void __iomem *clock = master + 0x11; |
165 | void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); |
166 | |
167 | u32 len; |
168 | |
169 | /* Check we keep host level locking here */ |
170 | if (adev->dma_mode > XFER_UDMA_2) |
171 | iowrite8(ioread8(clock) | sel66, clock); |
172 | else |
173 | iowrite8(ioread8(clock) & ~sel66, clock); |
174 | |
175 | /* The DMA clocks may have been trashed by a reset. FIXME: make conditional |
176 | and move to qc_issue ? */ |
177 | pdc202xx_set_dmamode(ap, qc->dev); |
178 | |
179 | /* Cases the state machine will not complete correctly without help */ |
180 | if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) { |
181 | len = qc->nbytes / 2; |
182 | |
183 | if (tf->flags & ATA_TFLAG_WRITE) |
184 | len |= 0x06000000; |
185 | else |
186 | len |= 0x05000000; |
187 | |
188 | iowrite32(len, atapi_reg); |
189 | } |
190 | |
191 | /* Activate DMA */ |
192 | ata_bmdma_start(qc); |
193 | } |
194 | |
195 | /** |
196 | * pdc2026x_bmdma_end - DMA engine stop |
197 | * @qc: ATA command |
198 | * |
199 | * After a DMA completes we need to put the clock back to 33MHz for |
200 | * PIO timings. |
201 | * |
202 | * Note: The host lock held by the libata layer protects |
203 | * us from two channels both trying to set DMA bits at once |
204 | */ |
205 | |
206 | static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc) |
207 | { |
208 | struct ata_port *ap = qc->ap; |
209 | struct ata_device *adev = qc->dev; |
210 | struct ata_taskfile *tf = &qc->tf; |
211 | |
212 | int sel66 = ap->port_no ? 0x08: 0x02; |
213 | /* The clock bits are in the same register for both channels */ |
214 | void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; |
215 | void __iomem *clock = master + 0x11; |
216 | void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); |
217 | |
218 | /* Cases the state machine will not complete correctly */ |
219 | if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) { |
220 | iowrite32(0, atapi_reg); |
221 | iowrite8(ioread8(clock) & ~sel66, clock); |
222 | } |
223 | /* Flip back to 33Mhz for PIO */ |
224 | if (adev->dma_mode > XFER_UDMA_2) |
225 | iowrite8(ioread8(clock) & ~sel66, clock); |
226 | ata_bmdma_stop(qc); |
227 | pdc202xx_set_piomode(ap, adev); |
228 | } |
229 | |
230 | /** |
231 | * pdc2026x_dev_config - device setup hook |
232 | * @adev: newly found device |
233 | * |
234 | * Perform chip specific early setup. We need to lock the transfer |
235 | * sizes to 8bit to avoid making the state engine on the 2026x cards |
236 | * barf. |
237 | */ |
238 | |
239 | static void pdc2026x_dev_config(struct ata_device *adev) |
240 | { |
241 | adev->max_sectors = 256; |
242 | } |
243 | |
244 | static int pdc2026x_port_start(struct ata_port *ap) |
245 | { |
246 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
247 | if (bmdma) { |
248 | /* Enable burst mode */ |
249 | u8 burst = ioread8(bmdma + 0x1f); |
250 | iowrite8(burst | 0x01, bmdma + 0x1f); |
251 | } |
252 | return ata_sff_port_start(ap); |
253 | } |
254 | |
255 | /** |
256 | * pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command |
257 | * @qc: Metadata associated with taskfile to check |
258 | * |
259 | * Just say no - not supported on older Promise. |
260 | * |
261 | * LOCKING: |
262 | * None (inherited from caller). |
263 | * |
264 | * RETURNS: 0 when ATAPI DMA can be used |
265 | * 1 otherwise |
266 | */ |
267 | |
268 | static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc) |
269 | { |
270 | return 1; |
271 | } |
272 | |
273 | static struct scsi_host_template pdc202xx_sht = { |
274 | ATA_BMDMA_SHT(DRV_NAME), |
275 | }; |
276 | |
277 | static struct ata_port_operations pdc2024x_port_ops = { |
278 | .inherits = &ata_bmdma_port_ops, |
279 | |
280 | .cable_detect = ata_cable_40wire, |
281 | .set_piomode = pdc202xx_set_piomode, |
282 | .set_dmamode = pdc202xx_set_dmamode, |
283 | |
284 | .sff_exec_command = pdc202xx_exec_command, |
285 | }; |
286 | |
287 | static struct ata_port_operations pdc2026x_port_ops = { |
288 | .inherits = &pdc2024x_port_ops, |
289 | |
290 | .check_atapi_dma = pdc2026x_check_atapi_dma, |
291 | .bmdma_start = pdc2026x_bmdma_start, |
292 | .bmdma_stop = pdc2026x_bmdma_stop, |
293 | |
294 | .cable_detect = pdc2026x_cable_detect, |
295 | .dev_config = pdc2026x_dev_config, |
296 | |
297 | .port_start = pdc2026x_port_start, |
298 | |
299 | .sff_exec_command = pdc202xx_exec_command, |
300 | }; |
301 | |
302 | static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
303 | { |
304 | static const struct ata_port_info info[3] = { |
305 | { |
306 | .flags = ATA_FLAG_SLAVE_POSS, |
307 | .pio_mask = ATA_PIO4, |
308 | .mwdma_mask = ATA_MWDMA2, |
309 | .udma_mask = ATA_UDMA2, |
310 | .port_ops = &pdc2024x_port_ops |
311 | }, |
312 | { |
313 | .flags = ATA_FLAG_SLAVE_POSS, |
314 | .pio_mask = ATA_PIO4, |
315 | .mwdma_mask = ATA_MWDMA2, |
316 | .udma_mask = ATA_UDMA4, |
317 | .port_ops = &pdc2026x_port_ops |
318 | }, |
319 | { |
320 | .flags = ATA_FLAG_SLAVE_POSS, |
321 | .pio_mask = ATA_PIO4, |
322 | .mwdma_mask = ATA_MWDMA2, |
323 | .udma_mask = ATA_UDMA5, |
324 | .port_ops = &pdc2026x_port_ops |
325 | } |
326 | |
327 | }; |
328 | const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; |
329 | |
330 | if (dev->device == PCI_DEVICE_ID_PROMISE_20265) { |
331 | struct pci_dev *bridge = dev->bus->self; |
332 | /* Don't grab anything behind a Promise I2O RAID */ |
333 | if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) { |
334 | if (bridge->device == PCI_DEVICE_ID_INTEL_I960) |
335 | return -ENODEV; |
336 | if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM) |
337 | return -ENODEV; |
338 | } |
339 | } |
340 | return ata_pci_sff_init_one(dev, ppi, &pdc202xx_sht, NULL, 0); |
341 | } |
342 | |
343 | static const struct pci_device_id pdc202xx[] = { |
344 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, |
345 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, |
346 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, |
347 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, |
348 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, |
349 | |
350 | { }, |
351 | }; |
352 | |
353 | static struct pci_driver pdc202xx_pci_driver = { |
354 | .name = DRV_NAME, |
355 | .id_table = pdc202xx, |
356 | .probe = pdc202xx_init_one, |
357 | .remove = ata_pci_remove_one, |
358 | #ifdef CONFIG_PM |
359 | .suspend = ata_pci_device_suspend, |
360 | .resume = ata_pci_device_resume, |
361 | #endif |
362 | }; |
363 | |
364 | static int __init pdc202xx_init(void) |
365 | { |
366 | return pci_register_driver(&pdc202xx_pci_driver); |
367 | } |
368 | |
369 | static void __exit pdc202xx_exit(void) |
370 | { |
371 | pci_unregister_driver(&pdc202xx_pci_driver); |
372 | } |
373 | |
374 | MODULE_AUTHOR("Alan Cox"); |
375 | MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267"); |
376 | MODULE_LICENSE("GPL"); |
377 | MODULE_DEVICE_TABLE(pci, pdc202xx); |
378 | MODULE_VERSION(DRV_VERSION); |
379 | |
380 | module_init(pdc202xx_init); |
381 | module_exit(pdc202xx_exit); |
382 |
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