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1 | /* |
2 | * Copyright (c) 2008 Nuovation System Designs, LLC |
3 | * Grant Erickson <gerickson@nuovations.com> |
4 | * |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License as |
7 | * published by the Free Software Foundation; version 2 of the |
8 | * License. |
9 | * |
10 | */ |
11 | |
12 | #include <linux/edac.h> |
13 | #include <linux/interrupt.h> |
14 | #include <linux/irq.h> |
15 | #include <linux/kernel.h> |
16 | #include <linux/mm.h> |
17 | #include <linux/module.h> |
18 | #include <linux/of_device.h> |
19 | #include <linux/of_platform.h> |
20 | #include <linux/types.h> |
21 | |
22 | #include <asm/dcr.h> |
23 | |
24 | #include "edac_core.h" |
25 | #include "ppc4xx_edac.h" |
26 | |
27 | /* |
28 | * This file implements a driver for monitoring and handling events |
29 | * associated with the IMB DDR2 ECC controller found in the AMCC/IBM |
30 | * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX. |
31 | * |
32 | * As realized in the 405EX[r], this controller features: |
33 | * |
34 | * - Support for registered- and non-registered DDR1 and DDR2 memory. |
35 | * - 32-bit or 16-bit memory interface with optional ECC. |
36 | * |
37 | * o ECC support includes: |
38 | * |
39 | * - 4-bit SEC/DED |
40 | * - Aligned-nibble error detect |
41 | * - Bypass mode |
42 | * |
43 | * - Two (2) memory banks/ranks. |
44 | * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per |
45 | * bank/rank in 16-bit mode. |
46 | * |
47 | * As realized in the 440SP and 440SPe, this controller changes/adds: |
48 | * |
49 | * - 64-bit or 32-bit memory interface with optional ECC. |
50 | * |
51 | * o ECC support includes: |
52 | * |
53 | * - 8-bit SEC/DED |
54 | * - Aligned-nibble error detect |
55 | * - Bypass mode |
56 | * |
57 | * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB |
58 | * per bank/rank in 32-bit mode. |
59 | * |
60 | * As realized in the 460EX and 460GT, this controller changes/adds: |
61 | * |
62 | * - 64-bit or 32-bit memory interface with optional ECC. |
63 | * |
64 | * o ECC support includes: |
65 | * |
66 | * - 8-bit SEC/DED |
67 | * - Aligned-nibble error detect |
68 | * - Bypass mode |
69 | * |
70 | * - Four (4) memory banks/ranks. |
71 | * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB |
72 | * per bank/rank in 32-bit mode. |
73 | * |
74 | * At present, this driver has ONLY been tested against the controller |
75 | * realization in the 405EX[r] on the AMCC Kilauea and Haleakala |
76 | * boards (256 MiB w/o ECC memory soldered onto the board) and a |
77 | * proprietary board based on those designs (128 MiB ECC memory, also |
78 | * soldered onto the board). |
79 | * |
80 | * Dynamic feature detection and handling needs to be added for the |
81 | * other realizations of this controller listed above. |
82 | * |
83 | * Eventually, this driver will likely be adapted to the above variant |
84 | * realizations of this controller as well as broken apart to handle |
85 | * the other known ECC-capable controllers prevalent in other 4xx |
86 | * processors: |
87 | * |
88 | * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx" |
89 | * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr" |
90 | * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2" |
91 | * |
92 | * For this controller, unfortunately, correctable errors report |
93 | * nothing more than the beat/cycle and byte/lane the correction |
94 | * occurred on and the check bit group that covered the error. |
95 | * |
96 | * In contrast, uncorrectable errors also report the failing address, |
97 | * the bus master and the transaction direction (i.e. read or write) |
98 | * |
99 | * Regardless of whether the error is a CE or a UE, we report the |
100 | * following pieces of information in the driver-unique message to the |
101 | * EDAC subsystem: |
102 | * |
103 | * - Device tree path |
104 | * - Bank(s) |
105 | * - Check bit error group |
106 | * - Beat(s)/lane(s) |
107 | */ |
108 | |
109 | /* Preprocessor Definitions */ |
110 | |
111 | #define EDAC_OPSTATE_INT_STR "interrupt" |
112 | #define EDAC_OPSTATE_POLL_STR "polled" |
113 | #define EDAC_OPSTATE_UNKNOWN_STR "unknown" |
114 | |
115 | #define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac" |
116 | #define PPC4XX_EDAC_MODULE_REVISION "v1.0.0 " __DATE__ |
117 | |
118 | #define PPC4XX_EDAC_MESSAGE_SIZE 256 |
119 | |
120 | /* |
121 | * Kernel logging without an EDAC instance |
122 | */ |
123 | #define ppc4xx_edac_printk(level, fmt, arg...) \ |
124 | edac_printk(level, "PPC4xx MC", fmt, ##arg) |
125 | |
126 | /* |
127 | * Kernel logging with an EDAC instance |
128 | */ |
129 | #define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \ |
130 | edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg) |
131 | |
132 | /* |
133 | * Macros to convert bank configuration size enumerations into MiB and |
134 | * page values. |
135 | */ |
136 | #define SDRAM_MBCF_SZ_MiB_MIN 4 |
137 | #define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \ |
138 | << (SDRAM_MBCF_SZ_DECODE(n))) |
139 | #define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \ |
140 | << (20 - PAGE_SHIFT + \ |
141 | SDRAM_MBCF_SZ_DECODE(n))) |
142 | |
143 | /* |
144 | * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are |
145 | * indirectly acccessed and have a base and length defined by the |
146 | * device tree. The base can be anything; however, we expect the |
147 | * length to be precisely two registers, the first for the address |
148 | * window and the second for the data window. |
149 | */ |
150 | #define SDRAM_DCR_RESOURCE_LEN 2 |
151 | #define SDRAM_DCR_ADDR_OFFSET 0 |
152 | #define SDRAM_DCR_DATA_OFFSET 1 |
153 | |
154 | /* |
155 | * Device tree interrupt indices |
156 | */ |
157 | #define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */ |
158 | #define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */ |
159 | |
160 | /* Type Definitions */ |
161 | |
162 | /* |
163 | * PPC4xx SDRAM memory controller private instance data |
164 | */ |
165 | struct ppc4xx_edac_pdata { |
166 | dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */ |
167 | struct { |
168 | int sec; /* Single-bit correctable error IRQ assigned */ |
169 | int ded; /* Double-bit detectable error IRQ assigned */ |
170 | } irqs; |
171 | }; |
172 | |
173 | /* |
174 | * Various status data gathered and manipulated when checking and |
175 | * reporting ECC status. |
176 | */ |
177 | struct ppc4xx_ecc_status { |
178 | u32 ecces; |
179 | u32 besr; |
180 | u32 bearh; |
181 | u32 bearl; |
182 | u32 wmirq; |
183 | }; |
184 | |
185 | /* Function Prototypes */ |
186 | |
187 | static int ppc4xx_edac_probe(struct of_device *device, |
188 | const struct of_device_id *device_id); |
189 | static int ppc4xx_edac_remove(struct of_device *device); |
190 | |
191 | /* Global Variables */ |
192 | |
193 | /* |
194 | * Device tree node type and compatible tuples this driver can match |
195 | * on. |
196 | */ |
197 | static struct of_device_id ppc4xx_edac_match[] = { |
198 | { |
199 | .compatible = "ibm,sdram-4xx-ddr2" |
200 | }, |
201 | { } |
202 | }; |
203 | |
204 | static struct of_platform_driver ppc4xx_edac_driver = { |
205 | .match_table = ppc4xx_edac_match, |
206 | .probe = ppc4xx_edac_probe, |
207 | .remove = ppc4xx_edac_remove, |
208 | .driver = { |
209 | .owner = THIS_MODULE, |
210 | .name = PPC4XX_EDAC_MODULE_NAME |
211 | } |
212 | }; |
213 | |
214 | /* |
215 | * TODO: The row and channel parameters likely need to be dynamically |
216 | * set based on the aforementioned variant controller realizations. |
217 | */ |
218 | static const unsigned ppc4xx_edac_nr_csrows = 2; |
219 | static const unsigned ppc4xx_edac_nr_chans = 1; |
220 | |
221 | /* |
222 | * Strings associated with PLB master IDs capable of being posted in |
223 | * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors. |
224 | */ |
225 | static const char * const ppc4xx_plb_masters[9] = { |
226 | [SDRAM_PLB_M0ID_ICU] = "ICU", |
227 | [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0", |
228 | [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1", |
229 | [SDRAM_PLB_M0ID_DMA] = "DMA", |
230 | [SDRAM_PLB_M0ID_DCU] = "DCU", |
231 | [SDRAM_PLB_M0ID_OPB] = "OPB", |
232 | [SDRAM_PLB_M0ID_MAL] = "MAL", |
233 | [SDRAM_PLB_M0ID_SEC] = "SEC", |
234 | [SDRAM_PLB_M0ID_AHB] = "AHB" |
235 | }; |
236 | |
237 | /** |
238 | * mfsdram - read and return controller register data |
239 | * @dcr_host: A pointer to the DCR mapping. |
240 | * @idcr_n: The indirect DCR register to read. |
241 | * |
242 | * This routine reads and returns the data associated with the |
243 | * controller's specified indirect DCR register. |
244 | * |
245 | * Returns the read data. |
246 | */ |
247 | static inline u32 |
248 | mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n) |
249 | { |
250 | return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, |
251 | dcr_host->base + SDRAM_DCR_DATA_OFFSET, |
252 | idcr_n); |
253 | } |
254 | |
255 | /** |
256 | * mtsdram - write controller register data |
257 | * @dcr_host: A pointer to the DCR mapping. |
258 | * @idcr_n: The indirect DCR register to write. |
259 | * @value: The data to write. |
260 | * |
261 | * This routine writes the provided data to the controller's specified |
262 | * indirect DCR register. |
263 | */ |
264 | static inline void |
265 | mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value) |
266 | { |
267 | return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, |
268 | dcr_host->base + SDRAM_DCR_DATA_OFFSET, |
269 | idcr_n, |
270 | value); |
271 | } |
272 | |
273 | /** |
274 | * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error |
275 | * @status: A pointer to the ECC status structure to check for an |
276 | * ECC bank error. |
277 | * @bank: The bank to check for an ECC error. |
278 | * |
279 | * This routine determines whether the specified bank has an ECC |
280 | * error. |
281 | * |
282 | * Returns true if the specified bank has an ECC error; otherwise, |
283 | * false. |
284 | */ |
285 | static bool |
286 | ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status, |
287 | unsigned int bank) |
288 | { |
289 | switch (bank) { |
290 | case 0: |
291 | return status->ecces & SDRAM_ECCES_BK0ER; |
292 | case 1: |
293 | return status->ecces & SDRAM_ECCES_BK1ER; |
294 | default: |
295 | return false; |
296 | } |
297 | } |
298 | |
299 | /** |
300 | * ppc4xx_edac_generate_bank_message - generate interpretted bank status message |
301 | * @mci: A pointer to the EDAC memory controller instance associated |
302 | * with the bank message being generated. |
303 | * @status: A pointer to the ECC status structure to generate the |
304 | * message from. |
305 | * @buffer: A pointer to the buffer in which to generate the |
306 | * message. |
307 | * @size: The size, in bytes, of space available in buffer. |
308 | * |
309 | * This routine generates to the provided buffer the portion of the |
310 | * driver-unique report message associated with the ECCESS[BKNER] |
311 | * field of the specified ECC status. |
312 | * |
313 | * Returns the number of characters generated on success; otherwise, < |
314 | * 0 on error. |
315 | */ |
316 | static int |
317 | ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci, |
318 | const struct ppc4xx_ecc_status *status, |
319 | char *buffer, |
320 | size_t size) |
321 | { |
322 | int n, total = 0; |
323 | unsigned int row, rows; |
324 | |
325 | n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name); |
326 | |
327 | if (n < 0 || n >= size) |
328 | goto fail; |
329 | |
330 | buffer += n; |
331 | size -= n; |
332 | total += n; |
333 | |
334 | for (rows = 0, row = 0; row < mci->nr_csrows; row++) { |
335 | if (ppc4xx_edac_check_bank_error(status, row)) { |
336 | n = snprintf(buffer, size, "%s%u", |
337 | (rows++ ? ", " : ""), row); |
338 | |
339 | if (n < 0 || n >= size) |
340 | goto fail; |
341 | |
342 | buffer += n; |
343 | size -= n; |
344 | total += n; |
345 | } |
346 | } |
347 | |
348 | n = snprintf(buffer, size, "%s; ", rows ? "" : "None"); |
349 | |
350 | if (n < 0 || n >= size) |
351 | goto fail; |
352 | |
353 | buffer += n; |
354 | size -= n; |
355 | total += n; |
356 | |
357 | fail: |
358 | return total; |
359 | } |
360 | |
361 | /** |
362 | * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message |
363 | * @mci: A pointer to the EDAC memory controller instance associated |
364 | * with the checkbit message being generated. |
365 | * @status: A pointer to the ECC status structure to generate the |
366 | * message from. |
367 | * @buffer: A pointer to the buffer in which to generate the |
368 | * message. |
369 | * @size: The size, in bytes, of space available in buffer. |
370 | * |
371 | * This routine generates to the provided buffer the portion of the |
372 | * driver-unique report message associated with the ECCESS[CKBER] |
373 | * field of the specified ECC status. |
374 | * |
375 | * Returns the number of characters generated on success; otherwise, < |
376 | * 0 on error. |
377 | */ |
378 | static int |
379 | ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci, |
380 | const struct ppc4xx_ecc_status *status, |
381 | char *buffer, |
382 | size_t size) |
383 | { |
384 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; |
385 | const char *ckber = NULL; |
386 | |
387 | switch (status->ecces & SDRAM_ECCES_CKBER_MASK) { |
388 | case SDRAM_ECCES_CKBER_NONE: |
389 | ckber = "None"; |
390 | break; |
391 | case SDRAM_ECCES_CKBER_32_ECC_0_3: |
392 | ckber = "ECC0:3"; |
393 | break; |
394 | case SDRAM_ECCES_CKBER_32_ECC_4_8: |
395 | switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) & |
396 | SDRAM_MCOPT1_WDTH_MASK) { |
397 | case SDRAM_MCOPT1_WDTH_16: |
398 | ckber = "ECC0:3"; |
399 | break; |
400 | case SDRAM_MCOPT1_WDTH_32: |
401 | ckber = "ECC4:8"; |
402 | break; |
403 | default: |
404 | ckber = "Unknown"; |
405 | break; |
406 | } |
407 | break; |
408 | case SDRAM_ECCES_CKBER_32_ECC_0_8: |
409 | ckber = "ECC0:8"; |
410 | break; |
411 | default: |
412 | ckber = "Unknown"; |
413 | break; |
414 | } |
415 | |
416 | return snprintf(buffer, size, "Checkbit Error: %s", ckber); |
417 | } |
418 | |
419 | /** |
420 | * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message |
421 | * @mci: A pointer to the EDAC memory controller instance associated |
422 | * with the byte lane message being generated. |
423 | * @status: A pointer to the ECC status structure to generate the |
424 | * message from. |
425 | * @buffer: A pointer to the buffer in which to generate the |
426 | * message. |
427 | * @size: The size, in bytes, of space available in buffer. |
428 | * |
429 | * This routine generates to the provided buffer the portion of the |
430 | * driver-unique report message associated with the ECCESS[BNCE] |
431 | * field of the specified ECC status. |
432 | * |
433 | * Returns the number of characters generated on success; otherwise, < |
434 | * 0 on error. |
435 | */ |
436 | static int |
437 | ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci, |
438 | const struct ppc4xx_ecc_status *status, |
439 | char *buffer, |
440 | size_t size) |
441 | { |
442 | int n, total = 0; |
443 | unsigned int lane, lanes; |
444 | const unsigned int first_lane = 0; |
445 | const unsigned int lane_count = 16; |
446 | |
447 | n = snprintf(buffer, size, "; Byte Lane Errors: "); |
448 | |
449 | if (n < 0 || n >= size) |
450 | goto fail; |
451 | |
452 | buffer += n; |
453 | size -= n; |
454 | total += n; |
455 | |
456 | for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { |
457 | if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) { |
458 | n = snprintf(buffer, size, |
459 | "%s%u", |
460 | (lanes++ ? ", " : ""), lane); |
461 | |
462 | if (n < 0 || n >= size) |
463 | goto fail; |
464 | |
465 | buffer += n; |
466 | size -= n; |
467 | total += n; |
468 | } |
469 | } |
470 | |
471 | n = snprintf(buffer, size, "%s; ", lanes ? "" : "None"); |
472 | |
473 | if (n < 0 || n >= size) |
474 | goto fail; |
475 | |
476 | buffer += n; |
477 | size -= n; |
478 | total += n; |
479 | |
480 | fail: |
481 | return total; |
482 | } |
483 | |
484 | /** |
485 | * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message |
486 | * @mci: A pointer to the EDAC memory controller instance associated |
487 | * with the ECCES message being generated. |
488 | * @status: A pointer to the ECC status structure to generate the |
489 | * message from. |
490 | * @buffer: A pointer to the buffer in which to generate the |
491 | * message. |
492 | * @size: The size, in bytes, of space available in buffer. |
493 | * |
494 | * This routine generates to the provided buffer the portion of the |
495 | * driver-unique report message associated with the ECCESS register of |
496 | * the specified ECC status. |
497 | * |
498 | * Returns the number of characters generated on success; otherwise, < |
499 | * 0 on error. |
500 | */ |
501 | static int |
502 | ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci, |
503 | const struct ppc4xx_ecc_status *status, |
504 | char *buffer, |
505 | size_t size) |
506 | { |
507 | int n, total = 0; |
508 | |
509 | n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size); |
510 | |
511 | if (n < 0 || n >= size) |
512 | goto fail; |
513 | |
514 | buffer += n; |
515 | size -= n; |
516 | total += n; |
517 | |
518 | n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size); |
519 | |
520 | if (n < 0 || n >= size) |
521 | goto fail; |
522 | |
523 | buffer += n; |
524 | size -= n; |
525 | total += n; |
526 | |
527 | n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size); |
528 | |
529 | if (n < 0 || n >= size) |
530 | goto fail; |
531 | |
532 | buffer += n; |
533 | size -= n; |
534 | total += n; |
535 | |
536 | fail: |
537 | return total; |
538 | } |
539 | |
540 | /** |
541 | * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message |
542 | * @mci: A pointer to the EDAC memory controller instance associated |
543 | * with the PLB message being generated. |
544 | * @status: A pointer to the ECC status structure to generate the |
545 | * message from. |
546 | * @buffer: A pointer to the buffer in which to generate the |
547 | * message. |
548 | * @size: The size, in bytes, of space available in buffer. |
549 | * |
550 | * This routine generates to the provided buffer the portion of the |
551 | * driver-unique report message associated with the PLB-related BESR |
552 | * and/or WMIRQ registers of the specified ECC status. |
553 | * |
554 | * Returns the number of characters generated on success; otherwise, < |
555 | * 0 on error. |
556 | */ |
557 | static int |
558 | ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci, |
559 | const struct ppc4xx_ecc_status *status, |
560 | char *buffer, |
561 | size_t size) |
562 | { |
563 | unsigned int master; |
564 | bool read; |
565 | |
566 | if ((status->besr & SDRAM_BESR_MASK) == 0) |
567 | return 0; |
568 | |
569 | if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE) |
570 | return 0; |
571 | |
572 | read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ); |
573 | |
574 | master = SDRAM_BESR_M0ID_DECODE(status->besr); |
575 | |
576 | return snprintf(buffer, size, |
577 | "%s error w/ PLB master %u \"%s\"; ", |
578 | (read ? "Read" : "Write"), |
579 | master, |
580 | (((master >= SDRAM_PLB_M0ID_FIRST) && |
581 | (master <= SDRAM_PLB_M0ID_LAST)) ? |
582 | ppc4xx_plb_masters[master] : "UNKNOWN")); |
583 | } |
584 | |
585 | /** |
586 | * ppc4xx_edac_generate_message - generate interpretted status message |
587 | * @mci: A pointer to the EDAC memory controller instance associated |
588 | * with the driver-unique message being generated. |
589 | * @status: A pointer to the ECC status structure to generate the |
590 | * message from. |
591 | * @buffer: A pointer to the buffer in which to generate the |
592 | * message. |
593 | * @size: The size, in bytes, of space available in buffer. |
594 | * |
595 | * This routine generates to the provided buffer the driver-unique |
596 | * EDAC report message from the specified ECC status. |
597 | */ |
598 | static void |
599 | ppc4xx_edac_generate_message(const struct mem_ctl_info *mci, |
600 | const struct ppc4xx_ecc_status *status, |
601 | char *buffer, |
602 | size_t size) |
603 | { |
604 | int n; |
605 | |
606 | if (buffer == NULL || size == 0) |
607 | return; |
608 | |
609 | n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size); |
610 | |
611 | if (n < 0 || n >= size) |
612 | return; |
613 | |
614 | buffer += n; |
615 | size -= n; |
616 | |
617 | ppc4xx_edac_generate_plb_message(mci, status, buffer, size); |
618 | } |
619 | |
620 | #ifdef DEBUG |
621 | /** |
622 | * ppc4xx_ecc_dump_status - dump controller ECC status registers |
623 | * @mci: A pointer to the EDAC memory controller instance |
624 | * associated with the status being dumped. |
625 | * @status: A pointer to the ECC status structure to generate the |
626 | * dump from. |
627 | * |
628 | * This routine dumps to the kernel log buffer the raw and |
629 | * interpretted specified ECC status. |
630 | */ |
631 | static void |
632 | ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci, |
633 | const struct ppc4xx_ecc_status *status) |
634 | { |
635 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; |
636 | |
637 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); |
638 | |
639 | ppc4xx_edac_mc_printk(KERN_INFO, mci, |
640 | "\n" |
641 | "\tECCES: 0x%08x\n" |
642 | "\tWMIRQ: 0x%08x\n" |
643 | "\tBESR: 0x%08x\n" |
644 | "\tBEAR: 0x%08x%08x\n" |
645 | "\t%s\n", |
646 | status->ecces, |
647 | status->wmirq, |
648 | status->besr, |
649 | status->bearh, |
650 | status->bearl, |
651 | message); |
652 | } |
653 | #endif /* DEBUG */ |
654 | |
655 | /** |
656 | * ppc4xx_ecc_get_status - get controller ECC status |
657 | * @mci: A pointer to the EDAC memory controller instance |
658 | * associated with the status being retrieved. |
659 | * @status: A pointer to the ECC status structure to populate the |
660 | * ECC status with. |
661 | * |
662 | * This routine reads and masks, as appropriate, all the relevant |
663 | * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors. |
664 | * While we read all of them, for correctable errors, we only expect |
665 | * to deal with ECCES. For uncorrectable errors, we expect to deal |
666 | * with all of them. |
667 | */ |
668 | static void |
669 | ppc4xx_ecc_get_status(const struct mem_ctl_info *mci, |
670 | struct ppc4xx_ecc_status *status) |
671 | { |
672 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; |
673 | const dcr_host_t *dcr_host = &pdata->dcr_host; |
674 | |
675 | status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK; |
676 | status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK; |
677 | status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK; |
678 | status->bearl = mfsdram(dcr_host, SDRAM_BEARL); |
679 | status->bearh = mfsdram(dcr_host, SDRAM_BEARH); |
680 | } |
681 | |
682 | /** |
683 | * ppc4xx_ecc_clear_status - clear controller ECC status |
684 | * @mci: A pointer to the EDAC memory controller instance |
685 | * associated with the status being cleared. |
686 | * @status: A pointer to the ECC status structure containing the |
687 | * values to write to clear the ECC status. |
688 | * |
689 | * This routine clears--by writing the masked (as appropriate) status |
690 | * values back to--the status registers that deal with |
691 | * ibm,sdram-4xx-ddr2 ECC errors. |
692 | */ |
693 | static void |
694 | ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci, |
695 | const struct ppc4xx_ecc_status *status) |
696 | { |
697 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; |
698 | const dcr_host_t *dcr_host = &pdata->dcr_host; |
699 | |
700 | mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK); |
701 | mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK); |
702 | mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK); |
703 | mtsdram(dcr_host, SDRAM_BEARL, 0); |
704 | mtsdram(dcr_host, SDRAM_BEARH, 0); |
705 | } |
706 | |
707 | /** |
708 | * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE) |
709 | * @mci: A pointer to the EDAC memory controller instance |
710 | * associated with the correctable error being handled and reported. |
711 | * @status: A pointer to the ECC status structure associated with |
712 | * the correctable error being handled and reported. |
713 | * |
714 | * This routine handles an ibm,sdram-4xx-ddr2 controller ECC |
715 | * correctable error. Per the aforementioned discussion, there's not |
716 | * enough status available to use the full EDAC correctable error |
717 | * interface, so we just pass driver-unique message to the "no info" |
718 | * interface. |
719 | */ |
720 | static void |
721 | ppc4xx_edac_handle_ce(struct mem_ctl_info *mci, |
722 | const struct ppc4xx_ecc_status *status) |
723 | { |
724 | int row; |
725 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; |
726 | |
727 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); |
728 | |
729 | for (row = 0; row < mci->nr_csrows; row++) |
730 | if (ppc4xx_edac_check_bank_error(status, row)) |
731 | edac_mc_handle_ce_no_info(mci, message); |
732 | } |
733 | |
734 | /** |
735 | * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE) |
736 | * @mci: A pointer to the EDAC memory controller instance |
737 | * associated with the uncorrectable error being handled and |
738 | * reported. |
739 | * @status: A pointer to the ECC status structure associated with |
740 | * the uncorrectable error being handled and reported. |
741 | * |
742 | * This routine handles an ibm,sdram-4xx-ddr2 controller ECC |
743 | * uncorrectable error. |
744 | */ |
745 | static void |
746 | ppc4xx_edac_handle_ue(struct mem_ctl_info *mci, |
747 | const struct ppc4xx_ecc_status *status) |
748 | { |
749 | const u64 bear = ((u64)status->bearh << 32 | status->bearl); |
750 | const unsigned long page = bear >> PAGE_SHIFT; |
751 | const unsigned long offset = bear & ~PAGE_MASK; |
752 | int row; |
753 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; |
754 | |
755 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); |
756 | |
757 | for (row = 0; row < mci->nr_csrows; row++) |
758 | if (ppc4xx_edac_check_bank_error(status, row)) |
759 | edac_mc_handle_ue(mci, page, offset, row, message); |
760 | } |
761 | |
762 | /** |
763 | * ppc4xx_edac_check - check controller for ECC errors |
764 | * @mci: A pointer to the EDAC memory controller instance |
765 | * associated with the ibm,sdram-4xx-ddr2 controller being |
766 | * checked. |
767 | * |
768 | * This routine is used to check and post ECC errors and is called by |
769 | * both the EDAC polling thread and this driver's CE and UE interrupt |
770 | * handler. |
771 | */ |
772 | static void |
773 | ppc4xx_edac_check(struct mem_ctl_info *mci) |
774 | { |
775 | #ifdef DEBUG |
776 | static unsigned int count; |
777 | #endif |
778 | struct ppc4xx_ecc_status status; |
779 | |
780 | ppc4xx_ecc_get_status(mci, &status); |
781 | |
782 | #ifdef DEBUG |
783 | if (count++ % 30 == 0) |
784 | ppc4xx_ecc_dump_status(mci, &status); |
785 | #endif |
786 | |
787 | if (status.ecces & SDRAM_ECCES_UE) |
788 | ppc4xx_edac_handle_ue(mci, &status); |
789 | |
790 | if (status.ecces & SDRAM_ECCES_CE) |
791 | ppc4xx_edac_handle_ce(mci, &status); |
792 | |
793 | ppc4xx_ecc_clear_status(mci, &status); |
794 | } |
795 | |
796 | /** |
797 | * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine |
798 | * @irq: The virtual interrupt number being serviced. |
799 | * @dev_id: A pointer to the EDAC memory controller instance |
800 | * associated with the interrupt being handled. |
801 | * |
802 | * This routine implements the interrupt handler for both correctable |
803 | * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2 |
804 | * controller. It simply calls through to the same routine used during |
805 | * polling to check, report and clear the ECC status. |
806 | * |
807 | * Unconditionally returns IRQ_HANDLED. |
808 | */ |
809 | static irqreturn_t |
810 | ppc4xx_edac_isr(int irq, void *dev_id) |
811 | { |
812 | struct mem_ctl_info *mci = dev_id; |
813 | |
814 | ppc4xx_edac_check(mci); |
815 | |
816 | return IRQ_HANDLED; |
817 | } |
818 | |
819 | /** |
820 | * ppc4xx_edac_get_dtype - return the controller memory width |
821 | * @mcopt1: The 32-bit Memory Controller Option 1 register value |
822 | * currently set for the controller, from which the width |
823 | * is derived. |
824 | * |
825 | * This routine returns the EDAC device type width appropriate for the |
826 | * current controller configuration. |
827 | * |
828 | * TODO: This needs to be conditioned dynamically through feature |
829 | * flags or some such when other controller variants are supported as |
830 | * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the |
831 | * 16- and 64-bit field definition/value/enumeration (b1) overloaded |
832 | * among them. |
833 | * |
834 | * Returns a device type width enumeration. |
835 | */ |
836 | static enum dev_type __devinit |
837 | ppc4xx_edac_get_dtype(u32 mcopt1) |
838 | { |
839 | switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) { |
840 | case SDRAM_MCOPT1_WDTH_16: |
841 | return DEV_X2; |
842 | case SDRAM_MCOPT1_WDTH_32: |
843 | return DEV_X4; |
844 | default: |
845 | return DEV_UNKNOWN; |
846 | } |
847 | } |
848 | |
849 | /** |
850 | * ppc4xx_edac_get_mtype - return controller memory type |
851 | * @mcopt1: The 32-bit Memory Controller Option 1 register value |
852 | * currently set for the controller, from which the memory type |
853 | * is derived. |
854 | * |
855 | * This routine returns the EDAC memory type appropriate for the |
856 | * current controller configuration. |
857 | * |
858 | * Returns a memory type enumeration. |
859 | */ |
860 | static enum mem_type __devinit |
861 | ppc4xx_edac_get_mtype(u32 mcopt1) |
862 | { |
863 | bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN); |
864 | |
865 | switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) { |
866 | case SDRAM_MCOPT1_DDR2_TYPE: |
867 | return rden ? MEM_RDDR2 : MEM_DDR2; |
868 | case SDRAM_MCOPT1_DDR1_TYPE: |
869 | return rden ? MEM_RDDR : MEM_DDR; |
870 | default: |
871 | return MEM_UNKNOWN; |
872 | } |
873 | } |
874 | |
875 | /** |
876 | * ppc4xx_edac_init_csrows - intialize driver instance rows |
877 | * @mci: A pointer to the EDAC memory controller instance |
878 | * associated with the ibm,sdram-4xx-ddr2 controller for which |
879 | * the csrows (i.e. banks/ranks) are being initialized. |
880 | * @mcopt1: The 32-bit Memory Controller Option 1 register value |
881 | * currently set for the controller, from which bank width |
882 | * and memory typ information is derived. |
883 | * |
884 | * This routine intializes the virtual "chip select rows" associated |
885 | * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2 |
886 | * controller bank/rank is mapped to a row. |
887 | * |
888 | * Returns 0 if OK; otherwise, -EINVAL if the memory bank size |
889 | * configuration cannot be determined. |
890 | */ |
891 | static int __devinit |
892 | ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1) |
893 | { |
894 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; |
895 | int status = 0; |
896 | enum mem_type mtype; |
897 | enum dev_type dtype; |
898 | enum edac_type edac_mode; |
899 | int row; |
900 | u32 mbxcf, size; |
901 | static u32 ppc4xx_last_page; |
902 | |
903 | /* Establish the memory type and width */ |
904 | |
905 | mtype = ppc4xx_edac_get_mtype(mcopt1); |
906 | dtype = ppc4xx_edac_get_dtype(mcopt1); |
907 | |
908 | /* Establish EDAC mode */ |
909 | |
910 | if (mci->edac_cap & EDAC_FLAG_SECDED) |
911 | edac_mode = EDAC_SECDED; |
912 | else if (mci->edac_cap & EDAC_FLAG_EC) |
913 | edac_mode = EDAC_EC; |
914 | else |
915 | edac_mode = EDAC_NONE; |
916 | |
917 | /* |
918 | * Initialize each chip select row structure which correspond |
919 | * 1:1 with a controller bank/rank. |
920 | */ |
921 | |
922 | for (row = 0; row < mci->nr_csrows; row++) { |
923 | struct csrow_info *csi = &mci->csrows[row]; |
924 | |
925 | /* |
926 | * Get the configuration settings for this |
927 | * row/bank/rank and skip disabled banks. |
928 | */ |
929 | |
930 | mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row)); |
931 | |
932 | if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE) |
933 | continue; |
934 | |
935 | /* Map the bank configuration size setting to pages. */ |
936 | |
937 | size = mbxcf & SDRAM_MBCF_SZ_MASK; |
938 | |
939 | switch (size) { |
940 | case SDRAM_MBCF_SZ_4MB: |
941 | case SDRAM_MBCF_SZ_8MB: |
942 | case SDRAM_MBCF_SZ_16MB: |
943 | case SDRAM_MBCF_SZ_32MB: |
944 | case SDRAM_MBCF_SZ_64MB: |
945 | case SDRAM_MBCF_SZ_128MB: |
946 | case SDRAM_MBCF_SZ_256MB: |
947 | case SDRAM_MBCF_SZ_512MB: |
948 | case SDRAM_MBCF_SZ_1GB: |
949 | case SDRAM_MBCF_SZ_2GB: |
950 | case SDRAM_MBCF_SZ_4GB: |
951 | case SDRAM_MBCF_SZ_8GB: |
952 | csi->nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size); |
953 | break; |
954 | default: |
955 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
956 | "Unrecognized memory bank %d " |
957 | "size 0x%08x\n", |
958 | row, SDRAM_MBCF_SZ_DECODE(size)); |
959 | status = -EINVAL; |
960 | goto done; |
961 | } |
962 | |
963 | csi->first_page = ppc4xx_last_page; |
964 | csi->last_page = csi->first_page + csi->nr_pages - 1; |
965 | csi->page_mask = 0; |
966 | |
967 | /* |
968 | * It's unclear exactly what grain should be set to |
969 | * here. The SDRAM_ECCES register allows resolution of |
970 | * an error down to a nibble which would potentially |
971 | * argue for a grain of '1' byte, even though we only |
972 | * know the associated address for uncorrectable |
973 | * errors. This value is not used at present for |
974 | * anything other than error reporting so getting it |
975 | * wrong should be of little consequence. Other |
976 | * possible values would be the PLB width (16), the |
977 | * page size (PAGE_SIZE) or the memory width (2 or 4). |
978 | */ |
979 | |
980 | csi->grain = 1; |
981 | |
982 | csi->mtype = mtype; |
983 | csi->dtype = dtype; |
984 | |
985 | csi->edac_mode = edac_mode; |
986 | |
987 | ppc4xx_last_page += csi->nr_pages; |
988 | } |
989 | |
990 | done: |
991 | return status; |
992 | } |
993 | |
994 | /** |
995 | * ppc4xx_edac_mc_init - intialize driver instance |
996 | * @mci: A pointer to the EDAC memory controller instance being |
997 | * initialized. |
998 | * @op: A pointer to the OpenFirmware device tree node associated |
999 | * with the controller this EDAC instance is bound to. |
1000 | * @match: A pointer to the OpenFirmware device tree match |
1001 | * information associated with the controller this EDAC instance |
1002 | * is bound to. |
1003 | * @dcr_host: A pointer to the DCR data containing the DCR mapping |
1004 | * for this controller instance. |
1005 | * @mcopt1: The 32-bit Memory Controller Option 1 register value |
1006 | * currently set for the controller, from which ECC capabilities |
1007 | * and scrub mode are derived. |
1008 | * |
1009 | * This routine performs initialization of the EDAC memory controller |
1010 | * instance and related driver-private data associated with the |
1011 | * ibm,sdram-4xx-ddr2 memory controller the instance is bound to. |
1012 | * |
1013 | * Returns 0 if OK; otherwise, < 0 on error. |
1014 | */ |
1015 | static int __devinit |
1016 | ppc4xx_edac_mc_init(struct mem_ctl_info *mci, |
1017 | struct of_device *op, |
1018 | const struct of_device_id *match, |
1019 | const dcr_host_t *dcr_host, |
1020 | u32 mcopt1) |
1021 | { |
1022 | int status = 0; |
1023 | const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK); |
1024 | struct ppc4xx_edac_pdata *pdata = NULL; |
1025 | const struct device_node *np = op->node; |
1026 | |
1027 | if (match == NULL) |
1028 | return -EINVAL; |
1029 | |
1030 | /* Initial driver pointers and private data */ |
1031 | |
1032 | mci->dev = &op->dev; |
1033 | |
1034 | dev_set_drvdata(mci->dev, mci); |
1035 | |
1036 | pdata = mci->pvt_info; |
1037 | |
1038 | pdata->dcr_host = *dcr_host; |
1039 | pdata->irqs.sec = NO_IRQ; |
1040 | pdata->irqs.ded = NO_IRQ; |
1041 | |
1042 | /* Initialize controller capabilities and configuration */ |
1043 | |
1044 | mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR | |
1045 | MEM_FLAG_DDR2 | MEM_FLAG_RDDR2); |
1046 | |
1047 | mci->edac_ctl_cap = (EDAC_FLAG_NONE | |
1048 | EDAC_FLAG_EC | |
1049 | EDAC_FLAG_SECDED); |
1050 | |
1051 | mci->scrub_cap = SCRUB_NONE; |
1052 | mci->scrub_mode = SCRUB_NONE; |
1053 | |
1054 | /* |
1055 | * Update the actual capabilites based on the MCOPT1[MCHK] |
1056 | * settings. Scrubbing is only useful if reporting is enabled. |
1057 | */ |
1058 | |
1059 | switch (memcheck) { |
1060 | case SDRAM_MCOPT1_MCHK_CHK: |
1061 | mci->edac_cap = EDAC_FLAG_EC; |
1062 | break; |
1063 | case SDRAM_MCOPT1_MCHK_CHK_REP: |
1064 | mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED); |
1065 | mci->scrub_mode = SCRUB_SW_SRC; |
1066 | break; |
1067 | default: |
1068 | mci->edac_cap = EDAC_FLAG_NONE; |
1069 | break; |
1070 | } |
1071 | |
1072 | /* Initialize strings */ |
1073 | |
1074 | mci->mod_name = PPC4XX_EDAC_MODULE_NAME; |
1075 | mci->mod_ver = PPC4XX_EDAC_MODULE_REVISION; |
1076 | mci->ctl_name = match->compatible, |
1077 | mci->dev_name = np->full_name; |
1078 | |
1079 | /* Initialize callbacks */ |
1080 | |
1081 | mci->edac_check = ppc4xx_edac_check; |
1082 | mci->ctl_page_to_phys = NULL; |
1083 | |
1084 | /* Initialize chip select rows */ |
1085 | |
1086 | status = ppc4xx_edac_init_csrows(mci, mcopt1); |
1087 | |
1088 | if (status) |
1089 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
1090 | "Failed to initialize rows!\n"); |
1091 | |
1092 | return status; |
1093 | } |
1094 | |
1095 | /** |
1096 | * ppc4xx_edac_register_irq - setup and register controller interrupts |
1097 | * @op: A pointer to the OpenFirmware device tree node associated |
1098 | * with the controller this EDAC instance is bound to. |
1099 | * @mci: A pointer to the EDAC memory controller instance |
1100 | * associated with the ibm,sdram-4xx-ddr2 controller for which |
1101 | * interrupts are being registered. |
1102 | * |
1103 | * This routine parses the correctable (CE) and uncorrectable error (UE) |
1104 | * interrupts from the device tree node and maps and assigns them to |
1105 | * the associated EDAC memory controller instance. |
1106 | * |
1107 | * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be |
1108 | * mapped and assigned. |
1109 | */ |
1110 | static int __devinit |
1111 | ppc4xx_edac_register_irq(struct of_device *op, struct mem_ctl_info *mci) |
1112 | { |
1113 | int status = 0; |
1114 | int ded_irq, sec_irq; |
1115 | struct ppc4xx_edac_pdata *pdata = mci->pvt_info; |
1116 | struct device_node *np = op->node; |
1117 | |
1118 | ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX); |
1119 | sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX); |
1120 | |
1121 | if (ded_irq == NO_IRQ || sec_irq == NO_IRQ) { |
1122 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
1123 | "Unable to map interrupts.\n"); |
1124 | status = -ENODEV; |
1125 | goto fail; |
1126 | } |
1127 | |
1128 | status = request_irq(ded_irq, |
1129 | ppc4xx_edac_isr, |
1130 | IRQF_DISABLED, |
1131 | "[EDAC] MC ECCDED", |
1132 | mci); |
1133 | |
1134 | if (status < 0) { |
1135 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
1136 | "Unable to request irq %d for ECC DED", |
1137 | ded_irq); |
1138 | status = -ENODEV; |
1139 | goto fail1; |
1140 | } |
1141 | |
1142 | status = request_irq(sec_irq, |
1143 | ppc4xx_edac_isr, |
1144 | IRQF_DISABLED, |
1145 | "[EDAC] MC ECCSEC", |
1146 | mci); |
1147 | |
1148 | if (status < 0) { |
1149 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
1150 | "Unable to request irq %d for ECC SEC", |
1151 | sec_irq); |
1152 | status = -ENODEV; |
1153 | goto fail2; |
1154 | } |
1155 | |
1156 | ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq); |
1157 | ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq); |
1158 | |
1159 | pdata->irqs.ded = ded_irq; |
1160 | pdata->irqs.sec = sec_irq; |
1161 | |
1162 | return 0; |
1163 | |
1164 | fail2: |
1165 | free_irq(sec_irq, mci); |
1166 | |
1167 | fail1: |
1168 | free_irq(ded_irq, mci); |
1169 | |
1170 | fail: |
1171 | return status; |
1172 | } |
1173 | |
1174 | /** |
1175 | * ppc4xx_edac_map_dcrs - locate and map controller registers |
1176 | * @np: A pointer to the device tree node containing the DCR |
1177 | * resources to map. |
1178 | * @dcr_host: A pointer to the DCR data to populate with the |
1179 | * DCR mapping. |
1180 | * |
1181 | * This routine attempts to locate in the device tree and map the DCR |
1182 | * register resources associated with the controller's indirect DCR |
1183 | * address and data windows. |
1184 | * |
1185 | * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on |
1186 | * error. |
1187 | */ |
1188 | static int __devinit |
1189 | ppc4xx_edac_map_dcrs(const struct device_node *np, dcr_host_t *dcr_host) |
1190 | { |
1191 | unsigned int dcr_base, dcr_len; |
1192 | |
1193 | if (np == NULL || dcr_host == NULL) |
1194 | return -EINVAL; |
1195 | |
1196 | /* Get the DCR resource extent and sanity check the values. */ |
1197 | |
1198 | dcr_base = dcr_resource_start(np, 0); |
1199 | dcr_len = dcr_resource_len(np, 0); |
1200 | |
1201 | if (dcr_base == 0 || dcr_len == 0) { |
1202 | ppc4xx_edac_printk(KERN_ERR, |
1203 | "Failed to obtain DCR property.\n"); |
1204 | return -ENODEV; |
1205 | } |
1206 | |
1207 | if (dcr_len != SDRAM_DCR_RESOURCE_LEN) { |
1208 | ppc4xx_edac_printk(KERN_ERR, |
1209 | "Unexpected DCR length %d, expected %d.\n", |
1210 | dcr_len, SDRAM_DCR_RESOURCE_LEN); |
1211 | return -ENODEV; |
1212 | } |
1213 | |
1214 | /* Attempt to map the DCR extent. */ |
1215 | |
1216 | *dcr_host = dcr_map(np, dcr_base, dcr_len); |
1217 | |
1218 | if (!DCR_MAP_OK(*dcr_host)) { |
1219 | ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n"); |
1220 | return -ENODEV; |
1221 | } |
1222 | |
1223 | return 0; |
1224 | } |
1225 | |
1226 | /** |
1227 | * ppc4xx_edac_probe - check controller and bind driver |
1228 | * @op: A pointer to the OpenFirmware device tree node associated |
1229 | * with the controller being probed for driver binding. |
1230 | * @match: A pointer to the OpenFirmware device tree match |
1231 | * information associated with the controller being probed |
1232 | * for driver binding. |
1233 | * |
1234 | * This routine probes a specific ibm,sdram-4xx-ddr2 controller |
1235 | * instance for binding with the driver. |
1236 | * |
1237 | * Returns 0 if the controller instance was successfully bound to the |
1238 | * driver; otherwise, < 0 on error. |
1239 | */ |
1240 | static int __devinit |
1241 | ppc4xx_edac_probe(struct of_device *op, const struct of_device_id *match) |
1242 | { |
1243 | int status = 0; |
1244 | u32 mcopt1, memcheck; |
1245 | dcr_host_t dcr_host; |
1246 | const struct device_node *np = op->node; |
1247 | struct mem_ctl_info *mci = NULL; |
1248 | static int ppc4xx_edac_instance; |
1249 | |
1250 | /* |
1251 | * At this point, we only support the controller realized on |
1252 | * the AMCC PPC 405EX[r]. Reject anything else. |
1253 | */ |
1254 | |
1255 | if (!of_device_is_compatible(np, "ibm,sdram-405ex") && |
1256 | !of_device_is_compatible(np, "ibm,sdram-405exr")) { |
1257 | ppc4xx_edac_printk(KERN_NOTICE, |
1258 | "Only the PPC405EX[r] is supported.\n"); |
1259 | return -ENODEV; |
1260 | } |
1261 | |
1262 | /* |
1263 | * Next, get the DCR property and attempt to map it so that we |
1264 | * can probe the controller. |
1265 | */ |
1266 | |
1267 | status = ppc4xx_edac_map_dcrs(np, &dcr_host); |
1268 | |
1269 | if (status) |
1270 | return status; |
1271 | |
1272 | /* |
1273 | * First determine whether ECC is enabled at all. If not, |
1274 | * there is no useful checking or monitoring that can be done |
1275 | * for this controller. |
1276 | */ |
1277 | |
1278 | mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1); |
1279 | memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK); |
1280 | |
1281 | if (memcheck == SDRAM_MCOPT1_MCHK_NON) { |
1282 | ppc4xx_edac_printk(KERN_INFO, "%s: No ECC memory detected or " |
1283 | "ECC is disabled.\n", np->full_name); |
1284 | status = -ENODEV; |
1285 | goto done; |
1286 | } |
1287 | |
1288 | /* |
1289 | * At this point, we know ECC is enabled, allocate an EDAC |
1290 | * controller instance and perform the appropriate |
1291 | * initialization. |
1292 | */ |
1293 | |
1294 | mci = edac_mc_alloc(sizeof(struct ppc4xx_edac_pdata), |
1295 | ppc4xx_edac_nr_csrows, |
1296 | ppc4xx_edac_nr_chans, |
1297 | ppc4xx_edac_instance); |
1298 | |
1299 | if (mci == NULL) { |
1300 | ppc4xx_edac_printk(KERN_ERR, "%s: " |
1301 | "Failed to allocate EDAC MC instance!\n", |
1302 | np->full_name); |
1303 | status = -ENOMEM; |
1304 | goto done; |
1305 | } |
1306 | |
1307 | status = ppc4xx_edac_mc_init(mci, op, match, &dcr_host, mcopt1); |
1308 | |
1309 | if (status) { |
1310 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
1311 | "Failed to initialize instance!\n"); |
1312 | goto fail; |
1313 | } |
1314 | |
1315 | /* |
1316 | * We have a valid, initialized EDAC instance bound to the |
1317 | * controller. Attempt to register it with the EDAC subsystem |
1318 | * and, if necessary, register interrupts. |
1319 | */ |
1320 | |
1321 | if (edac_mc_add_mc(mci)) { |
1322 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
1323 | "Failed to add instance!\n"); |
1324 | status = -ENODEV; |
1325 | goto fail; |
1326 | } |
1327 | |
1328 | if (edac_op_state == EDAC_OPSTATE_INT) { |
1329 | status = ppc4xx_edac_register_irq(op, mci); |
1330 | |
1331 | if (status) |
1332 | goto fail1; |
1333 | } |
1334 | |
1335 | ppc4xx_edac_instance++; |
1336 | |
1337 | return 0; |
1338 | |
1339 | fail1: |
1340 | edac_mc_del_mc(mci->dev); |
1341 | |
1342 | fail: |
1343 | edac_mc_free(mci); |
1344 | |
1345 | done: |
1346 | return status; |
1347 | } |
1348 | |
1349 | /** |
1350 | * ppc4xx_edac_remove - unbind driver from controller |
1351 | * @op: A pointer to the OpenFirmware device tree node associated |
1352 | * with the controller this EDAC instance is to be unbound/removed |
1353 | * from. |
1354 | * |
1355 | * This routine unbinds the EDAC memory controller instance associated |
1356 | * with the specified ibm,sdram-4xx-ddr2 controller described by the |
1357 | * OpenFirmware device tree node passed as a parameter. |
1358 | * |
1359 | * Unconditionally returns 0. |
1360 | */ |
1361 | static int |
1362 | ppc4xx_edac_remove(struct of_device *op) |
1363 | { |
1364 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); |
1365 | struct ppc4xx_edac_pdata *pdata = mci->pvt_info; |
1366 | |
1367 | if (edac_op_state == EDAC_OPSTATE_INT) { |
1368 | free_irq(pdata->irqs.sec, mci); |
1369 | free_irq(pdata->irqs.ded, mci); |
1370 | } |
1371 | |
1372 | dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN); |
1373 | |
1374 | edac_mc_del_mc(mci->dev); |
1375 | edac_mc_free(mci); |
1376 | |
1377 | return 0; |
1378 | } |
1379 | |
1380 | /** |
1381 | * ppc4xx_edac_opstate_init - initialize EDAC reporting method |
1382 | * |
1383 | * This routine ensures that the EDAC memory controller reporting |
1384 | * method is mapped to a sane value as the EDAC core defines the value |
1385 | * to EDAC_OPSTATE_INVAL by default. We don't call the global |
1386 | * opstate_init as that defaults to polling and we want interrupt as |
1387 | * the default. |
1388 | */ |
1389 | static inline void __init |
1390 | ppc4xx_edac_opstate_init(void) |
1391 | { |
1392 | switch (edac_op_state) { |
1393 | case EDAC_OPSTATE_POLL: |
1394 | case EDAC_OPSTATE_INT: |
1395 | break; |
1396 | default: |
1397 | edac_op_state = EDAC_OPSTATE_INT; |
1398 | break; |
1399 | } |
1400 | |
1401 | ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n", |
1402 | ((edac_op_state == EDAC_OPSTATE_POLL) ? |
1403 | EDAC_OPSTATE_POLL_STR : |
1404 | ((edac_op_state == EDAC_OPSTATE_INT) ? |
1405 | EDAC_OPSTATE_INT_STR : |
1406 | EDAC_OPSTATE_UNKNOWN_STR))); |
1407 | } |
1408 | |
1409 | /** |
1410 | * ppc4xx_edac_init - driver/module insertion entry point |
1411 | * |
1412 | * This routine is the driver/module insertion entry point. It |
1413 | * initializes the EDAC memory controller reporting state and |
1414 | * registers the driver as an OpenFirmware device tree platform |
1415 | * driver. |
1416 | */ |
1417 | static int __init |
1418 | ppc4xx_edac_init(void) |
1419 | { |
1420 | ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n"); |
1421 | |
1422 | ppc4xx_edac_opstate_init(); |
1423 | |
1424 | return of_register_platform_driver(&ppc4xx_edac_driver); |
1425 | } |
1426 | |
1427 | /** |
1428 | * ppc4xx_edac_exit - driver/module removal entry point |
1429 | * |
1430 | * This routine is the driver/module removal entry point. It |
1431 | * unregisters the driver as an OpenFirmware device tree platform |
1432 | * driver. |
1433 | */ |
1434 | static void __exit |
1435 | ppc4xx_edac_exit(void) |
1436 | { |
1437 | of_unregister_platform_driver(&ppc4xx_edac_driver); |
1438 | } |
1439 | |
1440 | module_init(ppc4xx_edac_init); |
1441 | module_exit(ppc4xx_edac_exit); |
1442 | |
1443 | MODULE_LICENSE("GPL v2"); |
1444 | MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>"); |
1445 | MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller"); |
1446 | module_param(edac_op_state, int, 0444); |
1447 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: " |
1448 | "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR); |
1449 |
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