Root/
1 | /* |
2 | * twl4030-irq.c - TWL4030/TPS659x0 irq support |
3 | * |
4 | * Copyright (C) 2005-2006 Texas Instruments, Inc. |
5 | * |
6 | * Modifications to defer interrupt handling to a kernel thread: |
7 | * Copyright (C) 2006 MontaVista Software, Inc. |
8 | * |
9 | * Based on tlv320aic23.c: |
10 | * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> |
11 | * |
12 | * Code cleanup and modifications to IRQ handler. |
13 | * by syed khasim <x0khasim@ti.com> |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License as published by |
17 | * the Free Software Foundation; either version 2 of the License, or |
18 | * (at your option) any later version. |
19 | * |
20 | * This program is distributed in the hope that it will be useful, |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
23 | * GNU General Public License for more details. |
24 | * |
25 | * You should have received a copy of the GNU General Public License |
26 | * along with this program; if not, write to the Free Software |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
28 | */ |
29 | |
30 | #include <linux/init.h> |
31 | #include <linux/interrupt.h> |
32 | #include <linux/irq.h> |
33 | #include <linux/kthread.h> |
34 | #include <linux/slab.h> |
35 | |
36 | #include <linux/i2c/twl.h> |
37 | |
38 | |
39 | /* |
40 | * TWL4030 IRQ handling has two stages in hardware, and thus in software. |
41 | * The Primary Interrupt Handler (PIH) stage exposes status bits saying |
42 | * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. |
43 | * SIH modules are more traditional IRQ components, which support per-IRQ |
44 | * enable/disable and trigger controls; they do most of the work. |
45 | * |
46 | * These chips are designed to support IRQ handling from two different |
47 | * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status |
48 | * and mask registers in the PIH and SIH modules. |
49 | * |
50 | * We set up IRQs starting at a platform-specified base, always starting |
51 | * with PIH and the SIH for PWR_INT and then usually adding GPIO: |
52 | * base + 0 .. base + 7 PIH |
53 | * base + 8 .. base + 15 SIH for PWR_INT |
54 | * base + 16 .. base + 33 SIH for GPIO |
55 | */ |
56 | |
57 | /* PIH register offsets */ |
58 | #define REG_PIH_ISR_P1 0x01 |
59 | #define REG_PIH_ISR_P2 0x02 |
60 | #define REG_PIH_SIR 0x03 /* for testing */ |
61 | |
62 | |
63 | /* Linux could (eventually) use either IRQ line */ |
64 | static int irq_line; |
65 | |
66 | struct sih { |
67 | char name[8]; |
68 | u8 module; /* module id */ |
69 | u8 control_offset; /* for SIH_CTRL */ |
70 | bool set_cor; |
71 | |
72 | u8 bits; /* valid in isr/imr */ |
73 | u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ |
74 | |
75 | u8 edr_offset; |
76 | u8 bytes_edr; /* bytelen of EDR */ |
77 | |
78 | u8 irq_lines; /* number of supported irq lines */ |
79 | |
80 | /* SIR ignored -- set interrupt, for testing only */ |
81 | struct irq_data { |
82 | u8 isr_offset; |
83 | u8 imr_offset; |
84 | } mask[2]; |
85 | /* + 2 bytes padding */ |
86 | }; |
87 | |
88 | static const struct sih *sih_modules; |
89 | static int nr_sih_modules; |
90 | |
91 | #define SIH_INITIALIZER(modname, nbits) \ |
92 | .module = TWL4030_MODULE_ ## modname, \ |
93 | .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ |
94 | .bits = nbits, \ |
95 | .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ |
96 | .edr_offset = TWL4030_ ## modname ## _EDR, \ |
97 | .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ |
98 | .irq_lines = 2, \ |
99 | .mask = { { \ |
100 | .isr_offset = TWL4030_ ## modname ## _ISR1, \ |
101 | .imr_offset = TWL4030_ ## modname ## _IMR1, \ |
102 | }, \ |
103 | { \ |
104 | .isr_offset = TWL4030_ ## modname ## _ISR2, \ |
105 | .imr_offset = TWL4030_ ## modname ## _IMR2, \ |
106 | }, }, |
107 | |
108 | /* register naming policies are inconsistent ... */ |
109 | #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 |
110 | #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD |
111 | #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT |
112 | |
113 | |
114 | /* Order in this table matches order in PIH_ISR. That is, |
115 | * BIT(n) in PIH_ISR is sih_modules[n]. |
116 | */ |
117 | /* sih_modules_twl4030 is used both in twl4030 and twl5030 */ |
118 | static const struct sih sih_modules_twl4030[6] = { |
119 | [0] = { |
120 | .name = "gpio", |
121 | .module = TWL4030_MODULE_GPIO, |
122 | .control_offset = REG_GPIO_SIH_CTRL, |
123 | .set_cor = true, |
124 | .bits = TWL4030_GPIO_MAX, |
125 | .bytes_ixr = 3, |
126 | /* Note: *all* of these IRQs default to no-trigger */ |
127 | .edr_offset = REG_GPIO_EDR1, |
128 | .bytes_edr = 5, |
129 | .irq_lines = 2, |
130 | .mask = { { |
131 | .isr_offset = REG_GPIO_ISR1A, |
132 | .imr_offset = REG_GPIO_IMR1A, |
133 | }, { |
134 | .isr_offset = REG_GPIO_ISR1B, |
135 | .imr_offset = REG_GPIO_IMR1B, |
136 | }, }, |
137 | }, |
138 | [1] = { |
139 | .name = "keypad", |
140 | .set_cor = true, |
141 | SIH_INITIALIZER(KEYPAD_KEYP, 4) |
142 | }, |
143 | [2] = { |
144 | .name = "bci", |
145 | .module = TWL4030_MODULE_INTERRUPTS, |
146 | .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, |
147 | .bits = 12, |
148 | .bytes_ixr = 2, |
149 | .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, |
150 | /* Note: most of these IRQs default to no-trigger */ |
151 | .bytes_edr = 3, |
152 | .irq_lines = 2, |
153 | .mask = { { |
154 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, |
155 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, |
156 | }, { |
157 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, |
158 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, |
159 | }, }, |
160 | }, |
161 | [3] = { |
162 | .name = "madc", |
163 | SIH_INITIALIZER(MADC, 4) |
164 | }, |
165 | [4] = { |
166 | /* USB doesn't use the same SIH organization */ |
167 | .name = "usb", |
168 | }, |
169 | [5] = { |
170 | .name = "power", |
171 | .set_cor = true, |
172 | SIH_INITIALIZER(INT_PWR, 8) |
173 | }, |
174 | /* there are no SIH modules #6 or #7 ... */ |
175 | }; |
176 | |
177 | static const struct sih sih_modules_twl5031[8] = { |
178 | [0] = { |
179 | .name = "gpio", |
180 | .module = TWL4030_MODULE_GPIO, |
181 | .control_offset = REG_GPIO_SIH_CTRL, |
182 | .set_cor = true, |
183 | .bits = TWL4030_GPIO_MAX, |
184 | .bytes_ixr = 3, |
185 | /* Note: *all* of these IRQs default to no-trigger */ |
186 | .edr_offset = REG_GPIO_EDR1, |
187 | .bytes_edr = 5, |
188 | .irq_lines = 2, |
189 | .mask = { { |
190 | .isr_offset = REG_GPIO_ISR1A, |
191 | .imr_offset = REG_GPIO_IMR1A, |
192 | }, { |
193 | .isr_offset = REG_GPIO_ISR1B, |
194 | .imr_offset = REG_GPIO_IMR1B, |
195 | }, }, |
196 | }, |
197 | [1] = { |
198 | .name = "keypad", |
199 | .set_cor = true, |
200 | SIH_INITIALIZER(KEYPAD_KEYP, 4) |
201 | }, |
202 | [2] = { |
203 | .name = "bci", |
204 | .module = TWL5031_MODULE_INTERRUPTS, |
205 | .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, |
206 | .bits = 7, |
207 | .bytes_ixr = 1, |
208 | .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, |
209 | /* Note: most of these IRQs default to no-trigger */ |
210 | .bytes_edr = 2, |
211 | .irq_lines = 2, |
212 | .mask = { { |
213 | .isr_offset = TWL5031_INTERRUPTS_BCIISR1, |
214 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, |
215 | }, { |
216 | .isr_offset = TWL5031_INTERRUPTS_BCIISR2, |
217 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, |
218 | }, }, |
219 | }, |
220 | [3] = { |
221 | .name = "madc", |
222 | SIH_INITIALIZER(MADC, 4) |
223 | }, |
224 | [4] = { |
225 | /* USB doesn't use the same SIH organization */ |
226 | .name = "usb", |
227 | }, |
228 | [5] = { |
229 | .name = "power", |
230 | .set_cor = true, |
231 | SIH_INITIALIZER(INT_PWR, 8) |
232 | }, |
233 | [6] = { |
234 | /* |
235 | * ACI doesn't use the same SIH organization. |
236 | * For example, it supports only one interrupt line |
237 | */ |
238 | .name = "aci", |
239 | .module = TWL5031_MODULE_ACCESSORY, |
240 | .bits = 9, |
241 | .bytes_ixr = 2, |
242 | .irq_lines = 1, |
243 | .mask = { { |
244 | .isr_offset = TWL5031_ACIIDR_LSB, |
245 | .imr_offset = TWL5031_ACIIMR_LSB, |
246 | }, }, |
247 | |
248 | }, |
249 | [7] = { |
250 | /* Accessory */ |
251 | .name = "acc", |
252 | .module = TWL5031_MODULE_ACCESSORY, |
253 | .control_offset = TWL5031_ACCSIHCTRL, |
254 | .bits = 2, |
255 | .bytes_ixr = 1, |
256 | .edr_offset = TWL5031_ACCEDR1, |
257 | /* Note: most of these IRQs default to no-trigger */ |
258 | .bytes_edr = 1, |
259 | .irq_lines = 2, |
260 | .mask = { { |
261 | .isr_offset = TWL5031_ACCISR1, |
262 | .imr_offset = TWL5031_ACCIMR1, |
263 | }, { |
264 | .isr_offset = TWL5031_ACCISR2, |
265 | .imr_offset = TWL5031_ACCIMR2, |
266 | }, }, |
267 | }, |
268 | }; |
269 | |
270 | #undef TWL4030_MODULE_KEYPAD_KEYP |
271 | #undef TWL4030_MODULE_INT_PWR |
272 | #undef TWL4030_INT_PWR_EDR |
273 | |
274 | /*----------------------------------------------------------------------*/ |
275 | |
276 | static unsigned twl4030_irq_base; |
277 | |
278 | static struct completion irq_event; |
279 | |
280 | /* |
281 | * This thread processes interrupts reported by the Primary Interrupt Handler. |
282 | */ |
283 | static int twl4030_irq_thread(void *data) |
284 | { |
285 | long irq = (long)data; |
286 | static unsigned i2c_errors; |
287 | static const unsigned max_i2c_errors = 100; |
288 | |
289 | |
290 | current->flags |= PF_NOFREEZE; |
291 | |
292 | while (!kthread_should_stop()) { |
293 | int ret; |
294 | int module_irq; |
295 | u8 pih_isr; |
296 | |
297 | /* Wait for IRQ, then read PIH irq status (also blocking) */ |
298 | wait_for_completion_interruptible(&irq_event); |
299 | |
300 | ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, |
301 | REG_PIH_ISR_P1); |
302 | if (ret) { |
303 | pr_warning("twl4030: I2C error %d reading PIH ISR\n", |
304 | ret); |
305 | if (++i2c_errors >= max_i2c_errors) { |
306 | printk(KERN_ERR "Maximum I2C error count" |
307 | " exceeded. Terminating %s.\n", |
308 | __func__); |
309 | break; |
310 | } |
311 | complete(&irq_event); |
312 | continue; |
313 | } |
314 | |
315 | /* these handlers deal with the relevant SIH irq status */ |
316 | local_irq_disable(); |
317 | for (module_irq = twl4030_irq_base; |
318 | pih_isr; |
319 | pih_isr >>= 1, module_irq++) { |
320 | if (pih_isr & 0x1) { |
321 | struct irq_desc *d = irq_to_desc(module_irq); |
322 | |
323 | if (!d) { |
324 | pr_err("twl4030: Invalid SIH IRQ: %d\n", |
325 | module_irq); |
326 | return -EINVAL; |
327 | } |
328 | |
329 | /* These can't be masked ... always warn |
330 | * if we get any surprises. |
331 | */ |
332 | if (d->status & IRQ_DISABLED) |
333 | note_interrupt(module_irq, d, |
334 | IRQ_NONE); |
335 | else |
336 | d->handle_irq(module_irq, d); |
337 | } |
338 | } |
339 | local_irq_enable(); |
340 | |
341 | enable_irq(irq); |
342 | } |
343 | |
344 | return 0; |
345 | } |
346 | |
347 | /* |
348 | * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. |
349 | * This is a chained interrupt, so there is no desc->action method for it. |
350 | * Now we need to query the interrupt controller in the twl4030 to determine |
351 | * which module is generating the interrupt request. However, we can't do i2c |
352 | * transactions in interrupt context, so we must defer that work to a kernel |
353 | * thread. All we do here is acknowledge and mask the interrupt and wakeup |
354 | * the kernel thread. |
355 | */ |
356 | static irqreturn_t handle_twl4030_pih(int irq, void *devid) |
357 | { |
358 | /* Acknowledge, clear *AND* mask the interrupt... */ |
359 | disable_irq_nosync(irq); |
360 | complete(devid); |
361 | return IRQ_HANDLED; |
362 | } |
363 | /*----------------------------------------------------------------------*/ |
364 | |
365 | /* |
366 | * twl4030_init_sih_modules() ... start from a known state where no |
367 | * IRQs will be coming in, and where we can quickly enable them then |
368 | * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. |
369 | * |
370 | * NOTE: we don't touch EDR registers here; they stay with hardware |
371 | * defaults or whatever the last value was. Note that when both EDR |
372 | * bits for an IRQ are clear, that's as if its IMR bit is set... |
373 | */ |
374 | static int twl4030_init_sih_modules(unsigned line) |
375 | { |
376 | const struct sih *sih; |
377 | u8 buf[4]; |
378 | int i; |
379 | int status; |
380 | |
381 | /* line 0 == int1_n signal; line 1 == int2_n signal */ |
382 | if (line > 1) |
383 | return -EINVAL; |
384 | |
385 | irq_line = line; |
386 | |
387 | /* disable all interrupts on our line */ |
388 | memset(buf, 0xff, sizeof buf); |
389 | sih = sih_modules; |
390 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
391 | |
392 | /* skip USB -- it's funky */ |
393 | if (!sih->bytes_ixr) |
394 | continue; |
395 | |
396 | /* Not all the SIH modules support multiple interrupt lines */ |
397 | if (sih->irq_lines <= line) |
398 | continue; |
399 | |
400 | status = twl_i2c_write(sih->module, buf, |
401 | sih->mask[line].imr_offset, sih->bytes_ixr); |
402 | if (status < 0) |
403 | pr_err("twl4030: err %d initializing %s %s\n", |
404 | status, sih->name, "IMR"); |
405 | |
406 | /* Maybe disable "exclusive" mode; buffer second pending irq; |
407 | * set Clear-On-Read (COR) bit. |
408 | * |
409 | * NOTE that sometimes COR polarity is documented as being |
410 | * inverted: for MADC and BCI, COR=1 means "clear on write". |
411 | * And for PWR_INT it's not documented... |
412 | */ |
413 | if (sih->set_cor) { |
414 | status = twl_i2c_write_u8(sih->module, |
415 | TWL4030_SIH_CTRL_COR_MASK, |
416 | sih->control_offset); |
417 | if (status < 0) |
418 | pr_err("twl4030: err %d initializing %s %s\n", |
419 | status, sih->name, "SIH_CTRL"); |
420 | } |
421 | } |
422 | |
423 | sih = sih_modules; |
424 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
425 | u8 rxbuf[4]; |
426 | int j; |
427 | |
428 | /* skip USB */ |
429 | if (!sih->bytes_ixr) |
430 | continue; |
431 | |
432 | /* Not all the SIH modules support multiple interrupt lines */ |
433 | if (sih->irq_lines <= line) |
434 | continue; |
435 | |
436 | /* Clear pending interrupt status. Either the read was |
437 | * enough, or we need to write those bits. Repeat, in |
438 | * case an IRQ is pending (PENDDIS=0) ... that's not |
439 | * uncommon with PWR_INT.PWRON. |
440 | */ |
441 | for (j = 0; j < 2; j++) { |
442 | status = twl_i2c_read(sih->module, rxbuf, |
443 | sih->mask[line].isr_offset, sih->bytes_ixr); |
444 | if (status < 0) |
445 | pr_err("twl4030: err %d initializing %s %s\n", |
446 | status, sih->name, "ISR"); |
447 | |
448 | if (!sih->set_cor) |
449 | status = twl_i2c_write(sih->module, buf, |
450 | sih->mask[line].isr_offset, |
451 | sih->bytes_ixr); |
452 | /* else COR=1 means read sufficed. |
453 | * (for most SIH modules...) |
454 | */ |
455 | } |
456 | } |
457 | |
458 | return 0; |
459 | } |
460 | |
461 | static inline void activate_irq(int irq) |
462 | { |
463 | #ifdef CONFIG_ARM |
464 | /* ARM requires an extra step to clear IRQ_NOREQUEST, which it |
465 | * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. |
466 | */ |
467 | set_irq_flags(irq, IRQF_VALID); |
468 | #else |
469 | /* same effect on other architectures */ |
470 | set_irq_noprobe(irq); |
471 | #endif |
472 | } |
473 | |
474 | /*----------------------------------------------------------------------*/ |
475 | |
476 | static DEFINE_SPINLOCK(sih_agent_lock); |
477 | |
478 | static struct workqueue_struct *wq; |
479 | |
480 | struct sih_agent { |
481 | int irq_base; |
482 | const struct sih *sih; |
483 | |
484 | u32 imr; |
485 | bool imr_change_pending; |
486 | struct work_struct mask_work; |
487 | |
488 | u32 edge_change; |
489 | struct work_struct edge_work; |
490 | }; |
491 | |
492 | static void twl4030_sih_do_mask(struct work_struct *work) |
493 | { |
494 | struct sih_agent *agent; |
495 | const struct sih *sih; |
496 | union { |
497 | u8 bytes[4]; |
498 | u32 word; |
499 | } imr; |
500 | int status; |
501 | |
502 | agent = container_of(work, struct sih_agent, mask_work); |
503 | |
504 | /* see what work we have */ |
505 | spin_lock_irq(&sih_agent_lock); |
506 | if (agent->imr_change_pending) { |
507 | sih = agent->sih; |
508 | /* byte[0] gets overwritten as we write ... */ |
509 | imr.word = cpu_to_le32(agent->imr << 8); |
510 | agent->imr_change_pending = false; |
511 | } else |
512 | sih = NULL; |
513 | spin_unlock_irq(&sih_agent_lock); |
514 | if (!sih) |
515 | return; |
516 | |
517 | /* write the whole mask ... simpler than subsetting it */ |
518 | status = twl_i2c_write(sih->module, imr.bytes, |
519 | sih->mask[irq_line].imr_offset, sih->bytes_ixr); |
520 | if (status) |
521 | pr_err("twl4030: %s, %s --> %d\n", __func__, |
522 | "write", status); |
523 | } |
524 | |
525 | static void twl4030_sih_do_edge(struct work_struct *work) |
526 | { |
527 | struct sih_agent *agent; |
528 | const struct sih *sih; |
529 | u8 bytes[6]; |
530 | u32 edge_change; |
531 | int status; |
532 | |
533 | agent = container_of(work, struct sih_agent, edge_work); |
534 | |
535 | /* see what work we have */ |
536 | spin_lock_irq(&sih_agent_lock); |
537 | edge_change = agent->edge_change; |
538 | agent->edge_change = 0; |
539 | sih = edge_change ? agent->sih : NULL; |
540 | spin_unlock_irq(&sih_agent_lock); |
541 | if (!sih) |
542 | return; |
543 | |
544 | /* Read, reserving first byte for write scratch. Yes, this |
545 | * could be cached for some speedup ... but be careful about |
546 | * any processor on the other IRQ line, EDR registers are |
547 | * shared. |
548 | */ |
549 | status = twl_i2c_read(sih->module, bytes + 1, |
550 | sih->edr_offset, sih->bytes_edr); |
551 | if (status) { |
552 | pr_err("twl4030: %s, %s --> %d\n", __func__, |
553 | "read", status); |
554 | return; |
555 | } |
556 | |
557 | /* Modify only the bits we know must change */ |
558 | while (edge_change) { |
559 | int i = fls(edge_change) - 1; |
560 | struct irq_desc *d = irq_to_desc(i + agent->irq_base); |
561 | int byte = 1 + (i >> 2); |
562 | int off = (i & 0x3) * 2; |
563 | |
564 | if (!d) { |
565 | pr_err("twl4030: Invalid IRQ: %d\n", |
566 | i + agent->irq_base); |
567 | return; |
568 | } |
569 | |
570 | bytes[byte] &= ~(0x03 << off); |
571 | |
572 | raw_spin_lock_irq(&d->lock); |
573 | if (d->status & IRQ_TYPE_EDGE_RISING) |
574 | bytes[byte] |= BIT(off + 1); |
575 | if (d->status & IRQ_TYPE_EDGE_FALLING) |
576 | bytes[byte] |= BIT(off + 0); |
577 | raw_spin_unlock_irq(&d->lock); |
578 | |
579 | edge_change &= ~BIT(i); |
580 | } |
581 | |
582 | /* Write */ |
583 | status = twl_i2c_write(sih->module, bytes, |
584 | sih->edr_offset, sih->bytes_edr); |
585 | if (status) |
586 | pr_err("twl4030: %s, %s --> %d\n", __func__, |
587 | "write", status); |
588 | } |
589 | |
590 | /*----------------------------------------------------------------------*/ |
591 | |
592 | /* |
593 | * All irq_chip methods get issued from code holding irq_desc[irq].lock, |
594 | * which can't perform the underlying I2C operations (because they sleep). |
595 | * So we must hand them off to a thread (workqueue) and cope with asynch |
596 | * completion, potentially including some re-ordering, of these requests. |
597 | */ |
598 | |
599 | static void twl4030_sih_mask(unsigned irq) |
600 | { |
601 | struct sih_agent *sih = get_irq_chip_data(irq); |
602 | unsigned long flags; |
603 | |
604 | spin_lock_irqsave(&sih_agent_lock, flags); |
605 | sih->imr |= BIT(irq - sih->irq_base); |
606 | sih->imr_change_pending = true; |
607 | queue_work(wq, &sih->mask_work); |
608 | spin_unlock_irqrestore(&sih_agent_lock, flags); |
609 | } |
610 | |
611 | static void twl4030_sih_unmask(unsigned irq) |
612 | { |
613 | struct sih_agent *sih = get_irq_chip_data(irq); |
614 | unsigned long flags; |
615 | |
616 | spin_lock_irqsave(&sih_agent_lock, flags); |
617 | sih->imr &= ~BIT(irq - sih->irq_base); |
618 | sih->imr_change_pending = true; |
619 | queue_work(wq, &sih->mask_work); |
620 | spin_unlock_irqrestore(&sih_agent_lock, flags); |
621 | } |
622 | |
623 | static int twl4030_sih_set_type(unsigned irq, unsigned trigger) |
624 | { |
625 | struct sih_agent *sih = get_irq_chip_data(irq); |
626 | struct irq_desc *desc = irq_to_desc(irq); |
627 | unsigned long flags; |
628 | |
629 | if (!desc) { |
630 | pr_err("twl4030: Invalid IRQ: %d\n", irq); |
631 | return -EINVAL; |
632 | } |
633 | |
634 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
635 | return -EINVAL; |
636 | |
637 | spin_lock_irqsave(&sih_agent_lock, flags); |
638 | if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) { |
639 | desc->status &= ~IRQ_TYPE_SENSE_MASK; |
640 | desc->status |= trigger; |
641 | sih->edge_change |= BIT(irq - sih->irq_base); |
642 | queue_work(wq, &sih->edge_work); |
643 | } |
644 | spin_unlock_irqrestore(&sih_agent_lock, flags); |
645 | return 0; |
646 | } |
647 | |
648 | static struct irq_chip twl4030_sih_irq_chip = { |
649 | .name = "twl4030", |
650 | .mask = twl4030_sih_mask, |
651 | .unmask = twl4030_sih_unmask, |
652 | .set_type = twl4030_sih_set_type, |
653 | }; |
654 | |
655 | /*----------------------------------------------------------------------*/ |
656 | |
657 | static inline int sih_read_isr(const struct sih *sih) |
658 | { |
659 | int status; |
660 | union { |
661 | u8 bytes[4]; |
662 | u32 word; |
663 | } isr; |
664 | |
665 | /* FIXME need retry-on-error ... */ |
666 | |
667 | isr.word = 0; |
668 | status = twl_i2c_read(sih->module, isr.bytes, |
669 | sih->mask[irq_line].isr_offset, sih->bytes_ixr); |
670 | |
671 | return (status < 0) ? status : le32_to_cpu(isr.word); |
672 | } |
673 | |
674 | /* |
675 | * Generic handler for SIH interrupts ... we "know" this is called |
676 | * in task context, with IRQs enabled. |
677 | */ |
678 | static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) |
679 | { |
680 | struct sih_agent *agent = get_irq_data(irq); |
681 | const struct sih *sih = agent->sih; |
682 | int isr; |
683 | |
684 | /* reading ISR acks the IRQs, using clear-on-read mode */ |
685 | local_irq_enable(); |
686 | isr = sih_read_isr(sih); |
687 | local_irq_disable(); |
688 | |
689 | if (isr < 0) { |
690 | pr_err("twl4030: %s SIH, read ISR error %d\n", |
691 | sih->name, isr); |
692 | /* REVISIT: recover; eventually mask it all, etc */ |
693 | return; |
694 | } |
695 | |
696 | while (isr) { |
697 | irq = fls(isr); |
698 | irq--; |
699 | isr &= ~BIT(irq); |
700 | |
701 | if (irq < sih->bits) |
702 | generic_handle_irq(agent->irq_base + irq); |
703 | else |
704 | pr_err("twl4030: %s SIH, invalid ISR bit %d\n", |
705 | sih->name, irq); |
706 | } |
707 | } |
708 | |
709 | static unsigned twl4030_irq_next; |
710 | |
711 | /* returns the first IRQ used by this SIH bank, |
712 | * or negative errno |
713 | */ |
714 | int twl4030_sih_setup(int module) |
715 | { |
716 | int sih_mod; |
717 | const struct sih *sih = NULL; |
718 | struct sih_agent *agent; |
719 | int i, irq; |
720 | int status = -EINVAL; |
721 | unsigned irq_base = twl4030_irq_next; |
722 | |
723 | /* only support modules with standard clear-on-read for now */ |
724 | for (sih_mod = 0, sih = sih_modules; |
725 | sih_mod < nr_sih_modules; |
726 | sih_mod++, sih++) { |
727 | if (sih->module == module && sih->set_cor) { |
728 | if (!WARN((irq_base + sih->bits) > NR_IRQS, |
729 | "irq %d for %s too big\n", |
730 | irq_base + sih->bits, |
731 | sih->name)) |
732 | status = 0; |
733 | break; |
734 | } |
735 | } |
736 | if (status < 0) |
737 | return status; |
738 | |
739 | agent = kzalloc(sizeof *agent, GFP_KERNEL); |
740 | if (!agent) |
741 | return -ENOMEM; |
742 | |
743 | status = 0; |
744 | |
745 | agent->irq_base = irq_base; |
746 | agent->sih = sih; |
747 | agent->imr = ~0; |
748 | INIT_WORK(&agent->mask_work, twl4030_sih_do_mask); |
749 | INIT_WORK(&agent->edge_work, twl4030_sih_do_edge); |
750 | |
751 | for (i = 0; i < sih->bits; i++) { |
752 | irq = irq_base + i; |
753 | |
754 | set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip, |
755 | handle_edge_irq); |
756 | set_irq_chip_data(irq, agent); |
757 | activate_irq(irq); |
758 | } |
759 | |
760 | status = irq_base; |
761 | twl4030_irq_next += i; |
762 | |
763 | /* replace generic PIH handler (handle_simple_irq) */ |
764 | irq = sih_mod + twl4030_irq_base; |
765 | set_irq_data(irq, agent); |
766 | set_irq_chained_handler(irq, handle_twl4030_sih); |
767 | |
768 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, |
769 | irq, irq_base, twl4030_irq_next - 1); |
770 | |
771 | return status; |
772 | } |
773 | |
774 | /* FIXME need a call to reverse twl4030_sih_setup() ... */ |
775 | |
776 | |
777 | /*----------------------------------------------------------------------*/ |
778 | |
779 | /* FIXME pass in which interrupt line we'll use ... */ |
780 | #define twl_irq_line 0 |
781 | |
782 | int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) |
783 | { |
784 | static struct irq_chip twl4030_irq_chip; |
785 | |
786 | int status; |
787 | int i; |
788 | struct task_struct *task; |
789 | |
790 | /* |
791 | * Mask and clear all TWL4030 interrupts since initially we do |
792 | * not have any TWL4030 module interrupt handlers present |
793 | */ |
794 | status = twl4030_init_sih_modules(twl_irq_line); |
795 | if (status < 0) |
796 | return status; |
797 | |
798 | wq = create_singlethread_workqueue("twl4030-irqchip"); |
799 | if (!wq) { |
800 | pr_err("twl4030: workqueue FAIL\n"); |
801 | return -ESRCH; |
802 | } |
803 | |
804 | twl4030_irq_base = irq_base; |
805 | |
806 | /* install an irq handler for each of the SIH modules; |
807 | * clone dummy irq_chip since PIH can't *do* anything |
808 | */ |
809 | twl4030_irq_chip = dummy_irq_chip; |
810 | twl4030_irq_chip.name = "twl4030"; |
811 | |
812 | twl4030_sih_irq_chip.ack = dummy_irq_chip.ack; |
813 | |
814 | for (i = irq_base; i < irq_end; i++) { |
815 | set_irq_chip_and_handler(i, &twl4030_irq_chip, |
816 | handle_simple_irq); |
817 | activate_irq(i); |
818 | } |
819 | twl4030_irq_next = i; |
820 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", |
821 | irq_num, irq_base, twl4030_irq_next - 1); |
822 | |
823 | /* ... and the PWR_INT module ... */ |
824 | status = twl4030_sih_setup(TWL4030_MODULE_INT); |
825 | if (status < 0) { |
826 | pr_err("twl4030: sih_setup PWR INT --> %d\n", status); |
827 | goto fail; |
828 | } |
829 | |
830 | /* install an irq handler to demultiplex the TWL4030 interrupt */ |
831 | |
832 | |
833 | init_completion(&irq_event); |
834 | |
835 | status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED, |
836 | "TWL4030-PIH", &irq_event); |
837 | if (status < 0) { |
838 | pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); |
839 | goto fail_rqirq; |
840 | } |
841 | |
842 | task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num, |
843 | "twl4030-irq"); |
844 | if (IS_ERR(task)) { |
845 | pr_err("twl4030: could not create irq %d thread!\n", irq_num); |
846 | status = PTR_ERR(task); |
847 | goto fail_kthread; |
848 | } |
849 | return status; |
850 | fail_kthread: |
851 | free_irq(irq_num, &irq_event); |
852 | fail_rqirq: |
853 | /* clean up twl4030_sih_setup */ |
854 | fail: |
855 | for (i = irq_base; i < irq_end; i++) |
856 | set_irq_chip_and_handler(i, NULL, NULL); |
857 | destroy_workqueue(wq); |
858 | wq = NULL; |
859 | return status; |
860 | } |
861 | |
862 | int twl4030_exit_irq(void) |
863 | { |
864 | /* FIXME undo twl_init_irq() */ |
865 | if (twl4030_irq_base) { |
866 | pr_err("twl4030: can't yet clean up IRQs?\n"); |
867 | return -ENOSYS; |
868 | } |
869 | return 0; |
870 | } |
871 | |
872 | int twl4030_init_chip_irq(const char *chip) |
873 | { |
874 | if (!strcmp(chip, "twl5031")) { |
875 | sih_modules = sih_modules_twl5031; |
876 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); |
877 | } else { |
878 | sih_modules = sih_modules_twl4030; |
879 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); |
880 | } |
881 | |
882 | return 0; |
883 | } |
884 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9