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1 | /* |
2 | * Network device driver for the BMAC ethernet controller on |
3 | * Apple Powermacs. Assumes it's under a DBDMA controller. |
4 | * |
5 | * Copyright (C) 1998 Randy Gobbel. |
6 | * |
7 | * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to |
8 | * dynamic procfs inode. |
9 | */ |
10 | #include <linux/module.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/netdevice.h> |
13 | #include <linux/etherdevice.h> |
14 | #include <linux/delay.h> |
15 | #include <linux/string.h> |
16 | #include <linux/timer.h> |
17 | #include <linux/proc_fs.h> |
18 | #include <linux/init.h> |
19 | #include <linux/spinlock.h> |
20 | #include <linux/crc32.h> |
21 | #include <linux/bitrev.h> |
22 | #include <linux/ethtool.h> |
23 | #include <linux/slab.h> |
24 | #include <asm/prom.h> |
25 | #include <asm/dbdma.h> |
26 | #include <asm/io.h> |
27 | #include <asm/page.h> |
28 | #include <asm/pgtable.h> |
29 | #include <asm/machdep.h> |
30 | #include <asm/pmac_feature.h> |
31 | #include <asm/macio.h> |
32 | #include <asm/irq.h> |
33 | |
34 | #include "bmac.h" |
35 | |
36 | #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1)))) |
37 | #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1))) |
38 | |
39 | /* |
40 | * CRC polynomial - used in working out multicast filter bits. |
41 | */ |
42 | #define ENET_CRCPOLY 0x04c11db7 |
43 | |
44 | /* switch to use multicast code lifted from sunhme driver */ |
45 | #define SUNHME_MULTICAST |
46 | |
47 | #define N_RX_RING 64 |
48 | #define N_TX_RING 32 |
49 | #define MAX_TX_ACTIVE 1 |
50 | #define ETHERCRC 4 |
51 | #define ETHERMINPACKET 64 |
52 | #define ETHERMTU 1500 |
53 | #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2) |
54 | #define TX_TIMEOUT HZ /* 1 second */ |
55 | |
56 | /* Bits in transmit DMA status */ |
57 | #define TX_DMA_ERR 0x80 |
58 | |
59 | #define XXDEBUG(args) |
60 | |
61 | struct bmac_data { |
62 | /* volatile struct bmac *bmac; */ |
63 | struct sk_buff_head *queue; |
64 | volatile struct dbdma_regs __iomem *tx_dma; |
65 | int tx_dma_intr; |
66 | volatile struct dbdma_regs __iomem *rx_dma; |
67 | int rx_dma_intr; |
68 | volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */ |
69 | volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */ |
70 | struct macio_dev *mdev; |
71 | int is_bmac_plus; |
72 | struct sk_buff *rx_bufs[N_RX_RING]; |
73 | int rx_fill; |
74 | int rx_empty; |
75 | struct sk_buff *tx_bufs[N_TX_RING]; |
76 | int tx_fill; |
77 | int tx_empty; |
78 | unsigned char tx_fullup; |
79 | struct timer_list tx_timeout; |
80 | int timeout_active; |
81 | int sleeping; |
82 | int opened; |
83 | unsigned short hash_use_count[64]; |
84 | unsigned short hash_table_mask[4]; |
85 | spinlock_t lock; |
86 | }; |
87 | |
88 | #if 0 /* Move that to ethtool */ |
89 | |
90 | typedef struct bmac_reg_entry { |
91 | char *name; |
92 | unsigned short reg_offset; |
93 | } bmac_reg_entry_t; |
94 | |
95 | #define N_REG_ENTRIES 31 |
96 | |
97 | static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = { |
98 | {"MEMADD", MEMADD}, |
99 | {"MEMDATAHI", MEMDATAHI}, |
100 | {"MEMDATALO", MEMDATALO}, |
101 | {"TXPNTR", TXPNTR}, |
102 | {"RXPNTR", RXPNTR}, |
103 | {"IPG1", IPG1}, |
104 | {"IPG2", IPG2}, |
105 | {"ALIMIT", ALIMIT}, |
106 | {"SLOT", SLOT}, |
107 | {"PALEN", PALEN}, |
108 | {"PAPAT", PAPAT}, |
109 | {"TXSFD", TXSFD}, |
110 | {"JAM", JAM}, |
111 | {"TXCFG", TXCFG}, |
112 | {"TXMAX", TXMAX}, |
113 | {"TXMIN", TXMIN}, |
114 | {"PAREG", PAREG}, |
115 | {"DCNT", DCNT}, |
116 | {"NCCNT", NCCNT}, |
117 | {"NTCNT", NTCNT}, |
118 | {"EXCNT", EXCNT}, |
119 | {"LTCNT", LTCNT}, |
120 | {"TXSM", TXSM}, |
121 | {"RXCFG", RXCFG}, |
122 | {"RXMAX", RXMAX}, |
123 | {"RXMIN", RXMIN}, |
124 | {"FRCNT", FRCNT}, |
125 | {"AECNT", AECNT}, |
126 | {"FECNT", FECNT}, |
127 | {"RXSM", RXSM}, |
128 | {"RXCV", RXCV} |
129 | }; |
130 | |
131 | #endif |
132 | |
133 | static unsigned char *bmac_emergency_rxbuf; |
134 | |
135 | /* |
136 | * Number of bytes of private data per BMAC: allow enough for |
137 | * the rx and tx dma commands plus a branch dma command each, |
138 | * and another 16 bytes to allow us to align the dma command |
139 | * buffers on a 16 byte boundary. |
140 | */ |
141 | #define PRIV_BYTES (sizeof(struct bmac_data) \ |
142 | + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \ |
143 | + sizeof(struct sk_buff_head)) |
144 | |
145 | static int bmac_open(struct net_device *dev); |
146 | static int bmac_close(struct net_device *dev); |
147 | static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev); |
148 | static void bmac_set_multicast(struct net_device *dev); |
149 | static void bmac_reset_and_enable(struct net_device *dev); |
150 | static void bmac_start_chip(struct net_device *dev); |
151 | static void bmac_init_chip(struct net_device *dev); |
152 | static void bmac_init_registers(struct net_device *dev); |
153 | static void bmac_enable_and_reset_chip(struct net_device *dev); |
154 | static int bmac_set_address(struct net_device *dev, void *addr); |
155 | static irqreturn_t bmac_misc_intr(int irq, void *dev_id); |
156 | static irqreturn_t bmac_txdma_intr(int irq, void *dev_id); |
157 | static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id); |
158 | static void bmac_set_timeout(struct net_device *dev); |
159 | static void bmac_tx_timeout(unsigned long data); |
160 | static int bmac_output(struct sk_buff *skb, struct net_device *dev); |
161 | static void bmac_start(struct net_device *dev); |
162 | |
163 | #define DBDMA_SET(x) ( ((x) | (x) << 16) ) |
164 | #define DBDMA_CLEAR(x) ( (x) << 16) |
165 | |
166 | static inline void |
167 | dbdma_st32(volatile __u32 __iomem *a, unsigned long x) |
168 | { |
169 | __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); |
170 | return; |
171 | } |
172 | |
173 | static inline unsigned long |
174 | dbdma_ld32(volatile __u32 __iomem *a) |
175 | { |
176 | __u32 swap; |
177 | __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a)); |
178 | return swap; |
179 | } |
180 | |
181 | static void |
182 | dbdma_continue(volatile struct dbdma_regs __iomem *dmap) |
183 | { |
184 | dbdma_st32(&dmap->control, |
185 | DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD)); |
186 | eieio(); |
187 | } |
188 | |
189 | static void |
190 | dbdma_reset(volatile struct dbdma_regs __iomem *dmap) |
191 | { |
192 | dbdma_st32(&dmap->control, |
193 | DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)); |
194 | eieio(); |
195 | while (dbdma_ld32(&dmap->status) & RUN) |
196 | eieio(); |
197 | } |
198 | |
199 | static void |
200 | dbdma_setcmd(volatile struct dbdma_cmd *cp, |
201 | unsigned short cmd, unsigned count, unsigned long addr, |
202 | unsigned long cmd_dep) |
203 | { |
204 | out_le16(&cp->command, cmd); |
205 | out_le16(&cp->req_count, count); |
206 | out_le32(&cp->phy_addr, addr); |
207 | out_le32(&cp->cmd_dep, cmd_dep); |
208 | out_le16(&cp->xfer_status, 0); |
209 | out_le16(&cp->res_count, 0); |
210 | } |
211 | |
212 | static inline |
213 | void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data ) |
214 | { |
215 | out_le16((void __iomem *)dev->base_addr + reg_offset, data); |
216 | } |
217 | |
218 | |
219 | static inline |
220 | unsigned short bmread(struct net_device *dev, unsigned long reg_offset ) |
221 | { |
222 | return in_le16((void __iomem *)dev->base_addr + reg_offset); |
223 | } |
224 | |
225 | static void |
226 | bmac_enable_and_reset_chip(struct net_device *dev) |
227 | { |
228 | struct bmac_data *bp = netdev_priv(dev); |
229 | volatile struct dbdma_regs __iomem *rd = bp->rx_dma; |
230 | volatile struct dbdma_regs __iomem *td = bp->tx_dma; |
231 | |
232 | if (rd) |
233 | dbdma_reset(rd); |
234 | if (td) |
235 | dbdma_reset(td); |
236 | |
237 | pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1); |
238 | } |
239 | |
240 | #define MIFDELAY udelay(10) |
241 | |
242 | static unsigned int |
243 | bmac_mif_readbits(struct net_device *dev, int nb) |
244 | { |
245 | unsigned int val = 0; |
246 | |
247 | while (--nb >= 0) { |
248 | bmwrite(dev, MIFCSR, 0); |
249 | MIFDELAY; |
250 | if (bmread(dev, MIFCSR) & 8) |
251 | val |= 1 << nb; |
252 | bmwrite(dev, MIFCSR, 1); |
253 | MIFDELAY; |
254 | } |
255 | bmwrite(dev, MIFCSR, 0); |
256 | MIFDELAY; |
257 | bmwrite(dev, MIFCSR, 1); |
258 | MIFDELAY; |
259 | return val; |
260 | } |
261 | |
262 | static void |
263 | bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb) |
264 | { |
265 | int b; |
266 | |
267 | while (--nb >= 0) { |
268 | b = (val & (1 << nb))? 6: 4; |
269 | bmwrite(dev, MIFCSR, b); |
270 | MIFDELAY; |
271 | bmwrite(dev, MIFCSR, b|1); |
272 | MIFDELAY; |
273 | } |
274 | } |
275 | |
276 | static unsigned int |
277 | bmac_mif_read(struct net_device *dev, unsigned int addr) |
278 | { |
279 | unsigned int val; |
280 | |
281 | bmwrite(dev, MIFCSR, 4); |
282 | MIFDELAY; |
283 | bmac_mif_writebits(dev, ~0U, 32); |
284 | bmac_mif_writebits(dev, 6, 4); |
285 | bmac_mif_writebits(dev, addr, 10); |
286 | bmwrite(dev, MIFCSR, 2); |
287 | MIFDELAY; |
288 | bmwrite(dev, MIFCSR, 1); |
289 | MIFDELAY; |
290 | val = bmac_mif_readbits(dev, 17); |
291 | bmwrite(dev, MIFCSR, 4); |
292 | MIFDELAY; |
293 | return val; |
294 | } |
295 | |
296 | static void |
297 | bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val) |
298 | { |
299 | bmwrite(dev, MIFCSR, 4); |
300 | MIFDELAY; |
301 | bmac_mif_writebits(dev, ~0U, 32); |
302 | bmac_mif_writebits(dev, 5, 4); |
303 | bmac_mif_writebits(dev, addr, 10); |
304 | bmac_mif_writebits(dev, 2, 2); |
305 | bmac_mif_writebits(dev, val, 16); |
306 | bmac_mif_writebits(dev, 3, 2); |
307 | } |
308 | |
309 | static void |
310 | bmac_init_registers(struct net_device *dev) |
311 | { |
312 | struct bmac_data *bp = netdev_priv(dev); |
313 | volatile unsigned short regValue; |
314 | unsigned short *pWord16; |
315 | int i; |
316 | |
317 | /* XXDEBUG(("bmac: enter init_registers\n")); */ |
318 | |
319 | bmwrite(dev, RXRST, RxResetValue); |
320 | bmwrite(dev, TXRST, TxResetBit); |
321 | |
322 | i = 100; |
323 | do { |
324 | --i; |
325 | udelay(10000); |
326 | regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */ |
327 | } while ((regValue & TxResetBit) && i > 0); |
328 | |
329 | if (!bp->is_bmac_plus) { |
330 | regValue = bmread(dev, XCVRIF); |
331 | regValue |= ClkBit | SerialMode | COLActiveLow; |
332 | bmwrite(dev, XCVRIF, regValue); |
333 | udelay(10000); |
334 | } |
335 | |
336 | bmwrite(dev, RSEED, (unsigned short)0x1968); |
337 | |
338 | regValue = bmread(dev, XIFC); |
339 | regValue |= TxOutputEnable; |
340 | bmwrite(dev, XIFC, regValue); |
341 | |
342 | bmread(dev, PAREG); |
343 | |
344 | /* set collision counters to 0 */ |
345 | bmwrite(dev, NCCNT, 0); |
346 | bmwrite(dev, NTCNT, 0); |
347 | bmwrite(dev, EXCNT, 0); |
348 | bmwrite(dev, LTCNT, 0); |
349 | |
350 | /* set rx counters to 0 */ |
351 | bmwrite(dev, FRCNT, 0); |
352 | bmwrite(dev, LECNT, 0); |
353 | bmwrite(dev, AECNT, 0); |
354 | bmwrite(dev, FECNT, 0); |
355 | bmwrite(dev, RXCV, 0); |
356 | |
357 | /* set tx fifo information */ |
358 | bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */ |
359 | |
360 | bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */ |
361 | bmwrite(dev, TXFIFOCSR, TxFIFOEnable ); |
362 | |
363 | /* set rx fifo information */ |
364 | bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */ |
365 | bmwrite(dev, RXFIFOCSR, RxFIFOEnable ); |
366 | |
367 | //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */ |
368 | bmread(dev, STATUS); /* read it just to clear it */ |
369 | |
370 | /* zero out the chip Hash Filter registers */ |
371 | for (i=0; i<4; i++) bp->hash_table_mask[i] = 0; |
372 | bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */ |
373 | bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */ |
374 | bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */ |
375 | bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */ |
376 | |
377 | pWord16 = (unsigned short *)dev->dev_addr; |
378 | bmwrite(dev, MADD0, *pWord16++); |
379 | bmwrite(dev, MADD1, *pWord16++); |
380 | bmwrite(dev, MADD2, *pWord16); |
381 | |
382 | bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets); |
383 | |
384 | bmwrite(dev, INTDISABLE, EnableNormal); |
385 | |
386 | return; |
387 | } |
388 | |
389 | #if 0 |
390 | static void |
391 | bmac_disable_interrupts(struct net_device *dev) |
392 | { |
393 | bmwrite(dev, INTDISABLE, DisableAll); |
394 | } |
395 | |
396 | static void |
397 | bmac_enable_interrupts(struct net_device *dev) |
398 | { |
399 | bmwrite(dev, INTDISABLE, EnableNormal); |
400 | } |
401 | #endif |
402 | |
403 | |
404 | static void |
405 | bmac_start_chip(struct net_device *dev) |
406 | { |
407 | struct bmac_data *bp = netdev_priv(dev); |
408 | volatile struct dbdma_regs __iomem *rd = bp->rx_dma; |
409 | unsigned short oldConfig; |
410 | |
411 | /* enable rx dma channel */ |
412 | dbdma_continue(rd); |
413 | |
414 | oldConfig = bmread(dev, TXCFG); |
415 | bmwrite(dev, TXCFG, oldConfig | TxMACEnable ); |
416 | |
417 | /* turn on rx plus any other bits already on (promiscuous possibly) */ |
418 | oldConfig = bmread(dev, RXCFG); |
419 | bmwrite(dev, RXCFG, oldConfig | RxMACEnable ); |
420 | udelay(20000); |
421 | } |
422 | |
423 | static void |
424 | bmac_init_phy(struct net_device *dev) |
425 | { |
426 | unsigned int addr; |
427 | struct bmac_data *bp = netdev_priv(dev); |
428 | |
429 | printk(KERN_DEBUG "phy registers:"); |
430 | for (addr = 0; addr < 32; ++addr) { |
431 | if ((addr & 7) == 0) |
432 | printk(KERN_DEBUG); |
433 | printk(KERN_CONT " %.4x", bmac_mif_read(dev, addr)); |
434 | } |
435 | printk(KERN_CONT "\n"); |
436 | |
437 | if (bp->is_bmac_plus) { |
438 | unsigned int capable, ctrl; |
439 | |
440 | ctrl = bmac_mif_read(dev, 0); |
441 | capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1; |
442 | if (bmac_mif_read(dev, 4) != capable || |
443 | (ctrl & 0x1000) == 0) { |
444 | bmac_mif_write(dev, 4, capable); |
445 | bmac_mif_write(dev, 0, 0x1200); |
446 | } else |
447 | bmac_mif_write(dev, 0, 0x1000); |
448 | } |
449 | } |
450 | |
451 | static void bmac_init_chip(struct net_device *dev) |
452 | { |
453 | bmac_init_phy(dev); |
454 | bmac_init_registers(dev); |
455 | } |
456 | |
457 | #ifdef CONFIG_PM |
458 | static int bmac_suspend(struct macio_dev *mdev, pm_message_t state) |
459 | { |
460 | struct net_device* dev = macio_get_drvdata(mdev); |
461 | struct bmac_data *bp = netdev_priv(dev); |
462 | unsigned long flags; |
463 | unsigned short config; |
464 | int i; |
465 | |
466 | netif_device_detach(dev); |
467 | /* prolly should wait for dma to finish & turn off the chip */ |
468 | spin_lock_irqsave(&bp->lock, flags); |
469 | if (bp->timeout_active) { |
470 | del_timer(&bp->tx_timeout); |
471 | bp->timeout_active = 0; |
472 | } |
473 | disable_irq(dev->irq); |
474 | disable_irq(bp->tx_dma_intr); |
475 | disable_irq(bp->rx_dma_intr); |
476 | bp->sleeping = 1; |
477 | spin_unlock_irqrestore(&bp->lock, flags); |
478 | if (bp->opened) { |
479 | volatile struct dbdma_regs __iomem *rd = bp->rx_dma; |
480 | volatile struct dbdma_regs __iomem *td = bp->tx_dma; |
481 | |
482 | config = bmread(dev, RXCFG); |
483 | bmwrite(dev, RXCFG, (config & ~RxMACEnable)); |
484 | config = bmread(dev, TXCFG); |
485 | bmwrite(dev, TXCFG, (config & ~TxMACEnable)); |
486 | bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */ |
487 | /* disable rx and tx dma */ |
488 | st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ |
489 | st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ |
490 | /* free some skb's */ |
491 | for (i=0; i<N_RX_RING; i++) { |
492 | if (bp->rx_bufs[i] != NULL) { |
493 | dev_kfree_skb(bp->rx_bufs[i]); |
494 | bp->rx_bufs[i] = NULL; |
495 | } |
496 | } |
497 | for (i = 0; i<N_TX_RING; i++) { |
498 | if (bp->tx_bufs[i] != NULL) { |
499 | dev_kfree_skb(bp->tx_bufs[i]); |
500 | bp->tx_bufs[i] = NULL; |
501 | } |
502 | } |
503 | } |
504 | pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); |
505 | return 0; |
506 | } |
507 | |
508 | static int bmac_resume(struct macio_dev *mdev) |
509 | { |
510 | struct net_device* dev = macio_get_drvdata(mdev); |
511 | struct bmac_data *bp = netdev_priv(dev); |
512 | |
513 | /* see if this is enough */ |
514 | if (bp->opened) |
515 | bmac_reset_and_enable(dev); |
516 | |
517 | enable_irq(dev->irq); |
518 | enable_irq(bp->tx_dma_intr); |
519 | enable_irq(bp->rx_dma_intr); |
520 | netif_device_attach(dev); |
521 | |
522 | return 0; |
523 | } |
524 | #endif /* CONFIG_PM */ |
525 | |
526 | static int bmac_set_address(struct net_device *dev, void *addr) |
527 | { |
528 | struct bmac_data *bp = netdev_priv(dev); |
529 | unsigned char *p = addr; |
530 | unsigned short *pWord16; |
531 | unsigned long flags; |
532 | int i; |
533 | |
534 | XXDEBUG(("bmac: enter set_address\n")); |
535 | spin_lock_irqsave(&bp->lock, flags); |
536 | |
537 | for (i = 0; i < 6; ++i) { |
538 | dev->dev_addr[i] = p[i]; |
539 | } |
540 | /* load up the hardware address */ |
541 | pWord16 = (unsigned short *)dev->dev_addr; |
542 | bmwrite(dev, MADD0, *pWord16++); |
543 | bmwrite(dev, MADD1, *pWord16++); |
544 | bmwrite(dev, MADD2, *pWord16); |
545 | |
546 | spin_unlock_irqrestore(&bp->lock, flags); |
547 | XXDEBUG(("bmac: exit set_address\n")); |
548 | return 0; |
549 | } |
550 | |
551 | static inline void bmac_set_timeout(struct net_device *dev) |
552 | { |
553 | struct bmac_data *bp = netdev_priv(dev); |
554 | unsigned long flags; |
555 | |
556 | spin_lock_irqsave(&bp->lock, flags); |
557 | if (bp->timeout_active) |
558 | del_timer(&bp->tx_timeout); |
559 | bp->tx_timeout.expires = jiffies + TX_TIMEOUT; |
560 | bp->tx_timeout.function = bmac_tx_timeout; |
561 | bp->tx_timeout.data = (unsigned long) dev; |
562 | add_timer(&bp->tx_timeout); |
563 | bp->timeout_active = 1; |
564 | spin_unlock_irqrestore(&bp->lock, flags); |
565 | } |
566 | |
567 | static void |
568 | bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp) |
569 | { |
570 | void *vaddr; |
571 | unsigned long baddr; |
572 | unsigned long len; |
573 | |
574 | len = skb->len; |
575 | vaddr = skb->data; |
576 | baddr = virt_to_bus(vaddr); |
577 | |
578 | dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0); |
579 | } |
580 | |
581 | static void |
582 | bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp) |
583 | { |
584 | unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf; |
585 | |
586 | dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN, |
587 | virt_to_bus(addr), 0); |
588 | } |
589 | |
590 | static void |
591 | bmac_init_tx_ring(struct bmac_data *bp) |
592 | { |
593 | volatile struct dbdma_regs __iomem *td = bp->tx_dma; |
594 | |
595 | memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd)); |
596 | |
597 | bp->tx_empty = 0; |
598 | bp->tx_fill = 0; |
599 | bp->tx_fullup = 0; |
600 | |
601 | /* put a branch at the end of the tx command list */ |
602 | dbdma_setcmd(&bp->tx_cmds[N_TX_RING], |
603 | (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds)); |
604 | |
605 | /* reset tx dma */ |
606 | dbdma_reset(td); |
607 | out_le32(&td->wait_sel, 0x00200020); |
608 | out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds)); |
609 | } |
610 | |
611 | static int |
612 | bmac_init_rx_ring(struct bmac_data *bp) |
613 | { |
614 | volatile struct dbdma_regs __iomem *rd = bp->rx_dma; |
615 | int i; |
616 | struct sk_buff *skb; |
617 | |
618 | /* initialize list of sk_buffs for receiving and set up recv dma */ |
619 | memset((char *)bp->rx_cmds, 0, |
620 | (N_RX_RING + 1) * sizeof(struct dbdma_cmd)); |
621 | for (i = 0; i < N_RX_RING; i++) { |
622 | if ((skb = bp->rx_bufs[i]) == NULL) { |
623 | bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2); |
624 | if (skb != NULL) |
625 | skb_reserve(skb, 2); |
626 | } |
627 | bmac_construct_rxbuff(skb, &bp->rx_cmds[i]); |
628 | } |
629 | |
630 | bp->rx_empty = 0; |
631 | bp->rx_fill = i; |
632 | |
633 | /* Put a branch back to the beginning of the receive command list */ |
634 | dbdma_setcmd(&bp->rx_cmds[N_RX_RING], |
635 | (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds)); |
636 | |
637 | /* start rx dma */ |
638 | dbdma_reset(rd); |
639 | out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds)); |
640 | |
641 | return 1; |
642 | } |
643 | |
644 | |
645 | static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev) |
646 | { |
647 | struct bmac_data *bp = netdev_priv(dev); |
648 | volatile struct dbdma_regs __iomem *td = bp->tx_dma; |
649 | int i; |
650 | |
651 | /* see if there's a free slot in the tx ring */ |
652 | /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */ |
653 | /* bp->tx_empty, bp->tx_fill)); */ |
654 | i = bp->tx_fill + 1; |
655 | if (i >= N_TX_RING) |
656 | i = 0; |
657 | if (i == bp->tx_empty) { |
658 | netif_stop_queue(dev); |
659 | bp->tx_fullup = 1; |
660 | XXDEBUG(("bmac_transmit_packet: tx ring full\n")); |
661 | return -1; /* can't take it at the moment */ |
662 | } |
663 | |
664 | dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0); |
665 | |
666 | bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]); |
667 | |
668 | bp->tx_bufs[bp->tx_fill] = skb; |
669 | bp->tx_fill = i; |
670 | |
671 | dev->stats.tx_bytes += skb->len; |
672 | |
673 | dbdma_continue(td); |
674 | |
675 | return 0; |
676 | } |
677 | |
678 | static int rxintcount; |
679 | |
680 | static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id) |
681 | { |
682 | struct net_device *dev = (struct net_device *) dev_id; |
683 | struct bmac_data *bp = netdev_priv(dev); |
684 | volatile struct dbdma_regs __iomem *rd = bp->rx_dma; |
685 | volatile struct dbdma_cmd *cp; |
686 | int i, nb, stat; |
687 | struct sk_buff *skb; |
688 | unsigned int residual; |
689 | int last; |
690 | unsigned long flags; |
691 | |
692 | spin_lock_irqsave(&bp->lock, flags); |
693 | |
694 | if (++rxintcount < 10) { |
695 | XXDEBUG(("bmac_rxdma_intr\n")); |
696 | } |
697 | |
698 | last = -1; |
699 | i = bp->rx_empty; |
700 | |
701 | while (1) { |
702 | cp = &bp->rx_cmds[i]; |
703 | stat = ld_le16(&cp->xfer_status); |
704 | residual = ld_le16(&cp->res_count); |
705 | if ((stat & ACTIVE) == 0) |
706 | break; |
707 | nb = RX_BUFLEN - residual - 2; |
708 | if (nb < (ETHERMINPACKET - ETHERCRC)) { |
709 | skb = NULL; |
710 | dev->stats.rx_length_errors++; |
711 | dev->stats.rx_errors++; |
712 | } else { |
713 | skb = bp->rx_bufs[i]; |
714 | bp->rx_bufs[i] = NULL; |
715 | } |
716 | if (skb != NULL) { |
717 | nb -= ETHERCRC; |
718 | skb_put(skb, nb); |
719 | skb->protocol = eth_type_trans(skb, dev); |
720 | netif_rx(skb); |
721 | ++dev->stats.rx_packets; |
722 | dev->stats.rx_bytes += nb; |
723 | } else { |
724 | ++dev->stats.rx_dropped; |
725 | } |
726 | if ((skb = bp->rx_bufs[i]) == NULL) { |
727 | bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2); |
728 | if (skb != NULL) |
729 | skb_reserve(bp->rx_bufs[i], 2); |
730 | } |
731 | bmac_construct_rxbuff(skb, &bp->rx_cmds[i]); |
732 | st_le16(&cp->res_count, 0); |
733 | st_le16(&cp->xfer_status, 0); |
734 | last = i; |
735 | if (++i >= N_RX_RING) i = 0; |
736 | } |
737 | |
738 | if (last != -1) { |
739 | bp->rx_fill = last; |
740 | bp->rx_empty = i; |
741 | } |
742 | |
743 | dbdma_continue(rd); |
744 | spin_unlock_irqrestore(&bp->lock, flags); |
745 | |
746 | if (rxintcount < 10) { |
747 | XXDEBUG(("bmac_rxdma_intr done\n")); |
748 | } |
749 | return IRQ_HANDLED; |
750 | } |
751 | |
752 | static int txintcount; |
753 | |
754 | static irqreturn_t bmac_txdma_intr(int irq, void *dev_id) |
755 | { |
756 | struct net_device *dev = (struct net_device *) dev_id; |
757 | struct bmac_data *bp = netdev_priv(dev); |
758 | volatile struct dbdma_cmd *cp; |
759 | int stat; |
760 | unsigned long flags; |
761 | |
762 | spin_lock_irqsave(&bp->lock, flags); |
763 | |
764 | if (txintcount++ < 10) { |
765 | XXDEBUG(("bmac_txdma_intr\n")); |
766 | } |
767 | |
768 | /* del_timer(&bp->tx_timeout); */ |
769 | /* bp->timeout_active = 0; */ |
770 | |
771 | while (1) { |
772 | cp = &bp->tx_cmds[bp->tx_empty]; |
773 | stat = ld_le16(&cp->xfer_status); |
774 | if (txintcount < 10) { |
775 | XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat)); |
776 | } |
777 | if (!(stat & ACTIVE)) { |
778 | /* |
779 | * status field might not have been filled by DBDMA |
780 | */ |
781 | if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr))) |
782 | break; |
783 | } |
784 | |
785 | if (bp->tx_bufs[bp->tx_empty]) { |
786 | ++dev->stats.tx_packets; |
787 | dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]); |
788 | } |
789 | bp->tx_bufs[bp->tx_empty] = NULL; |
790 | bp->tx_fullup = 0; |
791 | netif_wake_queue(dev); |
792 | if (++bp->tx_empty >= N_TX_RING) |
793 | bp->tx_empty = 0; |
794 | if (bp->tx_empty == bp->tx_fill) |
795 | break; |
796 | } |
797 | |
798 | spin_unlock_irqrestore(&bp->lock, flags); |
799 | |
800 | if (txintcount < 10) { |
801 | XXDEBUG(("bmac_txdma_intr done->bmac_start\n")); |
802 | } |
803 | |
804 | bmac_start(dev); |
805 | return IRQ_HANDLED; |
806 | } |
807 | |
808 | #ifndef SUNHME_MULTICAST |
809 | /* Real fast bit-reversal algorithm, 6-bit values */ |
810 | static int reverse6[64] = { |
811 | 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38, |
812 | 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c, |
813 | 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a, |
814 | 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e, |
815 | 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39, |
816 | 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d, |
817 | 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b, |
818 | 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f |
819 | }; |
820 | |
821 | static unsigned int |
822 | crc416(unsigned int curval, unsigned short nxtval) |
823 | { |
824 | register unsigned int counter, cur = curval, next = nxtval; |
825 | register int high_crc_set, low_data_set; |
826 | |
827 | /* Swap bytes */ |
828 | next = ((next & 0x00FF) << 8) | (next >> 8); |
829 | |
830 | /* Compute bit-by-bit */ |
831 | for (counter = 0; counter < 16; ++counter) { |
832 | /* is high CRC bit set? */ |
833 | if ((cur & 0x80000000) == 0) high_crc_set = 0; |
834 | else high_crc_set = 1; |
835 | |
836 | cur = cur << 1; |
837 | |
838 | if ((next & 0x0001) == 0) low_data_set = 0; |
839 | else low_data_set = 1; |
840 | |
841 | next = next >> 1; |
842 | |
843 | /* do the XOR */ |
844 | if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY; |
845 | } |
846 | return cur; |
847 | } |
848 | |
849 | static unsigned int |
850 | bmac_crc(unsigned short *address) |
851 | { |
852 | unsigned int newcrc; |
853 | |
854 | XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2])); |
855 | newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */ |
856 | newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */ |
857 | newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */ |
858 | |
859 | return(newcrc); |
860 | } |
861 | |
862 | /* |
863 | * Add requested mcast addr to BMac's hash table filter. |
864 | * |
865 | */ |
866 | |
867 | static void |
868 | bmac_addhash(struct bmac_data *bp, unsigned char *addr) |
869 | { |
870 | unsigned int crc; |
871 | unsigned short mask; |
872 | |
873 | if (!(*addr)) return; |
874 | crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */ |
875 | crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */ |
876 | if (bp->hash_use_count[crc]++) return; /* This bit is already set */ |
877 | mask = crc % 16; |
878 | mask = (unsigned char)1 << mask; |
879 | bp->hash_use_count[crc/16] |= mask; |
880 | } |
881 | |
882 | static void |
883 | bmac_removehash(struct bmac_data *bp, unsigned char *addr) |
884 | { |
885 | unsigned int crc; |
886 | unsigned char mask; |
887 | |
888 | /* Now, delete the address from the filter copy, as indicated */ |
889 | crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */ |
890 | crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */ |
891 | if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */ |
892 | if (--bp->hash_use_count[crc]) return; /* That bit is still in use */ |
893 | mask = crc % 16; |
894 | mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */ |
895 | bp->hash_table_mask[crc/16] &= mask; |
896 | } |
897 | |
898 | /* |
899 | * Sync the adapter with the software copy of the multicast mask |
900 | * (logical address filter). |
901 | */ |
902 | |
903 | static void |
904 | bmac_rx_off(struct net_device *dev) |
905 | { |
906 | unsigned short rx_cfg; |
907 | |
908 | rx_cfg = bmread(dev, RXCFG); |
909 | rx_cfg &= ~RxMACEnable; |
910 | bmwrite(dev, RXCFG, rx_cfg); |
911 | do { |
912 | rx_cfg = bmread(dev, RXCFG); |
913 | } while (rx_cfg & RxMACEnable); |
914 | } |
915 | |
916 | unsigned short |
917 | bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable) |
918 | { |
919 | unsigned short rx_cfg; |
920 | |
921 | rx_cfg = bmread(dev, RXCFG); |
922 | rx_cfg |= RxMACEnable; |
923 | if (hash_enable) rx_cfg |= RxHashFilterEnable; |
924 | else rx_cfg &= ~RxHashFilterEnable; |
925 | if (promisc_enable) rx_cfg |= RxPromiscEnable; |
926 | else rx_cfg &= ~RxPromiscEnable; |
927 | bmwrite(dev, RXRST, RxResetValue); |
928 | bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */ |
929 | bmwrite(dev, RXFIFOCSR, RxFIFOEnable ); |
930 | bmwrite(dev, RXCFG, rx_cfg ); |
931 | return rx_cfg; |
932 | } |
933 | |
934 | static void |
935 | bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp) |
936 | { |
937 | bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */ |
938 | bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */ |
939 | bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */ |
940 | bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */ |
941 | } |
942 | |
943 | #if 0 |
944 | static void |
945 | bmac_add_multi(struct net_device *dev, |
946 | struct bmac_data *bp, unsigned char *addr) |
947 | { |
948 | /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */ |
949 | bmac_addhash(bp, addr); |
950 | bmac_rx_off(dev); |
951 | bmac_update_hash_table_mask(dev, bp); |
952 | bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0); |
953 | /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */ |
954 | } |
955 | |
956 | static void |
957 | bmac_remove_multi(struct net_device *dev, |
958 | struct bmac_data *bp, unsigned char *addr) |
959 | { |
960 | bmac_removehash(bp, addr); |
961 | bmac_rx_off(dev); |
962 | bmac_update_hash_table_mask(dev, bp); |
963 | bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0); |
964 | } |
965 | #endif |
966 | |
967 | /* Set or clear the multicast filter for this adaptor. |
968 | num_addrs == -1 Promiscuous mode, receive all packets |
969 | num_addrs == 0 Normal mode, clear multicast list |
970 | num_addrs > 0 Multicast mode, receive normal and MC packets, and do |
971 | best-effort filtering. |
972 | */ |
973 | static void bmac_set_multicast(struct net_device *dev) |
974 | { |
975 | struct dev_mc_list *dmi; |
976 | struct bmac_data *bp = netdev_priv(dev); |
977 | int num_addrs = netdev_mc_count(dev); |
978 | unsigned short rx_cfg; |
979 | int i; |
980 | |
981 | if (bp->sleeping) |
982 | return; |
983 | |
984 | XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs)); |
985 | |
986 | if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { |
987 | for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff; |
988 | bmac_update_hash_table_mask(dev, bp); |
989 | rx_cfg = bmac_rx_on(dev, 1, 0); |
990 | XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n")); |
991 | } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) { |
992 | rx_cfg = bmread(dev, RXCFG); |
993 | rx_cfg |= RxPromiscEnable; |
994 | bmwrite(dev, RXCFG, rx_cfg); |
995 | rx_cfg = bmac_rx_on(dev, 0, 1); |
996 | XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg)); |
997 | } else { |
998 | for (i=0; i<4; i++) bp->hash_table_mask[i] = 0; |
999 | for (i=0; i<64; i++) bp->hash_use_count[i] = 0; |
1000 | if (num_addrs == 0) { |
1001 | rx_cfg = bmac_rx_on(dev, 0, 0); |
1002 | XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg)); |
1003 | } else { |
1004 | netdev_for_each_mc_addr(dmi, dev) |
1005 | bmac_addhash(bp, dmi->dmi_addr); |
1006 | bmac_update_hash_table_mask(dev, bp); |
1007 | rx_cfg = bmac_rx_on(dev, 1, 0); |
1008 | XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg)); |
1009 | } |
1010 | } |
1011 | /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */ |
1012 | } |
1013 | #else /* ifdef SUNHME_MULTICAST */ |
1014 | |
1015 | /* The version of set_multicast below was lifted from sunhme.c */ |
1016 | |
1017 | static void bmac_set_multicast(struct net_device *dev) |
1018 | { |
1019 | struct dev_mc_list *dmi; |
1020 | char *addrs; |
1021 | int i; |
1022 | unsigned short rx_cfg; |
1023 | u32 crc; |
1024 | |
1025 | if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { |
1026 | bmwrite(dev, BHASH0, 0xffff); |
1027 | bmwrite(dev, BHASH1, 0xffff); |
1028 | bmwrite(dev, BHASH2, 0xffff); |
1029 | bmwrite(dev, BHASH3, 0xffff); |
1030 | } else if(dev->flags & IFF_PROMISC) { |
1031 | rx_cfg = bmread(dev, RXCFG); |
1032 | rx_cfg |= RxPromiscEnable; |
1033 | bmwrite(dev, RXCFG, rx_cfg); |
1034 | } else { |
1035 | u16 hash_table[4]; |
1036 | |
1037 | rx_cfg = bmread(dev, RXCFG); |
1038 | rx_cfg &= ~RxPromiscEnable; |
1039 | bmwrite(dev, RXCFG, rx_cfg); |
1040 | |
1041 | for(i = 0; i < 4; i++) hash_table[i] = 0; |
1042 | |
1043 | netdev_for_each_mc_addr(dmi, dev) { |
1044 | addrs = dmi->dmi_addr; |
1045 | |
1046 | if(!(*addrs & 1)) |
1047 | continue; |
1048 | |
1049 | crc = ether_crc_le(6, addrs); |
1050 | crc >>= 26; |
1051 | hash_table[crc >> 4] |= 1 << (crc & 0xf); |
1052 | } |
1053 | bmwrite(dev, BHASH0, hash_table[0]); |
1054 | bmwrite(dev, BHASH1, hash_table[1]); |
1055 | bmwrite(dev, BHASH2, hash_table[2]); |
1056 | bmwrite(dev, BHASH3, hash_table[3]); |
1057 | } |
1058 | } |
1059 | #endif /* SUNHME_MULTICAST */ |
1060 | |
1061 | static int miscintcount; |
1062 | |
1063 | static irqreturn_t bmac_misc_intr(int irq, void *dev_id) |
1064 | { |
1065 | struct net_device *dev = (struct net_device *) dev_id; |
1066 | unsigned int status = bmread(dev, STATUS); |
1067 | if (miscintcount++ < 10) { |
1068 | XXDEBUG(("bmac_misc_intr\n")); |
1069 | } |
1070 | /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */ |
1071 | /* bmac_txdma_intr_inner(irq, dev_id); */ |
1072 | /* if (status & FrameReceived) dev->stats.rx_dropped++; */ |
1073 | if (status & RxErrorMask) dev->stats.rx_errors++; |
1074 | if (status & RxCRCCntExp) dev->stats.rx_crc_errors++; |
1075 | if (status & RxLenCntExp) dev->stats.rx_length_errors++; |
1076 | if (status & RxOverFlow) dev->stats.rx_over_errors++; |
1077 | if (status & RxAlignCntExp) dev->stats.rx_frame_errors++; |
1078 | |
1079 | /* if (status & FrameSent) dev->stats.tx_dropped++; */ |
1080 | if (status & TxErrorMask) dev->stats.tx_errors++; |
1081 | if (status & TxUnderrun) dev->stats.tx_fifo_errors++; |
1082 | if (status & TxNormalCollExp) dev->stats.collisions++; |
1083 | return IRQ_HANDLED; |
1084 | } |
1085 | |
1086 | /* |
1087 | * Procedure for reading EEPROM |
1088 | */ |
1089 | #define SROMAddressLength 5 |
1090 | #define DataInOn 0x0008 |
1091 | #define DataInOff 0x0000 |
1092 | #define Clk 0x0002 |
1093 | #define ChipSelect 0x0001 |
1094 | #define SDIShiftCount 3 |
1095 | #define SD0ShiftCount 2 |
1096 | #define DelayValue 1000 /* number of microseconds */ |
1097 | #define SROMStartOffset 10 /* this is in words */ |
1098 | #define SROMReadCount 3 /* number of words to read from SROM */ |
1099 | #define SROMAddressBits 6 |
1100 | #define EnetAddressOffset 20 |
1101 | |
1102 | static unsigned char |
1103 | bmac_clock_out_bit(struct net_device *dev) |
1104 | { |
1105 | unsigned short data; |
1106 | unsigned short val; |
1107 | |
1108 | bmwrite(dev, SROMCSR, ChipSelect | Clk); |
1109 | udelay(DelayValue); |
1110 | |
1111 | data = bmread(dev, SROMCSR); |
1112 | udelay(DelayValue); |
1113 | val = (data >> SD0ShiftCount) & 1; |
1114 | |
1115 | bmwrite(dev, SROMCSR, ChipSelect); |
1116 | udelay(DelayValue); |
1117 | |
1118 | return val; |
1119 | } |
1120 | |
1121 | static void |
1122 | bmac_clock_in_bit(struct net_device *dev, unsigned int val) |
1123 | { |
1124 | unsigned short data; |
1125 | |
1126 | if (val != 0 && val != 1) return; |
1127 | |
1128 | data = (val << SDIShiftCount); |
1129 | bmwrite(dev, SROMCSR, data | ChipSelect ); |
1130 | udelay(DelayValue); |
1131 | |
1132 | bmwrite(dev, SROMCSR, data | ChipSelect | Clk ); |
1133 | udelay(DelayValue); |
1134 | |
1135 | bmwrite(dev, SROMCSR, data | ChipSelect); |
1136 | udelay(DelayValue); |
1137 | } |
1138 | |
1139 | static void |
1140 | reset_and_select_srom(struct net_device *dev) |
1141 | { |
1142 | /* first reset */ |
1143 | bmwrite(dev, SROMCSR, 0); |
1144 | udelay(DelayValue); |
1145 | |
1146 | /* send it the read command (110) */ |
1147 | bmac_clock_in_bit(dev, 1); |
1148 | bmac_clock_in_bit(dev, 1); |
1149 | bmac_clock_in_bit(dev, 0); |
1150 | } |
1151 | |
1152 | static unsigned short |
1153 | read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len) |
1154 | { |
1155 | unsigned short data, val; |
1156 | int i; |
1157 | |
1158 | /* send out the address we want to read from */ |
1159 | for (i = 0; i < addr_len; i++) { |
1160 | val = addr >> (addr_len-i-1); |
1161 | bmac_clock_in_bit(dev, val & 1); |
1162 | } |
1163 | |
1164 | /* Now read in the 16-bit data */ |
1165 | data = 0; |
1166 | for (i = 0; i < 16; i++) { |
1167 | val = bmac_clock_out_bit(dev); |
1168 | data <<= 1; |
1169 | data |= val; |
1170 | } |
1171 | bmwrite(dev, SROMCSR, 0); |
1172 | |
1173 | return data; |
1174 | } |
1175 | |
1176 | /* |
1177 | * It looks like Cogent and SMC use different methods for calculating |
1178 | * checksums. What a pain.. |
1179 | */ |
1180 | |
1181 | static int |
1182 | bmac_verify_checksum(struct net_device *dev) |
1183 | { |
1184 | unsigned short data, storedCS; |
1185 | |
1186 | reset_and_select_srom(dev); |
1187 | data = read_srom(dev, 3, SROMAddressBits); |
1188 | storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00); |
1189 | |
1190 | return 0; |
1191 | } |
1192 | |
1193 | |
1194 | static void |
1195 | bmac_get_station_address(struct net_device *dev, unsigned char *ea) |
1196 | { |
1197 | int i; |
1198 | unsigned short data; |
1199 | |
1200 | for (i = 0; i < 6; i++) |
1201 | { |
1202 | reset_and_select_srom(dev); |
1203 | data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits); |
1204 | ea[2*i] = bitrev8(data & 0x0ff); |
1205 | ea[2*i+1] = bitrev8((data >> 8) & 0x0ff); |
1206 | } |
1207 | } |
1208 | |
1209 | static void bmac_reset_and_enable(struct net_device *dev) |
1210 | { |
1211 | struct bmac_data *bp = netdev_priv(dev); |
1212 | unsigned long flags; |
1213 | struct sk_buff *skb; |
1214 | unsigned char *data; |
1215 | |
1216 | spin_lock_irqsave(&bp->lock, flags); |
1217 | bmac_enable_and_reset_chip(dev); |
1218 | bmac_init_tx_ring(bp); |
1219 | bmac_init_rx_ring(bp); |
1220 | bmac_init_chip(dev); |
1221 | bmac_start_chip(dev); |
1222 | bmwrite(dev, INTDISABLE, EnableNormal); |
1223 | bp->sleeping = 0; |
1224 | |
1225 | /* |
1226 | * It seems that the bmac can't receive until it's transmitted |
1227 | * a packet. So we give it a dummy packet to transmit. |
1228 | */ |
1229 | skb = dev_alloc_skb(ETHERMINPACKET); |
1230 | if (skb != NULL) { |
1231 | data = skb_put(skb, ETHERMINPACKET); |
1232 | memset(data, 0, ETHERMINPACKET); |
1233 | memcpy(data, dev->dev_addr, 6); |
1234 | memcpy(data+6, dev->dev_addr, 6); |
1235 | bmac_transmit_packet(skb, dev); |
1236 | } |
1237 | spin_unlock_irqrestore(&bp->lock, flags); |
1238 | } |
1239 | static void bmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
1240 | { |
1241 | struct bmac_data *bp = netdev_priv(dev); |
1242 | strcpy(info->driver, "bmac"); |
1243 | strcpy(info->bus_info, dev_name(&bp->mdev->ofdev.dev)); |
1244 | } |
1245 | |
1246 | static const struct ethtool_ops bmac_ethtool_ops = { |
1247 | .get_drvinfo = bmac_get_drvinfo, |
1248 | .get_link = ethtool_op_get_link, |
1249 | }; |
1250 | |
1251 | static const struct net_device_ops bmac_netdev_ops = { |
1252 | .ndo_open = bmac_open, |
1253 | .ndo_stop = bmac_close, |
1254 | .ndo_start_xmit = bmac_output, |
1255 | .ndo_set_multicast_list = bmac_set_multicast, |
1256 | .ndo_set_mac_address = bmac_set_address, |
1257 | .ndo_change_mtu = eth_change_mtu, |
1258 | .ndo_validate_addr = eth_validate_addr, |
1259 | }; |
1260 | |
1261 | static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match) |
1262 | { |
1263 | int j, rev, ret; |
1264 | struct bmac_data *bp; |
1265 | const unsigned char *prop_addr; |
1266 | unsigned char addr[6]; |
1267 | struct net_device *dev; |
1268 | int is_bmac_plus = ((int)match->data) != 0; |
1269 | |
1270 | if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) { |
1271 | printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n"); |
1272 | return -ENODEV; |
1273 | } |
1274 | prop_addr = of_get_property(macio_get_of_node(mdev), |
1275 | "mac-address", NULL); |
1276 | if (prop_addr == NULL) { |
1277 | prop_addr = of_get_property(macio_get_of_node(mdev), |
1278 | "local-mac-address", NULL); |
1279 | if (prop_addr == NULL) { |
1280 | printk(KERN_ERR "BMAC: Can't get mac-address\n"); |
1281 | return -ENODEV; |
1282 | } |
1283 | } |
1284 | memcpy(addr, prop_addr, sizeof(addr)); |
1285 | |
1286 | dev = alloc_etherdev(PRIV_BYTES); |
1287 | if (!dev) { |
1288 | printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n"); |
1289 | return -ENOMEM; |
1290 | } |
1291 | |
1292 | bp = netdev_priv(dev); |
1293 | SET_NETDEV_DEV(dev, &mdev->ofdev.dev); |
1294 | macio_set_drvdata(mdev, dev); |
1295 | |
1296 | bp->mdev = mdev; |
1297 | spin_lock_init(&bp->lock); |
1298 | |
1299 | if (macio_request_resources(mdev, "bmac")) { |
1300 | printk(KERN_ERR "BMAC: can't request IO resource !\n"); |
1301 | goto out_free; |
1302 | } |
1303 | |
1304 | dev->base_addr = (unsigned long) |
1305 | ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0)); |
1306 | if (dev->base_addr == 0) |
1307 | goto out_release; |
1308 | |
1309 | dev->irq = macio_irq(mdev, 0); |
1310 | |
1311 | bmac_enable_and_reset_chip(dev); |
1312 | bmwrite(dev, INTDISABLE, DisableAll); |
1313 | |
1314 | rev = addr[0] == 0 && addr[1] == 0xA0; |
1315 | for (j = 0; j < 6; ++j) |
1316 | dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; |
1317 | |
1318 | /* Enable chip without interrupts for now */ |
1319 | bmac_enable_and_reset_chip(dev); |
1320 | bmwrite(dev, INTDISABLE, DisableAll); |
1321 | |
1322 | dev->netdev_ops = &bmac_netdev_ops; |
1323 | dev->ethtool_ops = &bmac_ethtool_ops; |
1324 | |
1325 | bmac_get_station_address(dev, addr); |
1326 | if (bmac_verify_checksum(dev) != 0) |
1327 | goto err_out_iounmap; |
1328 | |
1329 | bp->is_bmac_plus = is_bmac_plus; |
1330 | bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1)); |
1331 | if (!bp->tx_dma) |
1332 | goto err_out_iounmap; |
1333 | bp->tx_dma_intr = macio_irq(mdev, 1); |
1334 | bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2)); |
1335 | if (!bp->rx_dma) |
1336 | goto err_out_iounmap_tx; |
1337 | bp->rx_dma_intr = macio_irq(mdev, 2); |
1338 | |
1339 | bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1); |
1340 | bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1; |
1341 | |
1342 | bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1); |
1343 | skb_queue_head_init(bp->queue); |
1344 | |
1345 | init_timer(&bp->tx_timeout); |
1346 | |
1347 | ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev); |
1348 | if (ret) { |
1349 | printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq); |
1350 | goto err_out_iounmap_rx; |
1351 | } |
1352 | ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev); |
1353 | if (ret) { |
1354 | printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr); |
1355 | goto err_out_irq0; |
1356 | } |
1357 | ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev); |
1358 | if (ret) { |
1359 | printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr); |
1360 | goto err_out_irq1; |
1361 | } |
1362 | |
1363 | /* Mask chip interrupts and disable chip, will be |
1364 | * re-enabled on open() |
1365 | */ |
1366 | disable_irq(dev->irq); |
1367 | pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); |
1368 | |
1369 | if (register_netdev(dev) != 0) { |
1370 | printk(KERN_ERR "BMAC: Ethernet registration failed\n"); |
1371 | goto err_out_irq2; |
1372 | } |
1373 | |
1374 | printk(KERN_INFO "%s: BMAC%s at %pM", |
1375 | dev->name, (is_bmac_plus ? "+" : ""), dev->dev_addr); |
1376 | XXDEBUG((", base_addr=%#0lx", dev->base_addr)); |
1377 | printk("\n"); |
1378 | |
1379 | return 0; |
1380 | |
1381 | err_out_irq2: |
1382 | free_irq(bp->rx_dma_intr, dev); |
1383 | err_out_irq1: |
1384 | free_irq(bp->tx_dma_intr, dev); |
1385 | err_out_irq0: |
1386 | free_irq(dev->irq, dev); |
1387 | err_out_iounmap_rx: |
1388 | iounmap(bp->rx_dma); |
1389 | err_out_iounmap_tx: |
1390 | iounmap(bp->tx_dma); |
1391 | err_out_iounmap: |
1392 | iounmap((void __iomem *)dev->base_addr); |
1393 | out_release: |
1394 | macio_release_resources(mdev); |
1395 | out_free: |
1396 | pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); |
1397 | free_netdev(dev); |
1398 | |
1399 | return -ENODEV; |
1400 | } |
1401 | |
1402 | static int bmac_open(struct net_device *dev) |
1403 | { |
1404 | struct bmac_data *bp = netdev_priv(dev); |
1405 | /* XXDEBUG(("bmac: enter open\n")); */ |
1406 | /* reset the chip */ |
1407 | bp->opened = 1; |
1408 | bmac_reset_and_enable(dev); |
1409 | enable_irq(dev->irq); |
1410 | return 0; |
1411 | } |
1412 | |
1413 | static int bmac_close(struct net_device *dev) |
1414 | { |
1415 | struct bmac_data *bp = netdev_priv(dev); |
1416 | volatile struct dbdma_regs __iomem *rd = bp->rx_dma; |
1417 | volatile struct dbdma_regs __iomem *td = bp->tx_dma; |
1418 | unsigned short config; |
1419 | int i; |
1420 | |
1421 | bp->sleeping = 1; |
1422 | |
1423 | /* disable rx and tx */ |
1424 | config = bmread(dev, RXCFG); |
1425 | bmwrite(dev, RXCFG, (config & ~RxMACEnable)); |
1426 | |
1427 | config = bmread(dev, TXCFG); |
1428 | bmwrite(dev, TXCFG, (config & ~TxMACEnable)); |
1429 | |
1430 | bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */ |
1431 | |
1432 | /* disable rx and tx dma */ |
1433 | st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ |
1434 | st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ |
1435 | |
1436 | /* free some skb's */ |
1437 | XXDEBUG(("bmac: free rx bufs\n")); |
1438 | for (i=0; i<N_RX_RING; i++) { |
1439 | if (bp->rx_bufs[i] != NULL) { |
1440 | dev_kfree_skb(bp->rx_bufs[i]); |
1441 | bp->rx_bufs[i] = NULL; |
1442 | } |
1443 | } |
1444 | XXDEBUG(("bmac: free tx bufs\n")); |
1445 | for (i = 0; i<N_TX_RING; i++) { |
1446 | if (bp->tx_bufs[i] != NULL) { |
1447 | dev_kfree_skb(bp->tx_bufs[i]); |
1448 | bp->tx_bufs[i] = NULL; |
1449 | } |
1450 | } |
1451 | XXDEBUG(("bmac: all bufs freed\n")); |
1452 | |
1453 | bp->opened = 0; |
1454 | disable_irq(dev->irq); |
1455 | pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); |
1456 | |
1457 | return 0; |
1458 | } |
1459 | |
1460 | static void |
1461 | bmac_start(struct net_device *dev) |
1462 | { |
1463 | struct bmac_data *bp = netdev_priv(dev); |
1464 | int i; |
1465 | struct sk_buff *skb; |
1466 | unsigned long flags; |
1467 | |
1468 | if (bp->sleeping) |
1469 | return; |
1470 | |
1471 | spin_lock_irqsave(&bp->lock, flags); |
1472 | while (1) { |
1473 | i = bp->tx_fill + 1; |
1474 | if (i >= N_TX_RING) |
1475 | i = 0; |
1476 | if (i == bp->tx_empty) |
1477 | break; |
1478 | skb = skb_dequeue(bp->queue); |
1479 | if (skb == NULL) |
1480 | break; |
1481 | bmac_transmit_packet(skb, dev); |
1482 | } |
1483 | spin_unlock_irqrestore(&bp->lock, flags); |
1484 | } |
1485 | |
1486 | static int |
1487 | bmac_output(struct sk_buff *skb, struct net_device *dev) |
1488 | { |
1489 | struct bmac_data *bp = netdev_priv(dev); |
1490 | skb_queue_tail(bp->queue, skb); |
1491 | bmac_start(dev); |
1492 | return NETDEV_TX_OK; |
1493 | } |
1494 | |
1495 | static void bmac_tx_timeout(unsigned long data) |
1496 | { |
1497 | struct net_device *dev = (struct net_device *) data; |
1498 | struct bmac_data *bp = netdev_priv(dev); |
1499 | volatile struct dbdma_regs __iomem *td = bp->tx_dma; |
1500 | volatile struct dbdma_regs __iomem *rd = bp->rx_dma; |
1501 | volatile struct dbdma_cmd *cp; |
1502 | unsigned long flags; |
1503 | unsigned short config, oldConfig; |
1504 | int i; |
1505 | |
1506 | XXDEBUG(("bmac: tx_timeout called\n")); |
1507 | spin_lock_irqsave(&bp->lock, flags); |
1508 | bp->timeout_active = 0; |
1509 | |
1510 | /* update various counters */ |
1511 | /* bmac_handle_misc_intrs(bp, 0); */ |
1512 | |
1513 | cp = &bp->tx_cmds[bp->tx_empty]; |
1514 | /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */ |
1515 | /* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */ |
1516 | /* mb->pr, mb->xmtfs, mb->fifofc)); */ |
1517 | |
1518 | /* turn off both tx and rx and reset the chip */ |
1519 | config = bmread(dev, RXCFG); |
1520 | bmwrite(dev, RXCFG, (config & ~RxMACEnable)); |
1521 | config = bmread(dev, TXCFG); |
1522 | bmwrite(dev, TXCFG, (config & ~TxMACEnable)); |
1523 | out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); |
1524 | printk(KERN_ERR "bmac: transmit timeout - resetting\n"); |
1525 | bmac_enable_and_reset_chip(dev); |
1526 | |
1527 | /* restart rx dma */ |
1528 | cp = bus_to_virt(ld_le32(&rd->cmdptr)); |
1529 | out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); |
1530 | out_le16(&cp->xfer_status, 0); |
1531 | out_le32(&rd->cmdptr, virt_to_bus(cp)); |
1532 | out_le32(&rd->control, DBDMA_SET(RUN|WAKE)); |
1533 | |
1534 | /* fix up the transmit side */ |
1535 | XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n", |
1536 | bp->tx_empty, bp->tx_fill, bp->tx_fullup)); |
1537 | i = bp->tx_empty; |
1538 | ++dev->stats.tx_errors; |
1539 | if (i != bp->tx_fill) { |
1540 | dev_kfree_skb(bp->tx_bufs[i]); |
1541 | bp->tx_bufs[i] = NULL; |
1542 | if (++i >= N_TX_RING) i = 0; |
1543 | bp->tx_empty = i; |
1544 | } |
1545 | bp->tx_fullup = 0; |
1546 | netif_wake_queue(dev); |
1547 | if (i != bp->tx_fill) { |
1548 | cp = &bp->tx_cmds[i]; |
1549 | out_le16(&cp->xfer_status, 0); |
1550 | out_le16(&cp->command, OUTPUT_LAST); |
1551 | out_le32(&td->cmdptr, virt_to_bus(cp)); |
1552 | out_le32(&td->control, DBDMA_SET(RUN)); |
1553 | /* bmac_set_timeout(dev); */ |
1554 | XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i)); |
1555 | } |
1556 | |
1557 | /* turn it back on */ |
1558 | oldConfig = bmread(dev, RXCFG); |
1559 | bmwrite(dev, RXCFG, oldConfig | RxMACEnable ); |
1560 | oldConfig = bmread(dev, TXCFG); |
1561 | bmwrite(dev, TXCFG, oldConfig | TxMACEnable ); |
1562 | |
1563 | spin_unlock_irqrestore(&bp->lock, flags); |
1564 | } |
1565 | |
1566 | #if 0 |
1567 | static void dump_dbdma(volatile struct dbdma_cmd *cp,int count) |
1568 | { |
1569 | int i,*ip; |
1570 | |
1571 | for (i=0;i< count;i++) { |
1572 | ip = (int*)(cp+i); |
1573 | |
1574 | printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n", |
1575 | ld_le32(ip+0), |
1576 | ld_le32(ip+1), |
1577 | ld_le32(ip+2), |
1578 | ld_le32(ip+3)); |
1579 | } |
1580 | |
1581 | } |
1582 | #endif |
1583 | |
1584 | #if 0 |
1585 | static int |
1586 | bmac_proc_info(char *buffer, char **start, off_t offset, int length) |
1587 | { |
1588 | int len = 0; |
1589 | off_t pos = 0; |
1590 | off_t begin = 0; |
1591 | int i; |
1592 | |
1593 | if (bmac_devs == NULL) |
1594 | return (-ENOSYS); |
1595 | |
1596 | len += sprintf(buffer, "BMAC counters & registers\n"); |
1597 | |
1598 | for (i = 0; i<N_REG_ENTRIES; i++) { |
1599 | len += sprintf(buffer + len, "%s: %#08x\n", |
1600 | reg_entries[i].name, |
1601 | bmread(bmac_devs, reg_entries[i].reg_offset)); |
1602 | pos = begin + len; |
1603 | |
1604 | if (pos < offset) { |
1605 | len = 0; |
1606 | begin = pos; |
1607 | } |
1608 | |
1609 | if (pos > offset+length) break; |
1610 | } |
1611 | |
1612 | *start = buffer + (offset - begin); |
1613 | len -= (offset - begin); |
1614 | |
1615 | if (len > length) len = length; |
1616 | |
1617 | return len; |
1618 | } |
1619 | #endif |
1620 | |
1621 | static int __devexit bmac_remove(struct macio_dev *mdev) |
1622 | { |
1623 | struct net_device *dev = macio_get_drvdata(mdev); |
1624 | struct bmac_data *bp = netdev_priv(dev); |
1625 | |
1626 | unregister_netdev(dev); |
1627 | |
1628 | free_irq(dev->irq, dev); |
1629 | free_irq(bp->tx_dma_intr, dev); |
1630 | free_irq(bp->rx_dma_intr, dev); |
1631 | |
1632 | iounmap((void __iomem *)dev->base_addr); |
1633 | iounmap(bp->tx_dma); |
1634 | iounmap(bp->rx_dma); |
1635 | |
1636 | macio_release_resources(mdev); |
1637 | |
1638 | free_netdev(dev); |
1639 | |
1640 | return 0; |
1641 | } |
1642 | |
1643 | static struct of_device_id bmac_match[] = |
1644 | { |
1645 | { |
1646 | .name = "bmac", |
1647 | .data = (void *)0, |
1648 | }, |
1649 | { |
1650 | .type = "network", |
1651 | .compatible = "bmac+", |
1652 | .data = (void *)1, |
1653 | }, |
1654 | {}, |
1655 | }; |
1656 | MODULE_DEVICE_TABLE (of, bmac_match); |
1657 | |
1658 | static struct macio_driver bmac_driver = |
1659 | { |
1660 | .name = "bmac", |
1661 | .match_table = bmac_match, |
1662 | .probe = bmac_probe, |
1663 | .remove = bmac_remove, |
1664 | #ifdef CONFIG_PM |
1665 | .suspend = bmac_suspend, |
1666 | .resume = bmac_resume, |
1667 | #endif |
1668 | }; |
1669 | |
1670 | |
1671 | static int __init bmac_init(void) |
1672 | { |
1673 | if (bmac_emergency_rxbuf == NULL) { |
1674 | bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL); |
1675 | if (bmac_emergency_rxbuf == NULL) { |
1676 | printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n"); |
1677 | return -ENOMEM; |
1678 | } |
1679 | } |
1680 | |
1681 | return macio_register_driver(&bmac_driver); |
1682 | } |
1683 | |
1684 | static void __exit bmac_exit(void) |
1685 | { |
1686 | macio_unregister_driver(&bmac_driver); |
1687 | |
1688 | kfree(bmac_emergency_rxbuf); |
1689 | bmac_emergency_rxbuf = NULL; |
1690 | } |
1691 | |
1692 | MODULE_AUTHOR("Randy Gobbel/Paul Mackerras"); |
1693 | MODULE_DESCRIPTION("PowerMac BMAC ethernet driver."); |
1694 | MODULE_LICENSE("GPL"); |
1695 | |
1696 | module_init(bmac_init); |
1697 | module_exit(bmac_exit); |
1698 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
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jz-2.6.35
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jz-3.11
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jz-3.3
jz-3.4
jz-3.5
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jz-3.6-rc2-pwm
jz-3.9
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jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9