Root/
1 | /* |
2 | * DaVinci Ethernet Medium Access Controller |
3 | * |
4 | * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine |
5 | * |
6 | * Copyright (C) 2009 Texas Instruments. |
7 | * |
8 | * --------------------------------------------------------------------------- |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by |
12 | * the Free Software Foundation; either version 2 of the License, or |
13 | * (at your option) any later version. |
14 | * |
15 | * This program is distributed in the hope that it will be useful, |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
18 | * GNU General Public License for more details. |
19 | * |
20 | * You should have received a copy of the GNU General Public License |
21 | * along with this program; if not, write to the Free Software |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
23 | * --------------------------------------------------------------------------- |
24 | * History: |
25 | * 0-5 A number of folks worked on this driver in bits and pieces but the major |
26 | * contribution came from Suraj Iyer and Anant Gole |
27 | * 6.0 Anant Gole - rewrote the driver as per Linux conventions |
28 | * 6.1 Chaithrika U S - added support for Gigabit and RMII features, |
29 | * PHY layer usage |
30 | */ |
31 | |
32 | #include <linux/module.h> |
33 | #include <linux/kernel.h> |
34 | #include <linux/sched.h> |
35 | #include <linux/string.h> |
36 | #include <linux/timer.h> |
37 | #include <linux/errno.h> |
38 | #include <linux/in.h> |
39 | #include <linux/ioport.h> |
40 | #include <linux/slab.h> |
41 | #include <linux/mm.h> |
42 | #include <linux/interrupt.h> |
43 | #include <linux/init.h> |
44 | #include <linux/netdevice.h> |
45 | #include <linux/etherdevice.h> |
46 | #include <linux/skbuff.h> |
47 | #include <linux/ethtool.h> |
48 | #include <linux/highmem.h> |
49 | #include <linux/proc_fs.h> |
50 | #include <linux/ctype.h> |
51 | #include <linux/version.h> |
52 | #include <linux/spinlock.h> |
53 | #include <linux/dma-mapping.h> |
54 | #include <linux/clk.h> |
55 | #include <linux/platform_device.h> |
56 | #include <linux/semaphore.h> |
57 | #include <linux/phy.h> |
58 | #include <linux/bitops.h> |
59 | #include <linux/io.h> |
60 | #include <linux/uaccess.h> |
61 | #include <linux/davinci_emac.h> |
62 | |
63 | #include <asm/irq.h> |
64 | #include <asm/page.h> |
65 | |
66 | static int debug_level; |
67 | module_param(debug_level, int, 0); |
68 | MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); |
69 | |
70 | /* Netif debug messages possible */ |
71 | #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ |
72 | NETIF_MSG_PROBE | \ |
73 | NETIF_MSG_LINK | \ |
74 | NETIF_MSG_TIMER | \ |
75 | NETIF_MSG_IFDOWN | \ |
76 | NETIF_MSG_IFUP | \ |
77 | NETIF_MSG_RX_ERR | \ |
78 | NETIF_MSG_TX_ERR | \ |
79 | NETIF_MSG_TX_QUEUED | \ |
80 | NETIF_MSG_INTR | \ |
81 | NETIF_MSG_TX_DONE | \ |
82 | NETIF_MSG_RX_STATUS | \ |
83 | NETIF_MSG_PKTDATA | \ |
84 | NETIF_MSG_HW | \ |
85 | NETIF_MSG_WOL) |
86 | |
87 | /* version info */ |
88 | #define EMAC_MAJOR_VERSION 6 |
89 | #define EMAC_MINOR_VERSION 1 |
90 | #define EMAC_MODULE_VERSION "6.1" |
91 | MODULE_VERSION(EMAC_MODULE_VERSION); |
92 | static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; |
93 | |
94 | /* Configuration items */ |
95 | #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ |
96 | #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ |
97 | #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ |
98 | #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ |
99 | #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ |
100 | #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ |
101 | #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ |
102 | #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ |
103 | #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ |
104 | #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ |
105 | #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ |
106 | #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ |
107 | |
108 | #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ |
109 | #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ |
110 | |
111 | #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ |
112 | #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ |
113 | #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) |
114 | #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ |
115 | #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ |
116 | #define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ |
117 | #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ |
118 | #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ |
119 | #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ |
120 | |
121 | /* Buffer descriptor parameters */ |
122 | #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ |
123 | #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ |
124 | |
125 | /* EMAC register related defines */ |
126 | #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) |
127 | #define EMAC_NUM_MULTICAST_BITS (64) |
128 | #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) |
129 | #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) |
130 | #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) |
131 | #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) |
132 | #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) |
133 | #define EMAC_INT_MASK_CLEAR (0xFF) |
134 | |
135 | /* RX MBP register bit positions */ |
136 | #define EMAC_RXMBP_PASSCRC_MASK BIT(30) |
137 | #define EMAC_RXMBP_QOSEN_MASK BIT(29) |
138 | #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) |
139 | #define EMAC_RXMBP_CMFEN_MASK BIT(24) |
140 | #define EMAC_RXMBP_CSFEN_MASK BIT(23) |
141 | #define EMAC_RXMBP_CEFEN_MASK BIT(22) |
142 | #define EMAC_RXMBP_CAFEN_MASK BIT(21) |
143 | #define EMAC_RXMBP_PROMCH_SHIFT (16) |
144 | #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) |
145 | #define EMAC_RXMBP_BROADEN_MASK BIT(13) |
146 | #define EMAC_RXMBP_BROADCH_SHIFT (8) |
147 | #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) |
148 | #define EMAC_RXMBP_MULTIEN_MASK BIT(5) |
149 | #define EMAC_RXMBP_MULTICH_SHIFT (0) |
150 | #define EMAC_RXMBP_MULTICH_MASK (0x7) |
151 | #define EMAC_RXMBP_CHMASK (0x7) |
152 | |
153 | /* EMAC register definitions/bit maps used */ |
154 | # define EMAC_MBP_RXPROMISC (0x00200000) |
155 | # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) |
156 | # define EMAC_MBP_RXBCAST (0x00002000) |
157 | # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) |
158 | # define EMAC_MBP_RXMCAST (0x00000020) |
159 | # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) |
160 | |
161 | /* EMAC mac_control register */ |
162 | #define EMAC_MACCONTROL_TXPTYPE BIT(9) |
163 | #define EMAC_MACCONTROL_TXPACEEN BIT(6) |
164 | #define EMAC_MACCONTROL_GMIIEN BIT(5) |
165 | #define EMAC_MACCONTROL_GIGABITEN BIT(7) |
166 | #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) |
167 | #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) |
168 | |
169 | /* GIGABIT MODE related bits */ |
170 | #define EMAC_DM646X_MACCONTORL_GIG BIT(7) |
171 | #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) |
172 | |
173 | /* EMAC mac_status register */ |
174 | #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) |
175 | #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) |
176 | #define EMAC_MACSTATUS_TXERRCH_MASK (0x7) |
177 | #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) |
178 | #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) |
179 | #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) |
180 | #define EMAC_MACSTATUS_RXERRCH_MASK (0x7) |
181 | #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) |
182 | |
183 | /* EMAC RX register masks */ |
184 | #define EMAC_RX_MAX_LEN_MASK (0xFFFF) |
185 | #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) |
186 | |
187 | /* MAC_IN_VECTOR (0x180) register bit fields */ |
188 | #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) |
189 | #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) |
190 | #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) |
191 | #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) |
192 | |
193 | /** NOTE:: For DM646x the IN_VECTOR has changed */ |
194 | #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) |
195 | #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) |
196 | #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) |
197 | #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) |
198 | |
199 | /* CPPI bit positions */ |
200 | #define EMAC_CPPI_SOP_BIT BIT(31) |
201 | #define EMAC_CPPI_EOP_BIT BIT(30) |
202 | #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) |
203 | #define EMAC_CPPI_EOQ_BIT BIT(28) |
204 | #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) |
205 | #define EMAC_CPPI_PASS_CRC_BIT BIT(26) |
206 | #define EMAC_RX_BD_BUF_SIZE (0xFFFF) |
207 | #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ |
208 | #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) |
209 | |
210 | /* Max hardware defines */ |
211 | #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ |
212 | #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ |
213 | |
214 | /* EMAC Peripheral Device Register Memory Layout structure */ |
215 | #define EMAC_TXIDVER 0x0 |
216 | #define EMAC_TXCONTROL 0x4 |
217 | #define EMAC_TXTEARDOWN 0x8 |
218 | #define EMAC_RXIDVER 0x10 |
219 | #define EMAC_RXCONTROL 0x14 |
220 | #define EMAC_RXTEARDOWN 0x18 |
221 | #define EMAC_TXINTSTATRAW 0x80 |
222 | #define EMAC_TXINTSTATMASKED 0x84 |
223 | #define EMAC_TXINTMASKSET 0x88 |
224 | #define EMAC_TXINTMASKCLEAR 0x8C |
225 | #define EMAC_MACINVECTOR 0x90 |
226 | |
227 | #define EMAC_DM646X_MACEOIVECTOR 0x94 |
228 | |
229 | #define EMAC_RXINTSTATRAW 0xA0 |
230 | #define EMAC_RXINTSTATMASKED 0xA4 |
231 | #define EMAC_RXINTMASKSET 0xA8 |
232 | #define EMAC_RXINTMASKCLEAR 0xAC |
233 | #define EMAC_MACINTSTATRAW 0xB0 |
234 | #define EMAC_MACINTSTATMASKED 0xB4 |
235 | #define EMAC_MACINTMASKSET 0xB8 |
236 | #define EMAC_MACINTMASKCLEAR 0xBC |
237 | |
238 | #define EMAC_RXMBPENABLE 0x100 |
239 | #define EMAC_RXUNICASTSET 0x104 |
240 | #define EMAC_RXUNICASTCLEAR 0x108 |
241 | #define EMAC_RXMAXLEN 0x10C |
242 | #define EMAC_RXBUFFEROFFSET 0x110 |
243 | #define EMAC_RXFILTERLOWTHRESH 0x114 |
244 | |
245 | #define EMAC_MACCONTROL 0x160 |
246 | #define EMAC_MACSTATUS 0x164 |
247 | #define EMAC_EMCONTROL 0x168 |
248 | #define EMAC_FIFOCONTROL 0x16C |
249 | #define EMAC_MACCONFIG 0x170 |
250 | #define EMAC_SOFTRESET 0x174 |
251 | #define EMAC_MACSRCADDRLO 0x1D0 |
252 | #define EMAC_MACSRCADDRHI 0x1D4 |
253 | #define EMAC_MACHASH1 0x1D8 |
254 | #define EMAC_MACHASH2 0x1DC |
255 | #define EMAC_MACADDRLO 0x500 |
256 | #define EMAC_MACADDRHI 0x504 |
257 | #define EMAC_MACINDEX 0x508 |
258 | |
259 | /* EMAC HDP and Completion registors */ |
260 | #define EMAC_TXHDP(ch) (0x600 + (ch * 4)) |
261 | #define EMAC_RXHDP(ch) (0x620 + (ch * 4)) |
262 | #define EMAC_TXCP(ch) (0x640 + (ch * 4)) |
263 | #define EMAC_RXCP(ch) (0x660 + (ch * 4)) |
264 | |
265 | /* EMAC statistics registers */ |
266 | #define EMAC_RXGOODFRAMES 0x200 |
267 | #define EMAC_RXBCASTFRAMES 0x204 |
268 | #define EMAC_RXMCASTFRAMES 0x208 |
269 | #define EMAC_RXPAUSEFRAMES 0x20C |
270 | #define EMAC_RXCRCERRORS 0x210 |
271 | #define EMAC_RXALIGNCODEERRORS 0x214 |
272 | #define EMAC_RXOVERSIZED 0x218 |
273 | #define EMAC_RXJABBER 0x21C |
274 | #define EMAC_RXUNDERSIZED 0x220 |
275 | #define EMAC_RXFRAGMENTS 0x224 |
276 | #define EMAC_RXFILTERED 0x228 |
277 | #define EMAC_RXQOSFILTERED 0x22C |
278 | #define EMAC_RXOCTETS 0x230 |
279 | #define EMAC_TXGOODFRAMES 0x234 |
280 | #define EMAC_TXBCASTFRAMES 0x238 |
281 | #define EMAC_TXMCASTFRAMES 0x23C |
282 | #define EMAC_TXPAUSEFRAMES 0x240 |
283 | #define EMAC_TXDEFERRED 0x244 |
284 | #define EMAC_TXCOLLISION 0x248 |
285 | #define EMAC_TXSINGLECOLL 0x24C |
286 | #define EMAC_TXMULTICOLL 0x250 |
287 | #define EMAC_TXEXCESSIVECOLL 0x254 |
288 | #define EMAC_TXLATECOLL 0x258 |
289 | #define EMAC_TXUNDERRUN 0x25C |
290 | #define EMAC_TXCARRIERSENSE 0x260 |
291 | #define EMAC_TXOCTETS 0x264 |
292 | #define EMAC_NETOCTETS 0x280 |
293 | #define EMAC_RXSOFOVERRUNS 0x284 |
294 | #define EMAC_RXMOFOVERRUNS 0x288 |
295 | #define EMAC_RXDMAOVERRUNS 0x28C |
296 | |
297 | /* EMAC DM644x control registers */ |
298 | #define EMAC_CTRL_EWCTL (0x4) |
299 | #define EMAC_CTRL_EWINTTCNT (0x8) |
300 | |
301 | /* EMAC MDIO related */ |
302 | /* Mask & Control defines */ |
303 | #define MDIO_CONTROL_CLKDIV (0xFF) |
304 | #define MDIO_CONTROL_ENABLE BIT(30) |
305 | #define MDIO_USERACCESS_GO BIT(31) |
306 | #define MDIO_USERACCESS_WRITE BIT(30) |
307 | #define MDIO_USERACCESS_READ (0) |
308 | #define MDIO_USERACCESS_REGADR (0x1F << 21) |
309 | #define MDIO_USERACCESS_PHYADR (0x1F << 16) |
310 | #define MDIO_USERACCESS_DATA (0xFFFF) |
311 | #define MDIO_USERPHYSEL_LINKSEL BIT(7) |
312 | #define MDIO_VER_MODID (0xFFFF << 16) |
313 | #define MDIO_VER_REVMAJ (0xFF << 8) |
314 | #define MDIO_VER_REVMIN (0xFF) |
315 | |
316 | #define MDIO_USERACCESS(inst) (0x80 + (inst * 8)) |
317 | #define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8)) |
318 | #define MDIO_CONTROL (0x04) |
319 | |
320 | /* EMAC DM646X control module registers */ |
321 | #define EMAC_DM646X_CMRXINTEN (0x14) |
322 | #define EMAC_DM646X_CMTXINTEN (0x18) |
323 | |
324 | /* EMAC EOI codes for C0 */ |
325 | #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) |
326 | #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) |
327 | |
328 | /* EMAC Stats Clear Mask */ |
329 | #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) |
330 | |
331 | /** net_buf_obj: EMAC network bufferdata structure |
332 | * |
333 | * EMAC network buffer data structure |
334 | */ |
335 | struct emac_netbufobj { |
336 | void *buf_token; |
337 | char *data_ptr; |
338 | int length; |
339 | }; |
340 | |
341 | /** net_pkt_obj: EMAC network packet data structure |
342 | * |
343 | * EMAC network packet data structure - supports buffer list (for future) |
344 | */ |
345 | struct emac_netpktobj { |
346 | void *pkt_token; /* data token may hold tx/rx chan id */ |
347 | struct emac_netbufobj *buf_list; /* array of network buffer objects */ |
348 | int num_bufs; |
349 | int pkt_length; |
350 | }; |
351 | |
352 | /** emac_tx_bd: EMAC TX Buffer descriptor data structure |
353 | * |
354 | * EMAC TX Buffer descriptor data structure |
355 | */ |
356 | struct emac_tx_bd { |
357 | int h_next; |
358 | int buff_ptr; |
359 | int off_b_len; |
360 | int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ |
361 | struct emac_tx_bd __iomem *next; |
362 | void *buf_token; |
363 | }; |
364 | |
365 | /** emac_txch: EMAC TX Channel data structure |
366 | * |
367 | * EMAC TX Channel data structure |
368 | */ |
369 | struct emac_txch { |
370 | /* Config related */ |
371 | u32 num_bd; |
372 | u32 service_max; |
373 | |
374 | /* CPPI specific */ |
375 | u32 alloc_size; |
376 | void __iomem *bd_mem; |
377 | struct emac_tx_bd __iomem *bd_pool_head; |
378 | struct emac_tx_bd __iomem *active_queue_head; |
379 | struct emac_tx_bd __iomem *active_queue_tail; |
380 | struct emac_tx_bd __iomem *last_hw_bdprocessed; |
381 | u32 queue_active; |
382 | u32 teardown_pending; |
383 | u32 *tx_complete; |
384 | |
385 | /** statistics */ |
386 | u32 proc_count; /* TX: # of times emac_tx_bdproc is called */ |
387 | u32 mis_queued_packets; |
388 | u32 queue_reinit; |
389 | u32 end_of_queue_add; |
390 | u32 out_of_tx_bd; |
391 | u32 no_active_pkts; /* IRQ when there were no packets to process */ |
392 | u32 active_queue_count; |
393 | }; |
394 | |
395 | /** emac_rx_bd: EMAC RX Buffer descriptor data structure |
396 | * |
397 | * EMAC RX Buffer descriptor data structure |
398 | */ |
399 | struct emac_rx_bd { |
400 | int h_next; |
401 | int buff_ptr; |
402 | int off_b_len; |
403 | int mode; |
404 | struct emac_rx_bd __iomem *next; |
405 | void *data_ptr; |
406 | void *buf_token; |
407 | }; |
408 | |
409 | /** emac_rxch: EMAC RX Channel data structure |
410 | * |
411 | * EMAC RX Channel data structure |
412 | */ |
413 | struct emac_rxch { |
414 | /* configuration info */ |
415 | u32 num_bd; |
416 | u32 service_max; |
417 | u32 buf_size; |
418 | char mac_addr[6]; |
419 | |
420 | /** CPPI specific */ |
421 | u32 alloc_size; |
422 | void __iomem *bd_mem; |
423 | struct emac_rx_bd __iomem *bd_pool_head; |
424 | struct emac_rx_bd __iomem *active_queue_head; |
425 | struct emac_rx_bd __iomem *active_queue_tail; |
426 | u32 queue_active; |
427 | u32 teardown_pending; |
428 | |
429 | /* packet and buffer objects */ |
430 | struct emac_netpktobj pkt_queue; |
431 | struct emac_netbufobj buf_queue; |
432 | |
433 | /** statistics */ |
434 | u32 proc_count; /* number of times emac_rx_bdproc is called */ |
435 | u32 processed_bd; |
436 | u32 recycled_bd; |
437 | u32 out_of_rx_bd; |
438 | u32 out_of_rx_buffers; |
439 | u32 queue_reinit; |
440 | u32 end_of_queue_add; |
441 | u32 end_of_queue; |
442 | u32 mis_queued_packets; |
443 | }; |
444 | |
445 | /* emac_priv: EMAC private data structure |
446 | * |
447 | * EMAC adapter private data structure |
448 | */ |
449 | struct emac_priv { |
450 | u32 msg_enable; |
451 | struct net_device *ndev; |
452 | struct platform_device *pdev; |
453 | struct napi_struct napi; |
454 | char mac_addr[6]; |
455 | spinlock_t tx_lock; |
456 | spinlock_t rx_lock; |
457 | void __iomem *remap_addr; |
458 | u32 emac_base_phys; |
459 | void __iomem *emac_base; |
460 | void __iomem *ctrl_base; |
461 | void __iomem *emac_ctrl_ram; |
462 | u32 ctrl_ram_size; |
463 | u32 hw_ram_addr; |
464 | struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; |
465 | struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; |
466 | u32 link; /* 1=link on, 0=link off */ |
467 | u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ |
468 | u32 duplex; /* Link duplex: 0=Half, 1=Full */ |
469 | u32 rx_buf_size; |
470 | u32 isr_count; |
471 | u8 rmii_en; |
472 | u8 version; |
473 | struct net_device_stats net_dev_stats; |
474 | u32 mac_hash1; |
475 | u32 mac_hash2; |
476 | u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; |
477 | u32 rx_addr_type; |
478 | /* periodic timer required for MDIO polling */ |
479 | struct timer_list periodic_timer; |
480 | u32 periodic_ticks; |
481 | u32 timer_active; |
482 | u32 phy_mask; |
483 | /* mii_bus,phy members */ |
484 | struct mii_bus *mii_bus; |
485 | struct phy_device *phydev; |
486 | spinlock_t lock; |
487 | /*platform specific members*/ |
488 | void (*int_enable) (void); |
489 | void (*int_disable) (void); |
490 | }; |
491 | |
492 | /* clock frequency for EMAC */ |
493 | static struct clk *emac_clk; |
494 | static unsigned long emac_bus_frequency; |
495 | static unsigned long mdio_max_freq; |
496 | |
497 | #define emac_virt_to_phys(addr, priv) \ |
498 | (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \ |
499 | + priv->hw_ram_addr) |
500 | |
501 | /* Cache macros - Packet buffers would be from skb pool which is cached */ |
502 | #define EMAC_VIRT_NOCACHE(addr) (addr) |
503 | |
504 | /* DM644x does not have BD's in cached memory - so no cache functions */ |
505 | #define BD_CACHE_INVALIDATE(addr, size) |
506 | #define BD_CACHE_WRITEBACK(addr, size) |
507 | #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size) |
508 | |
509 | /* EMAC TX Host Error description strings */ |
510 | static char *emac_txhost_errcodes[16] = { |
511 | "No error", "SOP error", "Ownership bit not set in SOP buffer", |
512 | "Zero Next Buffer Descriptor Pointer Without EOP", |
513 | "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", |
514 | "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", |
515 | "Reserved", "Reserved", "Reserved", "Reserved" |
516 | }; |
517 | |
518 | /* EMAC RX Host Error description strings */ |
519 | static char *emac_rxhost_errcodes[16] = { |
520 | "No error", "Reserved", "Ownership bit not set in input buffer", |
521 | "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", |
522 | "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", |
523 | "Reserved", "Reserved", "Reserved", "Reserved" |
524 | }; |
525 | |
526 | /* Helper macros */ |
527 | #define emac_read(reg) ioread32(priv->emac_base + (reg)) |
528 | #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) |
529 | |
530 | #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) |
531 | #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) |
532 | |
533 | #define emac_mdio_read(reg) ioread32(bus->priv + (reg)) |
534 | #define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg))) |
535 | |
536 | /** |
537 | * emac_dump_regs: Dump important EMAC registers to debug terminal |
538 | * @priv: The DaVinci EMAC private adapter structure |
539 | * |
540 | * Executes ethtool set cmd & sets phy mode |
541 | * |
542 | */ |
543 | static void emac_dump_regs(struct emac_priv *priv) |
544 | { |
545 | struct device *emac_dev = &priv->ndev->dev; |
546 | |
547 | /* Print important registers in EMAC */ |
548 | dev_info(emac_dev, "EMAC Basic registers\n"); |
549 | dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n", |
550 | emac_ctrl_read(EMAC_CTRL_EWCTL), |
551 | emac_ctrl_read(EMAC_CTRL_EWINTTCNT)); |
552 | dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n", |
553 | emac_read(EMAC_TXIDVER), |
554 | ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"), |
555 | emac_read(EMAC_RXIDVER), |
556 | ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled")); |
557 | dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\ |
558 | "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW), |
559 | emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET)); |
560 | dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\ |
561 | "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW), |
562 | emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET)); |
563 | dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\ |
564 | "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW), |
565 | emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR)); |
566 | dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n", |
567 | emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL)); |
568 | dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\ |
569 | "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE), |
570 | emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN)); |
571 | dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\ |
572 | "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL), |
573 | emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG)); |
574 | dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n", |
575 | emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0))); |
576 | dev_info(emac_dev, "EMAC Statistics\n"); |
577 | dev_info(emac_dev, "EMAC: rx_good_frames:%d\n", |
578 | emac_read(EMAC_RXGOODFRAMES)); |
579 | dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n", |
580 | emac_read(EMAC_RXBCASTFRAMES)); |
581 | dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n", |
582 | emac_read(EMAC_RXMCASTFRAMES)); |
583 | dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n", |
584 | emac_read(EMAC_RXPAUSEFRAMES)); |
585 | dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n", |
586 | emac_read(EMAC_RXCRCERRORS)); |
587 | dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n", |
588 | emac_read(EMAC_RXALIGNCODEERRORS)); |
589 | dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n", |
590 | emac_read(EMAC_RXOVERSIZED)); |
591 | dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n", |
592 | emac_read(EMAC_RXJABBER)); |
593 | dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n", |
594 | emac_read(EMAC_RXUNDERSIZED)); |
595 | dev_info(emac_dev, "EMAC: rx_fragments:%d\n", |
596 | emac_read(EMAC_RXFRAGMENTS)); |
597 | dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n", |
598 | emac_read(EMAC_RXFILTERED)); |
599 | dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n", |
600 | emac_read(EMAC_RXQOSFILTERED)); |
601 | dev_info(emac_dev, "EMAC: rx_octets:%d\n", |
602 | emac_read(EMAC_RXOCTETS)); |
603 | dev_info(emac_dev, "EMAC: tx_goodframes:%d\n", |
604 | emac_read(EMAC_TXGOODFRAMES)); |
605 | dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n", |
606 | emac_read(EMAC_TXBCASTFRAMES)); |
607 | dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n", |
608 | emac_read(EMAC_TXMCASTFRAMES)); |
609 | dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n", |
610 | emac_read(EMAC_TXPAUSEFRAMES)); |
611 | dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n", |
612 | emac_read(EMAC_TXDEFERRED)); |
613 | dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n", |
614 | emac_read(EMAC_TXCOLLISION)); |
615 | dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n", |
616 | emac_read(EMAC_TXSINGLECOLL)); |
617 | dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n", |
618 | emac_read(EMAC_TXMULTICOLL)); |
619 | dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n", |
620 | emac_read(EMAC_TXEXCESSIVECOLL)); |
621 | dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n", |
622 | emac_read(EMAC_TXLATECOLL)); |
623 | dev_info(emac_dev, "EMAC: tx_underrun:%d\n", |
624 | emac_read(EMAC_TXUNDERRUN)); |
625 | dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n", |
626 | emac_read(EMAC_TXCARRIERSENSE)); |
627 | dev_info(emac_dev, "EMAC: tx_octets:%d\n", |
628 | emac_read(EMAC_TXOCTETS)); |
629 | dev_info(emac_dev, "EMAC: net_octets:%d\n", |
630 | emac_read(EMAC_NETOCTETS)); |
631 | dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n", |
632 | emac_read(EMAC_RXSOFOVERRUNS)); |
633 | dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n", |
634 | emac_read(EMAC_RXMOFOVERRUNS)); |
635 | dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n", |
636 | emac_read(EMAC_RXDMAOVERRUNS)); |
637 | } |
638 | |
639 | /************************************************************************* |
640 | * EMAC MDIO/Phy Functionality |
641 | *************************************************************************/ |
642 | /** |
643 | * emac_get_drvinfo: Get EMAC driver information |
644 | * @ndev: The DaVinci EMAC network adapter |
645 | * @info: ethtool info structure containing name and version |
646 | * |
647 | * Returns EMAC driver information (name and version) |
648 | * |
649 | */ |
650 | static void emac_get_drvinfo(struct net_device *ndev, |
651 | struct ethtool_drvinfo *info) |
652 | { |
653 | strcpy(info->driver, emac_version_string); |
654 | strcpy(info->version, EMAC_MODULE_VERSION); |
655 | } |
656 | |
657 | /** |
658 | * emac_get_settings: Get EMAC settings |
659 | * @ndev: The DaVinci EMAC network adapter |
660 | * @ecmd: ethtool command |
661 | * |
662 | * Executes ethool get command |
663 | * |
664 | */ |
665 | static int emac_get_settings(struct net_device *ndev, |
666 | struct ethtool_cmd *ecmd) |
667 | { |
668 | struct emac_priv *priv = netdev_priv(ndev); |
669 | if (priv->phy_mask) |
670 | return phy_ethtool_gset(priv->phydev, ecmd); |
671 | else |
672 | return -EOPNOTSUPP; |
673 | |
674 | } |
675 | |
676 | /** |
677 | * emac_set_settings: Set EMAC settings |
678 | * @ndev: The DaVinci EMAC network adapter |
679 | * @ecmd: ethtool command |
680 | * |
681 | * Executes ethool set command |
682 | * |
683 | */ |
684 | static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) |
685 | { |
686 | struct emac_priv *priv = netdev_priv(ndev); |
687 | if (priv->phy_mask) |
688 | return phy_ethtool_sset(priv->phydev, ecmd); |
689 | else |
690 | return -EOPNOTSUPP; |
691 | |
692 | } |
693 | |
694 | /** |
695 | * ethtool_ops: DaVinci EMAC Ethtool structure |
696 | * |
697 | * Ethtool support for EMAC adapter |
698 | * |
699 | */ |
700 | static const struct ethtool_ops ethtool_ops = { |
701 | .get_drvinfo = emac_get_drvinfo, |
702 | .get_settings = emac_get_settings, |
703 | .set_settings = emac_set_settings, |
704 | .get_link = ethtool_op_get_link, |
705 | }; |
706 | |
707 | /** |
708 | * emac_update_phystatus: Update Phy status |
709 | * @priv: The DaVinci EMAC private adapter structure |
710 | * |
711 | * Updates phy status and takes action for network queue if required |
712 | * based upon link status |
713 | * |
714 | */ |
715 | static void emac_update_phystatus(struct emac_priv *priv) |
716 | { |
717 | u32 mac_control; |
718 | u32 new_duplex; |
719 | u32 cur_duplex; |
720 | struct net_device *ndev = priv->ndev; |
721 | |
722 | mac_control = emac_read(EMAC_MACCONTROL); |
723 | cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? |
724 | DUPLEX_FULL : DUPLEX_HALF; |
725 | if (priv->phy_mask) |
726 | new_duplex = priv->phydev->duplex; |
727 | else |
728 | new_duplex = DUPLEX_FULL; |
729 | |
730 | /* We get called only if link has changed (speed/duplex/status) */ |
731 | if ((priv->link) && (new_duplex != cur_duplex)) { |
732 | priv->duplex = new_duplex; |
733 | if (DUPLEX_FULL == priv->duplex) |
734 | mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); |
735 | else |
736 | mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); |
737 | } |
738 | |
739 | if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { |
740 | mac_control = emac_read(EMAC_MACCONTROL); |
741 | mac_control |= (EMAC_DM646X_MACCONTORL_GIG | |
742 | EMAC_DM646X_MACCONTORL_GIGFORCE); |
743 | } else { |
744 | /* Clear the GIG bit and GIGFORCE bit */ |
745 | mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | |
746 | EMAC_DM646X_MACCONTORL_GIG); |
747 | |
748 | if (priv->rmii_en && (priv->speed == SPEED_100)) |
749 | mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; |
750 | else |
751 | mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; |
752 | } |
753 | |
754 | /* Update mac_control if changed */ |
755 | emac_write(EMAC_MACCONTROL, mac_control); |
756 | |
757 | if (priv->link) { |
758 | /* link ON */ |
759 | if (!netif_carrier_ok(ndev)) |
760 | netif_carrier_on(ndev); |
761 | /* reactivate the transmit queue if it is stopped */ |
762 | if (netif_running(ndev) && netif_queue_stopped(ndev)) |
763 | netif_wake_queue(ndev); |
764 | } else { |
765 | /* link OFF */ |
766 | if (netif_carrier_ok(ndev)) |
767 | netif_carrier_off(ndev); |
768 | if (!netif_queue_stopped(ndev)) |
769 | netif_stop_queue(ndev); |
770 | } |
771 | } |
772 | |
773 | /** |
774 | * hash_get: Calculate hash value from mac address |
775 | * @addr: mac address to delete from hash table |
776 | * |
777 | * Calculates hash value from mac address |
778 | * |
779 | */ |
780 | static u32 hash_get(u8 *addr) |
781 | { |
782 | u32 hash; |
783 | u8 tmpval; |
784 | int cnt; |
785 | hash = 0; |
786 | |
787 | for (cnt = 0; cnt < 2; cnt++) { |
788 | tmpval = *addr++; |
789 | hash ^= (tmpval >> 2) ^ (tmpval << 4); |
790 | tmpval = *addr++; |
791 | hash ^= (tmpval >> 4) ^ (tmpval << 2); |
792 | tmpval = *addr++; |
793 | hash ^= (tmpval >> 6) ^ (tmpval); |
794 | } |
795 | |
796 | return hash & 0x3F; |
797 | } |
798 | |
799 | /** |
800 | * hash_add: Hash function to add mac addr from hash table |
801 | * @priv: The DaVinci EMAC private adapter structure |
802 | * mac_addr: mac address to delete from hash table |
803 | * |
804 | * Adds mac address to the internal hash table |
805 | * |
806 | */ |
807 | static int hash_add(struct emac_priv *priv, u8 *mac_addr) |
808 | { |
809 | struct device *emac_dev = &priv->ndev->dev; |
810 | u32 rc = 0; |
811 | u32 hash_bit; |
812 | u32 hash_value = hash_get(mac_addr); |
813 | |
814 | if (hash_value >= EMAC_NUM_MULTICAST_BITS) { |
815 | if (netif_msg_drv(priv)) { |
816 | dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\ |
817 | "Hash %08x, should not be greater than %08x", |
818 | hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); |
819 | } |
820 | return -1; |
821 | } |
822 | |
823 | /* set the hash bit only if not previously set */ |
824 | if (priv->multicast_hash_cnt[hash_value] == 0) { |
825 | rc = 1; /* hash value changed */ |
826 | if (hash_value < 32) { |
827 | hash_bit = BIT(hash_value); |
828 | priv->mac_hash1 |= hash_bit; |
829 | } else { |
830 | hash_bit = BIT((hash_value - 32)); |
831 | priv->mac_hash2 |= hash_bit; |
832 | } |
833 | } |
834 | |
835 | /* incr counter for num of mcast addr's mapped to "this" hash bit */ |
836 | ++priv->multicast_hash_cnt[hash_value]; |
837 | |
838 | return rc; |
839 | } |
840 | |
841 | /** |
842 | * hash_del: Hash function to delete mac addr from hash table |
843 | * @priv: The DaVinci EMAC private adapter structure |
844 | * mac_addr: mac address to delete from hash table |
845 | * |
846 | * Removes mac address from the internal hash table |
847 | * |
848 | */ |
849 | static int hash_del(struct emac_priv *priv, u8 *mac_addr) |
850 | { |
851 | u32 hash_value; |
852 | u32 hash_bit; |
853 | |
854 | hash_value = hash_get(mac_addr); |
855 | if (priv->multicast_hash_cnt[hash_value] > 0) { |
856 | /* dec cntr for num of mcast addr's mapped to this hash bit */ |
857 | --priv->multicast_hash_cnt[hash_value]; |
858 | } |
859 | |
860 | /* if counter still > 0, at least one multicast address refers |
861 | * to this hash bit. so return 0 */ |
862 | if (priv->multicast_hash_cnt[hash_value] > 0) |
863 | return 0; |
864 | |
865 | if (hash_value < 32) { |
866 | hash_bit = BIT(hash_value); |
867 | priv->mac_hash1 &= ~hash_bit; |
868 | } else { |
869 | hash_bit = BIT((hash_value - 32)); |
870 | priv->mac_hash2 &= ~hash_bit; |
871 | } |
872 | |
873 | /* return 1 to indicate change in mac_hash registers reqd */ |
874 | return 1; |
875 | } |
876 | |
877 | /* EMAC multicast operation */ |
878 | #define EMAC_MULTICAST_ADD 0 |
879 | #define EMAC_MULTICAST_DEL 1 |
880 | #define EMAC_ALL_MULTI_SET 2 |
881 | #define EMAC_ALL_MULTI_CLR 3 |
882 | |
883 | /** |
884 | * emac_add_mcast: Set multicast address in the EMAC adapter (Internal) |
885 | * @priv: The DaVinci EMAC private adapter structure |
886 | * @action: multicast operation to perform |
887 | * mac_addr: mac address to set |
888 | * |
889 | * Set multicast addresses in EMAC adapter - internal function |
890 | * |
891 | */ |
892 | static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) |
893 | { |
894 | struct device *emac_dev = &priv->ndev->dev; |
895 | int update = -1; |
896 | |
897 | switch (action) { |
898 | case EMAC_MULTICAST_ADD: |
899 | update = hash_add(priv, mac_addr); |
900 | break; |
901 | case EMAC_MULTICAST_DEL: |
902 | update = hash_del(priv, mac_addr); |
903 | break; |
904 | case EMAC_ALL_MULTI_SET: |
905 | update = 1; |
906 | priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; |
907 | priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; |
908 | break; |
909 | case EMAC_ALL_MULTI_CLR: |
910 | update = 1; |
911 | priv->mac_hash1 = 0; |
912 | priv->mac_hash2 = 0; |
913 | memset(&(priv->multicast_hash_cnt[0]), 0, |
914 | sizeof(priv->multicast_hash_cnt[0]) * |
915 | EMAC_NUM_MULTICAST_BITS); |
916 | break; |
917 | default: |
918 | if (netif_msg_drv(priv)) |
919 | dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ |
920 | ": bad operation %d", action); |
921 | break; |
922 | } |
923 | |
924 | /* write to the hardware only if the register status chances */ |
925 | if (update > 0) { |
926 | emac_write(EMAC_MACHASH1, priv->mac_hash1); |
927 | emac_write(EMAC_MACHASH2, priv->mac_hash2); |
928 | } |
929 | } |
930 | |
931 | /** |
932 | * emac_dev_mcast_set: Set multicast address in the EMAC adapter |
933 | * @ndev: The DaVinci EMAC network adapter |
934 | * |
935 | * Set multicast addresses in EMAC adapter |
936 | * |
937 | */ |
938 | static void emac_dev_mcast_set(struct net_device *ndev) |
939 | { |
940 | u32 mbp_enable; |
941 | struct emac_priv *priv = netdev_priv(ndev); |
942 | |
943 | mbp_enable = emac_read(EMAC_RXMBPENABLE); |
944 | if (ndev->flags & IFF_PROMISC) { |
945 | mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); |
946 | mbp_enable |= (EMAC_MBP_RXPROMISC); |
947 | } else { |
948 | mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); |
949 | if ((ndev->flags & IFF_ALLMULTI) || |
950 | netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { |
951 | mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); |
952 | emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); |
953 | } |
954 | if (!netdev_mc_empty(ndev)) { |
955 | struct dev_mc_list *mc_ptr; |
956 | mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); |
957 | emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); |
958 | /* program multicast address list into EMAC hardware */ |
959 | netdev_for_each_mc_addr(mc_ptr, ndev) { |
960 | emac_add_mcast(priv, EMAC_MULTICAST_ADD, |
961 | (u8 *) mc_ptr->dmi_addr); |
962 | } |
963 | } else { |
964 | mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); |
965 | emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); |
966 | } |
967 | } |
968 | /* Set mbp config register */ |
969 | emac_write(EMAC_RXMBPENABLE, mbp_enable); |
970 | } |
971 | |
972 | /************************************************************************* |
973 | * EMAC Hardware manipulation |
974 | *************************************************************************/ |
975 | |
976 | /** |
977 | * emac_int_disable: Disable EMAC module interrupt (from adapter) |
978 | * @priv: The DaVinci EMAC private adapter structure |
979 | * |
980 | * Disable EMAC interrupt on the adapter |
981 | * |
982 | */ |
983 | static void emac_int_disable(struct emac_priv *priv) |
984 | { |
985 | if (priv->version == EMAC_VERSION_2) { |
986 | unsigned long flags; |
987 | |
988 | local_irq_save(flags); |
989 | |
990 | /* Program C0_Int_En to zero to turn off |
991 | * interrupts to the CPU */ |
992 | emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); |
993 | emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); |
994 | /* NOTE: Rx Threshold and Misc interrupts are not disabled */ |
995 | if (priv->int_disable) |
996 | priv->int_disable(); |
997 | |
998 | local_irq_restore(flags); |
999 | |
1000 | } else { |
1001 | /* Set DM644x control registers for interrupt control */ |
1002 | emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); |
1003 | } |
1004 | } |
1005 | |
1006 | /** |
1007 | * emac_int_enable: Enable EMAC module interrupt (from adapter) |
1008 | * @priv: The DaVinci EMAC private adapter structure |
1009 | * |
1010 | * Enable EMAC interrupt on the adapter |
1011 | * |
1012 | */ |
1013 | static void emac_int_enable(struct emac_priv *priv) |
1014 | { |
1015 | if (priv->version == EMAC_VERSION_2) { |
1016 | if (priv->int_enable) |
1017 | priv->int_enable(); |
1018 | |
1019 | emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); |
1020 | emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); |
1021 | |
1022 | /* In addition to turning on interrupt Enable, we need |
1023 | * ack by writing appropriate values to the EOI |
1024 | * register */ |
1025 | |
1026 | /* NOTE: Rx Threshold and Misc interrupts are not enabled */ |
1027 | |
1028 | /* ack rxen only then a new pulse will be generated */ |
1029 | emac_write(EMAC_DM646X_MACEOIVECTOR, |
1030 | EMAC_DM646X_MAC_EOI_C0_RXEN); |
1031 | |
1032 | /* ack txen- only then a new pulse will be generated */ |
1033 | emac_write(EMAC_DM646X_MACEOIVECTOR, |
1034 | EMAC_DM646X_MAC_EOI_C0_TXEN); |
1035 | |
1036 | } else { |
1037 | /* Set DM644x control registers for interrupt control */ |
1038 | emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); |
1039 | } |
1040 | } |
1041 | |
1042 | /** |
1043 | * emac_irq: EMAC interrupt handler |
1044 | * @irq: interrupt number |
1045 | * @dev_id: EMAC network adapter data structure ptr |
1046 | * |
1047 | * EMAC Interrupt handler - we only schedule NAPI and not process any packets |
1048 | * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function |
1049 | * |
1050 | * Returns interrupt handled condition |
1051 | */ |
1052 | static irqreturn_t emac_irq(int irq, void *dev_id) |
1053 | { |
1054 | struct net_device *ndev = (struct net_device *)dev_id; |
1055 | struct emac_priv *priv = netdev_priv(ndev); |
1056 | |
1057 | ++priv->isr_count; |
1058 | if (likely(netif_running(priv->ndev))) { |
1059 | emac_int_disable(priv); |
1060 | napi_schedule(&priv->napi); |
1061 | } else { |
1062 | /* we are closing down, so dont process anything */ |
1063 | } |
1064 | return IRQ_HANDLED; |
1065 | } |
1066 | |
1067 | /** EMAC on-chip buffer descriptor memory |
1068 | * |
1069 | * WARNING: Please note that the on chip memory is used for both TX and RX |
1070 | * buffer descriptor queues and is equally divided between TX and RX desc's |
1071 | * If the number of TX or RX descriptors change this memory pointers need |
1072 | * to be adjusted. If external memory is allocated then these pointers can |
1073 | * pointer to the memory |
1074 | * |
1075 | */ |
1076 | #define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram) |
1077 | #define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \ |
1078 | (((priv)->ctrl_ram_size) >> 1)) |
1079 | |
1080 | /** |
1081 | * emac_init_txch: TX channel initialization |
1082 | * @priv: The DaVinci EMAC private adapter structure |
1083 | * @ch: RX channel number |
1084 | * |
1085 | * Called during device init to setup a TX channel (allocate buffer desc |
1086 | * create free pool and keep ready for transmission |
1087 | * |
1088 | * Returns success(0) or mem alloc failures error code |
1089 | */ |
1090 | static int emac_init_txch(struct emac_priv *priv, u32 ch) |
1091 | { |
1092 | struct device *emac_dev = &priv->ndev->dev; |
1093 | u32 cnt, bd_size; |
1094 | void __iomem *mem; |
1095 | struct emac_tx_bd __iomem *curr_bd; |
1096 | struct emac_txch *txch = NULL; |
1097 | |
1098 | txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL); |
1099 | if (NULL == txch) { |
1100 | dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed"); |
1101 | return -ENOMEM; |
1102 | } |
1103 | priv->txch[ch] = txch; |
1104 | txch->service_max = EMAC_DEF_TX_MAX_SERVICE; |
1105 | txch->active_queue_head = NULL; |
1106 | txch->active_queue_tail = NULL; |
1107 | txch->queue_active = 0; |
1108 | txch->teardown_pending = 0; |
1109 | |
1110 | /* allocate memory for TX CPPI channel on a 4 byte boundry */ |
1111 | txch->tx_complete = kzalloc(txch->service_max * sizeof(u32), |
1112 | GFP_KERNEL); |
1113 | if (NULL == txch->tx_complete) { |
1114 | dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed"); |
1115 | kfree(txch); |
1116 | return -ENOMEM; |
1117 | } |
1118 | |
1119 | /* allocate buffer descriptor pool align every BD on four word |
1120 | * boundry for future requirements */ |
1121 | bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF; |
1122 | txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; |
1123 | txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF); |
1124 | |
1125 | /* alloc TX BD memory */ |
1126 | txch->bd_mem = EMAC_TX_BD_MEM(priv); |
1127 | __memzero((void __force *)txch->bd_mem, txch->alloc_size); |
1128 | |
1129 | /* initialize the BD linked list */ |
1130 | mem = (void __force __iomem *) |
1131 | (((u32 __force) txch->bd_mem + 0xF) & ~0xF); |
1132 | txch->bd_pool_head = NULL; |
1133 | for (cnt = 0; cnt < txch->num_bd; cnt++) { |
1134 | curr_bd = mem + (cnt * bd_size); |
1135 | curr_bd->next = txch->bd_pool_head; |
1136 | txch->bd_pool_head = curr_bd; |
1137 | } |
1138 | |
1139 | /* reset statistics counters */ |
1140 | txch->out_of_tx_bd = 0; |
1141 | txch->no_active_pkts = 0; |
1142 | txch->active_queue_count = 0; |
1143 | |
1144 | return 0; |
1145 | } |
1146 | |
1147 | /** |
1148 | * emac_cleanup_txch: Book-keep function to clean TX channel resources |
1149 | * @priv: The DaVinci EMAC private adapter structure |
1150 | * @ch: TX channel number |
1151 | * |
1152 | * Called to clean up TX channel resources |
1153 | * |
1154 | */ |
1155 | static void emac_cleanup_txch(struct emac_priv *priv, u32 ch) |
1156 | { |
1157 | struct emac_txch *txch = priv->txch[ch]; |
1158 | |
1159 | if (txch) { |
1160 | if (txch->bd_mem) |
1161 | txch->bd_mem = NULL; |
1162 | kfree(txch->tx_complete); |
1163 | kfree(txch); |
1164 | priv->txch[ch] = NULL; |
1165 | } |
1166 | } |
1167 | |
1168 | /** |
1169 | * emac_net_tx_complete: TX packet completion function |
1170 | * @priv: The DaVinci EMAC private adapter structure |
1171 | * @net_data_tokens: packet token - skb pointer |
1172 | * @num_tokens: number of skb's to free |
1173 | * @ch: TX channel number |
1174 | * |
1175 | * Frees the skb once packet is transmitted |
1176 | * |
1177 | */ |
1178 | static int emac_net_tx_complete(struct emac_priv *priv, |
1179 | void **net_data_tokens, |
1180 | int num_tokens, u32 ch) |
1181 | { |
1182 | u32 cnt; |
1183 | |
1184 | if (unlikely(num_tokens && netif_queue_stopped(priv->ndev))) |
1185 | netif_start_queue(priv->ndev); |
1186 | for (cnt = 0; cnt < num_tokens; cnt++) { |
1187 | struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt]; |
1188 | if (skb == NULL) |
1189 | continue; |
1190 | priv->net_dev_stats.tx_packets++; |
1191 | priv->net_dev_stats.tx_bytes += skb->len; |
1192 | dev_kfree_skb_any(skb); |
1193 | } |
1194 | return 0; |
1195 | } |
1196 | |
1197 | /** |
1198 | * emac_txch_teardown: TX channel teardown |
1199 | * @priv: The DaVinci EMAC private adapter structure |
1200 | * @ch: TX channel number |
1201 | * |
1202 | * Called to teardown TX channel |
1203 | * |
1204 | */ |
1205 | static void emac_txch_teardown(struct emac_priv *priv, u32 ch) |
1206 | { |
1207 | struct device *emac_dev = &priv->ndev->dev; |
1208 | u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */ |
1209 | struct emac_txch *txch = priv->txch[ch]; |
1210 | struct emac_tx_bd __iomem *curr_bd; |
1211 | |
1212 | while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) != |
1213 | EMAC_TEARDOWN_VALUE) { |
1214 | /* wait till tx teardown complete */ |
1215 | cpu_relax(); /* TODO: check if this helps ... */ |
1216 | --teardown_cnt; |
1217 | if (0 == teardown_cnt) { |
1218 | dev_err(emac_dev, "EMAC: TX teardown aborted\n"); |
1219 | break; |
1220 | } |
1221 | } |
1222 | emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE); |
1223 | |
1224 | /* process sent packets and return skb's to upper layer */ |
1225 | if (1 == txch->queue_active) { |
1226 | curr_bd = txch->active_queue_head; |
1227 | while (curr_bd != NULL) { |
1228 | dma_unmap_single(emac_dev, curr_bd->buff_ptr, |
1229 | curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE, |
1230 | DMA_TO_DEVICE); |
1231 | |
1232 | emac_net_tx_complete(priv, (void __force *) |
1233 | &curr_bd->buf_token, 1, ch); |
1234 | if (curr_bd != txch->active_queue_tail) |
1235 | curr_bd = curr_bd->next; |
1236 | else |
1237 | break; |
1238 | } |
1239 | txch->bd_pool_head = txch->active_queue_head; |
1240 | txch->active_queue_head = |
1241 | txch->active_queue_tail = NULL; |
1242 | } |
1243 | } |
1244 | |
1245 | /** |
1246 | * emac_stop_txch: Stop TX channel operation |
1247 | * @priv: The DaVinci EMAC private adapter structure |
1248 | * @ch: TX channel number |
1249 | * |
1250 | * Called to stop TX channel operation |
1251 | * |
1252 | */ |
1253 | static void emac_stop_txch(struct emac_priv *priv, u32 ch) |
1254 | { |
1255 | struct emac_txch *txch = priv->txch[ch]; |
1256 | |
1257 | if (txch) { |
1258 | txch->teardown_pending = 1; |
1259 | emac_write(EMAC_TXTEARDOWN, 0); |
1260 | emac_txch_teardown(priv, ch); |
1261 | txch->teardown_pending = 0; |
1262 | emac_write(EMAC_TXINTMASKCLEAR, BIT(ch)); |
1263 | } |
1264 | } |
1265 | |
1266 | /** |
1267 | * emac_tx_bdproc: TX buffer descriptor (packet) processing |
1268 | * @priv: The DaVinci EMAC private adapter structure |
1269 | * @ch: TX channel number to process buffer descriptors for |
1270 | * @budget: number of packets allowed to process |
1271 | * @pending: indication to caller that packets are pending to process |
1272 | * |
1273 | * Processes TX buffer descriptors after packets are transmitted - checks |
1274 | * ownership bit on the TX * descriptor and requeues it to free pool & frees |
1275 | * the SKB buffer. Only "budget" number of packets are processed and |
1276 | * indication of pending packets provided to the caller |
1277 | * |
1278 | * Returns number of packets processed |
1279 | */ |
1280 | static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget) |
1281 | { |
1282 | struct device *emac_dev = &priv->ndev->dev; |
1283 | unsigned long flags; |
1284 | u32 frame_status; |
1285 | u32 pkts_processed = 0; |
1286 | u32 tx_complete_cnt = 0; |
1287 | struct emac_tx_bd __iomem *curr_bd; |
1288 | struct emac_txch *txch = priv->txch[ch]; |
1289 | u32 *tx_complete_ptr = txch->tx_complete; |
1290 | |
1291 | if (unlikely(1 == txch->teardown_pending)) { |
1292 | if (netif_msg_tx_err(priv) && net_ratelimit()) { |
1293 | dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\ |
1294 | "teardown pending\n"); |
1295 | } |
1296 | return 0; /* dont handle any pkt completions */ |
1297 | } |
1298 | |
1299 | ++txch->proc_count; |
1300 | spin_lock_irqsave(&priv->tx_lock, flags); |
1301 | curr_bd = txch->active_queue_head; |
1302 | if (NULL == curr_bd) { |
1303 | emac_write(EMAC_TXCP(ch), |
1304 | emac_virt_to_phys(txch->last_hw_bdprocessed, priv)); |
1305 | txch->no_active_pkts++; |
1306 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
1307 | return 0; |
1308 | } |
1309 | BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); |
1310 | frame_status = curr_bd->mode; |
1311 | while ((curr_bd) && |
1312 | ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && |
1313 | (pkts_processed < budget)) { |
1314 | emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv)); |
1315 | txch->active_queue_head = curr_bd->next; |
1316 | if (frame_status & EMAC_CPPI_EOQ_BIT) { |
1317 | if (curr_bd->next) { /* misqueued packet */ |
1318 | emac_write(EMAC_TXHDP(ch), curr_bd->h_next); |
1319 | ++txch->mis_queued_packets; |
1320 | } else { |
1321 | txch->queue_active = 0; /* end of queue */ |
1322 | } |
1323 | } |
1324 | |
1325 | dma_unmap_single(emac_dev, curr_bd->buff_ptr, |
1326 | curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE, |
1327 | DMA_TO_DEVICE); |
1328 | |
1329 | *tx_complete_ptr = (u32) curr_bd->buf_token; |
1330 | ++tx_complete_ptr; |
1331 | ++tx_complete_cnt; |
1332 | curr_bd->next = txch->bd_pool_head; |
1333 | txch->bd_pool_head = curr_bd; |
1334 | --txch->active_queue_count; |
1335 | pkts_processed++; |
1336 | txch->last_hw_bdprocessed = curr_bd; |
1337 | curr_bd = txch->active_queue_head; |
1338 | if (curr_bd) { |
1339 | BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); |
1340 | frame_status = curr_bd->mode; |
1341 | } |
1342 | } /* end of pkt processing loop */ |
1343 | |
1344 | emac_net_tx_complete(priv, |
1345 | (void *)&txch->tx_complete[0], |
1346 | tx_complete_cnt, ch); |
1347 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
1348 | return pkts_processed; |
1349 | } |
1350 | |
1351 | #define EMAC_ERR_TX_OUT_OF_BD -1 |
1352 | |
1353 | /** |
1354 | * emac_send: EMAC Transmit function (internal) |
1355 | * @priv: The DaVinci EMAC private adapter structure |
1356 | * @pkt: packet pointer (contains skb ptr) |
1357 | * @ch: TX channel number |
1358 | * |
1359 | * Called by the transmit function to queue the packet in EMAC hardware queue |
1360 | * |
1361 | * Returns success(0) or error code (typically out of desc's) |
1362 | */ |
1363 | static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch) |
1364 | { |
1365 | unsigned long flags; |
1366 | struct emac_tx_bd __iomem *curr_bd; |
1367 | struct emac_txch *txch; |
1368 | struct emac_netbufobj *buf_list; |
1369 | |
1370 | txch = priv->txch[ch]; |
1371 | buf_list = pkt->buf_list; /* get handle to the buffer array */ |
1372 | |
1373 | /* check packet size and pad if short */ |
1374 | if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { |
1375 | buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); |
1376 | pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; |
1377 | } |
1378 | |
1379 | spin_lock_irqsave(&priv->tx_lock, flags); |
1380 | curr_bd = txch->bd_pool_head; |
1381 | if (curr_bd == NULL) { |
1382 | txch->out_of_tx_bd++; |
1383 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
1384 | return EMAC_ERR_TX_OUT_OF_BD; |
1385 | } |
1386 | |
1387 | txch->bd_pool_head = curr_bd->next; |
1388 | curr_bd->buf_token = buf_list->buf_token; |
1389 | curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buf_list->data_ptr, |
1390 | buf_list->length, DMA_TO_DEVICE); |
1391 | curr_bd->off_b_len = buf_list->length; |
1392 | curr_bd->h_next = 0; |
1393 | curr_bd->next = NULL; |
1394 | curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | |
1395 | EMAC_CPPI_EOP_BIT | pkt->pkt_length); |
1396 | |
1397 | /* flush the packet from cache if write back cache is present */ |
1398 | BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); |
1399 | |
1400 | /* send the packet */ |
1401 | if (txch->active_queue_head == NULL) { |
1402 | txch->active_queue_head = curr_bd; |
1403 | txch->active_queue_tail = curr_bd; |
1404 | if (1 != txch->queue_active) { |
1405 | emac_write(EMAC_TXHDP(ch), |
1406 | emac_virt_to_phys(curr_bd, priv)); |
1407 | txch->queue_active = 1; |
1408 | } |
1409 | ++txch->queue_reinit; |
1410 | } else { |
1411 | register struct emac_tx_bd __iomem *tail_bd; |
1412 | register u32 frame_status; |
1413 | |
1414 | tail_bd = txch->active_queue_tail; |
1415 | tail_bd->next = curr_bd; |
1416 | txch->active_queue_tail = curr_bd; |
1417 | tail_bd = EMAC_VIRT_NOCACHE(tail_bd); |
1418 | tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv); |
1419 | frame_status = tail_bd->mode; |
1420 | if (frame_status & EMAC_CPPI_EOQ_BIT) { |
1421 | emac_write(EMAC_TXHDP(ch), |
1422 | emac_virt_to_phys(curr_bd, priv)); |
1423 | frame_status &= ~(EMAC_CPPI_EOQ_BIT); |
1424 | tail_bd->mode = frame_status; |
1425 | ++txch->end_of_queue_add; |
1426 | } |
1427 | } |
1428 | txch->active_queue_count++; |
1429 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
1430 | return 0; |
1431 | } |
1432 | |
1433 | /** |
1434 | * emac_dev_xmit: EMAC Transmit function |
1435 | * @skb: SKB pointer |
1436 | * @ndev: The DaVinci EMAC network adapter |
1437 | * |
1438 | * Called by the system to transmit a packet - we queue the packet in |
1439 | * EMAC hardware transmit queue |
1440 | * |
1441 | * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) |
1442 | */ |
1443 | static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) |
1444 | { |
1445 | struct device *emac_dev = &ndev->dev; |
1446 | int ret_code; |
1447 | struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */ |
1448 | struct emac_netpktobj tx_packet; /* packet object */ |
1449 | struct emac_priv *priv = netdev_priv(ndev); |
1450 | |
1451 | /* If no link, return */ |
1452 | if (unlikely(!priv->link)) { |
1453 | if (netif_msg_tx_err(priv) && net_ratelimit()) |
1454 | dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); |
1455 | return NETDEV_TX_BUSY; |
1456 | } |
1457 | |
1458 | /* Build the buffer and packet objects - Since only single fragment is |
1459 | * supported, need not set length and token in both packet & object. |
1460 | * Doing so for completeness sake & to show that this needs to be done |
1461 | * in multifragment case |
1462 | */ |
1463 | tx_packet.buf_list = &tx_buf; |
1464 | tx_packet.num_bufs = 1; /* only single fragment supported */ |
1465 | tx_packet.pkt_length = skb->len; |
1466 | tx_packet.pkt_token = (void *)skb; |
1467 | tx_buf.length = skb->len; |
1468 | tx_buf.buf_token = (void *)skb; |
1469 | tx_buf.data_ptr = skb->data; |
1470 | ndev->trans_start = jiffies; |
1471 | ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); |
1472 | if (unlikely(ret_code != 0)) { |
1473 | if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { |
1474 | if (netif_msg_tx_err(priv) && net_ratelimit()) |
1475 | dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\ |
1476 | " err. Out of TX BD's"); |
1477 | netif_stop_queue(priv->ndev); |
1478 | } |
1479 | priv->net_dev_stats.tx_dropped++; |
1480 | return NETDEV_TX_BUSY; |
1481 | } |
1482 | |
1483 | return NETDEV_TX_OK; |
1484 | } |
1485 | |
1486 | /** |
1487 | * emac_dev_tx_timeout: EMAC Transmit timeout function |
1488 | * @ndev: The DaVinci EMAC network adapter |
1489 | * |
1490 | * Called when system detects that a skb timeout period has expired |
1491 | * potentially due to a fault in the adapter in not being able to send |
1492 | * it out on the wire. We teardown the TX channel assuming a hardware |
1493 | * error and re-initialize the TX channel for hardware operation |
1494 | * |
1495 | */ |
1496 | static void emac_dev_tx_timeout(struct net_device *ndev) |
1497 | { |
1498 | struct emac_priv *priv = netdev_priv(ndev); |
1499 | struct device *emac_dev = &ndev->dev; |
1500 | |
1501 | if (netif_msg_tx_err(priv)) |
1502 | dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); |
1503 | |
1504 | priv->net_dev_stats.tx_errors++; |
1505 | emac_int_disable(priv); |
1506 | emac_stop_txch(priv, EMAC_DEF_TX_CH); |
1507 | emac_cleanup_txch(priv, EMAC_DEF_TX_CH); |
1508 | emac_init_txch(priv, EMAC_DEF_TX_CH); |
1509 | emac_write(EMAC_TXHDP(0), 0); |
1510 | emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH)); |
1511 | emac_int_enable(priv); |
1512 | } |
1513 | |
1514 | /** |
1515 | * emac_net_alloc_rx_buf: Allocate a skb for RX |
1516 | * @priv: The DaVinci EMAC private adapter structure |
1517 | * @buf_size: size of SKB data buffer to allocate |
1518 | * @data_token: data token returned (skb handle for storing in buffer desc) |
1519 | * @ch: RX channel number |
1520 | * |
1521 | * Called during RX channel setup - allocates skb buffer of required size |
1522 | * and provides the skb handle and allocated buffer data pointer to caller |
1523 | * |
1524 | * Returns skb data pointer or 0 on failure to alloc skb |
1525 | */ |
1526 | static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size, |
1527 | void **data_token, u32 ch) |
1528 | { |
1529 | struct net_device *ndev = priv->ndev; |
1530 | struct device *emac_dev = &ndev->dev; |
1531 | struct sk_buff *p_skb; |
1532 | |
1533 | p_skb = dev_alloc_skb(buf_size); |
1534 | if (unlikely(NULL == p_skb)) { |
1535 | if (netif_msg_rx_err(priv) && net_ratelimit()) |
1536 | dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb"); |
1537 | return NULL; |
1538 | } |
1539 | |
1540 | /* set device pointer in skb and reserve space for extra bytes */ |
1541 | p_skb->dev = ndev; |
1542 | skb_reserve(p_skb, NET_IP_ALIGN); |
1543 | *data_token = (void *) p_skb; |
1544 | return p_skb->data; |
1545 | } |
1546 | |
1547 | /** |
1548 | * emac_init_rxch: RX channel initialization |
1549 | * @priv: The DaVinci EMAC private adapter structure |
1550 | * @ch: RX channel number |
1551 | * @param: mac address for RX channel |
1552 | * |
1553 | * Called during device init to setup a RX channel (allocate buffers and |
1554 | * buffer descriptors, create queue and keep ready for reception |
1555 | * |
1556 | * Returns success(0) or mem alloc failures error code |
1557 | */ |
1558 | static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param) |
1559 | { |
1560 | struct device *emac_dev = &priv->ndev->dev; |
1561 | u32 cnt, bd_size; |
1562 | void __iomem *mem; |
1563 | struct emac_rx_bd __iomem *curr_bd; |
1564 | struct emac_rxch *rxch = NULL; |
1565 | |
1566 | rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL); |
1567 | if (NULL == rxch) { |
1568 | dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed"); |
1569 | return -ENOMEM; |
1570 | } |
1571 | priv->rxch[ch] = rxch; |
1572 | rxch->buf_size = priv->rx_buf_size; |
1573 | rxch->service_max = EMAC_DEF_RX_MAX_SERVICE; |
1574 | rxch->queue_active = 0; |
1575 | rxch->teardown_pending = 0; |
1576 | |
1577 | /* save mac address */ |
1578 | for (cnt = 0; cnt < 6; cnt++) |
1579 | rxch->mac_addr[cnt] = param[cnt]; |
1580 | |
1581 | /* allocate buffer descriptor pool align every BD on four word |
1582 | * boundry for future requirements */ |
1583 | bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF; |
1584 | rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; |
1585 | rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF); |
1586 | rxch->bd_mem = EMAC_RX_BD_MEM(priv); |
1587 | __memzero((void __force *)rxch->bd_mem, rxch->alloc_size); |
1588 | rxch->pkt_queue.buf_list = &rxch->buf_queue; |
1589 | |
1590 | /* allocate RX buffer and initialize the BD linked list */ |
1591 | mem = (void __force __iomem *) |
1592 | (((u32 __force) rxch->bd_mem + 0xF) & ~0xF); |
1593 | rxch->active_queue_head = NULL; |
1594 | rxch->active_queue_tail = mem; |
1595 | for (cnt = 0; cnt < rxch->num_bd; cnt++) { |
1596 | curr_bd = mem + (cnt * bd_size); |
1597 | /* for future use the last parameter contains the BD ptr */ |
1598 | curr_bd->data_ptr = emac_net_alloc_rx_buf(priv, |
1599 | rxch->buf_size, |
1600 | (void __force **)&curr_bd->buf_token, |
1601 | EMAC_DEF_RX_CH); |
1602 | if (curr_bd->data_ptr == NULL) { |
1603 | dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \ |
1604 | "failed for ch %d\n", ch); |
1605 | kfree(rxch); |
1606 | return -ENOMEM; |
1607 | } |
1608 | |
1609 | /* populate the hardware descriptor */ |
1610 | curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head, |
1611 | priv); |
1612 | curr_bd->buff_ptr = dma_map_single(emac_dev, curr_bd->data_ptr, |
1613 | rxch->buf_size, DMA_FROM_DEVICE); |
1614 | curr_bd->off_b_len = rxch->buf_size; |
1615 | curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; |
1616 | |
1617 | /* write back to hardware memory */ |
1618 | BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd, |
1619 | EMAC_BD_LENGTH_FOR_CACHE); |
1620 | curr_bd->next = rxch->active_queue_head; |
1621 | rxch->active_queue_head = curr_bd; |
1622 | } |
1623 | |
1624 | /* At this point rxCppi->activeQueueHead points to the first |
1625 | RX BD ready to be given to RX HDP and rxch->active_queue_tail |
1626 | points to the last RX BD |
1627 | */ |
1628 | return 0; |
1629 | } |
1630 | |
1631 | /** |
1632 | * emac_rxch_teardown: RX channel teardown |
1633 | * @priv: The DaVinci EMAC private adapter structure |
1634 | * @ch: RX channel number |
1635 | * |
1636 | * Called during device stop to teardown RX channel |
1637 | * |
1638 | */ |
1639 | static void emac_rxch_teardown(struct emac_priv *priv, u32 ch) |
1640 | { |
1641 | struct device *emac_dev = &priv->ndev->dev; |
1642 | u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */ |
1643 | |
1644 | while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) != |
1645 | EMAC_TEARDOWN_VALUE) { |
1646 | /* wait till tx teardown complete */ |
1647 | cpu_relax(); /* TODO: check if this helps ... */ |
1648 | --teardown_cnt; |
1649 | if (0 == teardown_cnt) { |
1650 | dev_err(emac_dev, "EMAC: RX teardown aborted\n"); |
1651 | break; |
1652 | } |
1653 | } |
1654 | emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE); |
1655 | } |
1656 | |
1657 | /** |
1658 | * emac_stop_rxch: Stop RX channel operation |
1659 | * @priv: The DaVinci EMAC private adapter structure |
1660 | * @ch: RX channel number |
1661 | * |
1662 | * Called during device stop to stop RX channel operation |
1663 | * |
1664 | */ |
1665 | static void emac_stop_rxch(struct emac_priv *priv, u32 ch) |
1666 | { |
1667 | struct emac_rxch *rxch = priv->rxch[ch]; |
1668 | |
1669 | if (rxch) { |
1670 | rxch->teardown_pending = 1; |
1671 | emac_write(EMAC_RXTEARDOWN, ch); |
1672 | /* wait for teardown complete */ |
1673 | emac_rxch_teardown(priv, ch); |
1674 | rxch->teardown_pending = 0; |
1675 | emac_write(EMAC_RXINTMASKCLEAR, BIT(ch)); |
1676 | } |
1677 | } |
1678 | |
1679 | /** |
1680 | * emac_cleanup_rxch: Book-keep function to clean RX channel resources |
1681 | * @priv: The DaVinci EMAC private adapter structure |
1682 | * @ch: RX channel number |
1683 | * |
1684 | * Called during device stop to clean up RX channel resources |
1685 | * |
1686 | */ |
1687 | static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch) |
1688 | { |
1689 | struct emac_rxch *rxch = priv->rxch[ch]; |
1690 | struct emac_rx_bd __iomem *curr_bd; |
1691 | |
1692 | if (rxch) { |
1693 | /* free the receive buffers previously allocated */ |
1694 | curr_bd = rxch->active_queue_head; |
1695 | while (curr_bd) { |
1696 | if (curr_bd->buf_token) { |
1697 | dma_unmap_single(&priv->ndev->dev, |
1698 | curr_bd->buff_ptr, |
1699 | curr_bd->off_b_len |
1700 | & EMAC_RX_BD_BUF_SIZE, |
1701 | DMA_FROM_DEVICE); |
1702 | |
1703 | dev_kfree_skb_any((struct sk_buff *)\ |
1704 | curr_bd->buf_token); |
1705 | } |
1706 | curr_bd = curr_bd->next; |
1707 | } |
1708 | if (rxch->bd_mem) |
1709 | rxch->bd_mem = NULL; |
1710 | kfree(rxch); |
1711 | priv->rxch[ch] = NULL; |
1712 | } |
1713 | } |
1714 | |
1715 | /** |
1716 | * emac_set_type0addr: Set EMAC Type0 mac address |
1717 | * @priv: The DaVinci EMAC private adapter structure |
1718 | * @ch: RX channel number |
1719 | * @mac_addr: MAC address to set in device |
1720 | * |
1721 | * Called internally to set Type0 mac address of the adapter (Device) |
1722 | * |
1723 | * Returns success (0) or appropriate error code (none as of now) |
1724 | */ |
1725 | static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) |
1726 | { |
1727 | u32 val; |
1728 | val = ((mac_addr[5] << 8) | (mac_addr[4])); |
1729 | emac_write(EMAC_MACSRCADDRLO, val); |
1730 | |
1731 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ |
1732 | (mac_addr[1] << 8) | (mac_addr[0])); |
1733 | emac_write(EMAC_MACSRCADDRHI, val); |
1734 | val = emac_read(EMAC_RXUNICASTSET); |
1735 | val |= BIT(ch); |
1736 | emac_write(EMAC_RXUNICASTSET, val); |
1737 | val = emac_read(EMAC_RXUNICASTCLEAR); |
1738 | val &= ~BIT(ch); |
1739 | emac_write(EMAC_RXUNICASTCLEAR, val); |
1740 | } |
1741 | |
1742 | /** |
1743 | * emac_set_type1addr: Set EMAC Type1 mac address |
1744 | * @priv: The DaVinci EMAC private adapter structure |
1745 | * @ch: RX channel number |
1746 | * @mac_addr: MAC address to set in device |
1747 | * |
1748 | * Called internally to set Type1 mac address of the adapter (Device) |
1749 | * |
1750 | * Returns success (0) or appropriate error code (none as of now) |
1751 | */ |
1752 | static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) |
1753 | { |
1754 | u32 val; |
1755 | emac_write(EMAC_MACINDEX, ch); |
1756 | val = ((mac_addr[5] << 8) | mac_addr[4]); |
1757 | emac_write(EMAC_MACADDRLO, val); |
1758 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ |
1759 | (mac_addr[1] << 8) | (mac_addr[0])); |
1760 | emac_write(EMAC_MACADDRHI, val); |
1761 | emac_set_type0addr(priv, ch, mac_addr); |
1762 | } |
1763 | |
1764 | /** |
1765 | * emac_set_type2addr: Set EMAC Type2 mac address |
1766 | * @priv: The DaVinci EMAC private adapter structure |
1767 | * @ch: RX channel number |
1768 | * @mac_addr: MAC address to set in device |
1769 | * @index: index into RX address entries |
1770 | * @match: match parameter for RX address matching logic |
1771 | * |
1772 | * Called internally to set Type2 mac address of the adapter (Device) |
1773 | * |
1774 | * Returns success (0) or appropriate error code (none as of now) |
1775 | */ |
1776 | static void emac_set_type2addr(struct emac_priv *priv, u32 ch, |
1777 | char *mac_addr, int index, int match) |
1778 | { |
1779 | u32 val; |
1780 | emac_write(EMAC_MACINDEX, index); |
1781 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ |
1782 | (mac_addr[1] << 8) | (mac_addr[0])); |
1783 | emac_write(EMAC_MACADDRHI, val); |
1784 | val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ |
1785 | (match << 19) | BIT(20)); |
1786 | emac_write(EMAC_MACADDRLO, val); |
1787 | emac_set_type0addr(priv, ch, mac_addr); |
1788 | } |
1789 | |
1790 | /** |
1791 | * emac_setmac: Set mac address in the adapter (internal function) |
1792 | * @priv: The DaVinci EMAC private adapter structure |
1793 | * @ch: RX channel number |
1794 | * @mac_addr: MAC address to set in device |
1795 | * |
1796 | * Called internally to set the mac address of the adapter (Device) |
1797 | * |
1798 | * Returns success (0) or appropriate error code (none as of now) |
1799 | */ |
1800 | static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) |
1801 | { |
1802 | struct device *emac_dev = &priv->ndev->dev; |
1803 | |
1804 | if (priv->rx_addr_type == 0) { |
1805 | emac_set_type0addr(priv, ch, mac_addr); |
1806 | } else if (priv->rx_addr_type == 1) { |
1807 | u32 cnt; |
1808 | for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) |
1809 | emac_set_type1addr(priv, ch, mac_addr); |
1810 | } else if (priv->rx_addr_type == 2) { |
1811 | emac_set_type2addr(priv, ch, mac_addr, ch, 1); |
1812 | emac_set_type0addr(priv, ch, mac_addr); |
1813 | } else { |
1814 | if (netif_msg_drv(priv)) |
1815 | dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); |
1816 | } |
1817 | } |
1818 | |
1819 | /** |
1820 | * emac_dev_setmac_addr: Set mac address in the adapter |
1821 | * @ndev: The DaVinci EMAC network adapter |
1822 | * @addr: MAC address to set in device |
1823 | * |
1824 | * Called by the system to set the mac address of the adapter (Device) |
1825 | * |
1826 | * Returns success (0) or appropriate error code (none as of now) |
1827 | */ |
1828 | static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) |
1829 | { |
1830 | struct emac_priv *priv = netdev_priv(ndev); |
1831 | struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH]; |
1832 | struct device *emac_dev = &priv->ndev->dev; |
1833 | struct sockaddr *sa = addr; |
1834 | |
1835 | if (!is_valid_ether_addr(sa->sa_data)) |
1836 | return -EINVAL; |
1837 | |
1838 | /* Store mac addr in priv and rx channel and set it in EMAC hw */ |
1839 | memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); |
1840 | memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len); |
1841 | |
1842 | /* If the interface is down - rxch is NULL. */ |
1843 | /* MAC address is configured only after the interface is enabled. */ |
1844 | if (netif_running(ndev)) { |
1845 | memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len); |
1846 | emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr); |
1847 | } |
1848 | |
1849 | if (netif_msg_drv(priv)) |
1850 | dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", |
1851 | priv->mac_addr); |
1852 | |
1853 | return 0; |
1854 | } |
1855 | |
1856 | /** |
1857 | * emac_addbd_to_rx_queue: Recycle RX buffer descriptor |
1858 | * @priv: The DaVinci EMAC private adapter structure |
1859 | * @ch: RX channel number to process buffer descriptors for |
1860 | * @curr_bd: current buffer descriptor |
1861 | * @buffer: buffer pointer for descriptor |
1862 | * @buf_token: buffer token (stores skb information) |
1863 | * |
1864 | * Prepares the recycled buffer descriptor and addes it to hardware |
1865 | * receive queue - if queue empty this descriptor becomes the head |
1866 | * else addes the descriptor to end of queue |
1867 | * |
1868 | */ |
1869 | static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch, |
1870 | struct emac_rx_bd __iomem *curr_bd, |
1871 | char *buffer, void *buf_token) |
1872 | { |
1873 | struct emac_rxch *rxch = priv->rxch[ch]; |
1874 | |
1875 | /* populate the hardware descriptor */ |
1876 | curr_bd->h_next = 0; |
1877 | curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buffer, |
1878 | rxch->buf_size, DMA_FROM_DEVICE); |
1879 | curr_bd->off_b_len = rxch->buf_size; |
1880 | curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; |
1881 | curr_bd->next = NULL; |
1882 | curr_bd->data_ptr = buffer; |
1883 | curr_bd->buf_token = buf_token; |
1884 | |
1885 | /* write back */ |
1886 | BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); |
1887 | if (rxch->active_queue_head == NULL) { |
1888 | rxch->active_queue_head = curr_bd; |
1889 | rxch->active_queue_tail = curr_bd; |
1890 | if (0 != rxch->queue_active) { |
1891 | emac_write(EMAC_RXHDP(ch), |
1892 | emac_virt_to_phys(rxch->active_queue_head, priv)); |
1893 | rxch->queue_active = 1; |
1894 | } |
1895 | } else { |
1896 | struct emac_rx_bd __iomem *tail_bd; |
1897 | u32 frame_status; |
1898 | |
1899 | tail_bd = rxch->active_queue_tail; |
1900 | rxch->active_queue_tail = curr_bd; |
1901 | tail_bd->next = curr_bd; |
1902 | tail_bd = EMAC_VIRT_NOCACHE(tail_bd); |
1903 | tail_bd->h_next = emac_virt_to_phys(curr_bd, priv); |
1904 | frame_status = tail_bd->mode; |
1905 | if (frame_status & EMAC_CPPI_EOQ_BIT) { |
1906 | emac_write(EMAC_RXHDP(ch), |
1907 | emac_virt_to_phys(curr_bd, priv)); |
1908 | frame_status &= ~(EMAC_CPPI_EOQ_BIT); |
1909 | tail_bd->mode = frame_status; |
1910 | ++rxch->end_of_queue_add; |
1911 | } |
1912 | } |
1913 | ++rxch->recycled_bd; |
1914 | } |
1915 | |
1916 | /** |
1917 | * emac_net_rx_cb: Prepares packet and sends to upper layer |
1918 | * @priv: The DaVinci EMAC private adapter structure |
1919 | * @net_pkt_list: Network packet list (received packets) |
1920 | * |
1921 | * Invalidates packet buffer memory and sends the received packet to upper |
1922 | * layer |
1923 | * |
1924 | * Returns success or appropriate error code (none as of now) |
1925 | */ |
1926 | static int emac_net_rx_cb(struct emac_priv *priv, |
1927 | struct emac_netpktobj *net_pkt_list) |
1928 | { |
1929 | struct sk_buff *p_skb; |
1930 | p_skb = (struct sk_buff *)net_pkt_list->pkt_token; |
1931 | /* set length of packet */ |
1932 | skb_put(p_skb, net_pkt_list->pkt_length); |
1933 | p_skb->protocol = eth_type_trans(p_skb, priv->ndev); |
1934 | netif_receive_skb(p_skb); |
1935 | priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length; |
1936 | priv->net_dev_stats.rx_packets++; |
1937 | return 0; |
1938 | } |
1939 | |
1940 | /** |
1941 | * emac_rx_bdproc: RX buffer descriptor (packet) processing |
1942 | * @priv: The DaVinci EMAC private adapter structure |
1943 | * @ch: RX channel number to process buffer descriptors for |
1944 | * @budget: number of packets allowed to process |
1945 | * @pending: indication to caller that packets are pending to process |
1946 | * |
1947 | * Processes RX buffer descriptors - checks ownership bit on the RX buffer |
1948 | * descriptor, sends the receive packet to upper layer, allocates a new SKB |
1949 | * and recycles the buffer descriptor (requeues it in hardware RX queue). |
1950 | * Only "budget" number of packets are processed and indication of pending |
1951 | * packets provided to the caller. |
1952 | * |
1953 | * Returns number of packets processed (and indication of pending packets) |
1954 | */ |
1955 | static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget) |
1956 | { |
1957 | unsigned long flags; |
1958 | u32 frame_status; |
1959 | u32 pkts_processed = 0; |
1960 | char *new_buffer; |
1961 | struct emac_rx_bd __iomem *curr_bd; |
1962 | struct emac_rx_bd __iomem *last_bd; |
1963 | struct emac_netpktobj *curr_pkt, pkt_obj; |
1964 | struct emac_netbufobj buf_obj; |
1965 | struct emac_netbufobj *rx_buf_obj; |
1966 | void *new_buf_token; |
1967 | struct emac_rxch *rxch = priv->rxch[ch]; |
1968 | |
1969 | if (unlikely(1 == rxch->teardown_pending)) |
1970 | return 0; |
1971 | ++rxch->proc_count; |
1972 | spin_lock_irqsave(&priv->rx_lock, flags); |
1973 | pkt_obj.buf_list = &buf_obj; |
1974 | curr_pkt = &pkt_obj; |
1975 | curr_bd = rxch->active_queue_head; |
1976 | BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); |
1977 | frame_status = curr_bd->mode; |
1978 | |
1979 | while ((curr_bd) && |
1980 | ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && |
1981 | (pkts_processed < budget)) { |
1982 | |
1983 | new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size, |
1984 | &new_buf_token, EMAC_DEF_RX_CH); |
1985 | if (unlikely(NULL == new_buffer)) { |
1986 | ++rxch->out_of_rx_buffers; |
1987 | goto end_emac_rx_bdproc; |
1988 | } |
1989 | |
1990 | /* populate received packet data structure */ |
1991 | rx_buf_obj = &curr_pkt->buf_list[0]; |
1992 | rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; |
1993 | rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; |
1994 | rx_buf_obj->buf_token = curr_bd->buf_token; |
1995 | |
1996 | dma_unmap_single(&priv->ndev->dev, curr_bd->buff_ptr, |
1997 | curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE, |
1998 | DMA_FROM_DEVICE); |
1999 | |
2000 | curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; |
2001 | curr_pkt->num_bufs = 1; |
2002 | curr_pkt->pkt_length = |
2003 | (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); |
2004 | emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv)); |
2005 | ++rxch->processed_bd; |
2006 | last_bd = curr_bd; |
2007 | curr_bd = last_bd->next; |
2008 | rxch->active_queue_head = curr_bd; |
2009 | |
2010 | /* check if end of RX queue ? */ |
2011 | if (frame_status & EMAC_CPPI_EOQ_BIT) { |
2012 | if (curr_bd) { |
2013 | ++rxch->mis_queued_packets; |
2014 | emac_write(EMAC_RXHDP(ch), |
2015 | emac_virt_to_phys(curr_bd, priv)); |
2016 | } else { |
2017 | ++rxch->end_of_queue; |
2018 | rxch->queue_active = 0; |
2019 | } |
2020 | } |
2021 | |
2022 | /* recycle BD */ |
2023 | emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer, |
2024 | new_buf_token); |
2025 | |
2026 | /* return the packet to the user - BD ptr passed in |
2027 | * last parameter for potential *future* use */ |
2028 | spin_unlock_irqrestore(&priv->rx_lock, flags); |
2029 | emac_net_rx_cb(priv, curr_pkt); |
2030 | spin_lock_irqsave(&priv->rx_lock, flags); |
2031 | curr_bd = rxch->active_queue_head; |
2032 | if (curr_bd) { |
2033 | BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); |
2034 | frame_status = curr_bd->mode; |
2035 | } |
2036 | ++pkts_processed; |
2037 | } |
2038 | |
2039 | end_emac_rx_bdproc: |
2040 | spin_unlock_irqrestore(&priv->rx_lock, flags); |
2041 | return pkts_processed; |
2042 | } |
2043 | |
2044 | /** |
2045 | * emac_hw_enable: Enable EMAC hardware for packet transmission/reception |
2046 | * @priv: The DaVinci EMAC private adapter structure |
2047 | * |
2048 | * Enables EMAC hardware for packet processing - enables PHY, enables RX |
2049 | * for packet reception and enables device interrupts and then NAPI |
2050 | * |
2051 | * Returns success (0) or appropriate error code (none right now) |
2052 | */ |
2053 | static int emac_hw_enable(struct emac_priv *priv) |
2054 | { |
2055 | u32 ch, val, mbp_enable, mac_control; |
2056 | |
2057 | /* Soft reset */ |
2058 | emac_write(EMAC_SOFTRESET, 1); |
2059 | while (emac_read(EMAC_SOFTRESET)) |
2060 | cpu_relax(); |
2061 | |
2062 | /* Disable interrupt & Set pacing for more interrupts initially */ |
2063 | emac_int_disable(priv); |
2064 | |
2065 | /* Full duplex enable bit set when auto negotiation happens */ |
2066 | mac_control = |
2067 | (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | |
2068 | ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | |
2069 | ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | |
2070 | ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); |
2071 | emac_write(EMAC_MACCONTROL, mac_control); |
2072 | |
2073 | mbp_enable = |
2074 | (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | |
2075 | ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | |
2076 | ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | |
2077 | ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | |
2078 | ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | |
2079 | ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | |
2080 | ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | |
2081 | ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ |
2082 | EMAC_RXMBP_PROMCH_SHIFT) | |
2083 | ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | |
2084 | ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ |
2085 | EMAC_RXMBP_BROADCH_SHIFT) | |
2086 | ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | |
2087 | ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ |
2088 | EMAC_RXMBP_MULTICH_SHIFT)); |
2089 | emac_write(EMAC_RXMBPENABLE, mbp_enable); |
2090 | emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & |
2091 | EMAC_RX_MAX_LEN_MASK)); |
2092 | emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & |
2093 | EMAC_RX_BUFFER_OFFSET_MASK)); |
2094 | emac_write(EMAC_RXFILTERLOWTHRESH, 0); |
2095 | emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); |
2096 | priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; |
2097 | |
2098 | val = emac_read(EMAC_TXCONTROL); |
2099 | val |= EMAC_TX_CONTROL_TX_ENABLE_VAL; |
2100 | emac_write(EMAC_TXCONTROL, val); |
2101 | val = emac_read(EMAC_RXCONTROL); |
2102 | val |= EMAC_RX_CONTROL_RX_ENABLE_VAL; |
2103 | emac_write(EMAC_RXCONTROL, val); |
2104 | emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); |
2105 | |
2106 | for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { |
2107 | emac_write(EMAC_TXHDP(ch), 0); |
2108 | emac_write(EMAC_TXINTMASKSET, BIT(ch)); |
2109 | } |
2110 | for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) { |
2111 | struct emac_rxch *rxch = priv->rxch[ch]; |
2112 | emac_setmac(priv, ch, rxch->mac_addr); |
2113 | emac_write(EMAC_RXINTMASKSET, BIT(ch)); |
2114 | rxch->queue_active = 1; |
2115 | emac_write(EMAC_RXHDP(ch), |
2116 | emac_virt_to_phys(rxch->active_queue_head, priv)); |
2117 | } |
2118 | |
2119 | /* Enable MII */ |
2120 | val = emac_read(EMAC_MACCONTROL); |
2121 | val |= (EMAC_MACCONTROL_GMIIEN); |
2122 | emac_write(EMAC_MACCONTROL, val); |
2123 | |
2124 | /* Enable NAPI and interrupts */ |
2125 | napi_enable(&priv->napi); |
2126 | emac_int_enable(priv); |
2127 | return 0; |
2128 | |
2129 | } |
2130 | |
2131 | /** |
2132 | * emac_poll: EMAC NAPI Poll function |
2133 | * @ndev: The DaVinci EMAC network adapter |
2134 | * @budget: Number of receive packets to process (as told by NAPI layer) |
2135 | * |
2136 | * NAPI Poll function implemented to process packets as per budget. We check |
2137 | * the type of interrupt on the device and accordingly call the TX or RX |
2138 | * packet processing functions. We follow the budget for RX processing and |
2139 | * also put a cap on number of TX pkts processed through config param. The |
2140 | * NAPI schedule function is called if more packets pending. |
2141 | * |
2142 | * Returns number of packets received (in most cases; else TX pkts - rarely) |
2143 | */ |
2144 | static int emac_poll(struct napi_struct *napi, int budget) |
2145 | { |
2146 | unsigned int mask; |
2147 | struct emac_priv *priv = container_of(napi, struct emac_priv, napi); |
2148 | struct net_device *ndev = priv->ndev; |
2149 | struct device *emac_dev = &ndev->dev; |
2150 | u32 status = 0; |
2151 | u32 num_pkts = 0; |
2152 | |
2153 | /* Check interrupt vectors and call packet processing */ |
2154 | status = emac_read(EMAC_MACINVECTOR); |
2155 | |
2156 | mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; |
2157 | |
2158 | if (priv->version == EMAC_VERSION_2) |
2159 | mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; |
2160 | |
2161 | if (status & mask) { |
2162 | num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, |
2163 | EMAC_DEF_TX_MAX_SERVICE); |
2164 | } /* TX processing */ |
2165 | |
2166 | if (num_pkts) |
2167 | return budget; |
2168 | |
2169 | mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; |
2170 | |
2171 | if (priv->version == EMAC_VERSION_2) |
2172 | mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; |
2173 | |
2174 | if (status & mask) { |
2175 | num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget); |
2176 | } /* RX processing */ |
2177 | |
2178 | if (num_pkts < budget) { |
2179 | napi_complete(napi); |
2180 | emac_int_enable(priv); |
2181 | } |
2182 | |
2183 | mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; |
2184 | if (priv->version == EMAC_VERSION_2) |
2185 | mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; |
2186 | |
2187 | if (unlikely(status & mask)) { |
2188 | u32 ch, cause; |
2189 | dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); |
2190 | netif_stop_queue(ndev); |
2191 | napi_disable(&priv->napi); |
2192 | |
2193 | status = emac_read(EMAC_MACSTATUS); |
2194 | cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> |
2195 | EMAC_MACSTATUS_TXERRCODE_SHIFT); |
2196 | if (cause) { |
2197 | ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> |
2198 | EMAC_MACSTATUS_TXERRCH_SHIFT); |
2199 | if (net_ratelimit()) { |
2200 | dev_err(emac_dev, "TX Host error %s on ch=%d\n", |
2201 | &emac_txhost_errcodes[cause][0], ch); |
2202 | } |
2203 | } |
2204 | cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> |
2205 | EMAC_MACSTATUS_RXERRCODE_SHIFT); |
2206 | if (cause) { |
2207 | ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> |
2208 | EMAC_MACSTATUS_RXERRCH_SHIFT); |
2209 | if (netif_msg_hw(priv) && net_ratelimit()) |
2210 | dev_err(emac_dev, "RX Host error %s on ch=%d\n", |
2211 | &emac_rxhost_errcodes[cause][0], ch); |
2212 | } |
2213 | } /* Host error processing */ |
2214 | |
2215 | return num_pkts; |
2216 | } |
2217 | |
2218 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2219 | /** |
2220 | * emac_poll_controller: EMAC Poll controller function |
2221 | * @ndev: The DaVinci EMAC network adapter |
2222 | * |
2223 | * Polled functionality used by netconsole and others in non interrupt mode |
2224 | * |
2225 | */ |
2226 | void emac_poll_controller(struct net_device *ndev) |
2227 | { |
2228 | struct emac_priv *priv = netdev_priv(ndev); |
2229 | |
2230 | emac_int_disable(priv); |
2231 | emac_irq(ndev->irq, ndev); |
2232 | emac_int_enable(priv); |
2233 | } |
2234 | #endif |
2235 | |
2236 | /* PHY/MII bus related */ |
2237 | |
2238 | /* Wait until mdio is ready for next command */ |
2239 | #define MDIO_WAIT_FOR_USER_ACCESS\ |
2240 | while ((emac_mdio_read((MDIO_USERACCESS(0))) &\ |
2241 | MDIO_USERACCESS_GO) != 0) |
2242 | |
2243 | static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg) |
2244 | { |
2245 | unsigned int phy_data = 0; |
2246 | unsigned int phy_control; |
2247 | |
2248 | /* Wait until mdio is ready for next command */ |
2249 | MDIO_WAIT_FOR_USER_ACCESS; |
2250 | |
2251 | phy_control = (MDIO_USERACCESS_GO | |
2252 | MDIO_USERACCESS_READ | |
2253 | ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | |
2254 | ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | |
2255 | (phy_data & MDIO_USERACCESS_DATA)); |
2256 | emac_mdio_write(MDIO_USERACCESS(0), phy_control); |
2257 | |
2258 | /* Wait until mdio is ready for next command */ |
2259 | MDIO_WAIT_FOR_USER_ACCESS; |
2260 | |
2261 | return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA; |
2262 | |
2263 | } |
2264 | |
2265 | static int emac_mii_write(struct mii_bus *bus, int phy_id, |
2266 | int phy_reg, u16 phy_data) |
2267 | { |
2268 | |
2269 | unsigned int control; |
2270 | |
2271 | /* until mdio is ready for next command */ |
2272 | MDIO_WAIT_FOR_USER_ACCESS; |
2273 | |
2274 | control = (MDIO_USERACCESS_GO | |
2275 | MDIO_USERACCESS_WRITE | |
2276 | ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | |
2277 | ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | |
2278 | (phy_data & MDIO_USERACCESS_DATA)); |
2279 | emac_mdio_write(MDIO_USERACCESS(0), control); |
2280 | |
2281 | return 0; |
2282 | } |
2283 | |
2284 | static int emac_mii_reset(struct mii_bus *bus) |
2285 | { |
2286 | unsigned int clk_div; |
2287 | int mdio_bus_freq = emac_bus_frequency; |
2288 | |
2289 | if (mdio_max_freq && mdio_bus_freq) |
2290 | clk_div = ((mdio_bus_freq / mdio_max_freq) - 1); |
2291 | else |
2292 | clk_div = 0xFF; |
2293 | |
2294 | clk_div &= MDIO_CONTROL_CLKDIV; |
2295 | |
2296 | /* Set enable and clock divider in MDIOControl */ |
2297 | emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE)); |
2298 | |
2299 | return 0; |
2300 | |
2301 | } |
2302 | |
2303 | static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL }; |
2304 | |
2305 | /* emac_driver: EMAC MII bus structure */ |
2306 | |
2307 | static struct mii_bus *emac_mii; |
2308 | |
2309 | static void emac_adjust_link(struct net_device *ndev) |
2310 | { |
2311 | struct emac_priv *priv = netdev_priv(ndev); |
2312 | struct phy_device *phydev = priv->phydev; |
2313 | unsigned long flags; |
2314 | int new_state = 0; |
2315 | |
2316 | spin_lock_irqsave(&priv->lock, flags); |
2317 | |
2318 | if (phydev->link) { |
2319 | /* check the mode of operation - full/half duplex */ |
2320 | if (phydev->duplex != priv->duplex) { |
2321 | new_state = 1; |
2322 | priv->duplex = phydev->duplex; |
2323 | } |
2324 | if (phydev->speed != priv->speed) { |
2325 | new_state = 1; |
2326 | priv->speed = phydev->speed; |
2327 | } |
2328 | if (!priv->link) { |
2329 | new_state = 1; |
2330 | priv->link = 1; |
2331 | } |
2332 | |
2333 | } else if (priv->link) { |
2334 | new_state = 1; |
2335 | priv->link = 0; |
2336 | priv->speed = 0; |
2337 | priv->duplex = ~0; |
2338 | } |
2339 | if (new_state) { |
2340 | emac_update_phystatus(priv); |
2341 | phy_print_status(priv->phydev); |
2342 | } |
2343 | |
2344 | spin_unlock_irqrestore(&priv->lock, flags); |
2345 | } |
2346 | |
2347 | /************************************************************************* |
2348 | * Linux Driver Model |
2349 | *************************************************************************/ |
2350 | |
2351 | /** |
2352 | * emac_devioctl: EMAC adapter ioctl |
2353 | * @ndev: The DaVinci EMAC network adapter |
2354 | * @ifrq: request parameter |
2355 | * @cmd: command parameter |
2356 | * |
2357 | * EMAC driver ioctl function |
2358 | * |
2359 | * Returns success(0) or appropriate error code |
2360 | */ |
2361 | static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) |
2362 | { |
2363 | dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n"); |
2364 | |
2365 | if (!(netif_running(ndev))) |
2366 | return -EINVAL; |
2367 | |
2368 | /* TODO: Add phy read and write and private statistics get feature */ |
2369 | |
2370 | return -EOPNOTSUPP; |
2371 | } |
2372 | |
2373 | /** |
2374 | * emac_dev_open: EMAC device open |
2375 | * @ndev: The DaVinci EMAC network adapter |
2376 | * |
2377 | * Called when system wants to start the interface. We init TX/RX channels |
2378 | * and enable the hardware for packet reception/transmission and start the |
2379 | * network queue. |
2380 | * |
2381 | * Returns 0 for a successful open, or appropriate error code |
2382 | */ |
2383 | static int emac_dev_open(struct net_device *ndev) |
2384 | { |
2385 | struct device *emac_dev = &ndev->dev; |
2386 | u32 rc, cnt, ch; |
2387 | int phy_addr; |
2388 | struct resource *res; |
2389 | int q, m; |
2390 | int i = 0; |
2391 | int k = 0; |
2392 | struct emac_priv *priv = netdev_priv(ndev); |
2393 | |
2394 | netif_carrier_off(ndev); |
2395 | for (cnt = 0; cnt < ETH_ALEN; cnt++) |
2396 | ndev->dev_addr[cnt] = priv->mac_addr[cnt]; |
2397 | |
2398 | /* Configuration items */ |
2399 | priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; |
2400 | |
2401 | /* Clear basic hardware */ |
2402 | for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) { |
2403 | emac_write(EMAC_TXHDP(ch), 0); |
2404 | emac_write(EMAC_RXHDP(ch), 0); |
2405 | emac_write(EMAC_RXHDP(ch), 0); |
2406 | emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); |
2407 | emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); |
2408 | } |
2409 | priv->mac_hash1 = 0; |
2410 | priv->mac_hash2 = 0; |
2411 | emac_write(EMAC_MACHASH1, 0); |
2412 | emac_write(EMAC_MACHASH2, 0); |
2413 | |
2414 | /* multi ch not supported - open 1 TX, 1RX ch by default */ |
2415 | rc = emac_init_txch(priv, EMAC_DEF_TX_CH); |
2416 | if (0 != rc) { |
2417 | dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed"); |
2418 | return rc; |
2419 | } |
2420 | rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); |
2421 | if (0 != rc) { |
2422 | dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed"); |
2423 | return rc; |
2424 | } |
2425 | |
2426 | /* Request IRQ */ |
2427 | |
2428 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { |
2429 | for (i = res->start; i <= res->end; i++) { |
2430 | if (request_irq(i, emac_irq, IRQF_DISABLED, |
2431 | ndev->name, ndev)) |
2432 | goto rollback; |
2433 | } |
2434 | k++; |
2435 | } |
2436 | |
2437 | /* Start/Enable EMAC hardware */ |
2438 | emac_hw_enable(priv); |
2439 | |
2440 | /* find the first phy */ |
2441 | priv->phydev = NULL; |
2442 | if (priv->phy_mask) { |
2443 | emac_mii_reset(priv->mii_bus); |
2444 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { |
2445 | if (priv->mii_bus->phy_map[phy_addr]) { |
2446 | priv->phydev = priv->mii_bus->phy_map[phy_addr]; |
2447 | break; |
2448 | } |
2449 | } |
2450 | |
2451 | if (!priv->phydev) { |
2452 | printk(KERN_ERR "%s: no PHY found\n", ndev->name); |
2453 | return -1; |
2454 | } |
2455 | |
2456 | priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev), |
2457 | &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII); |
2458 | |
2459 | if (IS_ERR(priv->phydev)) { |
2460 | printk(KERN_ERR "%s: Could not attach to PHY\n", |
2461 | ndev->name); |
2462 | return PTR_ERR(priv->phydev); |
2463 | } |
2464 | |
2465 | priv->link = 0; |
2466 | priv->speed = 0; |
2467 | priv->duplex = ~0; |
2468 | |
2469 | printk(KERN_INFO "%s: attached PHY driver [%s] " |
2470 | "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name, |
2471 | priv->phydev->drv->name, dev_name(&priv->phydev->dev), |
2472 | priv->phydev->phy_id); |
2473 | } else{ |
2474 | /* No PHY , fix the link, speed and duplex settings */ |
2475 | priv->link = 1; |
2476 | priv->speed = SPEED_100; |
2477 | priv->duplex = DUPLEX_FULL; |
2478 | emac_update_phystatus(priv); |
2479 | } |
2480 | |
2481 | if (!netif_running(ndev)) /* debug only - to avoid compiler warning */ |
2482 | emac_dump_regs(priv); |
2483 | |
2484 | if (netif_msg_drv(priv)) |
2485 | dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); |
2486 | |
2487 | if (priv->phy_mask) |
2488 | phy_start(priv->phydev); |
2489 | |
2490 | return 0; |
2491 | |
2492 | rollback: |
2493 | |
2494 | dev_err(emac_dev, "DaVinci EMAC: request_irq() failed"); |
2495 | |
2496 | for (q = k; k >= 0; k--) { |
2497 | for (m = i; m >= res->start; m--) |
2498 | free_irq(m, ndev); |
2499 | res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1); |
2500 | m = res->end; |
2501 | } |
2502 | return -EBUSY; |
2503 | } |
2504 | |
2505 | /** |
2506 | * emac_dev_stop: EMAC device stop |
2507 | * @ndev: The DaVinci EMAC network adapter |
2508 | * |
2509 | * Called when system wants to stop or down the interface. We stop the network |
2510 | * queue, disable interrupts and cleanup TX/RX channels. |
2511 | * |
2512 | * We return the statistics in net_device_stats structure pulled from emac |
2513 | */ |
2514 | static int emac_dev_stop(struct net_device *ndev) |
2515 | { |
2516 | struct resource *res; |
2517 | int i = 0; |
2518 | int irq_num; |
2519 | struct emac_priv *priv = netdev_priv(ndev); |
2520 | struct device *emac_dev = &ndev->dev; |
2521 | |
2522 | /* inform the upper layers. */ |
2523 | netif_stop_queue(ndev); |
2524 | napi_disable(&priv->napi); |
2525 | |
2526 | netif_carrier_off(ndev); |
2527 | emac_int_disable(priv); |
2528 | emac_stop_txch(priv, EMAC_DEF_TX_CH); |
2529 | emac_stop_rxch(priv, EMAC_DEF_RX_CH); |
2530 | emac_cleanup_txch(priv, EMAC_DEF_TX_CH); |
2531 | emac_cleanup_rxch(priv, EMAC_DEF_RX_CH); |
2532 | emac_write(EMAC_SOFTRESET, 1); |
2533 | |
2534 | if (priv->phydev) |
2535 | phy_disconnect(priv->phydev); |
2536 | |
2537 | /* Free IRQ */ |
2538 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) { |
2539 | for (irq_num = res->start; irq_num <= res->end; irq_num++) |
2540 | free_irq(irq_num, priv->ndev); |
2541 | i++; |
2542 | } |
2543 | |
2544 | if (netif_msg_drv(priv)) |
2545 | dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); |
2546 | |
2547 | return 0; |
2548 | } |
2549 | |
2550 | /** |
2551 | * emac_dev_getnetstats: EMAC get statistics function |
2552 | * @ndev: The DaVinci EMAC network adapter |
2553 | * |
2554 | * Called when system wants to get statistics from the device. |
2555 | * |
2556 | * We return the statistics in net_device_stats structure pulled from emac |
2557 | */ |
2558 | static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) |
2559 | { |
2560 | struct emac_priv *priv = netdev_priv(ndev); |
2561 | u32 mac_control; |
2562 | u32 stats_clear_mask; |
2563 | |
2564 | /* update emac hardware stats and reset the registers*/ |
2565 | |
2566 | mac_control = emac_read(EMAC_MACCONTROL); |
2567 | |
2568 | if (mac_control & EMAC_MACCONTROL_GMIIEN) |
2569 | stats_clear_mask = EMAC_STATS_CLR_MASK; |
2570 | else |
2571 | stats_clear_mask = 0; |
2572 | |
2573 | priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES); |
2574 | emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); |
2575 | |
2576 | priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) + |
2577 | emac_read(EMAC_TXSINGLECOLL) + |
2578 | emac_read(EMAC_TXMULTICOLL)); |
2579 | emac_write(EMAC_TXCOLLISION, stats_clear_mask); |
2580 | emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); |
2581 | emac_write(EMAC_TXMULTICOLL, stats_clear_mask); |
2582 | |
2583 | priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + |
2584 | emac_read(EMAC_RXJABBER) + |
2585 | emac_read(EMAC_RXUNDERSIZED)); |
2586 | emac_write(EMAC_RXOVERSIZED, stats_clear_mask); |
2587 | emac_write(EMAC_RXJABBER, stats_clear_mask); |
2588 | emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); |
2589 | |
2590 | priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + |
2591 | emac_read(EMAC_RXMOFOVERRUNS)); |
2592 | emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); |
2593 | emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); |
2594 | |
2595 | priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); |
2596 | emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); |
2597 | |
2598 | priv->net_dev_stats.tx_carrier_errors += |
2599 | emac_read(EMAC_TXCARRIERSENSE); |
2600 | emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); |
2601 | |
2602 | priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); |
2603 | emac_write(EMAC_TXUNDERRUN, stats_clear_mask); |
2604 | |
2605 | return &priv->net_dev_stats; |
2606 | } |
2607 | |
2608 | static const struct net_device_ops emac_netdev_ops = { |
2609 | .ndo_open = emac_dev_open, |
2610 | .ndo_stop = emac_dev_stop, |
2611 | .ndo_start_xmit = emac_dev_xmit, |
2612 | .ndo_set_multicast_list = emac_dev_mcast_set, |
2613 | .ndo_set_mac_address = emac_dev_setmac_addr, |
2614 | .ndo_do_ioctl = emac_devioctl, |
2615 | .ndo_tx_timeout = emac_dev_tx_timeout, |
2616 | .ndo_get_stats = emac_dev_getnetstats, |
2617 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2618 | .ndo_poll_controller = emac_poll_controller, |
2619 | #endif |
2620 | }; |
2621 | |
2622 | /** |
2623 | * davinci_emac_probe: EMAC device probe |
2624 | * @pdev: The DaVinci EMAC device that we are removing |
2625 | * |
2626 | * Called when probing for emac devicesr. We get details of instances and |
2627 | * resource information from platform init and register a network device |
2628 | * and allocate resources necessary for driver to perform |
2629 | */ |
2630 | static int __devinit davinci_emac_probe(struct platform_device *pdev) |
2631 | { |
2632 | int rc = 0; |
2633 | struct resource *res; |
2634 | struct net_device *ndev; |
2635 | struct emac_priv *priv; |
2636 | unsigned long size; |
2637 | struct emac_platform_data *pdata; |
2638 | struct device *emac_dev; |
2639 | |
2640 | /* obtain emac clock from kernel */ |
2641 | emac_clk = clk_get(&pdev->dev, NULL); |
2642 | if (IS_ERR(emac_clk)) { |
2643 | printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n"); |
2644 | return -EBUSY; |
2645 | } |
2646 | emac_bus_frequency = clk_get_rate(emac_clk); |
2647 | /* TODO: Probe PHY here if possible */ |
2648 | |
2649 | ndev = alloc_etherdev(sizeof(struct emac_priv)); |
2650 | if (!ndev) { |
2651 | printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n"); |
2652 | clk_put(emac_clk); |
2653 | return -ENOMEM; |
2654 | } |
2655 | |
2656 | platform_set_drvdata(pdev, ndev); |
2657 | priv = netdev_priv(ndev); |
2658 | priv->pdev = pdev; |
2659 | priv->ndev = ndev; |
2660 | priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); |
2661 | |
2662 | spin_lock_init(&priv->tx_lock); |
2663 | spin_lock_init(&priv->rx_lock); |
2664 | spin_lock_init(&priv->lock); |
2665 | |
2666 | pdata = pdev->dev.platform_data; |
2667 | if (!pdata) { |
2668 | printk(KERN_ERR "DaVinci EMAC: No platform data\n"); |
2669 | return -ENODEV; |
2670 | } |
2671 | |
2672 | /* MAC addr and PHY mask , RMII enable info from platform_data */ |
2673 | memcpy(priv->mac_addr, pdata->mac_addr, 6); |
2674 | priv->phy_mask = pdata->phy_mask; |
2675 | priv->rmii_en = pdata->rmii_en; |
2676 | priv->version = pdata->version; |
2677 | priv->int_enable = pdata->interrupt_enable; |
2678 | priv->int_disable = pdata->interrupt_disable; |
2679 | |
2680 | emac_dev = &ndev->dev; |
2681 | /* Get EMAC platform data */ |
2682 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2683 | if (!res) { |
2684 | dev_err(emac_dev, "DaVinci EMAC: Error getting res\n"); |
2685 | rc = -ENOENT; |
2686 | goto probe_quit; |
2687 | } |
2688 | |
2689 | priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; |
2690 | size = res->end - res->start + 1; |
2691 | if (!request_mem_region(res->start, size, ndev->name)) { |
2692 | dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() for regs\n"); |
2693 | rc = -ENXIO; |
2694 | goto probe_quit; |
2695 | } |
2696 | |
2697 | priv->remap_addr = ioremap(res->start, size); |
2698 | if (!priv->remap_addr) { |
2699 | dev_err(emac_dev, "Unable to map IO\n"); |
2700 | rc = -ENOMEM; |
2701 | release_mem_region(res->start, size); |
2702 | goto probe_quit; |
2703 | } |
2704 | priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; |
2705 | ndev->base_addr = (unsigned long)priv->remap_addr; |
2706 | |
2707 | priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; |
2708 | priv->ctrl_ram_size = pdata->ctrl_ram_size; |
2709 | priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset; |
2710 | |
2711 | if (pdata->hw_ram_addr) |
2712 | priv->hw_ram_addr = pdata->hw_ram_addr; |
2713 | else |
2714 | priv->hw_ram_addr = (u32 __force)res->start + |
2715 | pdata->ctrl_ram_offset; |
2716 | |
2717 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2718 | if (!res) { |
2719 | dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n"); |
2720 | rc = -ENOENT; |
2721 | goto no_irq_res; |
2722 | } |
2723 | ndev->irq = res->start; |
2724 | |
2725 | if (!is_valid_ether_addr(priv->mac_addr)) { |
2726 | /* Use random MAC if none passed */ |
2727 | random_ether_addr(priv->mac_addr); |
2728 | printk(KERN_WARNING "%s: using random MAC addr: %pM\n", |
2729 | __func__, priv->mac_addr); |
2730 | } |
2731 | |
2732 | ndev->netdev_ops = &emac_netdev_ops; |
2733 | SET_ETHTOOL_OPS(ndev, ðtool_ops); |
2734 | netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); |
2735 | |
2736 | clk_enable(emac_clk); |
2737 | |
2738 | /* register the network device */ |
2739 | SET_NETDEV_DEV(ndev, &pdev->dev); |
2740 | rc = register_netdev(ndev); |
2741 | if (rc) { |
2742 | dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n"); |
2743 | rc = -ENODEV; |
2744 | goto netdev_reg_err; |
2745 | } |
2746 | |
2747 | |
2748 | /* MII/Phy intialisation, mdio bus registration */ |
2749 | emac_mii = mdiobus_alloc(); |
2750 | if (emac_mii == NULL) { |
2751 | dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n"); |
2752 | rc = -ENOMEM; |
2753 | goto mdio_alloc_err; |
2754 | } |
2755 | |
2756 | priv->mii_bus = emac_mii; |
2757 | emac_mii->name = "emac-mii", |
2758 | emac_mii->read = emac_mii_read, |
2759 | emac_mii->write = emac_mii_write, |
2760 | emac_mii->reset = emac_mii_reset, |
2761 | emac_mii->irq = mii_irqs, |
2762 | emac_mii->phy_mask = ~(priv->phy_mask); |
2763 | emac_mii->parent = &pdev->dev; |
2764 | emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset; |
2765 | snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id); |
2766 | mdio_max_freq = pdata->mdio_max_freq; |
2767 | emac_mii->reset(emac_mii); |
2768 | |
2769 | /* Register the MII bus */ |
2770 | rc = mdiobus_register(emac_mii); |
2771 | if (rc) |
2772 | goto mdiobus_quit; |
2773 | |
2774 | if (netif_msg_probe(priv)) { |
2775 | dev_notice(emac_dev, "DaVinci EMAC Probe found device "\ |
2776 | "(regs: %p, irq: %d)\n", |
2777 | (void *)priv->emac_base_phys, ndev->irq); |
2778 | } |
2779 | return 0; |
2780 | |
2781 | mdiobus_quit: |
2782 | mdiobus_free(emac_mii); |
2783 | |
2784 | netdev_reg_err: |
2785 | mdio_alloc_err: |
2786 | clk_disable(emac_clk); |
2787 | no_irq_res: |
2788 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2789 | release_mem_region(res->start, res->end - res->start + 1); |
2790 | iounmap(priv->remap_addr); |
2791 | |
2792 | probe_quit: |
2793 | clk_put(emac_clk); |
2794 | free_netdev(ndev); |
2795 | return rc; |
2796 | } |
2797 | |
2798 | /** |
2799 | * davinci_emac_remove: EMAC device remove |
2800 | * @pdev: The DaVinci EMAC device that we are removing |
2801 | * |
2802 | * Called when removing the device driver. We disable clock usage and release |
2803 | * the resources taken up by the driver and unregister network device |
2804 | */ |
2805 | static int __devexit davinci_emac_remove(struct platform_device *pdev) |
2806 | { |
2807 | struct resource *res; |
2808 | struct net_device *ndev = platform_get_drvdata(pdev); |
2809 | struct emac_priv *priv = netdev_priv(ndev); |
2810 | |
2811 | dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); |
2812 | |
2813 | platform_set_drvdata(pdev, NULL); |
2814 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2815 | mdiobus_unregister(priv->mii_bus); |
2816 | mdiobus_free(priv->mii_bus); |
2817 | |
2818 | release_mem_region(res->start, res->end - res->start + 1); |
2819 | |
2820 | unregister_netdev(ndev); |
2821 | free_netdev(ndev); |
2822 | iounmap(priv->remap_addr); |
2823 | |
2824 | clk_disable(emac_clk); |
2825 | clk_put(emac_clk); |
2826 | |
2827 | return 0; |
2828 | } |
2829 | |
2830 | static int davinci_emac_suspend(struct device *dev) |
2831 | { |
2832 | struct platform_device *pdev = to_platform_device(dev); |
2833 | struct net_device *ndev = platform_get_drvdata(pdev); |
2834 | |
2835 | if (netif_running(ndev)) |
2836 | emac_dev_stop(ndev); |
2837 | |
2838 | clk_disable(emac_clk); |
2839 | |
2840 | return 0; |
2841 | } |
2842 | |
2843 | static int davinci_emac_resume(struct device *dev) |
2844 | { |
2845 | struct platform_device *pdev = to_platform_device(dev); |
2846 | struct net_device *ndev = platform_get_drvdata(pdev); |
2847 | |
2848 | clk_enable(emac_clk); |
2849 | |
2850 | if (netif_running(ndev)) |
2851 | emac_dev_open(ndev); |
2852 | |
2853 | return 0; |
2854 | } |
2855 | |
2856 | static const struct dev_pm_ops davinci_emac_pm_ops = { |
2857 | .suspend = davinci_emac_suspend, |
2858 | .resume = davinci_emac_resume, |
2859 | }; |
2860 | |
2861 | /** |
2862 | * davinci_emac_driver: EMAC platform driver structure |
2863 | */ |
2864 | static struct platform_driver davinci_emac_driver = { |
2865 | .driver = { |
2866 | .name = "davinci_emac", |
2867 | .owner = THIS_MODULE, |
2868 | .pm = &davinci_emac_pm_ops, |
2869 | }, |
2870 | .probe = davinci_emac_probe, |
2871 | .remove = __devexit_p(davinci_emac_remove), |
2872 | }; |
2873 | |
2874 | /** |
2875 | * davinci_emac_init: EMAC driver module init |
2876 | * |
2877 | * Called when initializing the driver. We register the driver with |
2878 | * the platform. |
2879 | */ |
2880 | static int __init davinci_emac_init(void) |
2881 | { |
2882 | return platform_driver_register(&davinci_emac_driver); |
2883 | } |
2884 | late_initcall(davinci_emac_init); |
2885 | |
2886 | /** |
2887 | * davinci_emac_exit: EMAC driver module exit |
2888 | * |
2889 | * Called when exiting the driver completely. We unregister the driver with |
2890 | * the platform and exit |
2891 | */ |
2892 | static void __exit davinci_emac_exit(void) |
2893 | { |
2894 | platform_driver_unregister(&davinci_emac_driver); |
2895 | } |
2896 | module_exit(davinci_emac_exit); |
2897 | |
2898 | MODULE_LICENSE("GPL"); |
2899 | MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); |
2900 | MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); |
2901 | MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); |
2902 |
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