Root/
1 | /** |
2 | * drivers/net/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver |
3 | * |
4 | * Copyright (c) 2009-2010 Micrel, Inc. |
5 | * Tristram Ha <Tristram.Ha@micrel.com> |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License version 2 as |
9 | * published by the Free Software Foundation. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | */ |
16 | |
17 | #include <linux/init.h> |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> |
20 | #include <linux/version.h> |
21 | #include <linux/ioport.h> |
22 | #include <linux/pci.h> |
23 | #include <linux/proc_fs.h> |
24 | #include <linux/mii.h> |
25 | #include <linux/platform_device.h> |
26 | #include <linux/ethtool.h> |
27 | #include <linux/etherdevice.h> |
28 | #include <linux/in.h> |
29 | #include <linux/ip.h> |
30 | #include <linux/if_vlan.h> |
31 | #include <linux/crc32.h> |
32 | #include <linux/sched.h> |
33 | #include <linux/slab.h> |
34 | |
35 | |
36 | /* DMA Registers */ |
37 | |
38 | #define KS_DMA_TX_CTRL 0x0000 |
39 | #define DMA_TX_ENABLE 0x00000001 |
40 | #define DMA_TX_CRC_ENABLE 0x00000002 |
41 | #define DMA_TX_PAD_ENABLE 0x00000004 |
42 | #define DMA_TX_LOOPBACK 0x00000100 |
43 | #define DMA_TX_FLOW_ENABLE 0x00000200 |
44 | #define DMA_TX_CSUM_IP 0x00010000 |
45 | #define DMA_TX_CSUM_TCP 0x00020000 |
46 | #define DMA_TX_CSUM_UDP 0x00040000 |
47 | #define DMA_TX_BURST_SIZE 0x3F000000 |
48 | |
49 | #define KS_DMA_RX_CTRL 0x0004 |
50 | #define DMA_RX_ENABLE 0x00000001 |
51 | #define KS884X_DMA_RX_MULTICAST 0x00000002 |
52 | #define DMA_RX_PROMISCUOUS 0x00000004 |
53 | #define DMA_RX_ERROR 0x00000008 |
54 | #define DMA_RX_UNICAST 0x00000010 |
55 | #define DMA_RX_ALL_MULTICAST 0x00000020 |
56 | #define DMA_RX_BROADCAST 0x00000040 |
57 | #define DMA_RX_FLOW_ENABLE 0x00000200 |
58 | #define DMA_RX_CSUM_IP 0x00010000 |
59 | #define DMA_RX_CSUM_TCP 0x00020000 |
60 | #define DMA_RX_CSUM_UDP 0x00040000 |
61 | #define DMA_RX_BURST_SIZE 0x3F000000 |
62 | |
63 | #define DMA_BURST_SHIFT 24 |
64 | #define DMA_BURST_DEFAULT 8 |
65 | |
66 | #define KS_DMA_TX_START 0x0008 |
67 | #define KS_DMA_RX_START 0x000C |
68 | #define DMA_START 0x00000001 |
69 | |
70 | #define KS_DMA_TX_ADDR 0x0010 |
71 | #define KS_DMA_RX_ADDR 0x0014 |
72 | |
73 | #define DMA_ADDR_LIST_MASK 0xFFFFFFFC |
74 | #define DMA_ADDR_LIST_SHIFT 2 |
75 | |
76 | /* MTR0 */ |
77 | #define KS884X_MULTICAST_0_OFFSET 0x0020 |
78 | #define KS884X_MULTICAST_1_OFFSET 0x0021 |
79 | #define KS884X_MULTICAST_2_OFFSET 0x0022 |
80 | #define KS884x_MULTICAST_3_OFFSET 0x0023 |
81 | /* MTR1 */ |
82 | #define KS884X_MULTICAST_4_OFFSET 0x0024 |
83 | #define KS884X_MULTICAST_5_OFFSET 0x0025 |
84 | #define KS884X_MULTICAST_6_OFFSET 0x0026 |
85 | #define KS884X_MULTICAST_7_OFFSET 0x0027 |
86 | |
87 | /* Interrupt Registers */ |
88 | |
89 | /* INTEN */ |
90 | #define KS884X_INTERRUPTS_ENABLE 0x0028 |
91 | /* INTST */ |
92 | #define KS884X_INTERRUPTS_STATUS 0x002C |
93 | |
94 | #define KS884X_INT_RX_STOPPED 0x02000000 |
95 | #define KS884X_INT_TX_STOPPED 0x04000000 |
96 | #define KS884X_INT_RX_OVERRUN 0x08000000 |
97 | #define KS884X_INT_TX_EMPTY 0x10000000 |
98 | #define KS884X_INT_RX 0x20000000 |
99 | #define KS884X_INT_TX 0x40000000 |
100 | #define KS884X_INT_PHY 0x80000000 |
101 | |
102 | #define KS884X_INT_RX_MASK \ |
103 | (KS884X_INT_RX | KS884X_INT_RX_OVERRUN) |
104 | #define KS884X_INT_TX_MASK \ |
105 | (KS884X_INT_TX | KS884X_INT_TX_EMPTY) |
106 | #define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY) |
107 | |
108 | /* MAC Additional Station Address */ |
109 | |
110 | /* MAAL0 */ |
111 | #define KS_ADD_ADDR_0_LO 0x0080 |
112 | /* MAAH0 */ |
113 | #define KS_ADD_ADDR_0_HI 0x0084 |
114 | /* MAAL1 */ |
115 | #define KS_ADD_ADDR_1_LO 0x0088 |
116 | /* MAAH1 */ |
117 | #define KS_ADD_ADDR_1_HI 0x008C |
118 | /* MAAL2 */ |
119 | #define KS_ADD_ADDR_2_LO 0x0090 |
120 | /* MAAH2 */ |
121 | #define KS_ADD_ADDR_2_HI 0x0094 |
122 | /* MAAL3 */ |
123 | #define KS_ADD_ADDR_3_LO 0x0098 |
124 | /* MAAH3 */ |
125 | #define KS_ADD_ADDR_3_HI 0x009C |
126 | /* MAAL4 */ |
127 | #define KS_ADD_ADDR_4_LO 0x00A0 |
128 | /* MAAH4 */ |
129 | #define KS_ADD_ADDR_4_HI 0x00A4 |
130 | /* MAAL5 */ |
131 | #define KS_ADD_ADDR_5_LO 0x00A8 |
132 | /* MAAH5 */ |
133 | #define KS_ADD_ADDR_5_HI 0x00AC |
134 | /* MAAL6 */ |
135 | #define KS_ADD_ADDR_6_LO 0x00B0 |
136 | /* MAAH6 */ |
137 | #define KS_ADD_ADDR_6_HI 0x00B4 |
138 | /* MAAL7 */ |
139 | #define KS_ADD_ADDR_7_LO 0x00B8 |
140 | /* MAAH7 */ |
141 | #define KS_ADD_ADDR_7_HI 0x00BC |
142 | /* MAAL8 */ |
143 | #define KS_ADD_ADDR_8_LO 0x00C0 |
144 | /* MAAH8 */ |
145 | #define KS_ADD_ADDR_8_HI 0x00C4 |
146 | /* MAAL9 */ |
147 | #define KS_ADD_ADDR_9_LO 0x00C8 |
148 | /* MAAH9 */ |
149 | #define KS_ADD_ADDR_9_HI 0x00CC |
150 | /* MAAL10 */ |
151 | #define KS_ADD_ADDR_A_LO 0x00D0 |
152 | /* MAAH10 */ |
153 | #define KS_ADD_ADDR_A_HI 0x00D4 |
154 | /* MAAL11 */ |
155 | #define KS_ADD_ADDR_B_LO 0x00D8 |
156 | /* MAAH11 */ |
157 | #define KS_ADD_ADDR_B_HI 0x00DC |
158 | /* MAAL12 */ |
159 | #define KS_ADD_ADDR_C_LO 0x00E0 |
160 | /* MAAH12 */ |
161 | #define KS_ADD_ADDR_C_HI 0x00E4 |
162 | /* MAAL13 */ |
163 | #define KS_ADD_ADDR_D_LO 0x00E8 |
164 | /* MAAH13 */ |
165 | #define KS_ADD_ADDR_D_HI 0x00EC |
166 | /* MAAL14 */ |
167 | #define KS_ADD_ADDR_E_LO 0x00F0 |
168 | /* MAAH14 */ |
169 | #define KS_ADD_ADDR_E_HI 0x00F4 |
170 | /* MAAL15 */ |
171 | #define KS_ADD_ADDR_F_LO 0x00F8 |
172 | /* MAAH15 */ |
173 | #define KS_ADD_ADDR_F_HI 0x00FC |
174 | |
175 | #define ADD_ADDR_HI_MASK 0x0000FFFF |
176 | #define ADD_ADDR_ENABLE 0x80000000 |
177 | #define ADD_ADDR_INCR 8 |
178 | |
179 | /* Miscellaneous Registers */ |
180 | |
181 | /* MARL */ |
182 | #define KS884X_ADDR_0_OFFSET 0x0200 |
183 | #define KS884X_ADDR_1_OFFSET 0x0201 |
184 | /* MARM */ |
185 | #define KS884X_ADDR_2_OFFSET 0x0202 |
186 | #define KS884X_ADDR_3_OFFSET 0x0203 |
187 | /* MARH */ |
188 | #define KS884X_ADDR_4_OFFSET 0x0204 |
189 | #define KS884X_ADDR_5_OFFSET 0x0205 |
190 | |
191 | /* OBCR */ |
192 | #define KS884X_BUS_CTRL_OFFSET 0x0210 |
193 | |
194 | #define BUS_SPEED_125_MHZ 0x0000 |
195 | #define BUS_SPEED_62_5_MHZ 0x0001 |
196 | #define BUS_SPEED_41_66_MHZ 0x0002 |
197 | #define BUS_SPEED_25_MHZ 0x0003 |
198 | |
199 | /* EEPCR */ |
200 | #define KS884X_EEPROM_CTRL_OFFSET 0x0212 |
201 | |
202 | #define EEPROM_CHIP_SELECT 0x0001 |
203 | #define EEPROM_SERIAL_CLOCK 0x0002 |
204 | #define EEPROM_DATA_OUT 0x0004 |
205 | #define EEPROM_DATA_IN 0x0008 |
206 | #define EEPROM_ACCESS_ENABLE 0x0010 |
207 | |
208 | /* MBIR */ |
209 | #define KS884X_MEM_INFO_OFFSET 0x0214 |
210 | |
211 | #define RX_MEM_TEST_FAILED 0x0008 |
212 | #define RX_MEM_TEST_FINISHED 0x0010 |
213 | #define TX_MEM_TEST_FAILED 0x0800 |
214 | #define TX_MEM_TEST_FINISHED 0x1000 |
215 | |
216 | /* GCR */ |
217 | #define KS884X_GLOBAL_CTRL_OFFSET 0x0216 |
218 | #define GLOBAL_SOFTWARE_RESET 0x0001 |
219 | |
220 | #define KS8841_POWER_MANAGE_OFFSET 0x0218 |
221 | |
222 | /* WFCR */ |
223 | #define KS8841_WOL_CTRL_OFFSET 0x021A |
224 | #define KS8841_WOL_MAGIC_ENABLE 0x0080 |
225 | #define KS8841_WOL_FRAME3_ENABLE 0x0008 |
226 | #define KS8841_WOL_FRAME2_ENABLE 0x0004 |
227 | #define KS8841_WOL_FRAME1_ENABLE 0x0002 |
228 | #define KS8841_WOL_FRAME0_ENABLE 0x0001 |
229 | |
230 | /* WF0 */ |
231 | #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220 |
232 | #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224 |
233 | #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228 |
234 | |
235 | /* IACR */ |
236 | #define KS884X_IACR_P 0x04A0 |
237 | #define KS884X_IACR_OFFSET KS884X_IACR_P |
238 | |
239 | /* IADR1 */ |
240 | #define KS884X_IADR1_P 0x04A2 |
241 | #define KS884X_IADR2_P 0x04A4 |
242 | #define KS884X_IADR3_P 0x04A6 |
243 | #define KS884X_IADR4_P 0x04A8 |
244 | #define KS884X_IADR5_P 0x04AA |
245 | |
246 | #define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P |
247 | #define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1) |
248 | |
249 | #define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P |
250 | #define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1) |
251 | #define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P |
252 | #define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1) |
253 | #define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P |
254 | #define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1) |
255 | #define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P |
256 | #define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1) |
257 | #define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P |
258 | |
259 | /* P1MBCR */ |
260 | #define KS884X_P1MBCR_P 0x04D0 |
261 | #define KS884X_P1MBSR_P 0x04D2 |
262 | #define KS884X_PHY1ILR_P 0x04D4 |
263 | #define KS884X_PHY1IHR_P 0x04D6 |
264 | #define KS884X_P1ANAR_P 0x04D8 |
265 | #define KS884X_P1ANLPR_P 0x04DA |
266 | |
267 | /* P2MBCR */ |
268 | #define KS884X_P2MBCR_P 0x04E0 |
269 | #define KS884X_P2MBSR_P 0x04E2 |
270 | #define KS884X_PHY2ILR_P 0x04E4 |
271 | #define KS884X_PHY2IHR_P 0x04E6 |
272 | #define KS884X_P2ANAR_P 0x04E8 |
273 | #define KS884X_P2ANLPR_P 0x04EA |
274 | |
275 | #define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P |
276 | #define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P) |
277 | |
278 | #define KS884X_PHY_CTRL_OFFSET 0x00 |
279 | |
280 | /* Mode Control Register */ |
281 | #define PHY_REG_CTRL 0 |
282 | |
283 | #define PHY_RESET 0x8000 |
284 | #define PHY_LOOPBACK 0x4000 |
285 | #define PHY_SPEED_100MBIT 0x2000 |
286 | #define PHY_AUTO_NEG_ENABLE 0x1000 |
287 | #define PHY_POWER_DOWN 0x0800 |
288 | #define PHY_MII_DISABLE 0x0400 |
289 | #define PHY_AUTO_NEG_RESTART 0x0200 |
290 | #define PHY_FULL_DUPLEX 0x0100 |
291 | #define PHY_COLLISION_TEST 0x0080 |
292 | #define PHY_HP_MDIX 0x0020 |
293 | #define PHY_FORCE_MDIX 0x0010 |
294 | #define PHY_AUTO_MDIX_DISABLE 0x0008 |
295 | #define PHY_REMOTE_FAULT_DISABLE 0x0004 |
296 | #define PHY_TRANSMIT_DISABLE 0x0002 |
297 | #define PHY_LED_DISABLE 0x0001 |
298 | |
299 | #define KS884X_PHY_STATUS_OFFSET 0x02 |
300 | |
301 | /* Mode Status Register */ |
302 | #define PHY_REG_STATUS 1 |
303 | |
304 | #define PHY_100BT4_CAPABLE 0x8000 |
305 | #define PHY_100BTX_FD_CAPABLE 0x4000 |
306 | #define PHY_100BTX_CAPABLE 0x2000 |
307 | #define PHY_10BT_FD_CAPABLE 0x1000 |
308 | #define PHY_10BT_CAPABLE 0x0800 |
309 | #define PHY_MII_SUPPRESS_CAPABLE 0x0040 |
310 | #define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020 |
311 | #define PHY_REMOTE_FAULT 0x0010 |
312 | #define PHY_AUTO_NEG_CAPABLE 0x0008 |
313 | #define PHY_LINK_STATUS 0x0004 |
314 | #define PHY_JABBER_DETECT 0x0002 |
315 | #define PHY_EXTENDED_CAPABILITY 0x0001 |
316 | |
317 | #define KS884X_PHY_ID_1_OFFSET 0x04 |
318 | #define KS884X_PHY_ID_2_OFFSET 0x06 |
319 | |
320 | /* PHY Identifier Registers */ |
321 | #define PHY_REG_ID_1 2 |
322 | #define PHY_REG_ID_2 3 |
323 | |
324 | #define KS884X_PHY_AUTO_NEG_OFFSET 0x08 |
325 | |
326 | /* Auto-Negotiation Advertisement Register */ |
327 | #define PHY_REG_AUTO_NEGOTIATION 4 |
328 | |
329 | #define PHY_AUTO_NEG_NEXT_PAGE 0x8000 |
330 | #define PHY_AUTO_NEG_REMOTE_FAULT 0x2000 |
331 | /* Not supported. */ |
332 | #define PHY_AUTO_NEG_ASYM_PAUSE 0x0800 |
333 | #define PHY_AUTO_NEG_SYM_PAUSE 0x0400 |
334 | #define PHY_AUTO_NEG_100BT4 0x0200 |
335 | #define PHY_AUTO_NEG_100BTX_FD 0x0100 |
336 | #define PHY_AUTO_NEG_100BTX 0x0080 |
337 | #define PHY_AUTO_NEG_10BT_FD 0x0040 |
338 | #define PHY_AUTO_NEG_10BT 0x0020 |
339 | #define PHY_AUTO_NEG_SELECTOR 0x001F |
340 | #define PHY_AUTO_NEG_802_3 0x0001 |
341 | |
342 | #define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE) |
343 | |
344 | #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A |
345 | |
346 | /* Auto-Negotiation Link Partner Ability Register */ |
347 | #define PHY_REG_REMOTE_CAPABILITY 5 |
348 | |
349 | #define PHY_REMOTE_NEXT_PAGE 0x8000 |
350 | #define PHY_REMOTE_ACKNOWLEDGE 0x4000 |
351 | #define PHY_REMOTE_REMOTE_FAULT 0x2000 |
352 | #define PHY_REMOTE_SYM_PAUSE 0x0400 |
353 | #define PHY_REMOTE_100BTX_FD 0x0100 |
354 | #define PHY_REMOTE_100BTX 0x0080 |
355 | #define PHY_REMOTE_10BT_FD 0x0040 |
356 | #define PHY_REMOTE_10BT 0x0020 |
357 | |
358 | /* P1VCT */ |
359 | #define KS884X_P1VCT_P 0x04F0 |
360 | #define KS884X_P1PHYCTRL_P 0x04F2 |
361 | |
362 | /* P2VCT */ |
363 | #define KS884X_P2VCT_P 0x04F4 |
364 | #define KS884X_P2PHYCTRL_P 0x04F6 |
365 | |
366 | #define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P |
367 | #define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P) |
368 | |
369 | #define KS884X_PHY_LINK_MD_OFFSET 0x00 |
370 | |
371 | #define PHY_START_CABLE_DIAG 0x8000 |
372 | #define PHY_CABLE_DIAG_RESULT 0x6000 |
373 | #define PHY_CABLE_STAT_NORMAL 0x0000 |
374 | #define PHY_CABLE_STAT_OPEN 0x2000 |
375 | #define PHY_CABLE_STAT_SHORT 0x4000 |
376 | #define PHY_CABLE_STAT_FAILED 0x6000 |
377 | #define PHY_CABLE_10M_SHORT 0x1000 |
378 | #define PHY_CABLE_FAULT_COUNTER 0x01FF |
379 | |
380 | #define KS884X_PHY_PHY_CTRL_OFFSET 0x02 |
381 | |
382 | #define PHY_STAT_REVERSED_POLARITY 0x0020 |
383 | #define PHY_STAT_MDIX 0x0010 |
384 | #define PHY_FORCE_LINK 0x0008 |
385 | #define PHY_POWER_SAVING_DISABLE 0x0004 |
386 | #define PHY_REMOTE_LOOPBACK 0x0002 |
387 | |
388 | /* SIDER */ |
389 | #define KS884X_SIDER_P 0x0400 |
390 | #define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P |
391 | #define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1) |
392 | |
393 | #define REG_FAMILY_ID 0x88 |
394 | |
395 | #define REG_CHIP_ID_41 0x8810 |
396 | #define REG_CHIP_ID_42 0x8800 |
397 | |
398 | #define KS884X_CHIP_ID_MASK_41 0xFF10 |
399 | #define KS884X_CHIP_ID_MASK 0xFFF0 |
400 | #define KS884X_CHIP_ID_SHIFT 4 |
401 | #define KS884X_REVISION_MASK 0x000E |
402 | #define KS884X_REVISION_SHIFT 1 |
403 | #define KS8842_START 0x0001 |
404 | |
405 | #define CHIP_IP_41_M 0x8810 |
406 | #define CHIP_IP_42_M 0x8800 |
407 | #define CHIP_IP_61_M 0x8890 |
408 | #define CHIP_IP_62_M 0x8880 |
409 | |
410 | #define CHIP_IP_41_P 0x8850 |
411 | #define CHIP_IP_42_P 0x8840 |
412 | #define CHIP_IP_61_P 0x88D0 |
413 | #define CHIP_IP_62_P 0x88C0 |
414 | |
415 | /* SGCR1 */ |
416 | #define KS8842_SGCR1_P 0x0402 |
417 | #define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P |
418 | |
419 | #define SWITCH_PASS_ALL 0x8000 |
420 | #define SWITCH_TX_FLOW_CTRL 0x2000 |
421 | #define SWITCH_RX_FLOW_CTRL 0x1000 |
422 | #define SWITCH_CHECK_LENGTH 0x0800 |
423 | #define SWITCH_AGING_ENABLE 0x0400 |
424 | #define SWITCH_FAST_AGING 0x0200 |
425 | #define SWITCH_AGGR_BACKOFF 0x0100 |
426 | #define SWITCH_PASS_PAUSE 0x0008 |
427 | #define SWITCH_LINK_AUTO_AGING 0x0001 |
428 | |
429 | /* SGCR2 */ |
430 | #define KS8842_SGCR2_P 0x0404 |
431 | #define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P |
432 | |
433 | #define SWITCH_VLAN_ENABLE 0x8000 |
434 | #define SWITCH_IGMP_SNOOP 0x4000 |
435 | #define IPV6_MLD_SNOOP_ENABLE 0x2000 |
436 | #define IPV6_MLD_SNOOP_OPTION 0x1000 |
437 | #define PRIORITY_SCHEME_SELECT 0x0800 |
438 | #define SWITCH_MIRROR_RX_TX 0x0100 |
439 | #define UNICAST_VLAN_BOUNDARY 0x0080 |
440 | #define MULTICAST_STORM_DISABLE 0x0040 |
441 | #define SWITCH_BACK_PRESSURE 0x0020 |
442 | #define FAIR_FLOW_CTRL 0x0010 |
443 | #define NO_EXC_COLLISION_DROP 0x0008 |
444 | #define SWITCH_HUGE_PACKET 0x0004 |
445 | #define SWITCH_LEGAL_PACKET 0x0002 |
446 | #define SWITCH_BUF_RESERVE 0x0001 |
447 | |
448 | /* SGCR3 */ |
449 | #define KS8842_SGCR3_P 0x0406 |
450 | #define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P |
451 | |
452 | #define BROADCAST_STORM_RATE_LO 0xFF00 |
453 | #define SWITCH_REPEATER 0x0080 |
454 | #define SWITCH_HALF_DUPLEX 0x0040 |
455 | #define SWITCH_FLOW_CTRL 0x0020 |
456 | #define SWITCH_10_MBIT 0x0010 |
457 | #define SWITCH_REPLACE_NULL_VID 0x0008 |
458 | #define BROADCAST_STORM_RATE_HI 0x0007 |
459 | |
460 | #define BROADCAST_STORM_RATE 0x07FF |
461 | |
462 | /* SGCR4 */ |
463 | #define KS8842_SGCR4_P 0x0408 |
464 | |
465 | /* SGCR5 */ |
466 | #define KS8842_SGCR5_P 0x040A |
467 | #define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P |
468 | |
469 | #define LED_MODE 0x8200 |
470 | #define LED_SPEED_DUPLEX_ACT 0x0000 |
471 | #define LED_SPEED_DUPLEX_LINK_ACT 0x8000 |
472 | #define LED_DUPLEX_10_100 0x0200 |
473 | |
474 | /* SGCR6 */ |
475 | #define KS8842_SGCR6_P 0x0410 |
476 | #define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P |
477 | |
478 | #define KS8842_PRIORITY_MASK 3 |
479 | #define KS8842_PRIORITY_SHIFT 2 |
480 | |
481 | /* SGCR7 */ |
482 | #define KS8842_SGCR7_P 0x0412 |
483 | #define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P |
484 | |
485 | #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008 |
486 | #define SWITCH_UNK_DEF_PORT_3 0x0004 |
487 | #define SWITCH_UNK_DEF_PORT_2 0x0002 |
488 | #define SWITCH_UNK_DEF_PORT_1 0x0001 |
489 | |
490 | /* MACAR1 */ |
491 | #define KS8842_MACAR1_P 0x0470 |
492 | #define KS8842_MACAR2_P 0x0472 |
493 | #define KS8842_MACAR3_P 0x0474 |
494 | #define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P |
495 | #define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1) |
496 | #define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P |
497 | #define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1) |
498 | #define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P |
499 | #define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1) |
500 | |
501 | /* TOSR1 */ |
502 | #define KS8842_TOSR1_P 0x0480 |
503 | #define KS8842_TOSR2_P 0x0482 |
504 | #define KS8842_TOSR3_P 0x0484 |
505 | #define KS8842_TOSR4_P 0x0486 |
506 | #define KS8842_TOSR5_P 0x0488 |
507 | #define KS8842_TOSR6_P 0x048A |
508 | #define KS8842_TOSR7_P 0x0490 |
509 | #define KS8842_TOSR8_P 0x0492 |
510 | #define KS8842_TOS_1_OFFSET KS8842_TOSR1_P |
511 | #define KS8842_TOS_2_OFFSET KS8842_TOSR2_P |
512 | #define KS8842_TOS_3_OFFSET KS8842_TOSR3_P |
513 | #define KS8842_TOS_4_OFFSET KS8842_TOSR4_P |
514 | #define KS8842_TOS_5_OFFSET KS8842_TOSR5_P |
515 | #define KS8842_TOS_6_OFFSET KS8842_TOSR6_P |
516 | |
517 | #define KS8842_TOS_7_OFFSET KS8842_TOSR7_P |
518 | #define KS8842_TOS_8_OFFSET KS8842_TOSR8_P |
519 | |
520 | /* P1CR1 */ |
521 | #define KS8842_P1CR1_P 0x0500 |
522 | #define KS8842_P1CR2_P 0x0502 |
523 | #define KS8842_P1VIDR_P 0x0504 |
524 | #define KS8842_P1CR3_P 0x0506 |
525 | #define KS8842_P1IRCR_P 0x0508 |
526 | #define KS8842_P1ERCR_P 0x050A |
527 | #define KS884X_P1SCSLMD_P 0x0510 |
528 | #define KS884X_P1CR4_P 0x0512 |
529 | #define KS884X_P1SR_P 0x0514 |
530 | |
531 | /* P2CR1 */ |
532 | #define KS8842_P2CR1_P 0x0520 |
533 | #define KS8842_P2CR2_P 0x0522 |
534 | #define KS8842_P2VIDR_P 0x0524 |
535 | #define KS8842_P2CR3_P 0x0526 |
536 | #define KS8842_P2IRCR_P 0x0528 |
537 | #define KS8842_P2ERCR_P 0x052A |
538 | #define KS884X_P2SCSLMD_P 0x0530 |
539 | #define KS884X_P2CR4_P 0x0532 |
540 | #define KS884X_P2SR_P 0x0534 |
541 | |
542 | /* P3CR1 */ |
543 | #define KS8842_P3CR1_P 0x0540 |
544 | #define KS8842_P3CR2_P 0x0542 |
545 | #define KS8842_P3VIDR_P 0x0544 |
546 | #define KS8842_P3CR3_P 0x0546 |
547 | #define KS8842_P3IRCR_P 0x0548 |
548 | #define KS8842_P3ERCR_P 0x054A |
549 | |
550 | #define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P |
551 | #define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P |
552 | #define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P |
553 | |
554 | #define PORT_CTRL_ADDR(port, addr) \ |
555 | (addr = KS8842_PORT_1_CTRL_1 + (port) * \ |
556 | (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1)) |
557 | |
558 | #define KS8842_PORT_CTRL_1_OFFSET 0x00 |
559 | |
560 | #define PORT_BROADCAST_STORM 0x0080 |
561 | #define PORT_DIFFSERV_ENABLE 0x0040 |
562 | #define PORT_802_1P_ENABLE 0x0020 |
563 | #define PORT_BASED_PRIORITY_MASK 0x0018 |
564 | #define PORT_BASED_PRIORITY_BASE 0x0003 |
565 | #define PORT_BASED_PRIORITY_SHIFT 3 |
566 | #define PORT_BASED_PRIORITY_0 0x0000 |
567 | #define PORT_BASED_PRIORITY_1 0x0008 |
568 | #define PORT_BASED_PRIORITY_2 0x0010 |
569 | #define PORT_BASED_PRIORITY_3 0x0018 |
570 | #define PORT_INSERT_TAG 0x0004 |
571 | #define PORT_REMOVE_TAG 0x0002 |
572 | #define PORT_PRIO_QUEUE_ENABLE 0x0001 |
573 | |
574 | #define KS8842_PORT_CTRL_2_OFFSET 0x02 |
575 | |
576 | #define PORT_INGRESS_VLAN_FILTER 0x4000 |
577 | #define PORT_DISCARD_NON_VID 0x2000 |
578 | #define PORT_FORCE_FLOW_CTRL 0x1000 |
579 | #define PORT_BACK_PRESSURE 0x0800 |
580 | #define PORT_TX_ENABLE 0x0400 |
581 | #define PORT_RX_ENABLE 0x0200 |
582 | #define PORT_LEARN_DISABLE 0x0100 |
583 | #define PORT_MIRROR_SNIFFER 0x0080 |
584 | #define PORT_MIRROR_RX 0x0040 |
585 | #define PORT_MIRROR_TX 0x0020 |
586 | #define PORT_USER_PRIORITY_CEILING 0x0008 |
587 | #define PORT_VLAN_MEMBERSHIP 0x0007 |
588 | |
589 | #define KS8842_PORT_CTRL_VID_OFFSET 0x04 |
590 | |
591 | #define PORT_DEFAULT_VID 0x0001 |
592 | |
593 | #define KS8842_PORT_CTRL_3_OFFSET 0x06 |
594 | |
595 | #define PORT_INGRESS_LIMIT_MODE 0x000C |
596 | #define PORT_INGRESS_ALL 0x0000 |
597 | #define PORT_INGRESS_UNICAST 0x0004 |
598 | #define PORT_INGRESS_MULTICAST 0x0008 |
599 | #define PORT_INGRESS_BROADCAST 0x000C |
600 | #define PORT_COUNT_IFG 0x0002 |
601 | #define PORT_COUNT_PREAMBLE 0x0001 |
602 | |
603 | #define KS8842_PORT_IN_RATE_OFFSET 0x08 |
604 | #define KS8842_PORT_OUT_RATE_OFFSET 0x0A |
605 | |
606 | #define PORT_PRIORITY_RATE 0x0F |
607 | #define PORT_PRIORITY_RATE_SHIFT 4 |
608 | |
609 | #define KS884X_PORT_LINK_MD 0x10 |
610 | |
611 | #define PORT_CABLE_10M_SHORT 0x8000 |
612 | #define PORT_CABLE_DIAG_RESULT 0x6000 |
613 | #define PORT_CABLE_STAT_NORMAL 0x0000 |
614 | #define PORT_CABLE_STAT_OPEN 0x2000 |
615 | #define PORT_CABLE_STAT_SHORT 0x4000 |
616 | #define PORT_CABLE_STAT_FAILED 0x6000 |
617 | #define PORT_START_CABLE_DIAG 0x1000 |
618 | #define PORT_FORCE_LINK 0x0800 |
619 | #define PORT_POWER_SAVING_DISABLE 0x0400 |
620 | #define PORT_PHY_REMOTE_LOOPBACK 0x0200 |
621 | #define PORT_CABLE_FAULT_COUNTER 0x01FF |
622 | |
623 | #define KS884X_PORT_CTRL_4_OFFSET 0x12 |
624 | |
625 | #define PORT_LED_OFF 0x8000 |
626 | #define PORT_TX_DISABLE 0x4000 |
627 | #define PORT_AUTO_NEG_RESTART 0x2000 |
628 | #define PORT_REMOTE_FAULT_DISABLE 0x1000 |
629 | #define PORT_POWER_DOWN 0x0800 |
630 | #define PORT_AUTO_MDIX_DISABLE 0x0400 |
631 | #define PORT_FORCE_MDIX 0x0200 |
632 | #define PORT_LOOPBACK 0x0100 |
633 | #define PORT_AUTO_NEG_ENABLE 0x0080 |
634 | #define PORT_FORCE_100_MBIT 0x0040 |
635 | #define PORT_FORCE_FULL_DUPLEX 0x0020 |
636 | #define PORT_AUTO_NEG_SYM_PAUSE 0x0010 |
637 | #define PORT_AUTO_NEG_100BTX_FD 0x0008 |
638 | #define PORT_AUTO_NEG_100BTX 0x0004 |
639 | #define PORT_AUTO_NEG_10BT_FD 0x0002 |
640 | #define PORT_AUTO_NEG_10BT 0x0001 |
641 | |
642 | #define KS884X_PORT_STATUS_OFFSET 0x14 |
643 | |
644 | #define PORT_HP_MDIX 0x8000 |
645 | #define PORT_REVERSED_POLARITY 0x2000 |
646 | #define PORT_RX_FLOW_CTRL 0x0800 |
647 | #define PORT_TX_FLOW_CTRL 0x1000 |
648 | #define PORT_STATUS_SPEED_100MBIT 0x0400 |
649 | #define PORT_STATUS_FULL_DUPLEX 0x0200 |
650 | #define PORT_REMOTE_FAULT 0x0100 |
651 | #define PORT_MDIX_STATUS 0x0080 |
652 | #define PORT_AUTO_NEG_COMPLETE 0x0040 |
653 | #define PORT_STATUS_LINK_GOOD 0x0020 |
654 | #define PORT_REMOTE_SYM_PAUSE 0x0010 |
655 | #define PORT_REMOTE_100BTX_FD 0x0008 |
656 | #define PORT_REMOTE_100BTX 0x0004 |
657 | #define PORT_REMOTE_10BT_FD 0x0002 |
658 | #define PORT_REMOTE_10BT 0x0001 |
659 | |
660 | /* |
661 | #define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF |
662 | #define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000 |
663 | #define STATIC_MAC_TABLE_VALID 00-00080000-00000000 |
664 | #define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000 |
665 | #define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000 |
666 | #define STATIC_MAC_TABLE_FID 00-03C00000-00000000 |
667 | */ |
668 | |
669 | #define STATIC_MAC_TABLE_ADDR 0x0000FFFF |
670 | #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000 |
671 | #define STATIC_MAC_TABLE_VALID 0x00080000 |
672 | #define STATIC_MAC_TABLE_OVERRIDE 0x00100000 |
673 | #define STATIC_MAC_TABLE_USE_FID 0x00200000 |
674 | #define STATIC_MAC_TABLE_FID 0x03C00000 |
675 | |
676 | #define STATIC_MAC_FWD_PORTS_SHIFT 16 |
677 | #define STATIC_MAC_FID_SHIFT 22 |
678 | |
679 | /* |
680 | #define VLAN_TABLE_VID 00-00000000-00000FFF |
681 | #define VLAN_TABLE_FID 00-00000000-0000F000 |
682 | #define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000 |
683 | #define VLAN_TABLE_VALID 00-00000000-00080000 |
684 | */ |
685 | |
686 | #define VLAN_TABLE_VID 0x00000FFF |
687 | #define VLAN_TABLE_FID 0x0000F000 |
688 | #define VLAN_TABLE_MEMBERSHIP 0x00070000 |
689 | #define VLAN_TABLE_VALID 0x00080000 |
690 | |
691 | #define VLAN_TABLE_FID_SHIFT 12 |
692 | #define VLAN_TABLE_MEMBERSHIP_SHIFT 16 |
693 | |
694 | /* |
695 | #define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF |
696 | #define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000 |
697 | #define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000 |
698 | #define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000 |
699 | #define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000 |
700 | #define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000 |
701 | #define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000 |
702 | #define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000 |
703 | */ |
704 | |
705 | #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF |
706 | #define DYNAMIC_MAC_TABLE_FID 0x000F0000 |
707 | #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000 |
708 | #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000 |
709 | #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000 |
710 | |
711 | #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03 |
712 | #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04 |
713 | #define DYNAMIC_MAC_TABLE_RESERVED 0x78 |
714 | #define DYNAMIC_MAC_TABLE_NOT_READY 0x80 |
715 | |
716 | #define DYNAMIC_MAC_FID_SHIFT 16 |
717 | #define DYNAMIC_MAC_SRC_PORT_SHIFT 20 |
718 | #define DYNAMIC_MAC_TIMESTAMP_SHIFT 22 |
719 | #define DYNAMIC_MAC_ENTRIES_SHIFT 24 |
720 | #define DYNAMIC_MAC_ENTRIES_H_SHIFT 8 |
721 | |
722 | /* |
723 | #define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF |
724 | #define MIB_COUNTER_VALID 00-00000000-40000000 |
725 | #define MIB_COUNTER_OVERFLOW 00-00000000-80000000 |
726 | */ |
727 | |
728 | #define MIB_COUNTER_VALUE 0x3FFFFFFF |
729 | #define MIB_COUNTER_VALID 0x40000000 |
730 | #define MIB_COUNTER_OVERFLOW 0x80000000 |
731 | |
732 | #define MIB_PACKET_DROPPED 0x0000FFFF |
733 | |
734 | #define KS_MIB_PACKET_DROPPED_TX_0 0x100 |
735 | #define KS_MIB_PACKET_DROPPED_TX_1 0x101 |
736 | #define KS_MIB_PACKET_DROPPED_TX 0x102 |
737 | #define KS_MIB_PACKET_DROPPED_RX_0 0x103 |
738 | #define KS_MIB_PACKET_DROPPED_RX_1 0x104 |
739 | #define KS_MIB_PACKET_DROPPED_RX 0x105 |
740 | |
741 | /* Change default LED mode. */ |
742 | #define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT |
743 | |
744 | #define MAC_ADDR_LEN 6 |
745 | #define MAC_ADDR_ORDER(i) (MAC_ADDR_LEN - 1 - (i)) |
746 | |
747 | #define MAX_ETHERNET_BODY_SIZE 1500 |
748 | #define ETHERNET_HEADER_SIZE 14 |
749 | |
750 | #define MAX_ETHERNET_PACKET_SIZE \ |
751 | (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE) |
752 | |
753 | #define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4) |
754 | #define MAX_RX_BUF_SIZE (1912 + 4) |
755 | |
756 | #define ADDITIONAL_ENTRIES 16 |
757 | #define MAX_MULTICAST_LIST 32 |
758 | |
759 | #define HW_MULTICAST_SIZE 8 |
760 | |
761 | #define HW_TO_DEV_PORT(port) (port - 1) |
762 | |
763 | enum { |
764 | media_connected, |
765 | media_disconnected |
766 | }; |
767 | |
768 | enum { |
769 | OID_COUNTER_UNKOWN, |
770 | |
771 | OID_COUNTER_FIRST, |
772 | |
773 | /* total transmit errors */ |
774 | OID_COUNTER_XMIT_ERROR, |
775 | |
776 | /* total receive errors */ |
777 | OID_COUNTER_RCV_ERROR, |
778 | |
779 | OID_COUNTER_LAST |
780 | }; |
781 | |
782 | /* |
783 | * Hardware descriptor definitions |
784 | */ |
785 | |
786 | #define DESC_ALIGNMENT 16 |
787 | #define BUFFER_ALIGNMENT 8 |
788 | |
789 | #define NUM_OF_RX_DESC 64 |
790 | #define NUM_OF_TX_DESC 64 |
791 | |
792 | #define KS_DESC_RX_FRAME_LEN 0x000007FF |
793 | #define KS_DESC_RX_FRAME_TYPE 0x00008000 |
794 | #define KS_DESC_RX_ERROR_CRC 0x00010000 |
795 | #define KS_DESC_RX_ERROR_RUNT 0x00020000 |
796 | #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000 |
797 | #define KS_DESC_RX_ERROR_PHY 0x00080000 |
798 | #define KS884X_DESC_RX_PORT_MASK 0x00300000 |
799 | #define KS_DESC_RX_MULTICAST 0x01000000 |
800 | #define KS_DESC_RX_ERROR 0x02000000 |
801 | #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000 |
802 | #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000 |
803 | #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000 |
804 | #define KS_DESC_RX_LAST 0x20000000 |
805 | #define KS_DESC_RX_FIRST 0x40000000 |
806 | #define KS_DESC_RX_ERROR_COND \ |
807 | (KS_DESC_RX_ERROR_CRC | \ |
808 | KS_DESC_RX_ERROR_RUNT | \ |
809 | KS_DESC_RX_ERROR_PHY | \ |
810 | KS_DESC_RX_ERROR_TOO_LONG) |
811 | |
812 | #define KS_DESC_HW_OWNED 0x80000000 |
813 | |
814 | #define KS_DESC_BUF_SIZE 0x000007FF |
815 | #define KS884X_DESC_TX_PORT_MASK 0x00300000 |
816 | #define KS_DESC_END_OF_RING 0x02000000 |
817 | #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000 |
818 | #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000 |
819 | #define KS_DESC_TX_CSUM_GEN_IP 0x10000000 |
820 | #define KS_DESC_TX_LAST 0x20000000 |
821 | #define KS_DESC_TX_FIRST 0x40000000 |
822 | #define KS_DESC_TX_INTERRUPT 0x80000000 |
823 | |
824 | #define KS_DESC_PORT_SHIFT 20 |
825 | |
826 | #define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE) |
827 | |
828 | #define KS_DESC_TX_MASK \ |
829 | (KS_DESC_TX_INTERRUPT | \ |
830 | KS_DESC_TX_FIRST | \ |
831 | KS_DESC_TX_LAST | \ |
832 | KS_DESC_TX_CSUM_GEN_IP | \ |
833 | KS_DESC_TX_CSUM_GEN_TCP | \ |
834 | KS_DESC_TX_CSUM_GEN_UDP | \ |
835 | KS_DESC_BUF_SIZE) |
836 | |
837 | struct ksz_desc_rx_stat { |
838 | #ifdef __BIG_ENDIAN_BITFIELD |
839 | u32 hw_owned:1; |
840 | u32 first_desc:1; |
841 | u32 last_desc:1; |
842 | u32 csum_err_ip:1; |
843 | u32 csum_err_tcp:1; |
844 | u32 csum_err_udp:1; |
845 | u32 error:1; |
846 | u32 multicast:1; |
847 | u32 src_port:4; |
848 | u32 err_phy:1; |
849 | u32 err_too_long:1; |
850 | u32 err_runt:1; |
851 | u32 err_crc:1; |
852 | u32 frame_type:1; |
853 | u32 reserved1:4; |
854 | u32 frame_len:11; |
855 | #else |
856 | u32 frame_len:11; |
857 | u32 reserved1:4; |
858 | u32 frame_type:1; |
859 | u32 err_crc:1; |
860 | u32 err_runt:1; |
861 | u32 err_too_long:1; |
862 | u32 err_phy:1; |
863 | u32 src_port:4; |
864 | u32 multicast:1; |
865 | u32 error:1; |
866 | u32 csum_err_udp:1; |
867 | u32 csum_err_tcp:1; |
868 | u32 csum_err_ip:1; |
869 | u32 last_desc:1; |
870 | u32 first_desc:1; |
871 | u32 hw_owned:1; |
872 | #endif |
873 | }; |
874 | |
875 | struct ksz_desc_tx_stat { |
876 | #ifdef __BIG_ENDIAN_BITFIELD |
877 | u32 hw_owned:1; |
878 | u32 reserved1:31; |
879 | #else |
880 | u32 reserved1:31; |
881 | u32 hw_owned:1; |
882 | #endif |
883 | }; |
884 | |
885 | struct ksz_desc_rx_buf { |
886 | #ifdef __BIG_ENDIAN_BITFIELD |
887 | u32 reserved4:6; |
888 | u32 end_of_ring:1; |
889 | u32 reserved3:14; |
890 | u32 buf_size:11; |
891 | #else |
892 | u32 buf_size:11; |
893 | u32 reserved3:14; |
894 | u32 end_of_ring:1; |
895 | u32 reserved4:6; |
896 | #endif |
897 | }; |
898 | |
899 | struct ksz_desc_tx_buf { |
900 | #ifdef __BIG_ENDIAN_BITFIELD |
901 | u32 intr:1; |
902 | u32 first_seg:1; |
903 | u32 last_seg:1; |
904 | u32 csum_gen_ip:1; |
905 | u32 csum_gen_tcp:1; |
906 | u32 csum_gen_udp:1; |
907 | u32 end_of_ring:1; |
908 | u32 reserved4:1; |
909 | u32 dest_port:4; |
910 | u32 reserved3:9; |
911 | u32 buf_size:11; |
912 | #else |
913 | u32 buf_size:11; |
914 | u32 reserved3:9; |
915 | u32 dest_port:4; |
916 | u32 reserved4:1; |
917 | u32 end_of_ring:1; |
918 | u32 csum_gen_udp:1; |
919 | u32 csum_gen_tcp:1; |
920 | u32 csum_gen_ip:1; |
921 | u32 last_seg:1; |
922 | u32 first_seg:1; |
923 | u32 intr:1; |
924 | #endif |
925 | }; |
926 | |
927 | union desc_stat { |
928 | struct ksz_desc_rx_stat rx; |
929 | struct ksz_desc_tx_stat tx; |
930 | u32 data; |
931 | }; |
932 | |
933 | union desc_buf { |
934 | struct ksz_desc_rx_buf rx; |
935 | struct ksz_desc_tx_buf tx; |
936 | u32 data; |
937 | }; |
938 | |
939 | /** |
940 | * struct ksz_hw_desc - Hardware descriptor data structure |
941 | * @ctrl: Descriptor control value. |
942 | * @buf: Descriptor buffer value. |
943 | * @addr: Physical address of memory buffer. |
944 | * @next: Pointer to next hardware descriptor. |
945 | */ |
946 | struct ksz_hw_desc { |
947 | union desc_stat ctrl; |
948 | union desc_buf buf; |
949 | u32 addr; |
950 | u32 next; |
951 | }; |
952 | |
953 | /** |
954 | * struct ksz_sw_desc - Software descriptor data structure |
955 | * @ctrl: Descriptor control value. |
956 | * @buf: Descriptor buffer value. |
957 | * @buf_size: Current buffers size value in hardware descriptor. |
958 | */ |
959 | struct ksz_sw_desc { |
960 | union desc_stat ctrl; |
961 | union desc_buf buf; |
962 | u32 buf_size; |
963 | }; |
964 | |
965 | /** |
966 | * struct ksz_dma_buf - OS dependent DMA buffer data structure |
967 | * @skb: Associated socket buffer. |
968 | * @dma: Associated physical DMA address. |
969 | * len: Actual len used. |
970 | */ |
971 | struct ksz_dma_buf { |
972 | struct sk_buff *skb; |
973 | dma_addr_t dma; |
974 | int len; |
975 | }; |
976 | |
977 | /** |
978 | * struct ksz_desc - Descriptor structure |
979 | * @phw: Hardware descriptor pointer to uncached physical memory. |
980 | * @sw: Cached memory to hold hardware descriptor values for |
981 | * manipulation. |
982 | * @dma_buf: Operating system dependent data structure to hold physical |
983 | * memory buffer allocation information. |
984 | */ |
985 | struct ksz_desc { |
986 | struct ksz_hw_desc *phw; |
987 | struct ksz_sw_desc sw; |
988 | struct ksz_dma_buf dma_buf; |
989 | }; |
990 | |
991 | #define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf)) |
992 | |
993 | /** |
994 | * struct ksz_desc_info - Descriptor information data structure |
995 | * @ring: First descriptor in the ring. |
996 | * @cur: Current descriptor being manipulated. |
997 | * @ring_virt: First hardware descriptor in the ring. |
998 | * @ring_phys: The physical address of the first descriptor of the ring. |
999 | * @size: Size of hardware descriptor. |
1000 | * @alloc: Number of descriptors allocated. |
1001 | * @avail: Number of descriptors available for use. |
1002 | * @last: Index for last descriptor released to hardware. |
1003 | * @next: Index for next descriptor available for use. |
1004 | * @mask: Mask for index wrapping. |
1005 | */ |
1006 | struct ksz_desc_info { |
1007 | struct ksz_desc *ring; |
1008 | struct ksz_desc *cur; |
1009 | struct ksz_hw_desc *ring_virt; |
1010 | u32 ring_phys; |
1011 | int size; |
1012 | int alloc; |
1013 | int avail; |
1014 | int last; |
1015 | int next; |
1016 | int mask; |
1017 | }; |
1018 | |
1019 | /* |
1020 | * KSZ8842 switch definitions |
1021 | */ |
1022 | |
1023 | enum { |
1024 | TABLE_STATIC_MAC = 0, |
1025 | TABLE_VLAN, |
1026 | TABLE_DYNAMIC_MAC, |
1027 | TABLE_MIB |
1028 | }; |
1029 | |
1030 | #define LEARNED_MAC_TABLE_ENTRIES 1024 |
1031 | #define STATIC_MAC_TABLE_ENTRIES 8 |
1032 | |
1033 | /** |
1034 | * struct ksz_mac_table - Static MAC table data structure |
1035 | * @mac_addr: MAC address to filter. |
1036 | * @vid: VID value. |
1037 | * @fid: FID value. |
1038 | * @ports: Port membership. |
1039 | * @override: Override setting. |
1040 | * @use_fid: FID use setting. |
1041 | * @valid: Valid setting indicating the entry is being used. |
1042 | */ |
1043 | struct ksz_mac_table { |
1044 | u8 mac_addr[MAC_ADDR_LEN]; |
1045 | u16 vid; |
1046 | u8 fid; |
1047 | u8 ports; |
1048 | u8 override:1; |
1049 | u8 use_fid:1; |
1050 | u8 valid:1; |
1051 | }; |
1052 | |
1053 | #define VLAN_TABLE_ENTRIES 16 |
1054 | |
1055 | /** |
1056 | * struct ksz_vlan_table - VLAN table data structure |
1057 | * @vid: VID value. |
1058 | * @fid: FID value. |
1059 | * @member: Port membership. |
1060 | */ |
1061 | struct ksz_vlan_table { |
1062 | u16 vid; |
1063 | u8 fid; |
1064 | u8 member; |
1065 | }; |
1066 | |
1067 | #define DIFFSERV_ENTRIES 64 |
1068 | #define PRIO_802_1P_ENTRIES 8 |
1069 | #define PRIO_QUEUES 4 |
1070 | |
1071 | #define SWITCH_PORT_NUM 2 |
1072 | #define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1) |
1073 | #define HOST_MASK (1 << SWITCH_PORT_NUM) |
1074 | #define PORT_MASK 7 |
1075 | |
1076 | #define MAIN_PORT 0 |
1077 | #define OTHER_PORT 1 |
1078 | #define HOST_PORT SWITCH_PORT_NUM |
1079 | |
1080 | #define PORT_COUNTER_NUM 0x20 |
1081 | #define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2) |
1082 | |
1083 | #define MIB_COUNTER_RX_LO_PRIORITY 0x00 |
1084 | #define MIB_COUNTER_RX_HI_PRIORITY 0x01 |
1085 | #define MIB_COUNTER_RX_UNDERSIZE 0x02 |
1086 | #define MIB_COUNTER_RX_FRAGMENT 0x03 |
1087 | #define MIB_COUNTER_RX_OVERSIZE 0x04 |
1088 | #define MIB_COUNTER_RX_JABBER 0x05 |
1089 | #define MIB_COUNTER_RX_SYMBOL_ERR 0x06 |
1090 | #define MIB_COUNTER_RX_CRC_ERR 0x07 |
1091 | #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08 |
1092 | #define MIB_COUNTER_RX_CTRL_8808 0x09 |
1093 | #define MIB_COUNTER_RX_PAUSE 0x0A |
1094 | #define MIB_COUNTER_RX_BROADCAST 0x0B |
1095 | #define MIB_COUNTER_RX_MULTICAST 0x0C |
1096 | #define MIB_COUNTER_RX_UNICAST 0x0D |
1097 | #define MIB_COUNTER_RX_OCTET_64 0x0E |
1098 | #define MIB_COUNTER_RX_OCTET_65_127 0x0F |
1099 | #define MIB_COUNTER_RX_OCTET_128_255 0x10 |
1100 | #define MIB_COUNTER_RX_OCTET_256_511 0x11 |
1101 | #define MIB_COUNTER_RX_OCTET_512_1023 0x12 |
1102 | #define MIB_COUNTER_RX_OCTET_1024_1522 0x13 |
1103 | #define MIB_COUNTER_TX_LO_PRIORITY 0x14 |
1104 | #define MIB_COUNTER_TX_HI_PRIORITY 0x15 |
1105 | #define MIB_COUNTER_TX_LATE_COLLISION 0x16 |
1106 | #define MIB_COUNTER_TX_PAUSE 0x17 |
1107 | #define MIB_COUNTER_TX_BROADCAST 0x18 |
1108 | #define MIB_COUNTER_TX_MULTICAST 0x19 |
1109 | #define MIB_COUNTER_TX_UNICAST 0x1A |
1110 | #define MIB_COUNTER_TX_DEFERRED 0x1B |
1111 | #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C |
1112 | #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D |
1113 | #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E |
1114 | #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F |
1115 | |
1116 | #define MIB_COUNTER_RX_DROPPED_PACKET 0x20 |
1117 | #define MIB_COUNTER_TX_DROPPED_PACKET 0x21 |
1118 | |
1119 | /** |
1120 | * struct ksz_port_mib - Port MIB data structure |
1121 | * @cnt_ptr: Current pointer to MIB counter index. |
1122 | * @link_down: Indication the link has just gone down. |
1123 | * @state: Connection status of the port. |
1124 | * @mib_start: The starting counter index. Some ports do not start at 0. |
1125 | * @counter: 64-bit MIB counter value. |
1126 | * @dropped: Temporary buffer to remember last read packet dropped values. |
1127 | * |
1128 | * MIB counters needs to be read periodically so that counters do not get |
1129 | * overflowed and give incorrect values. A right balance is needed to |
1130 | * satisfy this condition and not waste too much CPU time. |
1131 | * |
1132 | * It is pointless to read MIB counters when the port is disconnected. The |
1133 | * @state provides the connection status so that MIB counters are read only |
1134 | * when the port is connected. The @link_down indicates the port is just |
1135 | * disconnected so that all MIB counters are read one last time to update the |
1136 | * information. |
1137 | */ |
1138 | struct ksz_port_mib { |
1139 | u8 cnt_ptr; |
1140 | u8 link_down; |
1141 | u8 state; |
1142 | u8 mib_start; |
1143 | |
1144 | u64 counter[TOTAL_PORT_COUNTER_NUM]; |
1145 | u32 dropped[2]; |
1146 | }; |
1147 | |
1148 | /** |
1149 | * struct ksz_port_cfg - Port configuration data structure |
1150 | * @vid: VID value. |
1151 | * @member: Port membership. |
1152 | * @port_prio: Port priority. |
1153 | * @rx_rate: Receive priority rate. |
1154 | * @tx_rate: Transmit priority rate. |
1155 | * @stp_state: Current Spanning Tree Protocol state. |
1156 | */ |
1157 | struct ksz_port_cfg { |
1158 | u16 vid; |
1159 | u8 member; |
1160 | u8 port_prio; |
1161 | u32 rx_rate[PRIO_QUEUES]; |
1162 | u32 tx_rate[PRIO_QUEUES]; |
1163 | int stp_state; |
1164 | }; |
1165 | |
1166 | /** |
1167 | * struct ksz_switch - KSZ8842 switch data structure |
1168 | * @mac_table: MAC table entries information. |
1169 | * @vlan_table: VLAN table entries information. |
1170 | * @port_cfg: Port configuration information. |
1171 | * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS |
1172 | * (bit7 ~ bit2) field. |
1173 | * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p |
1174 | * Tag priority field. |
1175 | * @br_addr: Bridge address. Used for STP. |
1176 | * @other_addr: Other MAC address. Used for multiple network device mode. |
1177 | * @broad_per: Broadcast storm percentage. |
1178 | * @member: Current port membership. Used for STP. |
1179 | */ |
1180 | struct ksz_switch { |
1181 | struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES]; |
1182 | struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES]; |
1183 | struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM]; |
1184 | |
1185 | u8 diffserv[DIFFSERV_ENTRIES]; |
1186 | u8 p_802_1p[PRIO_802_1P_ENTRIES]; |
1187 | |
1188 | u8 br_addr[MAC_ADDR_LEN]; |
1189 | u8 other_addr[MAC_ADDR_LEN]; |
1190 | |
1191 | u8 broad_per; |
1192 | u8 member; |
1193 | }; |
1194 | |
1195 | #define TX_RATE_UNIT 10000 |
1196 | |
1197 | /** |
1198 | * struct ksz_port_info - Port information data structure |
1199 | * @state: Connection status of the port. |
1200 | * @tx_rate: Transmit rate divided by 10000 to get Mbit. |
1201 | * @duplex: Duplex mode. |
1202 | * @advertised: Advertised auto-negotiation setting. Used to determine link. |
1203 | * @partner: Auto-negotiation partner setting. Used to determine link. |
1204 | * @port_id: Port index to access actual hardware register. |
1205 | * @pdev: Pointer to OS dependent network device. |
1206 | */ |
1207 | struct ksz_port_info { |
1208 | uint state; |
1209 | uint tx_rate; |
1210 | u8 duplex; |
1211 | u8 advertised; |
1212 | u8 partner; |
1213 | u8 port_id; |
1214 | void *pdev; |
1215 | }; |
1216 | |
1217 | #define MAX_TX_HELD_SIZE 52000 |
1218 | |
1219 | /* Hardware features and bug fixes. */ |
1220 | #define LINK_INT_WORKING (1 << 0) |
1221 | #define SMALL_PACKET_TX_BUG (1 << 1) |
1222 | #define HALF_DUPLEX_SIGNAL_BUG (1 << 2) |
1223 | #define IPV6_CSUM_GEN_HACK (1 << 3) |
1224 | #define RX_HUGE_FRAME (1 << 4) |
1225 | #define STP_SUPPORT (1 << 8) |
1226 | |
1227 | /* Software overrides. */ |
1228 | #define PAUSE_FLOW_CTRL (1 << 0) |
1229 | #define FAST_AGING (1 << 1) |
1230 | |
1231 | /** |
1232 | * struct ksz_hw - KSZ884X hardware data structure |
1233 | * @io: Virtual address assigned. |
1234 | * @ksz_switch: Pointer to KSZ8842 switch. |
1235 | * @port_info: Port information. |
1236 | * @port_mib: Port MIB information. |
1237 | * @dev_count: Number of network devices this hardware supports. |
1238 | * @dst_ports: Destination ports in switch for transmission. |
1239 | * @id: Hardware ID. Used for display only. |
1240 | * @mib_cnt: Number of MIB counters this hardware has. |
1241 | * @mib_port_cnt: Number of ports with MIB counters. |
1242 | * @tx_cfg: Cached transmit control settings. |
1243 | * @rx_cfg: Cached receive control settings. |
1244 | * @intr_mask: Current interrupt mask. |
1245 | * @intr_set: Current interrup set. |
1246 | * @intr_blocked: Interrupt blocked. |
1247 | * @rx_desc_info: Receive descriptor information. |
1248 | * @tx_desc_info: Transmit descriptor information. |
1249 | * @tx_int_cnt: Transmit interrupt count. Used for TX optimization. |
1250 | * @tx_int_mask: Transmit interrupt mask. Used for TX optimization. |
1251 | * @tx_size: Transmit data size. Used for TX optimization. |
1252 | * The maximum is defined by MAX_TX_HELD_SIZE. |
1253 | * @perm_addr: Permanent MAC address. |
1254 | * @override_addr: Overrided MAC address. |
1255 | * @address: Additional MAC address entries. |
1256 | * @addr_list_size: Additional MAC address list size. |
1257 | * @mac_override: Indication of MAC address overrided. |
1258 | * @promiscuous: Counter to keep track of promiscuous mode set. |
1259 | * @all_multi: Counter to keep track of all multicast mode set. |
1260 | * @multi_list: Multicast address entries. |
1261 | * @multi_bits: Cached multicast hash table settings. |
1262 | * @multi_list_size: Multicast address list size. |
1263 | * @enabled: Indication of hardware enabled. |
1264 | * @rx_stop: Indication of receive process stop. |
1265 | * @features: Hardware features to enable. |
1266 | * @overrides: Hardware features to override. |
1267 | * @parent: Pointer to parent, network device private structure. |
1268 | */ |
1269 | struct ksz_hw { |
1270 | void __iomem *io; |
1271 | |
1272 | struct ksz_switch *ksz_switch; |
1273 | struct ksz_port_info port_info[SWITCH_PORT_NUM]; |
1274 | struct ksz_port_mib port_mib[TOTAL_PORT_NUM]; |
1275 | int dev_count; |
1276 | int dst_ports; |
1277 | int id; |
1278 | int mib_cnt; |
1279 | int mib_port_cnt; |
1280 | |
1281 | u32 tx_cfg; |
1282 | u32 rx_cfg; |
1283 | u32 intr_mask; |
1284 | u32 intr_set; |
1285 | uint intr_blocked; |
1286 | |
1287 | struct ksz_desc_info rx_desc_info; |
1288 | struct ksz_desc_info tx_desc_info; |
1289 | |
1290 | int tx_int_cnt; |
1291 | int tx_int_mask; |
1292 | int tx_size; |
1293 | |
1294 | u8 perm_addr[MAC_ADDR_LEN]; |
1295 | u8 override_addr[MAC_ADDR_LEN]; |
1296 | u8 address[ADDITIONAL_ENTRIES][MAC_ADDR_LEN]; |
1297 | u8 addr_list_size; |
1298 | u8 mac_override; |
1299 | u8 promiscuous; |
1300 | u8 all_multi; |
1301 | u8 multi_list[MAX_MULTICAST_LIST][MAC_ADDR_LEN]; |
1302 | u8 multi_bits[HW_MULTICAST_SIZE]; |
1303 | u8 multi_list_size; |
1304 | |
1305 | u8 enabled; |
1306 | u8 rx_stop; |
1307 | u8 reserved2[1]; |
1308 | |
1309 | uint features; |
1310 | uint overrides; |
1311 | |
1312 | void *parent; |
1313 | }; |
1314 | |
1315 | enum { |
1316 | PHY_NO_FLOW_CTRL, |
1317 | PHY_FLOW_CTRL, |
1318 | PHY_TX_ONLY, |
1319 | PHY_RX_ONLY |
1320 | }; |
1321 | |
1322 | /** |
1323 | * struct ksz_port - Virtual port data structure |
1324 | * @duplex: Duplex mode setting. 1 for half duplex, 2 for full |
1325 | * duplex, and 0 for auto, which normally results in full |
1326 | * duplex. |
1327 | * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and |
1328 | * 0 for auto, which normally results in 100 Mbit. |
1329 | * @force_link: Force link setting. 0 for auto-negotiation, and 1 for |
1330 | * force. |
1331 | * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow |
1332 | * control, and PHY_FLOW_CTRL for flow control. |
1333 | * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100 |
1334 | * Mbit PHY. |
1335 | * @first_port: Index of first port this port supports. |
1336 | * @mib_port_cnt: Number of ports with MIB counters. |
1337 | * @port_cnt: Number of ports this port supports. |
1338 | * @counter: Port statistics counter. |
1339 | * @hw: Pointer to hardware structure. |
1340 | * @linked: Pointer to port information linked to this port. |
1341 | */ |
1342 | struct ksz_port { |
1343 | u8 duplex; |
1344 | u8 speed; |
1345 | u8 force_link; |
1346 | u8 flow_ctrl; |
1347 | |
1348 | int first_port; |
1349 | int mib_port_cnt; |
1350 | int port_cnt; |
1351 | u64 counter[OID_COUNTER_LAST]; |
1352 | |
1353 | struct ksz_hw *hw; |
1354 | struct ksz_port_info *linked; |
1355 | }; |
1356 | |
1357 | /** |
1358 | * struct ksz_timer_info - Timer information data structure |
1359 | * @timer: Kernel timer. |
1360 | * @cnt: Running timer counter. |
1361 | * @max: Number of times to run timer; -1 for infinity. |
1362 | * @period: Timer period in jiffies. |
1363 | */ |
1364 | struct ksz_timer_info { |
1365 | struct timer_list timer; |
1366 | int cnt; |
1367 | int max; |
1368 | int period; |
1369 | }; |
1370 | |
1371 | /** |
1372 | * struct ksz_shared_mem - OS dependent shared memory data structure |
1373 | * @dma_addr: Physical DMA address allocated. |
1374 | * @alloc_size: Allocation size. |
1375 | * @phys: Actual physical address used. |
1376 | * @alloc_virt: Virtual address allocated. |
1377 | * @virt: Actual virtual address used. |
1378 | */ |
1379 | struct ksz_shared_mem { |
1380 | dma_addr_t dma_addr; |
1381 | uint alloc_size; |
1382 | uint phys; |
1383 | u8 *alloc_virt; |
1384 | u8 *virt; |
1385 | }; |
1386 | |
1387 | /** |
1388 | * struct ksz_counter_info - OS dependent counter information data structure |
1389 | * @counter: Wait queue to wakeup after counters are read. |
1390 | * @time: Next time in jiffies to read counter. |
1391 | * @read: Indication of counters read in full or not. |
1392 | */ |
1393 | struct ksz_counter_info { |
1394 | wait_queue_head_t counter; |
1395 | unsigned long time; |
1396 | int read; |
1397 | }; |
1398 | |
1399 | /** |
1400 | * struct dev_info - Network device information data structure |
1401 | * @dev: Pointer to network device. |
1402 | * @pdev: Pointer to PCI device. |
1403 | * @hw: Hardware structure. |
1404 | * @desc_pool: Physical memory used for descriptor pool. |
1405 | * @hwlock: Spinlock to prevent hardware from accessing. |
1406 | * @lock: Mutex lock to prevent device from accessing. |
1407 | * @dev_rcv: Receive process function used. |
1408 | * @last_skb: Socket buffer allocated for descriptor rx fragments. |
1409 | * @skb_index: Buffer index for receiving fragments. |
1410 | * @skb_len: Buffer length for receiving fragments. |
1411 | * @mib_read: Workqueue to read MIB counters. |
1412 | * @mib_timer_info: Timer to read MIB counters. |
1413 | * @counter: Used for MIB reading. |
1414 | * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE; |
1415 | * the maximum is MAX_RX_BUF_SIZE. |
1416 | * @opened: Counter to keep track of device open. |
1417 | * @rx_tasklet: Receive processing tasklet. |
1418 | * @tx_tasklet: Transmit processing tasklet. |
1419 | * @wol_enable: Wake-on-LAN enable set by ethtool. |
1420 | * @wol_support: Wake-on-LAN support used by ethtool. |
1421 | * @pme_wait: Used for KSZ8841 power management. |
1422 | */ |
1423 | struct dev_info { |
1424 | struct net_device *dev; |
1425 | struct pci_dev *pdev; |
1426 | |
1427 | struct ksz_hw hw; |
1428 | struct ksz_shared_mem desc_pool; |
1429 | |
1430 | spinlock_t hwlock; |
1431 | struct mutex lock; |
1432 | |
1433 | int (*dev_rcv)(struct dev_info *); |
1434 | |
1435 | struct sk_buff *last_skb; |
1436 | int skb_index; |
1437 | int skb_len; |
1438 | |
1439 | struct work_struct mib_read; |
1440 | struct ksz_timer_info mib_timer_info; |
1441 | struct ksz_counter_info counter[TOTAL_PORT_NUM]; |
1442 | |
1443 | int mtu; |
1444 | int opened; |
1445 | |
1446 | struct tasklet_struct rx_tasklet; |
1447 | struct tasklet_struct tx_tasklet; |
1448 | |
1449 | int wol_enable; |
1450 | int wol_support; |
1451 | unsigned long pme_wait; |
1452 | }; |
1453 | |
1454 | /** |
1455 | * struct dev_priv - Network device private data structure |
1456 | * @adapter: Adapter device information. |
1457 | * @port: Port information. |
1458 | * @monitor_time_info: Timer to monitor ports. |
1459 | * @stats: Network statistics. |
1460 | * @proc_sem: Semaphore for proc accessing. |
1461 | * @id: Device ID. |
1462 | * @mii_if: MII interface information. |
1463 | * @advertising: Temporary variable to store advertised settings. |
1464 | * @msg_enable: The message flags controlling driver output. |
1465 | * @media_state: The connection status of the device. |
1466 | * @multicast: The all multicast state of the device. |
1467 | * @promiscuous: The promiscuous state of the device. |
1468 | */ |
1469 | struct dev_priv { |
1470 | struct dev_info *adapter; |
1471 | struct ksz_port port; |
1472 | struct ksz_timer_info monitor_timer_info; |
1473 | struct net_device_stats stats; |
1474 | |
1475 | struct semaphore proc_sem; |
1476 | int id; |
1477 | |
1478 | struct mii_if_info mii_if; |
1479 | u32 advertising; |
1480 | |
1481 | u32 msg_enable; |
1482 | int media_state; |
1483 | int multicast; |
1484 | int promiscuous; |
1485 | }; |
1486 | |
1487 | #define ks_info(_ks, _msg...) dev_info(&(_ks)->pdev->dev, _msg) |
1488 | #define ks_warn(_ks, _msg...) dev_warn(&(_ks)->pdev->dev, _msg) |
1489 | #define ks_dbg(_ks, _msg...) dev_dbg(&(_ks)->pdev->dev, _msg) |
1490 | #define ks_err(_ks, _msg...) dev_err(&(_ks)->pdev->dev, _msg) |
1491 | |
1492 | #define DRV_NAME "KSZ884X PCI" |
1493 | #define DEVICE_NAME "KSZ884x PCI" |
1494 | #define DRV_VERSION "1.0.0" |
1495 | #define DRV_RELDATE "Feb 8, 2010" |
1496 | |
1497 | static char version[] __devinitdata = |
1498 | "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")"; |
1499 | |
1500 | static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 }; |
1501 | |
1502 | /* |
1503 | * Interrupt processing primary routines |
1504 | */ |
1505 | |
1506 | static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt) |
1507 | { |
1508 | writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS); |
1509 | } |
1510 | |
1511 | static inline void hw_dis_intr(struct ksz_hw *hw) |
1512 | { |
1513 | hw->intr_blocked = hw->intr_mask; |
1514 | writel(0, hw->io + KS884X_INTERRUPTS_ENABLE); |
1515 | hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE); |
1516 | } |
1517 | |
1518 | static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt) |
1519 | { |
1520 | hw->intr_set = interrupt; |
1521 | writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE); |
1522 | } |
1523 | |
1524 | static inline void hw_ena_intr(struct ksz_hw *hw) |
1525 | { |
1526 | hw->intr_blocked = 0; |
1527 | hw_set_intr(hw, hw->intr_mask); |
1528 | } |
1529 | |
1530 | static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit) |
1531 | { |
1532 | hw->intr_mask &= ~(bit); |
1533 | } |
1534 | |
1535 | static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt) |
1536 | { |
1537 | u32 read_intr; |
1538 | |
1539 | read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); |
1540 | hw->intr_set = read_intr & ~interrupt; |
1541 | writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); |
1542 | hw_dis_intr_bit(hw, interrupt); |
1543 | } |
1544 | |
1545 | /** |
1546 | * hw_turn_on_intr - turn on specified interrupts |
1547 | * @hw: The hardware instance. |
1548 | * @bit: The interrupt bits to be on. |
1549 | * |
1550 | * This routine turns on the specified interrupts in the interrupt mask so that |
1551 | * those interrupts will be enabled. |
1552 | */ |
1553 | static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit) |
1554 | { |
1555 | hw->intr_mask |= bit; |
1556 | |
1557 | if (!hw->intr_blocked) |
1558 | hw_set_intr(hw, hw->intr_mask); |
1559 | } |
1560 | |
1561 | static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt) |
1562 | { |
1563 | u32 read_intr; |
1564 | |
1565 | read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); |
1566 | hw->intr_set = read_intr | interrupt; |
1567 | writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); |
1568 | } |
1569 | |
1570 | static inline void hw_read_intr(struct ksz_hw *hw, uint *status) |
1571 | { |
1572 | *status = readl(hw->io + KS884X_INTERRUPTS_STATUS); |
1573 | *status = *status & hw->intr_set; |
1574 | } |
1575 | |
1576 | static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt) |
1577 | { |
1578 | if (interrupt) |
1579 | hw_ena_intr(hw); |
1580 | } |
1581 | |
1582 | /** |
1583 | * hw_block_intr - block hardware interrupts |
1584 | * |
1585 | * This function blocks all interrupts of the hardware and returns the current |
1586 | * interrupt enable mask so that interrupts can be restored later. |
1587 | * |
1588 | * Return the current interrupt enable mask. |
1589 | */ |
1590 | static uint hw_block_intr(struct ksz_hw *hw) |
1591 | { |
1592 | uint interrupt = 0; |
1593 | |
1594 | if (!hw->intr_blocked) { |
1595 | hw_dis_intr(hw); |
1596 | interrupt = hw->intr_blocked; |
1597 | } |
1598 | return interrupt; |
1599 | } |
1600 | |
1601 | /* |
1602 | * Hardware descriptor routines |
1603 | */ |
1604 | |
1605 | static inline void reset_desc(struct ksz_desc *desc, union desc_stat status) |
1606 | { |
1607 | status.rx.hw_owned = 0; |
1608 | desc->phw->ctrl.data = cpu_to_le32(status.data); |
1609 | } |
1610 | |
1611 | static inline void release_desc(struct ksz_desc *desc) |
1612 | { |
1613 | desc->sw.ctrl.tx.hw_owned = 1; |
1614 | if (desc->sw.buf_size != desc->sw.buf.data) { |
1615 | desc->sw.buf_size = desc->sw.buf.data; |
1616 | desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data); |
1617 | } |
1618 | desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data); |
1619 | } |
1620 | |
1621 | static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc) |
1622 | { |
1623 | *desc = &info->ring[info->last]; |
1624 | info->last++; |
1625 | info->last &= info->mask; |
1626 | info->avail--; |
1627 | (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK; |
1628 | } |
1629 | |
1630 | static inline void set_rx_buf(struct ksz_desc *desc, u32 addr) |
1631 | { |
1632 | desc->phw->addr = cpu_to_le32(addr); |
1633 | } |
1634 | |
1635 | static inline void set_rx_len(struct ksz_desc *desc, u32 len) |
1636 | { |
1637 | desc->sw.buf.rx.buf_size = len; |
1638 | } |
1639 | |
1640 | static inline void get_tx_pkt(struct ksz_desc_info *info, |
1641 | struct ksz_desc **desc) |
1642 | { |
1643 | *desc = &info->ring[info->next]; |
1644 | info->next++; |
1645 | info->next &= info->mask; |
1646 | info->avail--; |
1647 | (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK; |
1648 | } |
1649 | |
1650 | static inline void set_tx_buf(struct ksz_desc *desc, u32 addr) |
1651 | { |
1652 | desc->phw->addr = cpu_to_le32(addr); |
1653 | } |
1654 | |
1655 | static inline void set_tx_len(struct ksz_desc *desc, u32 len) |
1656 | { |
1657 | desc->sw.buf.tx.buf_size = len; |
1658 | } |
1659 | |
1660 | /* Switch functions */ |
1661 | |
1662 | #define TABLE_READ 0x10 |
1663 | #define TABLE_SEL_SHIFT 2 |
1664 | |
1665 | #define HW_DELAY(hw, reg) \ |
1666 | do { \ |
1667 | u16 dummy; \ |
1668 | dummy = readw(hw->io + reg); \ |
1669 | } while (0) |
1670 | |
1671 | /** |
1672 | * sw_r_table - read 4 bytes of data from switch table |
1673 | * @hw: The hardware instance. |
1674 | * @table: The table selector. |
1675 | * @addr: The address of the table entry. |
1676 | * @data: Buffer to store the read data. |
1677 | * |
1678 | * This routine reads 4 bytes of data from the table of the switch. |
1679 | * Hardware interrupts are disabled to minimize corruption of read data. |
1680 | */ |
1681 | static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data) |
1682 | { |
1683 | u16 ctrl_addr; |
1684 | uint interrupt; |
1685 | |
1686 | ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr; |
1687 | |
1688 | interrupt = hw_block_intr(hw); |
1689 | |
1690 | writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); |
1691 | HW_DELAY(hw, KS884X_IACR_OFFSET); |
1692 | *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); |
1693 | |
1694 | hw_restore_intr(hw, interrupt); |
1695 | } |
1696 | |
1697 | /** |
1698 | * sw_w_table_64 - write 8 bytes of data to the switch table |
1699 | * @hw: The hardware instance. |
1700 | * @table: The table selector. |
1701 | * @addr: The address of the table entry. |
1702 | * @data_hi: The high part of data to be written (bit63 ~ bit32). |
1703 | * @data_lo: The low part of data to be written (bit31 ~ bit0). |
1704 | * |
1705 | * This routine writes 8 bytes of data to the table of the switch. |
1706 | * Hardware interrupts are disabled to minimize corruption of written data. |
1707 | */ |
1708 | static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi, |
1709 | u32 data_lo) |
1710 | { |
1711 | u16 ctrl_addr; |
1712 | uint interrupt; |
1713 | |
1714 | ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr; |
1715 | |
1716 | interrupt = hw_block_intr(hw); |
1717 | |
1718 | writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET); |
1719 | writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET); |
1720 | |
1721 | writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); |
1722 | HW_DELAY(hw, KS884X_IACR_OFFSET); |
1723 | |
1724 | hw_restore_intr(hw, interrupt); |
1725 | } |
1726 | |
1727 | /** |
1728 | * sw_w_sta_mac_table - write to the static MAC table |
1729 | * @hw: The hardware instance. |
1730 | * @addr: The address of the table entry. |
1731 | * @mac_addr: The MAC address. |
1732 | * @ports: The port members. |
1733 | * @override: The flag to override the port receive/transmit settings. |
1734 | * @valid: The flag to indicate entry is valid. |
1735 | * @use_fid: The flag to indicate the FID is valid. |
1736 | * @fid: The FID value. |
1737 | * |
1738 | * This routine writes an entry of the static MAC table of the switch. It |
1739 | * calls sw_w_table_64() to write the data. |
1740 | */ |
1741 | static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr, |
1742 | u8 ports, int override, int valid, int use_fid, u8 fid) |
1743 | { |
1744 | u32 data_hi; |
1745 | u32 data_lo; |
1746 | |
1747 | data_lo = ((u32) mac_addr[2] << 24) | |
1748 | ((u32) mac_addr[3] << 16) | |
1749 | ((u32) mac_addr[4] << 8) | mac_addr[5]; |
1750 | data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1]; |
1751 | data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT; |
1752 | |
1753 | if (override) |
1754 | data_hi |= STATIC_MAC_TABLE_OVERRIDE; |
1755 | if (use_fid) { |
1756 | data_hi |= STATIC_MAC_TABLE_USE_FID; |
1757 | data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT; |
1758 | } |
1759 | if (valid) |
1760 | data_hi |= STATIC_MAC_TABLE_VALID; |
1761 | |
1762 | sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo); |
1763 | } |
1764 | |
1765 | /** |
1766 | * sw_r_vlan_table - read from the VLAN table |
1767 | * @hw: The hardware instance. |
1768 | * @addr: The address of the table entry. |
1769 | * @vid: Buffer to store the VID. |
1770 | * @fid: Buffer to store the VID. |
1771 | * @member: Buffer to store the port membership. |
1772 | * |
1773 | * This function reads an entry of the VLAN table of the switch. It calls |
1774 | * sw_r_table() to get the data. |
1775 | * |
1776 | * Return 0 if the entry is valid; otherwise -1. |
1777 | */ |
1778 | static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid, |
1779 | u8 *member) |
1780 | { |
1781 | u32 data; |
1782 | |
1783 | sw_r_table(hw, TABLE_VLAN, addr, &data); |
1784 | if (data & VLAN_TABLE_VALID) { |
1785 | *vid = (u16)(data & VLAN_TABLE_VID); |
1786 | *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT); |
1787 | *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >> |
1788 | VLAN_TABLE_MEMBERSHIP_SHIFT); |
1789 | return 0; |
1790 | } |
1791 | return -1; |
1792 | } |
1793 | |
1794 | /** |
1795 | * port_r_mib_cnt - read MIB counter |
1796 | * @hw: The hardware instance. |
1797 | * @port: The port index. |
1798 | * @addr: The address of the counter. |
1799 | * @cnt: Buffer to store the counter. |
1800 | * |
1801 | * This routine reads a MIB counter of the port. |
1802 | * Hardware interrupts are disabled to minimize corruption of read data. |
1803 | */ |
1804 | static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt) |
1805 | { |
1806 | u32 data; |
1807 | u16 ctrl_addr; |
1808 | uint interrupt; |
1809 | int timeout; |
1810 | |
1811 | ctrl_addr = addr + PORT_COUNTER_NUM * port; |
1812 | |
1813 | interrupt = hw_block_intr(hw); |
1814 | |
1815 | ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8); |
1816 | writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); |
1817 | HW_DELAY(hw, KS884X_IACR_OFFSET); |
1818 | |
1819 | for (timeout = 100; timeout > 0; timeout--) { |
1820 | data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); |
1821 | |
1822 | if (data & MIB_COUNTER_VALID) { |
1823 | if (data & MIB_COUNTER_OVERFLOW) |
1824 | *cnt += MIB_COUNTER_VALUE + 1; |
1825 | *cnt += data & MIB_COUNTER_VALUE; |
1826 | break; |
1827 | } |
1828 | } |
1829 | |
1830 | hw_restore_intr(hw, interrupt); |
1831 | } |
1832 | |
1833 | /** |
1834 | * port_r_mib_pkt - read dropped packet counts |
1835 | * @hw: The hardware instance. |
1836 | * @port: The port index. |
1837 | * @cnt: Buffer to store the receive and transmit dropped packet counts. |
1838 | * |
1839 | * This routine reads the dropped packet counts of the port. |
1840 | * Hardware interrupts are disabled to minimize corruption of read data. |
1841 | */ |
1842 | static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt) |
1843 | { |
1844 | u32 cur; |
1845 | u32 data; |
1846 | u16 ctrl_addr; |
1847 | uint interrupt; |
1848 | int index; |
1849 | |
1850 | index = KS_MIB_PACKET_DROPPED_RX_0 + port; |
1851 | do { |
1852 | interrupt = hw_block_intr(hw); |
1853 | |
1854 | ctrl_addr = (u16) index; |
1855 | ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) |
1856 | << 8); |
1857 | writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); |
1858 | HW_DELAY(hw, KS884X_IACR_OFFSET); |
1859 | data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); |
1860 | |
1861 | hw_restore_intr(hw, interrupt); |
1862 | |
1863 | data &= MIB_PACKET_DROPPED; |
1864 | cur = *last; |
1865 | if (data != cur) { |
1866 | *last = data; |
1867 | if (data < cur) |
1868 | data += MIB_PACKET_DROPPED + 1; |
1869 | data -= cur; |
1870 | *cnt += data; |
1871 | } |
1872 | ++last; |
1873 | ++cnt; |
1874 | index -= KS_MIB_PACKET_DROPPED_TX - |
1875 | KS_MIB_PACKET_DROPPED_TX_0 + 1; |
1876 | } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port); |
1877 | } |
1878 | |
1879 | /** |
1880 | * port_r_cnt - read MIB counters periodically |
1881 | * @hw: The hardware instance. |
1882 | * @port: The port index. |
1883 | * |
1884 | * This routine is used to read the counters of the port periodically to avoid |
1885 | * counter overflow. The hardware should be acquired first before calling this |
1886 | * routine. |
1887 | * |
1888 | * Return non-zero when not all counters not read. |
1889 | */ |
1890 | static int port_r_cnt(struct ksz_hw *hw, int port) |
1891 | { |
1892 | struct ksz_port_mib *mib = &hw->port_mib[port]; |
1893 | |
1894 | if (mib->mib_start < PORT_COUNTER_NUM) |
1895 | while (mib->cnt_ptr < PORT_COUNTER_NUM) { |
1896 | port_r_mib_cnt(hw, port, mib->cnt_ptr, |
1897 | &mib->counter[mib->cnt_ptr]); |
1898 | ++mib->cnt_ptr; |
1899 | } |
1900 | if (hw->mib_cnt > PORT_COUNTER_NUM) |
1901 | port_r_mib_pkt(hw, port, mib->dropped, |
1902 | &mib->counter[PORT_COUNTER_NUM]); |
1903 | mib->cnt_ptr = 0; |
1904 | return 0; |
1905 | } |
1906 | |
1907 | /** |
1908 | * port_init_cnt - initialize MIB counter values |
1909 | * @hw: The hardware instance. |
1910 | * @port: The port index. |
1911 | * |
1912 | * This routine is used to initialize all counters to zero if the hardware |
1913 | * cannot do it after reset. |
1914 | */ |
1915 | static void port_init_cnt(struct ksz_hw *hw, int port) |
1916 | { |
1917 | struct ksz_port_mib *mib = &hw->port_mib[port]; |
1918 | |
1919 | mib->cnt_ptr = 0; |
1920 | if (mib->mib_start < PORT_COUNTER_NUM) |
1921 | do { |
1922 | port_r_mib_cnt(hw, port, mib->cnt_ptr, |
1923 | &mib->counter[mib->cnt_ptr]); |
1924 | ++mib->cnt_ptr; |
1925 | } while (mib->cnt_ptr < PORT_COUNTER_NUM); |
1926 | if (hw->mib_cnt > PORT_COUNTER_NUM) |
1927 | port_r_mib_pkt(hw, port, mib->dropped, |
1928 | &mib->counter[PORT_COUNTER_NUM]); |
1929 | memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); |
1930 | mib->cnt_ptr = 0; |
1931 | } |
1932 | |
1933 | /* |
1934 | * Port functions |
1935 | */ |
1936 | |
1937 | /** |
1938 | * port_chk - check port register bits |
1939 | * @hw: The hardware instance. |
1940 | * @port: The port index. |
1941 | * @offset: The offset of the port register. |
1942 | * @bits: The data bits to check. |
1943 | * |
1944 | * This function checks whether the specified bits of the port register are set |
1945 | * or not. |
1946 | * |
1947 | * Return 0 if the bits are not set. |
1948 | */ |
1949 | static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits) |
1950 | { |
1951 | u32 addr; |
1952 | u16 data; |
1953 | |
1954 | PORT_CTRL_ADDR(port, addr); |
1955 | addr += offset; |
1956 | data = readw(hw->io + addr); |
1957 | return (data & bits) == bits; |
1958 | } |
1959 | |
1960 | /** |
1961 | * port_cfg - set port register bits |
1962 | * @hw: The hardware instance. |
1963 | * @port: The port index. |
1964 | * @offset: The offset of the port register. |
1965 | * @bits: The data bits to set. |
1966 | * @set: The flag indicating whether the bits are to be set or not. |
1967 | * |
1968 | * This routine sets or resets the specified bits of the port register. |
1969 | */ |
1970 | static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits, |
1971 | int set) |
1972 | { |
1973 | u32 addr; |
1974 | u16 data; |
1975 | |
1976 | PORT_CTRL_ADDR(port, addr); |
1977 | addr += offset; |
1978 | data = readw(hw->io + addr); |
1979 | if (set) |
1980 | data |= bits; |
1981 | else |
1982 | data &= ~bits; |
1983 | writew(data, hw->io + addr); |
1984 | } |
1985 | |
1986 | /** |
1987 | * port_chk_shift - check port bit |
1988 | * @hw: The hardware instance. |
1989 | * @port: The port index. |
1990 | * @offset: The offset of the register. |
1991 | * @shift: Number of bits to shift. |
1992 | * |
1993 | * This function checks whether the specified port is set in the register or |
1994 | * not. |
1995 | * |
1996 | * Return 0 if the port is not set. |
1997 | */ |
1998 | static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift) |
1999 | { |
2000 | u16 data; |
2001 | u16 bit = 1 << port; |
2002 | |
2003 | data = readw(hw->io + addr); |
2004 | data >>= shift; |
2005 | return (data & bit) == bit; |
2006 | } |
2007 | |
2008 | /** |
2009 | * port_cfg_shift - set port bit |
2010 | * @hw: The hardware instance. |
2011 | * @port: The port index. |
2012 | * @offset: The offset of the register. |
2013 | * @shift: Number of bits to shift. |
2014 | * @set: The flag indicating whether the port is to be set or not. |
2015 | * |
2016 | * This routine sets or resets the specified port in the register. |
2017 | */ |
2018 | static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift, |
2019 | int set) |
2020 | { |
2021 | u16 data; |
2022 | u16 bits = 1 << port; |
2023 | |
2024 | data = readw(hw->io + addr); |
2025 | bits <<= shift; |
2026 | if (set) |
2027 | data |= bits; |
2028 | else |
2029 | data &= ~bits; |
2030 | writew(data, hw->io + addr); |
2031 | } |
2032 | |
2033 | /** |
2034 | * port_r8 - read byte from port register |
2035 | * @hw: The hardware instance. |
2036 | * @port: The port index. |
2037 | * @offset: The offset of the port register. |
2038 | * @data: Buffer to store the data. |
2039 | * |
2040 | * This routine reads a byte from the port register. |
2041 | */ |
2042 | static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data) |
2043 | { |
2044 | u32 addr; |
2045 | |
2046 | PORT_CTRL_ADDR(port, addr); |
2047 | addr += offset; |
2048 | *data = readb(hw->io + addr); |
2049 | } |
2050 | |
2051 | /** |
2052 | * port_r16 - read word from port register. |
2053 | * @hw: The hardware instance. |
2054 | * @port: The port index. |
2055 | * @offset: The offset of the port register. |
2056 | * @data: Buffer to store the data. |
2057 | * |
2058 | * This routine reads a word from the port register. |
2059 | */ |
2060 | static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data) |
2061 | { |
2062 | u32 addr; |
2063 | |
2064 | PORT_CTRL_ADDR(port, addr); |
2065 | addr += offset; |
2066 | *data = readw(hw->io + addr); |
2067 | } |
2068 | |
2069 | /** |
2070 | * port_w16 - write word to port register. |
2071 | * @hw: The hardware instance. |
2072 | * @port: The port index. |
2073 | * @offset: The offset of the port register. |
2074 | * @data: Data to write. |
2075 | * |
2076 | * This routine writes a word to the port register. |
2077 | */ |
2078 | static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data) |
2079 | { |
2080 | u32 addr; |
2081 | |
2082 | PORT_CTRL_ADDR(port, addr); |
2083 | addr += offset; |
2084 | writew(data, hw->io + addr); |
2085 | } |
2086 | |
2087 | /** |
2088 | * sw_chk - check switch register bits |
2089 | * @hw: The hardware instance. |
2090 | * @addr: The address of the switch register. |
2091 | * @bits: The data bits to check. |
2092 | * |
2093 | * This function checks whether the specified bits of the switch register are |
2094 | * set or not. |
2095 | * |
2096 | * Return 0 if the bits are not set. |
2097 | */ |
2098 | static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits) |
2099 | { |
2100 | u16 data; |
2101 | |
2102 | data = readw(hw->io + addr); |
2103 | return (data & bits) == bits; |
2104 | } |
2105 | |
2106 | /** |
2107 | * sw_cfg - set switch register bits |
2108 | * @hw: The hardware instance. |
2109 | * @addr: The address of the switch register. |
2110 | * @bits: The data bits to set. |
2111 | * @set: The flag indicating whether the bits are to be set or not. |
2112 | * |
2113 | * This function sets or resets the specified bits of the switch register. |
2114 | */ |
2115 | static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set) |
2116 | { |
2117 | u16 data; |
2118 | |
2119 | data = readw(hw->io + addr); |
2120 | if (set) |
2121 | data |= bits; |
2122 | else |
2123 | data &= ~bits; |
2124 | writew(data, hw->io + addr); |
2125 | } |
2126 | |
2127 | /* Bandwidth */ |
2128 | |
2129 | static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set) |
2130 | { |
2131 | port_cfg(hw, p, |
2132 | KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set); |
2133 | } |
2134 | |
2135 | static inline int port_chk_broad_storm(struct ksz_hw *hw, int p) |
2136 | { |
2137 | return port_chk(hw, p, |
2138 | KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM); |
2139 | } |
2140 | |
2141 | /* Driver set switch broadcast storm protection at 10% rate. */ |
2142 | #define BROADCAST_STORM_PROTECTION_RATE 10 |
2143 | |
2144 | /* 148,800 frames * 67 ms / 100 */ |
2145 | #define BROADCAST_STORM_VALUE 9969 |
2146 | |
2147 | /** |
2148 | * sw_cfg_broad_storm - configure broadcast storm threshold |
2149 | * @hw: The hardware instance. |
2150 | * @percent: Broadcast storm threshold in percent of transmit rate. |
2151 | * |
2152 | * This routine configures the broadcast storm threshold of the switch. |
2153 | */ |
2154 | static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent) |
2155 | { |
2156 | u16 data; |
2157 | u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100); |
2158 | |
2159 | if (value > BROADCAST_STORM_RATE) |
2160 | value = BROADCAST_STORM_RATE; |
2161 | |
2162 | data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); |
2163 | data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI); |
2164 | data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8); |
2165 | writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); |
2166 | } |
2167 | |
2168 | /** |
2169 | * sw_get_board_storm - get broadcast storm threshold |
2170 | * @hw: The hardware instance. |
2171 | * @percent: Buffer to store the broadcast storm threshold percentage. |
2172 | * |
2173 | * This routine retrieves the broadcast storm threshold of the switch. |
2174 | */ |
2175 | static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent) |
2176 | { |
2177 | int num; |
2178 | u16 data; |
2179 | |
2180 | data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); |
2181 | num = (data & BROADCAST_STORM_RATE_HI); |
2182 | num <<= 8; |
2183 | num |= (data & BROADCAST_STORM_RATE_LO) >> 8; |
2184 | num = (num * 100 + BROADCAST_STORM_VALUE / 2) / BROADCAST_STORM_VALUE; |
2185 | *percent = (u8) num; |
2186 | } |
2187 | |
2188 | /** |
2189 | * sw_dis_broad_storm - disable broadstorm |
2190 | * @hw: The hardware instance. |
2191 | * @port: The port index. |
2192 | * |
2193 | * This routine disables the broadcast storm limit function of the switch. |
2194 | */ |
2195 | static void sw_dis_broad_storm(struct ksz_hw *hw, int port) |
2196 | { |
2197 | port_cfg_broad_storm(hw, port, 0); |
2198 | } |
2199 | |
2200 | /** |
2201 | * sw_ena_broad_storm - enable broadcast storm |
2202 | * @hw: The hardware instance. |
2203 | * @port: The port index. |
2204 | * |
2205 | * This routine enables the broadcast storm limit function of the switch. |
2206 | */ |
2207 | static void sw_ena_broad_storm(struct ksz_hw *hw, int port) |
2208 | { |
2209 | sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per); |
2210 | port_cfg_broad_storm(hw, port, 1); |
2211 | } |
2212 | |
2213 | /** |
2214 | * sw_init_broad_storm - initialize broadcast storm |
2215 | * @hw: The hardware instance. |
2216 | * |
2217 | * This routine initializes the broadcast storm limit function of the switch. |
2218 | */ |
2219 | static void sw_init_broad_storm(struct ksz_hw *hw) |
2220 | { |
2221 | int port; |
2222 | |
2223 | hw->ksz_switch->broad_per = 1; |
2224 | sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per); |
2225 | for (port = 0; port < TOTAL_PORT_NUM; port++) |
2226 | sw_dis_broad_storm(hw, port); |
2227 | sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1); |
2228 | } |
2229 | |
2230 | /** |
2231 | * hw_cfg_broad_storm - configure broadcast storm |
2232 | * @hw: The hardware instance. |
2233 | * @percent: Broadcast storm threshold in percent of transmit rate. |
2234 | * |
2235 | * This routine configures the broadcast storm threshold of the switch. |
2236 | * It is called by user functions. The hardware should be acquired first. |
2237 | */ |
2238 | static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent) |
2239 | { |
2240 | if (percent > 100) |
2241 | percent = 100; |
2242 | |
2243 | sw_cfg_broad_storm(hw, percent); |
2244 | sw_get_broad_storm(hw, &percent); |
2245 | hw->ksz_switch->broad_per = percent; |
2246 | } |
2247 | |
2248 | /** |
2249 | * sw_dis_prio_rate - disable switch priority rate |
2250 | * @hw: The hardware instance. |
2251 | * @port: The port index. |
2252 | * |
2253 | * This routine disables the priority rate function of the switch. |
2254 | */ |
2255 | static void sw_dis_prio_rate(struct ksz_hw *hw, int port) |
2256 | { |
2257 | u32 addr; |
2258 | |
2259 | PORT_CTRL_ADDR(port, addr); |
2260 | addr += KS8842_PORT_IN_RATE_OFFSET; |
2261 | writel(0, hw->io + addr); |
2262 | } |
2263 | |
2264 | /** |
2265 | * sw_init_prio_rate - initialize switch prioirty rate |
2266 | * @hw: The hardware instance. |
2267 | * |
2268 | * This routine initializes the priority rate function of the switch. |
2269 | */ |
2270 | static void sw_init_prio_rate(struct ksz_hw *hw) |
2271 | { |
2272 | int port; |
2273 | int prio; |
2274 | struct ksz_switch *sw = hw->ksz_switch; |
2275 | |
2276 | for (port = 0; port < TOTAL_PORT_NUM; port++) { |
2277 | for (prio = 0; prio < PRIO_QUEUES; prio++) { |
2278 | sw->port_cfg[port].rx_rate[prio] = |
2279 | sw->port_cfg[port].tx_rate[prio] = 0; |
2280 | } |
2281 | sw_dis_prio_rate(hw, port); |
2282 | } |
2283 | } |
2284 | |
2285 | /* Communication */ |
2286 | |
2287 | static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set) |
2288 | { |
2289 | port_cfg(hw, p, |
2290 | KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set); |
2291 | } |
2292 | |
2293 | static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set) |
2294 | { |
2295 | port_cfg(hw, p, |
2296 | KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set); |
2297 | } |
2298 | |
2299 | static inline int port_chk_back_pressure(struct ksz_hw *hw, int p) |
2300 | { |
2301 | return port_chk(hw, p, |
2302 | KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE); |
2303 | } |
2304 | |
2305 | static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p) |
2306 | { |
2307 | return port_chk(hw, p, |
2308 | KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL); |
2309 | } |
2310 | |
2311 | /* Spanning Tree */ |
2312 | |
2313 | static inline void port_cfg_dis_learn(struct ksz_hw *hw, int p, int set) |
2314 | { |
2315 | port_cfg(hw, p, |
2316 | KS8842_PORT_CTRL_2_OFFSET, PORT_LEARN_DISABLE, set); |
2317 | } |
2318 | |
2319 | static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set) |
2320 | { |
2321 | port_cfg(hw, p, |
2322 | KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set); |
2323 | } |
2324 | |
2325 | static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set) |
2326 | { |
2327 | port_cfg(hw, p, |
2328 | KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set); |
2329 | } |
2330 | |
2331 | static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set) |
2332 | { |
2333 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set); |
2334 | } |
2335 | |
2336 | static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw) |
2337 | { |
2338 | if (!(hw->overrides & FAST_AGING)) { |
2339 | sw_cfg_fast_aging(hw, 1); |
2340 | mdelay(1); |
2341 | sw_cfg_fast_aging(hw, 0); |
2342 | } |
2343 | } |
2344 | |
2345 | /* VLAN */ |
2346 | |
2347 | static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert) |
2348 | { |
2349 | port_cfg(hw, p, |
2350 | KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert); |
2351 | } |
2352 | |
2353 | static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove) |
2354 | { |
2355 | port_cfg(hw, p, |
2356 | KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove); |
2357 | } |
2358 | |
2359 | static inline int port_chk_ins_tag(struct ksz_hw *hw, int p) |
2360 | { |
2361 | return port_chk(hw, p, |
2362 | KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG); |
2363 | } |
2364 | |
2365 | static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p) |
2366 | { |
2367 | return port_chk(hw, p, |
2368 | KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG); |
2369 | } |
2370 | |
2371 | static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set) |
2372 | { |
2373 | port_cfg(hw, p, |
2374 | KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set); |
2375 | } |
2376 | |
2377 | static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set) |
2378 | { |
2379 | port_cfg(hw, p, |
2380 | KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set); |
2381 | } |
2382 | |
2383 | static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p) |
2384 | { |
2385 | return port_chk(hw, p, |
2386 | KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID); |
2387 | } |
2388 | |
2389 | static inline int port_chk_in_filter(struct ksz_hw *hw, int p) |
2390 | { |
2391 | return port_chk(hw, p, |
2392 | KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER); |
2393 | } |
2394 | |
2395 | /* Mirroring */ |
2396 | |
2397 | static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set) |
2398 | { |
2399 | port_cfg(hw, p, |
2400 | KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set); |
2401 | } |
2402 | |
2403 | static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set) |
2404 | { |
2405 | port_cfg(hw, p, |
2406 | KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set); |
2407 | } |
2408 | |
2409 | static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set) |
2410 | { |
2411 | port_cfg(hw, p, |
2412 | KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set); |
2413 | } |
2414 | |
2415 | static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set) |
2416 | { |
2417 | sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set); |
2418 | } |
2419 | |
2420 | static void sw_init_mirror(struct ksz_hw *hw) |
2421 | { |
2422 | int port; |
2423 | |
2424 | for (port = 0; port < TOTAL_PORT_NUM; port++) { |
2425 | port_cfg_mirror_sniffer(hw, port, 0); |
2426 | port_cfg_mirror_rx(hw, port, 0); |
2427 | port_cfg_mirror_tx(hw, port, 0); |
2428 | } |
2429 | sw_cfg_mirror_rx_tx(hw, 0); |
2430 | } |
2431 | |
2432 | static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set) |
2433 | { |
2434 | sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET, |
2435 | SWITCH_UNK_DEF_PORT_ENABLE, set); |
2436 | } |
2437 | |
2438 | static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw) |
2439 | { |
2440 | return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET, |
2441 | SWITCH_UNK_DEF_PORT_ENABLE); |
2442 | } |
2443 | |
2444 | static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set) |
2445 | { |
2446 | port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set); |
2447 | } |
2448 | |
2449 | static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port) |
2450 | { |
2451 | return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0); |
2452 | } |
2453 | |
2454 | /* Priority */ |
2455 | |
2456 | static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set) |
2457 | { |
2458 | port_cfg(hw, p, |
2459 | KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set); |
2460 | } |
2461 | |
2462 | static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set) |
2463 | { |
2464 | port_cfg(hw, p, |
2465 | KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set); |
2466 | } |
2467 | |
2468 | static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set) |
2469 | { |
2470 | port_cfg(hw, p, |
2471 | KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set); |
2472 | } |
2473 | |
2474 | static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set) |
2475 | { |
2476 | port_cfg(hw, p, |
2477 | KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set); |
2478 | } |
2479 | |
2480 | static inline int port_chk_diffserv(struct ksz_hw *hw, int p) |
2481 | { |
2482 | return port_chk(hw, p, |
2483 | KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE); |
2484 | } |
2485 | |
2486 | static inline int port_chk_802_1p(struct ksz_hw *hw, int p) |
2487 | { |
2488 | return port_chk(hw, p, |
2489 | KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE); |
2490 | } |
2491 | |
2492 | static inline int port_chk_replace_vid(struct ksz_hw *hw, int p) |
2493 | { |
2494 | return port_chk(hw, p, |
2495 | KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING); |
2496 | } |
2497 | |
2498 | static inline int port_chk_prio(struct ksz_hw *hw, int p) |
2499 | { |
2500 | return port_chk(hw, p, |
2501 | KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE); |
2502 | } |
2503 | |
2504 | /** |
2505 | * sw_dis_diffserv - disable switch DiffServ priority |
2506 | * @hw: The hardware instance. |
2507 | * @port: The port index. |
2508 | * |
2509 | * This routine disables the DiffServ priority function of the switch. |
2510 | */ |
2511 | static void sw_dis_diffserv(struct ksz_hw *hw, int port) |
2512 | { |
2513 | port_cfg_diffserv(hw, port, 0); |
2514 | } |
2515 | |
2516 | /** |
2517 | * sw_dis_802_1p - disable switch 802.1p priority |
2518 | * @hw: The hardware instance. |
2519 | * @port: The port index. |
2520 | * |
2521 | * This routine disables the 802.1p priority function of the switch. |
2522 | */ |
2523 | static void sw_dis_802_1p(struct ksz_hw *hw, int port) |
2524 | { |
2525 | port_cfg_802_1p(hw, port, 0); |
2526 | } |
2527 | |
2528 | /** |
2529 | * sw_cfg_replace_null_vid - |
2530 | * @hw: The hardware instance. |
2531 | * @set: The flag to disable or enable. |
2532 | * |
2533 | */ |
2534 | static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set) |
2535 | { |
2536 | sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set); |
2537 | } |
2538 | |
2539 | /** |
2540 | * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping |
2541 | * @hw: The hardware instance. |
2542 | * @port: The port index. |
2543 | * @set: The flag to disable or enable. |
2544 | * |
2545 | * This routine enables the 802.1p priority re-mapping function of the switch. |
2546 | * That allows 802.1p priority field to be replaced with the port's default |
2547 | * tag's priority value if the ingress packet's 802.1p priority has a higher |
2548 | * priority than port's default tag's priority. |
2549 | */ |
2550 | static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set) |
2551 | { |
2552 | port_cfg_replace_vid(hw, port, set); |
2553 | } |
2554 | |
2555 | /** |
2556 | * sw_cfg_port_based - configure switch port based priority |
2557 | * @hw: The hardware instance. |
2558 | * @port: The port index. |
2559 | * @prio: The priority to set. |
2560 | * |
2561 | * This routine configures the port based priority of the switch. |
2562 | */ |
2563 | static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio) |
2564 | { |
2565 | u16 data; |
2566 | |
2567 | if (prio > PORT_BASED_PRIORITY_BASE) |
2568 | prio = PORT_BASED_PRIORITY_BASE; |
2569 | |
2570 | hw->ksz_switch->port_cfg[port].port_prio = prio; |
2571 | |
2572 | port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data); |
2573 | data &= ~PORT_BASED_PRIORITY_MASK; |
2574 | data |= prio << PORT_BASED_PRIORITY_SHIFT; |
2575 | port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data); |
2576 | } |
2577 | |
2578 | /** |
2579 | * sw_dis_multi_queue - disable transmit multiple queues |
2580 | * @hw: The hardware instance. |
2581 | * @port: The port index. |
2582 | * |
2583 | * This routine disables the transmit multiple queues selection of the switch |
2584 | * port. Only single transmit queue on the port. |
2585 | */ |
2586 | static void sw_dis_multi_queue(struct ksz_hw *hw, int port) |
2587 | { |
2588 | port_cfg_prio(hw, port, 0); |
2589 | } |
2590 | |
2591 | /** |
2592 | * sw_init_prio - initialize switch priority |
2593 | * @hw: The hardware instance. |
2594 | * |
2595 | * This routine initializes the switch QoS priority functions. |
2596 | */ |
2597 | static void sw_init_prio(struct ksz_hw *hw) |
2598 | { |
2599 | int port; |
2600 | int tos; |
2601 | struct ksz_switch *sw = hw->ksz_switch; |
2602 | |
2603 | /* |
2604 | * Init all the 802.1p tag priority value to be assigned to different |
2605 | * priority queue. |
2606 | */ |
2607 | sw->p_802_1p[0] = 0; |
2608 | sw->p_802_1p[1] = 0; |
2609 | sw->p_802_1p[2] = 1; |
2610 | sw->p_802_1p[3] = 1; |
2611 | sw->p_802_1p[4] = 2; |
2612 | sw->p_802_1p[5] = 2; |
2613 | sw->p_802_1p[6] = 3; |
2614 | sw->p_802_1p[7] = 3; |
2615 | |
2616 | /* |
2617 | * Init all the DiffServ priority value to be assigned to priority |
2618 | * queue 0. |
2619 | */ |
2620 | for (tos = 0; tos < DIFFSERV_ENTRIES; tos++) |
2621 | sw->diffserv[tos] = 0; |
2622 | |
2623 | /* All QoS functions disabled. */ |
2624 | for (port = 0; port < TOTAL_PORT_NUM; port++) { |
2625 | sw_dis_multi_queue(hw, port); |
2626 | sw_dis_diffserv(hw, port); |
2627 | sw_dis_802_1p(hw, port); |
2628 | sw_cfg_replace_vid(hw, port, 0); |
2629 | |
2630 | sw->port_cfg[port].port_prio = 0; |
2631 | sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio); |
2632 | } |
2633 | sw_cfg_replace_null_vid(hw, 0); |
2634 | } |
2635 | |
2636 | /** |
2637 | * port_get_def_vid - get port default VID. |
2638 | * @hw: The hardware instance. |
2639 | * @port: The port index. |
2640 | * @vid: Buffer to store the VID. |
2641 | * |
2642 | * This routine retrieves the default VID of the port. |
2643 | */ |
2644 | static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid) |
2645 | { |
2646 | u32 addr; |
2647 | |
2648 | PORT_CTRL_ADDR(port, addr); |
2649 | addr += KS8842_PORT_CTRL_VID_OFFSET; |
2650 | *vid = readw(hw->io + addr); |
2651 | } |
2652 | |
2653 | /** |
2654 | * sw_init_vlan - initialize switch VLAN |
2655 | * @hw: The hardware instance. |
2656 | * |
2657 | * This routine initializes the VLAN function of the switch. |
2658 | */ |
2659 | static void sw_init_vlan(struct ksz_hw *hw) |
2660 | { |
2661 | int port; |
2662 | int entry; |
2663 | struct ksz_switch *sw = hw->ksz_switch; |
2664 | |
2665 | /* Read 16 VLAN entries from device's VLAN table. */ |
2666 | for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) { |
2667 | sw_r_vlan_table(hw, entry, |
2668 | &sw->vlan_table[entry].vid, |
2669 | &sw->vlan_table[entry].fid, |
2670 | &sw->vlan_table[entry].member); |
2671 | } |
2672 | |
2673 | for (port = 0; port < TOTAL_PORT_NUM; port++) { |
2674 | port_get_def_vid(hw, port, &sw->port_cfg[port].vid); |
2675 | sw->port_cfg[port].member = PORT_MASK; |
2676 | } |
2677 | } |
2678 | |
2679 | /** |
2680 | * sw_cfg_port_base_vlan - configure port-based VLAN membership |
2681 | * @hw: The hardware instance. |
2682 | * @port: The port index. |
2683 | * @member: The port-based VLAN membership. |
2684 | * |
2685 | * This routine configures the port-based VLAN membership of the port. |
2686 | */ |
2687 | static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member) |
2688 | { |
2689 | u32 addr; |
2690 | u8 data; |
2691 | |
2692 | PORT_CTRL_ADDR(port, addr); |
2693 | addr += KS8842_PORT_CTRL_2_OFFSET; |
2694 | |
2695 | data = readb(hw->io + addr); |
2696 | data &= ~PORT_VLAN_MEMBERSHIP; |
2697 | data |= (member & PORT_MASK); |
2698 | writeb(data, hw->io + addr); |
2699 | |
2700 | hw->ksz_switch->port_cfg[port].member = member; |
2701 | } |
2702 | |
2703 | /** |
2704 | * sw_get_addr - get the switch MAC address. |
2705 | * @hw: The hardware instance. |
2706 | * @mac_addr: Buffer to store the MAC address. |
2707 | * |
2708 | * This function retrieves the MAC address of the switch. |
2709 | */ |
2710 | static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr) |
2711 | { |
2712 | int i; |
2713 | |
2714 | for (i = 0; i < 6; i += 2) { |
2715 | mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i); |
2716 | mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i); |
2717 | } |
2718 | } |
2719 | |
2720 | /** |
2721 | * sw_set_addr - configure switch MAC address |
2722 | * @hw: The hardware instance. |
2723 | * @mac_addr: The MAC address. |
2724 | * |
2725 | * This function configures the MAC address of the switch. |
2726 | */ |
2727 | static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr) |
2728 | { |
2729 | int i; |
2730 | |
2731 | for (i = 0; i < 6; i += 2) { |
2732 | writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i); |
2733 | writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i); |
2734 | } |
2735 | } |
2736 | |
2737 | /** |
2738 | * sw_set_global_ctrl - set switch global control |
2739 | * @hw: The hardware instance. |
2740 | * |
2741 | * This routine sets the global control of the switch function. |
2742 | */ |
2743 | static void sw_set_global_ctrl(struct ksz_hw *hw) |
2744 | { |
2745 | u16 data; |
2746 | |
2747 | /* Enable switch MII flow control. */ |
2748 | data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); |
2749 | data |= SWITCH_FLOW_CTRL; |
2750 | writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); |
2751 | |
2752 | data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET); |
2753 | |
2754 | /* Enable aggressive back off algorithm in half duplex mode. */ |
2755 | data |= SWITCH_AGGR_BACKOFF; |
2756 | |
2757 | /* Enable automatic fast aging when link changed detected. */ |
2758 | data |= SWITCH_AGING_ENABLE; |
2759 | data |= SWITCH_LINK_AUTO_AGING; |
2760 | |
2761 | if (hw->overrides & FAST_AGING) |
2762 | data |= SWITCH_FAST_AGING; |
2763 | else |
2764 | data &= ~SWITCH_FAST_AGING; |
2765 | writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET); |
2766 | |
2767 | data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); |
2768 | |
2769 | /* Enable no excessive collision drop. */ |
2770 | data |= NO_EXC_COLLISION_DROP; |
2771 | writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); |
2772 | } |
2773 | |
2774 | enum { |
2775 | STP_STATE_DISABLED = 0, |
2776 | STP_STATE_LISTENING, |
2777 | STP_STATE_LEARNING, |
2778 | STP_STATE_FORWARDING, |
2779 | STP_STATE_BLOCKED, |
2780 | STP_STATE_SIMPLE |
2781 | }; |
2782 | |
2783 | /** |
2784 | * port_set_stp_state - configure port spanning tree state |
2785 | * @hw: The hardware instance. |
2786 | * @port: The port index. |
2787 | * @state: The spanning tree state. |
2788 | * |
2789 | * This routine configures the spanning tree state of the port. |
2790 | */ |
2791 | static void port_set_stp_state(struct ksz_hw *hw, int port, int state) |
2792 | { |
2793 | u16 data; |
2794 | |
2795 | port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data); |
2796 | switch (state) { |
2797 | case STP_STATE_DISABLED: |
2798 | data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE); |
2799 | data |= PORT_LEARN_DISABLE; |
2800 | break; |
2801 | case STP_STATE_LISTENING: |
2802 | /* |
2803 | * No need to turn on transmit because of port direct mode. |
2804 | * Turning on receive is required if static MAC table is not setup. |
2805 | */ |
2806 | data &= ~PORT_TX_ENABLE; |
2807 | data |= PORT_RX_ENABLE; |
2808 | data |= PORT_LEARN_DISABLE; |
2809 | break; |
2810 | case STP_STATE_LEARNING: |
2811 | data &= ~PORT_TX_ENABLE; |
2812 | data |= PORT_RX_ENABLE; |
2813 | data &= ~PORT_LEARN_DISABLE; |
2814 | break; |
2815 | case STP_STATE_FORWARDING: |
2816 | data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); |
2817 | data &= ~PORT_LEARN_DISABLE; |
2818 | break; |
2819 | case STP_STATE_BLOCKED: |
2820 | /* |
2821 | * Need to setup static MAC table with override to keep receiving BPDU |
2822 | * messages. See sw_init_stp routine. |
2823 | */ |
2824 | data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE); |
2825 | data |= PORT_LEARN_DISABLE; |
2826 | break; |
2827 | case STP_STATE_SIMPLE: |
2828 | data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); |
2829 | data |= PORT_LEARN_DISABLE; |
2830 | break; |
2831 | } |
2832 | port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data); |
2833 | hw->ksz_switch->port_cfg[port].stp_state = state; |
2834 | } |
2835 | |
2836 | #define STP_ENTRY 0 |
2837 | #define BROADCAST_ENTRY 1 |
2838 | #define BRIDGE_ADDR_ENTRY 2 |
2839 | #define IPV6_ADDR_ENTRY 3 |
2840 | |
2841 | /** |
2842 | * sw_clr_sta_mac_table - clear static MAC table |
2843 | * @hw: The hardware instance. |
2844 | * |
2845 | * This routine clears the static MAC table. |
2846 | */ |
2847 | static void sw_clr_sta_mac_table(struct ksz_hw *hw) |
2848 | { |
2849 | struct ksz_mac_table *entry; |
2850 | int i; |
2851 | |
2852 | for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) { |
2853 | entry = &hw->ksz_switch->mac_table[i]; |
2854 | sw_w_sta_mac_table(hw, i, |
2855 | entry->mac_addr, entry->ports, |
2856 | entry->override, 0, |
2857 | entry->use_fid, entry->fid); |
2858 | } |
2859 | } |
2860 | |
2861 | /** |
2862 | * sw_init_stp - initialize switch spanning tree support |
2863 | * @hw: The hardware instance. |
2864 | * |
2865 | * This routine initializes the spanning tree support of the switch. |
2866 | */ |
2867 | static void sw_init_stp(struct ksz_hw *hw) |
2868 | { |
2869 | struct ksz_mac_table *entry; |
2870 | |
2871 | entry = &hw->ksz_switch->mac_table[STP_ENTRY]; |
2872 | entry->mac_addr[0] = 0x01; |
2873 | entry->mac_addr[1] = 0x80; |
2874 | entry->mac_addr[2] = 0xC2; |
2875 | entry->mac_addr[3] = 0x00; |
2876 | entry->mac_addr[4] = 0x00; |
2877 | entry->mac_addr[5] = 0x00; |
2878 | entry->ports = HOST_MASK; |
2879 | entry->override = 1; |
2880 | entry->valid = 1; |
2881 | sw_w_sta_mac_table(hw, STP_ENTRY, |
2882 | entry->mac_addr, entry->ports, |
2883 | entry->override, entry->valid, |
2884 | entry->use_fid, entry->fid); |
2885 | } |
2886 | |
2887 | /** |
2888 | * sw_block_addr - block certain packets from the host port |
2889 | * @hw: The hardware instance. |
2890 | * |
2891 | * This routine blocks certain packets from reaching to the host port. |
2892 | */ |
2893 | static void sw_block_addr(struct ksz_hw *hw) |
2894 | { |
2895 | struct ksz_mac_table *entry; |
2896 | int i; |
2897 | |
2898 | for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) { |
2899 | entry = &hw->ksz_switch->mac_table[i]; |
2900 | entry->valid = 0; |
2901 | sw_w_sta_mac_table(hw, i, |
2902 | entry->mac_addr, entry->ports, |
2903 | entry->override, entry->valid, |
2904 | entry->use_fid, entry->fid); |
2905 | } |
2906 | } |
2907 | |
2908 | #define PHY_LINK_SUPPORT \ |
2909 | (PHY_AUTO_NEG_ASYM_PAUSE | \ |
2910 | PHY_AUTO_NEG_SYM_PAUSE | \ |
2911 | PHY_AUTO_NEG_100BT4 | \ |
2912 | PHY_AUTO_NEG_100BTX_FD | \ |
2913 | PHY_AUTO_NEG_100BTX | \ |
2914 | PHY_AUTO_NEG_10BT_FD | \ |
2915 | PHY_AUTO_NEG_10BT) |
2916 | |
2917 | static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data) |
2918 | { |
2919 | *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); |
2920 | } |
2921 | |
2922 | static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data) |
2923 | { |
2924 | writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); |
2925 | } |
2926 | |
2927 | static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data) |
2928 | { |
2929 | *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET); |
2930 | } |
2931 | |
2932 | static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data) |
2933 | { |
2934 | *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); |
2935 | } |
2936 | |
2937 | static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data) |
2938 | { |
2939 | writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); |
2940 | } |
2941 | |
2942 | static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data) |
2943 | { |
2944 | *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET); |
2945 | } |
2946 | |
2947 | static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data) |
2948 | { |
2949 | *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); |
2950 | } |
2951 | |
2952 | static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data) |
2953 | { |
2954 | writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); |
2955 | } |
2956 | |
2957 | static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data) |
2958 | { |
2959 | *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); |
2960 | } |
2961 | |
2962 | static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data) |
2963 | { |
2964 | writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); |
2965 | } |
2966 | |
2967 | static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data) |
2968 | { |
2969 | *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); |
2970 | } |
2971 | |
2972 | static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data) |
2973 | { |
2974 | writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); |
2975 | } |
2976 | |
2977 | /** |
2978 | * hw_r_phy - read data from PHY register |
2979 | * @hw: The hardware instance. |
2980 | * @port: Port to read. |
2981 | * @reg: PHY register to read. |
2982 | * @val: Buffer to store the read data. |
2983 | * |
2984 | * This routine reads data from the PHY register. |
2985 | */ |
2986 | static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val) |
2987 | { |
2988 | int phy; |
2989 | |
2990 | phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg; |
2991 | *val = readw(hw->io + phy); |
2992 | } |
2993 | |
2994 | /** |
2995 | * port_w_phy - write data to PHY register |
2996 | * @hw: The hardware instance. |
2997 | * @port: Port to write. |
2998 | * @reg: PHY register to write. |
2999 | * @val: Word data to write. |
3000 | * |
3001 | * This routine writes data to the PHY register. |
3002 | */ |
3003 | static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val) |
3004 | { |
3005 | int phy; |
3006 | |
3007 | phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg; |
3008 | writew(val, hw->io + phy); |
3009 | } |
3010 | |
3011 | /* |
3012 | * EEPROM access functions |
3013 | */ |
3014 | |
3015 | #define AT93C_CODE 0 |
3016 | #define AT93C_WR_OFF 0x00 |
3017 | #define AT93C_WR_ALL 0x10 |
3018 | #define AT93C_ER_ALL 0x20 |
3019 | #define AT93C_WR_ON 0x30 |
3020 | |
3021 | #define AT93C_WRITE 1 |
3022 | #define AT93C_READ 2 |
3023 | #define AT93C_ERASE 3 |
3024 | |
3025 | #define EEPROM_DELAY 4 |
3026 | |
3027 | static inline void drop_gpio(struct ksz_hw *hw, u8 gpio) |
3028 | { |
3029 | u16 data; |
3030 | |
3031 | data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); |
3032 | data &= ~gpio; |
3033 | writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); |
3034 | } |
3035 | |
3036 | static inline void raise_gpio(struct ksz_hw *hw, u8 gpio) |
3037 | { |
3038 | u16 data; |
3039 | |
3040 | data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); |
3041 | data |= gpio; |
3042 | writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); |
3043 | } |
3044 | |
3045 | static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio) |
3046 | { |
3047 | u16 data; |
3048 | |
3049 | data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); |
3050 | return (u8)(data & gpio); |
3051 | } |
3052 | |
3053 | static void eeprom_clk(struct ksz_hw *hw) |
3054 | { |
3055 | raise_gpio(hw, EEPROM_SERIAL_CLOCK); |
3056 | udelay(EEPROM_DELAY); |
3057 | drop_gpio(hw, EEPROM_SERIAL_CLOCK); |
3058 | udelay(EEPROM_DELAY); |
3059 | } |
3060 | |
3061 | static u16 spi_r(struct ksz_hw *hw) |
3062 | { |
3063 | int i; |
3064 | u16 temp = 0; |
3065 | |
3066 | for (i = 15; i >= 0; i--) { |
3067 | raise_gpio(hw, EEPROM_SERIAL_CLOCK); |
3068 | udelay(EEPROM_DELAY); |
3069 | |
3070 | temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0; |
3071 | |
3072 | drop_gpio(hw, EEPROM_SERIAL_CLOCK); |
3073 | udelay(EEPROM_DELAY); |
3074 | } |
3075 | return temp; |
3076 | } |
3077 | |
3078 | static void spi_w(struct ksz_hw *hw, u16 data) |
3079 | { |
3080 | int i; |
3081 | |
3082 | for (i = 15; i >= 0; i--) { |
3083 | (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : |
3084 | drop_gpio(hw, EEPROM_DATA_OUT); |
3085 | eeprom_clk(hw); |
3086 | } |
3087 | } |
3088 | |
3089 | static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg) |
3090 | { |
3091 | int i; |
3092 | |
3093 | /* Initial start bit */ |
3094 | raise_gpio(hw, EEPROM_DATA_OUT); |
3095 | eeprom_clk(hw); |
3096 | |
3097 | /* AT93C operation */ |
3098 | for (i = 1; i >= 0; i--) { |
3099 | (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : |
3100 | drop_gpio(hw, EEPROM_DATA_OUT); |
3101 | eeprom_clk(hw); |
3102 | } |
3103 | |
3104 | /* Address location */ |
3105 | for (i = 5; i >= 0; i--) { |
3106 | (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : |
3107 | drop_gpio(hw, EEPROM_DATA_OUT); |
3108 | eeprom_clk(hw); |
3109 | } |
3110 | } |
3111 | |
3112 | #define EEPROM_DATA_RESERVED 0 |
3113 | #define EEPROM_DATA_MAC_ADDR_0 1 |
3114 | #define EEPROM_DATA_MAC_ADDR_1 2 |
3115 | #define EEPROM_DATA_MAC_ADDR_2 3 |
3116 | #define EEPROM_DATA_SUBSYS_ID 4 |
3117 | #define EEPROM_DATA_SUBSYS_VEN_ID 5 |
3118 | #define EEPROM_DATA_PM_CAP 6 |
3119 | |
3120 | /* User defined EEPROM data */ |
3121 | #define EEPROM_DATA_OTHER_MAC_ADDR 9 |
3122 | |
3123 | /** |
3124 | * eeprom_read - read from AT93C46 EEPROM |
3125 | * @hw: The hardware instance. |
3126 | * @reg: The register offset. |
3127 | * |
3128 | * This function reads a word from the AT93C46 EEPROM. |
3129 | * |
3130 | * Return the data value. |
3131 | */ |
3132 | static u16 eeprom_read(struct ksz_hw *hw, u8 reg) |
3133 | { |
3134 | u16 data; |
3135 | |
3136 | raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); |
3137 | |
3138 | spi_reg(hw, AT93C_READ, reg); |
3139 | data = spi_r(hw); |
3140 | |
3141 | drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); |
3142 | |
3143 | return data; |
3144 | } |
3145 | |
3146 | /** |
3147 | * eeprom_write - write to AT93C46 EEPROM |
3148 | * @hw: The hardware instance. |
3149 | * @reg: The register offset. |
3150 | * @data: The data value. |
3151 | * |
3152 | * This procedure writes a word to the AT93C46 EEPROM. |
3153 | */ |
3154 | static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data) |
3155 | { |
3156 | int timeout; |
3157 | |
3158 | raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); |
3159 | |
3160 | /* Enable write. */ |
3161 | spi_reg(hw, AT93C_CODE, AT93C_WR_ON); |
3162 | drop_gpio(hw, EEPROM_CHIP_SELECT); |
3163 | udelay(1); |
3164 | |
3165 | /* Erase the register. */ |
3166 | raise_gpio(hw, EEPROM_CHIP_SELECT); |
3167 | spi_reg(hw, AT93C_ERASE, reg); |
3168 | drop_gpio(hw, EEPROM_CHIP_SELECT); |
3169 | udelay(1); |
3170 | |
3171 | /* Check operation complete. */ |
3172 | raise_gpio(hw, EEPROM_CHIP_SELECT); |
3173 | timeout = 8; |
3174 | mdelay(2); |
3175 | do { |
3176 | mdelay(1); |
3177 | } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout); |
3178 | drop_gpio(hw, EEPROM_CHIP_SELECT); |
3179 | udelay(1); |
3180 | |
3181 | /* Write the register. */ |
3182 | raise_gpio(hw, EEPROM_CHIP_SELECT); |
3183 | spi_reg(hw, AT93C_WRITE, reg); |
3184 | spi_w(hw, data); |
3185 | drop_gpio(hw, EEPROM_CHIP_SELECT); |
3186 | udelay(1); |
3187 | |
3188 | /* Check operation complete. */ |
3189 | raise_gpio(hw, EEPROM_CHIP_SELECT); |
3190 | timeout = 8; |
3191 | mdelay(2); |
3192 | do { |
3193 | mdelay(1); |
3194 | } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout); |
3195 | drop_gpio(hw, EEPROM_CHIP_SELECT); |
3196 | udelay(1); |
3197 | |
3198 | /* Disable write. */ |
3199 | raise_gpio(hw, EEPROM_CHIP_SELECT); |
3200 | spi_reg(hw, AT93C_CODE, AT93C_WR_OFF); |
3201 | |
3202 | drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); |
3203 | } |
3204 | |
3205 | /* |
3206 | * Link detection routines |
3207 | */ |
3208 | |
3209 | static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl) |
3210 | { |
3211 | ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE; |
3212 | switch (port->flow_ctrl) { |
3213 | case PHY_FLOW_CTRL: |
3214 | ctrl |= PORT_AUTO_NEG_SYM_PAUSE; |
3215 | break; |
3216 | /* Not supported. */ |
3217 | case PHY_TX_ONLY: |
3218 | case PHY_RX_ONLY: |
3219 | default: |
3220 | break; |
3221 | } |
3222 | return ctrl; |
3223 | } |
3224 | |
3225 | static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx) |
3226 | { |
3227 | u32 rx_cfg; |
3228 | u32 tx_cfg; |
3229 | |
3230 | rx_cfg = hw->rx_cfg; |
3231 | tx_cfg = hw->tx_cfg; |
3232 | if (rx) |
3233 | hw->rx_cfg |= DMA_RX_FLOW_ENABLE; |
3234 | else |
3235 | hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE; |
3236 | if (tx) |
3237 | hw->tx_cfg |= DMA_TX_FLOW_ENABLE; |
3238 | else |
3239 | hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE; |
3240 | if (hw->enabled) { |
3241 | if (rx_cfg != hw->rx_cfg) |
3242 | writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); |
3243 | if (tx_cfg != hw->tx_cfg) |
3244 | writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); |
3245 | } |
3246 | } |
3247 | |
3248 | static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port, |
3249 | u16 local, u16 remote) |
3250 | { |
3251 | int rx; |
3252 | int tx; |
3253 | |
3254 | if (hw->overrides & PAUSE_FLOW_CTRL) |
3255 | return; |
3256 | |
3257 | rx = tx = 0; |
3258 | if (port->force_link) |
3259 | rx = tx = 1; |
3260 | if (remote & PHY_AUTO_NEG_SYM_PAUSE) { |
3261 | if (local & PHY_AUTO_NEG_SYM_PAUSE) { |
3262 | rx = tx = 1; |
3263 | } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) && |
3264 | (local & PHY_AUTO_NEG_PAUSE) == |
3265 | PHY_AUTO_NEG_ASYM_PAUSE) { |
3266 | tx = 1; |
3267 | } |
3268 | } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) { |
3269 | if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE) |
3270 | rx = 1; |
3271 | } |
3272 | if (!hw->ksz_switch) |
3273 | set_flow_ctrl(hw, rx, tx); |
3274 | } |
3275 | |
3276 | static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port, |
3277 | struct ksz_port_info *info, u16 link_status) |
3278 | { |
3279 | if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) && |
3280 | !(hw->overrides & PAUSE_FLOW_CTRL)) { |
3281 | u32 cfg = hw->tx_cfg; |
3282 | |
3283 | /* Disable flow control in the half duplex mode. */ |
3284 | if (1 == info->duplex) |
3285 | hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE; |
3286 | if (hw->enabled && cfg != hw->tx_cfg) |
3287 | writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); |
3288 | } |
3289 | } |
3290 | |
3291 | /** |
3292 | * port_get_link_speed - get current link status |
3293 | * @port: The port instance. |
3294 | * |
3295 | * This routine reads PHY registers to determine the current link status of the |
3296 | * switch ports. |
3297 | */ |
3298 | static void port_get_link_speed(struct ksz_port *port) |
3299 | { |
3300 | uint interrupt; |
3301 | struct ksz_port_info *info; |
3302 | struct ksz_port_info *linked = NULL; |
3303 | struct ksz_hw *hw = port->hw; |
3304 | u16 data; |
3305 | u16 status; |
3306 | u8 local; |
3307 | u8 remote; |
3308 | int i; |
3309 | int p; |
3310 | int change = 0; |
3311 | |
3312 | interrupt = hw_block_intr(hw); |
3313 | |
3314 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { |
3315 | info = &hw->port_info[p]; |
3316 | port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data); |
3317 | port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status); |
3318 | |
3319 | /* |
3320 | * Link status is changing all the time even when there is no |
3321 | * cable connection! |
3322 | */ |
3323 | remote = status & (PORT_AUTO_NEG_COMPLETE | |
3324 | PORT_STATUS_LINK_GOOD); |
3325 | local = (u8) data; |
3326 | |
3327 | /* No change to status. */ |
3328 | if (local == info->advertised && remote == info->partner) |
3329 | continue; |
3330 | |
3331 | info->advertised = local; |
3332 | info->partner = remote; |
3333 | if (status & PORT_STATUS_LINK_GOOD) { |
3334 | |
3335 | /* Remember the first linked port. */ |
3336 | if (!linked) |
3337 | linked = info; |
3338 | |
3339 | info->tx_rate = 10 * TX_RATE_UNIT; |
3340 | if (status & PORT_STATUS_SPEED_100MBIT) |
3341 | info->tx_rate = 100 * TX_RATE_UNIT; |
3342 | |
3343 | info->duplex = 1; |
3344 | if (status & PORT_STATUS_FULL_DUPLEX) |
3345 | info->duplex = 2; |
3346 | |
3347 | if (media_connected != info->state) { |
3348 | hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET, |
3349 | &data); |
3350 | hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET, |
3351 | &status); |
3352 | determine_flow_ctrl(hw, port, data, status); |
3353 | if (hw->ksz_switch) { |
3354 | port_cfg_back_pressure(hw, p, |
3355 | (1 == info->duplex)); |
3356 | } |
3357 | change |= 1 << i; |
3358 | port_cfg_change(hw, port, info, status); |
3359 | } |
3360 | info->state = media_connected; |
3361 | } else { |
3362 | if (media_disconnected != info->state) { |
3363 | change |= 1 << i; |
3364 | |
3365 | /* Indicate the link just goes down. */ |
3366 | hw->port_mib[p].link_down = 1; |
3367 | } |
3368 | info->state = media_disconnected; |
3369 | } |
3370 | hw->port_mib[p].state = (u8) info->state; |
3371 | } |
3372 | |
3373 | if (linked && media_disconnected == port->linked->state) |
3374 | port->linked = linked; |
3375 | |
3376 | hw_restore_intr(hw, interrupt); |
3377 | } |
3378 | |
3379 | #define PHY_RESET_TIMEOUT 10 |
3380 | |
3381 | /** |
3382 | * port_set_link_speed - set port speed |
3383 | * @port: The port instance. |
3384 | * |
3385 | * This routine sets the link speed of the switch ports. |
3386 | */ |
3387 | static void port_set_link_speed(struct ksz_port *port) |
3388 | { |
3389 | struct ksz_port_info *info; |
3390 | struct ksz_hw *hw = port->hw; |
3391 | u16 data; |
3392 | u16 cfg; |
3393 | u8 status; |
3394 | int i; |
3395 | int p; |
3396 | |
3397 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { |
3398 | info = &hw->port_info[p]; |
3399 | |
3400 | port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data); |
3401 | port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status); |
3402 | |
3403 | cfg = 0; |
3404 | if (status & PORT_STATUS_LINK_GOOD) |
3405 | cfg = data; |
3406 | |
3407 | data |= PORT_AUTO_NEG_ENABLE; |
3408 | data = advertised_flow_ctrl(port, data); |
3409 | |
3410 | data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX | |
3411 | PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT; |
3412 | |
3413 | /* Check if manual configuration is specified by the user. */ |
3414 | if (port->speed || port->duplex) { |
3415 | if (10 == port->speed) |
3416 | data &= ~(PORT_AUTO_NEG_100BTX_FD | |
3417 | PORT_AUTO_NEG_100BTX); |
3418 | else if (100 == port->speed) |
3419 | data &= ~(PORT_AUTO_NEG_10BT_FD | |
3420 | PORT_AUTO_NEG_10BT); |
3421 | if (1 == port->duplex) |
3422 | data &= ~(PORT_AUTO_NEG_100BTX_FD | |
3423 | PORT_AUTO_NEG_10BT_FD); |
3424 | else if (2 == port->duplex) |
3425 | data &= ~(PORT_AUTO_NEG_100BTX | |
3426 | PORT_AUTO_NEG_10BT); |
3427 | } |
3428 | if (data != cfg) { |
3429 | data |= PORT_AUTO_NEG_RESTART; |
3430 | port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data); |
3431 | } |
3432 | } |
3433 | } |
3434 | |
3435 | /** |
3436 | * port_force_link_speed - force port speed |
3437 | * @port: The port instance. |
3438 | * |
3439 | * This routine forces the link speed of the switch ports. |
3440 | */ |
3441 | static void port_force_link_speed(struct ksz_port *port) |
3442 | { |
3443 | struct ksz_hw *hw = port->hw; |
3444 | u16 data; |
3445 | int i; |
3446 | int phy; |
3447 | int p; |
3448 | |
3449 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { |
3450 | phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL; |
3451 | hw_r_phy_ctrl(hw, phy, &data); |
3452 | |
3453 | data &= ~PHY_AUTO_NEG_ENABLE; |
3454 | |
3455 | if (10 == port->speed) |
3456 | data &= ~PHY_SPEED_100MBIT; |
3457 | else if (100 == port->speed) |
3458 | data |= PHY_SPEED_100MBIT; |
3459 | if (1 == port->duplex) |
3460 | data &= ~PHY_FULL_DUPLEX; |
3461 | else if (2 == port->duplex) |
3462 | data |= PHY_FULL_DUPLEX; |
3463 | hw_w_phy_ctrl(hw, phy, data); |
3464 | } |
3465 | } |
3466 | |
3467 | static void port_set_power_saving(struct ksz_port *port, int enable) |
3468 | { |
3469 | struct ksz_hw *hw = port->hw; |
3470 | int i; |
3471 | int p; |
3472 | |
3473 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) |
3474 | port_cfg(hw, p, |
3475 | KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable); |
3476 | } |
3477 | |
3478 | /* |
3479 | * KSZ8841 power management functions |
3480 | */ |
3481 | |
3482 | /** |
3483 | * hw_chk_wol_pme_status - check PMEN pin |
3484 | * @hw: The hardware instance. |
3485 | * |
3486 | * This function is used to check PMEN pin is asserted. |
3487 | * |
3488 | * Return 1 if PMEN pin is asserted; otherwise, 0. |
3489 | */ |
3490 | static int hw_chk_wol_pme_status(struct ksz_hw *hw) |
3491 | { |
3492 | struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); |
3493 | struct pci_dev *pdev = hw_priv->pdev; |
3494 | u16 data; |
3495 | |
3496 | if (!pdev->pm_cap) |
3497 | return 0; |
3498 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); |
3499 | return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS; |
3500 | } |
3501 | |
3502 | /** |
3503 | * hw_clr_wol_pme_status - clear PMEN pin |
3504 | * @hw: The hardware instance. |
3505 | * |
3506 | * This routine is used to clear PME_Status to deassert PMEN pin. |
3507 | */ |
3508 | static void hw_clr_wol_pme_status(struct ksz_hw *hw) |
3509 | { |
3510 | struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); |
3511 | struct pci_dev *pdev = hw_priv->pdev; |
3512 | u16 data; |
3513 | |
3514 | if (!pdev->pm_cap) |
3515 | return; |
3516 | |
3517 | /* Clear PME_Status to deassert PMEN pin. */ |
3518 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); |
3519 | data |= PCI_PM_CTRL_PME_STATUS; |
3520 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data); |
3521 | } |
3522 | |
3523 | /** |
3524 | * hw_cfg_wol_pme - enable or disable Wake-on-LAN |
3525 | * @hw: The hardware instance. |
3526 | * @set: The flag indicating whether to enable or disable. |
3527 | * |
3528 | * This routine is used to enable or disable Wake-on-LAN. |
3529 | */ |
3530 | static void hw_cfg_wol_pme(struct ksz_hw *hw, int set) |
3531 | { |
3532 | struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); |
3533 | struct pci_dev *pdev = hw_priv->pdev; |
3534 | u16 data; |
3535 | |
3536 | if (!pdev->pm_cap) |
3537 | return; |
3538 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); |
3539 | data &= ~PCI_PM_CTRL_STATE_MASK; |
3540 | if (set) |
3541 | data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot; |
3542 | else |
3543 | data &= ~PCI_PM_CTRL_PME_ENABLE; |
3544 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data); |
3545 | } |
3546 | |
3547 | /** |
3548 | * hw_cfg_wol - configure Wake-on-LAN features |
3549 | * @hw: The hardware instance. |
3550 | * @frame: The pattern frame bit. |
3551 | * @set: The flag indicating whether to enable or disable. |
3552 | * |
3553 | * This routine is used to enable or disable certain Wake-on-LAN features. |
3554 | */ |
3555 | static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set) |
3556 | { |
3557 | u16 data; |
3558 | |
3559 | data = readw(hw->io + KS8841_WOL_CTRL_OFFSET); |
3560 | if (set) |
3561 | data |= frame; |
3562 | else |
3563 | data &= ~frame; |
3564 | writew(data, hw->io + KS8841_WOL_CTRL_OFFSET); |
3565 | } |
3566 | |
3567 | /** |
3568 | * hw_set_wol_frame - program Wake-on-LAN pattern |
3569 | * @hw: The hardware instance. |
3570 | * @i: The frame index. |
3571 | * @mask_size: The size of the mask. |
3572 | * @mask: Mask to ignore certain bytes in the pattern. |
3573 | * @frame_size: The size of the frame. |
3574 | * @pattern: The frame data. |
3575 | * |
3576 | * This routine is used to program Wake-on-LAN pattern. |
3577 | */ |
3578 | static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size, |
3579 | u8 *mask, uint frame_size, u8 *pattern) |
3580 | { |
3581 | int bits; |
3582 | int from; |
3583 | int len; |
3584 | int to; |
3585 | u32 crc; |
3586 | u8 data[64]; |
3587 | u8 val = 0; |
3588 | |
3589 | if (frame_size > mask_size * 8) |
3590 | frame_size = mask_size * 8; |
3591 | if (frame_size > 64) |
3592 | frame_size = 64; |
3593 | |
3594 | i *= 0x10; |
3595 | writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i); |
3596 | writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i); |
3597 | |
3598 | bits = len = from = to = 0; |
3599 | do { |
3600 | if (bits) { |
3601 | if ((val & 1)) |
3602 | data[to++] = pattern[from]; |
3603 | val >>= 1; |
3604 | ++from; |
3605 | --bits; |
3606 | } else { |
3607 | val = mask[len]; |
3608 | writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i |
3609 | + len); |
3610 | ++len; |
3611 | if (val) |
3612 | bits = 8; |
3613 | else |
3614 | from += 8; |
3615 | } |
3616 | } while (from < (int) frame_size); |
3617 | if (val) { |
3618 | bits = mask[len - 1]; |
3619 | val <<= (from % 8); |
3620 | bits &= ~val; |
3621 | writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len - |
3622 | 1); |
3623 | } |
3624 | crc = ether_crc(to, data); |
3625 | writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i); |
3626 | } |
3627 | |
3628 | /** |
3629 | * hw_add_wol_arp - add ARP pattern |
3630 | * @hw: The hardware instance. |
3631 | * @ip_addr: The IPv4 address assigned to the device. |
3632 | * |
3633 | * This routine is used to add ARP pattern for waking up the host. |
3634 | */ |
3635 | static void hw_add_wol_arp(struct ksz_hw *hw, u8 *ip_addr) |
3636 | { |
3637 | u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 }; |
3638 | u8 pattern[42] = { |
3639 | 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, |
3640 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
3641 | 0x08, 0x06, |
3642 | 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, |
3643 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
3644 | 0x00, 0x00, 0x00, 0x00, |
3645 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
3646 | 0x00, 0x00, 0x00, 0x00 }; |
3647 | |
3648 | memcpy(&pattern[38], ip_addr, 4); |
3649 | hw_set_wol_frame(hw, 3, 6, mask, 42, pattern); |
3650 | } |
3651 | |
3652 | /** |
3653 | * hw_add_wol_bcast - add broadcast pattern |
3654 | * @hw: The hardware instance. |
3655 | * |
3656 | * This routine is used to add broadcast pattern for waking up the host. |
3657 | */ |
3658 | static void hw_add_wol_bcast(struct ksz_hw *hw) |
3659 | { |
3660 | u8 mask[] = { 0x3F }; |
3661 | u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
3662 | |
3663 | hw_set_wol_frame(hw, 2, 1, mask, MAC_ADDR_LEN, pattern); |
3664 | } |
3665 | |
3666 | /** |
3667 | * hw_add_wol_mcast - add multicast pattern |
3668 | * @hw: The hardware instance. |
3669 | * |
3670 | * This routine is used to add multicast pattern for waking up the host. |
3671 | * |
3672 | * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used |
3673 | * by IPv6 ping command. Note that multicast packets are filtred through the |
3674 | * multicast hash table, so not all multicast packets can wake up the host. |
3675 | */ |
3676 | static void hw_add_wol_mcast(struct ksz_hw *hw) |
3677 | { |
3678 | u8 mask[] = { 0x3F }; |
3679 | u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 }; |
3680 | |
3681 | memcpy(&pattern[3], &hw->override_addr[3], 3); |
3682 | hw_set_wol_frame(hw, 1, 1, mask, 6, pattern); |
3683 | } |
3684 | |
3685 | /** |
3686 | * hw_add_wol_ucast - add unicast pattern |
3687 | * @hw: The hardware instance. |
3688 | * |
3689 | * This routine is used to add unicast pattern to wakeup the host. |
3690 | * |
3691 | * It is assumed the unicast packet is directed to the device, as the hardware |
3692 | * can only receive them in normal case. |
3693 | */ |
3694 | static void hw_add_wol_ucast(struct ksz_hw *hw) |
3695 | { |
3696 | u8 mask[] = { 0x3F }; |
3697 | |
3698 | hw_set_wol_frame(hw, 0, 1, mask, MAC_ADDR_LEN, hw->override_addr); |
3699 | } |
3700 | |
3701 | /** |
3702 | * hw_enable_wol - enable Wake-on-LAN |
3703 | * @hw: The hardware instance. |
3704 | * @wol_enable: The Wake-on-LAN settings. |
3705 | * @net_addr: The IPv4 address assigned to the device. |
3706 | * |
3707 | * This routine is used to enable Wake-on-LAN depending on driver settings. |
3708 | */ |
3709 | static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, u8 *net_addr) |
3710 | { |
3711 | hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC)); |
3712 | hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST)); |
3713 | hw_add_wol_ucast(hw); |
3714 | hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST)); |
3715 | hw_add_wol_mcast(hw); |
3716 | hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST)); |
3717 | hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP)); |
3718 | hw_add_wol_arp(hw, net_addr); |
3719 | } |
3720 | |
3721 | /** |
3722 | * hw_init - check driver is correct for the hardware |
3723 | * @hw: The hardware instance. |
3724 | * |
3725 | * This function checks the hardware is correct for this driver and sets the |
3726 | * hardware up for proper initialization. |
3727 | * |
3728 | * Return number of ports or 0 if not right. |
3729 | */ |
3730 | static int hw_init(struct ksz_hw *hw) |
3731 | { |
3732 | int rc = 0; |
3733 | u16 data; |
3734 | u16 revision; |
3735 | |
3736 | /* Set bus speed to 125MHz. */ |
3737 | writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET); |
3738 | |
3739 | /* Check KSZ884x chip ID. */ |
3740 | data = readw(hw->io + KS884X_CHIP_ID_OFFSET); |
3741 | |
3742 | revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT; |
3743 | data &= KS884X_CHIP_ID_MASK_41; |
3744 | if (REG_CHIP_ID_41 == data) |
3745 | rc = 1; |
3746 | else if (REG_CHIP_ID_42 == data) |
3747 | rc = 2; |
3748 | else |
3749 | return 0; |
3750 | |
3751 | /* Setup hardware features or bug workarounds. */ |
3752 | if (revision <= 1) { |
3753 | hw->features |= SMALL_PACKET_TX_BUG; |
3754 | if (1 == rc) |
3755 | hw->features |= HALF_DUPLEX_SIGNAL_BUG; |
3756 | } |
3757 | hw->features |= IPV6_CSUM_GEN_HACK; |
3758 | return rc; |
3759 | } |
3760 | |
3761 | /** |
3762 | * hw_reset - reset the hardware |
3763 | * @hw: The hardware instance. |
3764 | * |
3765 | * This routine resets the hardware. |
3766 | */ |
3767 | static void hw_reset(struct ksz_hw *hw) |
3768 | { |
3769 | writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET); |
3770 | |
3771 | /* Wait for device to reset. */ |
3772 | mdelay(10); |
3773 | |
3774 | /* Write 0 to clear device reset. */ |
3775 | writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET); |
3776 | } |
3777 | |
3778 | /** |
3779 | * hw_setup - setup the hardware |
3780 | * @hw: The hardware instance. |
3781 | * |
3782 | * This routine setup the hardware for proper operation. |
3783 | */ |
3784 | static void hw_setup(struct ksz_hw *hw) |
3785 | { |
3786 | #if SET_DEFAULT_LED |
3787 | u16 data; |
3788 | |
3789 | /* Change default LED mode. */ |
3790 | data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET); |
3791 | data &= ~LED_MODE; |
3792 | data |= SET_DEFAULT_LED; |
3793 | writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET); |
3794 | #endif |
3795 | |
3796 | /* Setup transmit control. */ |
3797 | hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE | |
3798 | (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE); |
3799 | |
3800 | /* Setup receive control. */ |
3801 | hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST | |
3802 | (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE); |
3803 | hw->rx_cfg |= KS884X_DMA_RX_MULTICAST; |
3804 | |
3805 | /* Hardware cannot handle UDP packet in IP fragments. */ |
3806 | hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP); |
3807 | |
3808 | if (hw->all_multi) |
3809 | hw->rx_cfg |= DMA_RX_ALL_MULTICAST; |
3810 | if (hw->promiscuous) |
3811 | hw->rx_cfg |= DMA_RX_PROMISCUOUS; |
3812 | } |
3813 | |
3814 | /** |
3815 | * hw_setup_intr - setup interrupt mask |
3816 | * @hw: The hardware instance. |
3817 | * |
3818 | * This routine setup the interrupt mask for proper operation. |
3819 | */ |
3820 | static void hw_setup_intr(struct ksz_hw *hw) |
3821 | { |
3822 | hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN; |
3823 | } |
3824 | |
3825 | static void ksz_check_desc_num(struct ksz_desc_info *info) |
3826 | { |
3827 | #define MIN_DESC_SHIFT 2 |
3828 | |
3829 | int alloc = info->alloc; |
3830 | int shift; |
3831 | |
3832 | shift = 0; |
3833 | while (!(alloc & 1)) { |
3834 | shift++; |
3835 | alloc >>= 1; |
3836 | } |
3837 | if (alloc != 1 || shift < MIN_DESC_SHIFT) { |
3838 | printk(KERN_ALERT "Hardware descriptor numbers not right!\n"); |
3839 | while (alloc) { |
3840 | shift++; |
3841 | alloc >>= 1; |
3842 | } |
3843 | if (shift < MIN_DESC_SHIFT) |
3844 | shift = MIN_DESC_SHIFT; |
3845 | alloc = 1 << shift; |
3846 | info->alloc = alloc; |
3847 | } |
3848 | info->mask = info->alloc - 1; |
3849 | } |
3850 | |
3851 | static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit) |
3852 | { |
3853 | int i; |
3854 | u32 phys = desc_info->ring_phys; |
3855 | struct ksz_hw_desc *desc = desc_info->ring_virt; |
3856 | struct ksz_desc *cur = desc_info->ring; |
3857 | struct ksz_desc *previous = NULL; |
3858 | |
3859 | for (i = 0; i < desc_info->alloc; i++) { |
3860 | cur->phw = desc++; |
3861 | phys += desc_info->size; |
3862 | previous = cur++; |
3863 | previous->phw->next = cpu_to_le32(phys); |
3864 | } |
3865 | previous->phw->next = cpu_to_le32(desc_info->ring_phys); |
3866 | previous->sw.buf.rx.end_of_ring = 1; |
3867 | previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data); |
3868 | |
3869 | desc_info->avail = desc_info->alloc; |
3870 | desc_info->last = desc_info->next = 0; |
3871 | |
3872 | desc_info->cur = desc_info->ring; |
3873 | } |
3874 | |
3875 | /** |
3876 | * hw_set_desc_base - set descriptor base addresses |
3877 | * @hw: The hardware instance. |
3878 | * @tx_addr: The transmit descriptor base. |
3879 | * @rx_addr: The receive descriptor base. |
3880 | * |
3881 | * This routine programs the descriptor base addresses after reset. |
3882 | */ |
3883 | static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr) |
3884 | { |
3885 | /* Set base address of Tx/Rx descriptors. */ |
3886 | writel(tx_addr, hw->io + KS_DMA_TX_ADDR); |
3887 | writel(rx_addr, hw->io + KS_DMA_RX_ADDR); |
3888 | } |
3889 | |
3890 | static void hw_reset_pkts(struct ksz_desc_info *info) |
3891 | { |
3892 | info->cur = info->ring; |
3893 | info->avail = info->alloc; |
3894 | info->last = info->next = 0; |
3895 | } |
3896 | |
3897 | static inline void hw_resume_rx(struct ksz_hw *hw) |
3898 | { |
3899 | writel(DMA_START, hw->io + KS_DMA_RX_START); |
3900 | } |
3901 | |
3902 | /** |
3903 | * hw_start_rx - start receiving |
3904 | * @hw: The hardware instance. |
3905 | * |
3906 | * This routine starts the receive function of the hardware. |
3907 | */ |
3908 | static void hw_start_rx(struct ksz_hw *hw) |
3909 | { |
3910 | writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); |
3911 | |
3912 | /* Notify when the receive stops. */ |
3913 | hw->intr_mask |= KS884X_INT_RX_STOPPED; |
3914 | |
3915 | writel(DMA_START, hw->io + KS_DMA_RX_START); |
3916 | hw_ack_intr(hw, KS884X_INT_RX_STOPPED); |
3917 | hw->rx_stop++; |
3918 | |
3919 | /* Variable overflows. */ |
3920 | if (0 == hw->rx_stop) |
3921 | hw->rx_stop = 2; |
3922 | } |
3923 | |
3924 | /* |
3925 | * hw_stop_rx - stop receiving |
3926 | * @hw: The hardware instance. |
3927 | * |
3928 | * This routine stops the receive function of the hardware. |
3929 | */ |
3930 | static void hw_stop_rx(struct ksz_hw *hw) |
3931 | { |
3932 | hw->rx_stop = 0; |
3933 | hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED); |
3934 | writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL); |
3935 | } |
3936 | |
3937 | /** |
3938 | * hw_start_tx - start transmitting |
3939 | * @hw: The hardware instance. |
3940 | * |
3941 | * This routine starts the transmit function of the hardware. |
3942 | */ |
3943 | static void hw_start_tx(struct ksz_hw *hw) |
3944 | { |
3945 | writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); |
3946 | } |
3947 | |
3948 | /** |
3949 | * hw_stop_tx - stop transmitting |
3950 | * @hw: The hardware instance. |
3951 | * |
3952 | * This routine stops the transmit function of the hardware. |
3953 | */ |
3954 | static void hw_stop_tx(struct ksz_hw *hw) |
3955 | { |
3956 | writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL); |
3957 | } |
3958 | |
3959 | /** |
3960 | * hw_disable - disable hardware |
3961 | * @hw: The hardware instance. |
3962 | * |
3963 | * This routine disables the hardware. |
3964 | */ |
3965 | static void hw_disable(struct ksz_hw *hw) |
3966 | { |
3967 | hw_stop_rx(hw); |
3968 | hw_stop_tx(hw); |
3969 | hw->enabled = 0; |
3970 | } |
3971 | |
3972 | /** |
3973 | * hw_enable - enable hardware |
3974 | * @hw: The hardware instance. |
3975 | * |
3976 | * This routine enables the hardware. |
3977 | */ |
3978 | static void hw_enable(struct ksz_hw *hw) |
3979 | { |
3980 | hw_start_tx(hw); |
3981 | hw_start_rx(hw); |
3982 | hw->enabled = 1; |
3983 | } |
3984 | |
3985 | /** |
3986 | * hw_alloc_pkt - allocate enough descriptors for transmission |
3987 | * @hw: The hardware instance. |
3988 | * @length: The length of the packet. |
3989 | * @physical: Number of descriptors required. |
3990 | * |
3991 | * This function allocates descriptors for transmission. |
3992 | * |
3993 | * Return 0 if not successful; 1 for buffer copy; or number of descriptors. |
3994 | */ |
3995 | static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical) |
3996 | { |
3997 | /* Always leave one descriptor free. */ |
3998 | if (hw->tx_desc_info.avail <= 1) |
3999 | return 0; |
4000 | |
4001 | /* Allocate a descriptor for transmission and mark it current. */ |
4002 | get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur); |
4003 | hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1; |
4004 | |
4005 | /* Keep track of number of transmit descriptors used so far. */ |
4006 | ++hw->tx_int_cnt; |
4007 | hw->tx_size += length; |
4008 | |
4009 | /* Cannot hold on too much data. */ |
4010 | if (hw->tx_size >= MAX_TX_HELD_SIZE) |
4011 | hw->tx_int_cnt = hw->tx_int_mask + 1; |
4012 | |
4013 | if (physical > hw->tx_desc_info.avail) |
4014 | return 1; |
4015 | |
4016 | return hw->tx_desc_info.avail; |
4017 | } |
4018 | |
4019 | /** |
4020 | * hw_send_pkt - mark packet for transmission |
4021 | * @hw: The hardware instance. |
4022 | * |
4023 | * This routine marks the packet for transmission in PCI version. |
4024 | */ |
4025 | static void hw_send_pkt(struct ksz_hw *hw) |
4026 | { |
4027 | struct ksz_desc *cur = hw->tx_desc_info.cur; |
4028 | |
4029 | cur->sw.buf.tx.last_seg = 1; |
4030 | |
4031 | /* Interrupt only after specified number of descriptors used. */ |
4032 | if (hw->tx_int_cnt > hw->tx_int_mask) { |
4033 | cur->sw.buf.tx.intr = 1; |
4034 | hw->tx_int_cnt = 0; |
4035 | hw->tx_size = 0; |
4036 | } |
4037 | |
4038 | /* KSZ8842 supports port directed transmission. */ |
4039 | cur->sw.buf.tx.dest_port = hw->dst_ports; |
4040 | |
4041 | release_desc(cur); |
4042 | |
4043 | writel(0, hw->io + KS_DMA_TX_START); |
4044 | } |
4045 | |
4046 | static int empty_addr(u8 *addr) |
4047 | { |
4048 | u32 *addr1 = (u32 *) addr; |
4049 | u16 *addr2 = (u16 *) &addr[4]; |
4050 | |
4051 | return 0 == *addr1 && 0 == *addr2; |
4052 | } |
4053 | |
4054 | /** |
4055 | * hw_set_addr - set MAC address |
4056 | * @hw: The hardware instance. |
4057 | * |
4058 | * This routine programs the MAC address of the hardware when the address is |
4059 | * overrided. |
4060 | */ |
4061 | static void hw_set_addr(struct ksz_hw *hw) |
4062 | { |
4063 | int i; |
4064 | |
4065 | for (i = 0; i < MAC_ADDR_LEN; i++) |
4066 | writeb(hw->override_addr[MAC_ADDR_ORDER(i)], |
4067 | hw->io + KS884X_ADDR_0_OFFSET + i); |
4068 | |
4069 | sw_set_addr(hw, hw->override_addr); |
4070 | } |
4071 | |
4072 | /** |
4073 | * hw_read_addr - read MAC address |
4074 | * @hw: The hardware instance. |
4075 | * |
4076 | * This routine retrieves the MAC address of the hardware. |
4077 | */ |
4078 | static void hw_read_addr(struct ksz_hw *hw) |
4079 | { |
4080 | int i; |
4081 | |
4082 | for (i = 0; i < MAC_ADDR_LEN; i++) |
4083 | hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io + |
4084 | KS884X_ADDR_0_OFFSET + i); |
4085 | |
4086 | if (!hw->mac_override) { |
4087 | memcpy(hw->override_addr, hw->perm_addr, MAC_ADDR_LEN); |
4088 | if (empty_addr(hw->override_addr)) { |
4089 | memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, |
4090 | MAC_ADDR_LEN); |
4091 | memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS, |
4092 | MAC_ADDR_LEN); |
4093 | hw->override_addr[5] += hw->id; |
4094 | hw_set_addr(hw); |
4095 | } |
4096 | } |
4097 | } |
4098 | |
4099 | static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr) |
4100 | { |
4101 | int i; |
4102 | u32 mac_addr_lo; |
4103 | u32 mac_addr_hi; |
4104 | |
4105 | mac_addr_hi = 0; |
4106 | for (i = 0; i < 2; i++) { |
4107 | mac_addr_hi <<= 8; |
4108 | mac_addr_hi |= mac_addr[i]; |
4109 | } |
4110 | mac_addr_hi |= ADD_ADDR_ENABLE; |
4111 | mac_addr_lo = 0; |
4112 | for (i = 2; i < 6; i++) { |
4113 | mac_addr_lo <<= 8; |
4114 | mac_addr_lo |= mac_addr[i]; |
4115 | } |
4116 | index *= ADD_ADDR_INCR; |
4117 | |
4118 | writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO); |
4119 | writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI); |
4120 | } |
4121 | |
4122 | static void hw_set_add_addr(struct ksz_hw *hw) |
4123 | { |
4124 | int i; |
4125 | |
4126 | for (i = 0; i < ADDITIONAL_ENTRIES; i++) { |
4127 | if (empty_addr(hw->address[i])) |
4128 | writel(0, hw->io + ADD_ADDR_INCR * i + |
4129 | KS_ADD_ADDR_0_HI); |
4130 | else |
4131 | hw_ena_add_addr(hw, i, hw->address[i]); |
4132 | } |
4133 | } |
4134 | |
4135 | static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr) |
4136 | { |
4137 | int i; |
4138 | int j = ADDITIONAL_ENTRIES; |
4139 | |
4140 | if (!memcmp(hw->override_addr, mac_addr, MAC_ADDR_LEN)) |
4141 | return 0; |
4142 | for (i = 0; i < hw->addr_list_size; i++) { |
4143 | if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN)) |
4144 | return 0; |
4145 | if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i])) |
4146 | j = i; |
4147 | } |
4148 | if (j < ADDITIONAL_ENTRIES) { |
4149 | memcpy(hw->address[j], mac_addr, MAC_ADDR_LEN); |
4150 | hw_ena_add_addr(hw, j, hw->address[j]); |
4151 | return 0; |
4152 | } |
4153 | return -1; |
4154 | } |
4155 | |
4156 | static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr) |
4157 | { |
4158 | int i; |
4159 | |
4160 | for (i = 0; i < hw->addr_list_size; i++) { |
4161 | if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN)) { |
4162 | memset(hw->address[i], 0, MAC_ADDR_LEN); |
4163 | writel(0, hw->io + ADD_ADDR_INCR * i + |
4164 | KS_ADD_ADDR_0_HI); |
4165 | return 0; |
4166 | } |
4167 | } |
4168 | return -1; |
4169 | } |
4170 | |
4171 | /** |
4172 | * hw_clr_multicast - clear multicast addresses |
4173 | * @hw: The hardware instance. |
4174 | * |
4175 | * This routine removes all multicast addresses set in the hardware. |
4176 | */ |
4177 | static void hw_clr_multicast(struct ksz_hw *hw) |
4178 | { |
4179 | int i; |
4180 | |
4181 | for (i = 0; i < HW_MULTICAST_SIZE; i++) { |
4182 | hw->multi_bits[i] = 0; |
4183 | |
4184 | writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i); |
4185 | } |
4186 | } |
4187 | |
4188 | /** |
4189 | * hw_set_grp_addr - set multicast addresses |
4190 | * @hw: The hardware instance. |
4191 | * |
4192 | * This routine programs multicast addresses for the hardware to accept those |
4193 | * addresses. |
4194 | */ |
4195 | static void hw_set_grp_addr(struct ksz_hw *hw) |
4196 | { |
4197 | int i; |
4198 | int index; |
4199 | int position; |
4200 | int value; |
4201 | |
4202 | memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE); |
4203 | |
4204 | for (i = 0; i < hw->multi_list_size; i++) { |
4205 | position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f; |
4206 | index = position >> 3; |
4207 | value = 1 << (position & 7); |
4208 | hw->multi_bits[index] |= (u8) value; |
4209 | } |
4210 | |
4211 | for (i = 0; i < HW_MULTICAST_SIZE; i++) |
4212 | writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET + |
4213 | i); |
4214 | } |
4215 | |
4216 | /** |
4217 | * hw_set_multicast - enable or disable all multicast receiving |
4218 | * @hw: The hardware instance. |
4219 | * @multicast: To turn on or off the all multicast feature. |
4220 | * |
4221 | * This routine enables/disables the hardware to accept all multicast packets. |
4222 | */ |
4223 | static void hw_set_multicast(struct ksz_hw *hw, u8 multicast) |
4224 | { |
4225 | /* Stop receiving for reconfiguration. */ |
4226 | hw_stop_rx(hw); |
4227 | |
4228 | if (multicast) |
4229 | hw->rx_cfg |= DMA_RX_ALL_MULTICAST; |
4230 | else |
4231 | hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST; |
4232 | |
4233 | if (hw->enabled) |
4234 | hw_start_rx(hw); |
4235 | } |
4236 | |
4237 | /** |
4238 | * hw_set_promiscuous - enable or disable promiscuous receiving |
4239 | * @hw: The hardware instance. |
4240 | * @prom: To turn on or off the promiscuous feature. |
4241 | * |
4242 | * This routine enables/disables the hardware to accept all packets. |
4243 | */ |
4244 | static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom) |
4245 | { |
4246 | /* Stop receiving for reconfiguration. */ |
4247 | hw_stop_rx(hw); |
4248 | |
4249 | if (prom) |
4250 | hw->rx_cfg |= DMA_RX_PROMISCUOUS; |
4251 | else |
4252 | hw->rx_cfg &= ~DMA_RX_PROMISCUOUS; |
4253 | |
4254 | if (hw->enabled) |
4255 | hw_start_rx(hw); |
4256 | } |
4257 | |
4258 | /** |
4259 | * sw_enable - enable the switch |
4260 | * @hw: The hardware instance. |
4261 | * @enable: The flag to enable or disable the switch |
4262 | * |
4263 | * This routine is used to enable/disable the switch in KSZ8842. |
4264 | */ |
4265 | static void sw_enable(struct ksz_hw *hw, int enable) |
4266 | { |
4267 | int port; |
4268 | |
4269 | for (port = 0; port < SWITCH_PORT_NUM; port++) { |
4270 | if (hw->dev_count > 1) { |
4271 | /* Set port-base vlan membership with host port. */ |
4272 | sw_cfg_port_base_vlan(hw, port, |
4273 | HOST_MASK | (1 << port)); |
4274 | port_set_stp_state(hw, port, STP_STATE_DISABLED); |
4275 | } else { |
4276 | sw_cfg_port_base_vlan(hw, port, PORT_MASK); |
4277 | port_set_stp_state(hw, port, STP_STATE_FORWARDING); |
4278 | } |
4279 | } |
4280 | if (hw->dev_count > 1) |
4281 | port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE); |
4282 | else |
4283 | port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING); |
4284 | |
4285 | if (enable) |
4286 | enable = KS8842_START; |
4287 | writew(enable, hw->io + KS884X_CHIP_ID_OFFSET); |
4288 | } |
4289 | |
4290 | /** |
4291 | * sw_setup - setup the switch |
4292 | * @hw: The hardware instance. |
4293 | * |
4294 | * This routine setup the hardware switch engine for default operation. |
4295 | */ |
4296 | static void sw_setup(struct ksz_hw *hw) |
4297 | { |
4298 | int port; |
4299 | |
4300 | sw_set_global_ctrl(hw); |
4301 | |
4302 | /* Enable switch broadcast storm protection at 10% percent rate. */ |
4303 | sw_init_broad_storm(hw); |
4304 | hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE); |
4305 | for (port = 0; port < SWITCH_PORT_NUM; port++) |
4306 | sw_ena_broad_storm(hw, port); |
4307 | |
4308 | sw_init_prio(hw); |
4309 | |
4310 | sw_init_mirror(hw); |
4311 | |
4312 | sw_init_prio_rate(hw); |
4313 | |
4314 | sw_init_vlan(hw); |
4315 | |
4316 | if (hw->features & STP_SUPPORT) |
4317 | sw_init_stp(hw); |
4318 | if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, |
4319 | SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL)) |
4320 | hw->overrides |= PAUSE_FLOW_CTRL; |
4321 | sw_enable(hw, 1); |
4322 | } |
4323 | |
4324 | /** |
4325 | * ksz_start_timer - start kernel timer |
4326 | * @info: Kernel timer information. |
4327 | * @time: The time tick. |
4328 | * |
4329 | * This routine starts the kernel timer after the specified time tick. |
4330 | */ |
4331 | static void ksz_start_timer(struct ksz_timer_info *info, int time) |
4332 | { |
4333 | info->cnt = 0; |
4334 | info->timer.expires = jiffies + time; |
4335 | add_timer(&info->timer); |
4336 | |
4337 | /* infinity */ |
4338 | info->max = -1; |
4339 | } |
4340 | |
4341 | /** |
4342 | * ksz_stop_timer - stop kernel timer |
4343 | * @info: Kernel timer information. |
4344 | * |
4345 | * This routine stops the kernel timer. |
4346 | */ |
4347 | static void ksz_stop_timer(struct ksz_timer_info *info) |
4348 | { |
4349 | if (info->max) { |
4350 | info->max = 0; |
4351 | del_timer_sync(&info->timer); |
4352 | } |
4353 | } |
4354 | |
4355 | static void ksz_init_timer(struct ksz_timer_info *info, int period, |
4356 | void (*function)(unsigned long), void *data) |
4357 | { |
4358 | info->max = 0; |
4359 | info->period = period; |
4360 | init_timer(&info->timer); |
4361 | info->timer.function = function; |
4362 | info->timer.data = (unsigned long) data; |
4363 | } |
4364 | |
4365 | static void ksz_update_timer(struct ksz_timer_info *info) |
4366 | { |
4367 | ++info->cnt; |
4368 | if (info->max > 0) { |
4369 | if (info->cnt < info->max) { |
4370 | info->timer.expires = jiffies + info->period; |
4371 | add_timer(&info->timer); |
4372 | } else |
4373 | info->max = 0; |
4374 | } else if (info->max < 0) { |
4375 | info->timer.expires = jiffies + info->period; |
4376 | add_timer(&info->timer); |
4377 | } |
4378 | } |
4379 | |
4380 | /** |
4381 | * ksz_alloc_soft_desc - allocate software descriptors |
4382 | * @desc_info: Descriptor information structure. |
4383 | * @transmit: Indication that descriptors are for transmit. |
4384 | * |
4385 | * This local function allocates software descriptors for manipulation in |
4386 | * memory. |
4387 | * |
4388 | * Return 0 if successful. |
4389 | */ |
4390 | static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit) |
4391 | { |
4392 | desc_info->ring = kmalloc(sizeof(struct ksz_desc) * desc_info->alloc, |
4393 | GFP_KERNEL); |
4394 | if (!desc_info->ring) |
4395 | return 1; |
4396 | memset((void *) desc_info->ring, 0, |
4397 | sizeof(struct ksz_desc) * desc_info->alloc); |
4398 | hw_init_desc(desc_info, transmit); |
4399 | return 0; |
4400 | } |
4401 | |
4402 | /** |
4403 | * ksz_alloc_desc - allocate hardware descriptors |
4404 | * @adapter: Adapter information structure. |
4405 | * |
4406 | * This local function allocates hardware descriptors for receiving and |
4407 | * transmitting. |
4408 | * |
4409 | * Return 0 if successful. |
4410 | */ |
4411 | static int ksz_alloc_desc(struct dev_info *adapter) |
4412 | { |
4413 | struct ksz_hw *hw = &adapter->hw; |
4414 | int offset; |
4415 | |
4416 | /* Allocate memory for RX & TX descriptors. */ |
4417 | adapter->desc_pool.alloc_size = |
4418 | hw->rx_desc_info.size * hw->rx_desc_info.alloc + |
4419 | hw->tx_desc_info.size * hw->tx_desc_info.alloc + |
4420 | DESC_ALIGNMENT; |
4421 | |
4422 | adapter->desc_pool.alloc_virt = |
4423 | pci_alloc_consistent( |
4424 | adapter->pdev, adapter->desc_pool.alloc_size, |
4425 | &adapter->desc_pool.dma_addr); |
4426 | if (adapter->desc_pool.alloc_virt == NULL) { |
4427 | adapter->desc_pool.alloc_size = 0; |
4428 | return 1; |
4429 | } |
4430 | memset(adapter->desc_pool.alloc_virt, 0, adapter->desc_pool.alloc_size); |
4431 | |
4432 | /* Align to the next cache line boundary. */ |
4433 | offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ? |
4434 | (DESC_ALIGNMENT - |
4435 | ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0); |
4436 | adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset; |
4437 | adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset; |
4438 | |
4439 | /* Allocate receive/transmit descriptors. */ |
4440 | hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *) |
4441 | adapter->desc_pool.virt; |
4442 | hw->rx_desc_info.ring_phys = adapter->desc_pool.phys; |
4443 | offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size; |
4444 | hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *) |
4445 | (adapter->desc_pool.virt + offset); |
4446 | hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset; |
4447 | |
4448 | if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0)) |
4449 | return 1; |
4450 | if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1)) |
4451 | return 1; |
4452 | |
4453 | return 0; |
4454 | } |
4455 | |
4456 | /** |
4457 | * free_dma_buf - release DMA buffer resources |
4458 | * @adapter: Adapter information structure. |
4459 | * |
4460 | * This routine is just a helper function to release the DMA buffer resources. |
4461 | */ |
4462 | static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf, |
4463 | int direction) |
4464 | { |
4465 | pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction); |
4466 | dev_kfree_skb(dma_buf->skb); |
4467 | dma_buf->skb = NULL; |
4468 | dma_buf->dma = 0; |
4469 | } |
4470 | |
4471 | /** |
4472 | * ksz_init_rx_buffers - initialize receive descriptors |
4473 | * @adapter: Adapter information structure. |
4474 | * |
4475 | * This routine initializes DMA buffers for receiving. |
4476 | */ |
4477 | static void ksz_init_rx_buffers(struct dev_info *adapter) |
4478 | { |
4479 | int i; |
4480 | struct ksz_desc *desc; |
4481 | struct ksz_dma_buf *dma_buf; |
4482 | struct ksz_hw *hw = &adapter->hw; |
4483 | struct ksz_desc_info *info = &hw->rx_desc_info; |
4484 | |
4485 | for (i = 0; i < hw->rx_desc_info.alloc; i++) { |
4486 | get_rx_pkt(info, &desc); |
4487 | |
4488 | dma_buf = DMA_BUFFER(desc); |
4489 | if (dma_buf->skb && dma_buf->len != adapter->mtu) |
4490 | free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE); |
4491 | dma_buf->len = adapter->mtu; |
4492 | if (!dma_buf->skb) |
4493 | dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC); |
4494 | if (dma_buf->skb && !dma_buf->dma) { |
4495 | dma_buf->skb->dev = adapter->dev; |
4496 | dma_buf->dma = pci_map_single( |
4497 | adapter->pdev, |
4498 | skb_tail_pointer(dma_buf->skb), |
4499 | dma_buf->len, |
4500 | PCI_DMA_FROMDEVICE); |
4501 | } |
4502 | |
4503 | /* Set descriptor. */ |
4504 | set_rx_buf(desc, dma_buf->dma); |
4505 | set_rx_len(desc, dma_buf->len); |
4506 | release_desc(desc); |
4507 | } |
4508 | } |
4509 | |
4510 | /** |
4511 | * ksz_alloc_mem - allocate memory for hardware descriptors |
4512 | * @adapter: Adapter information structure. |
4513 | * |
4514 | * This function allocates memory for use by hardware descriptors for receiving |
4515 | * and transmitting. |
4516 | * |
4517 | * Return 0 if successful. |
4518 | */ |
4519 | static int ksz_alloc_mem(struct dev_info *adapter) |
4520 | { |
4521 | struct ksz_hw *hw = &adapter->hw; |
4522 | |
4523 | /* Determine the number of receive and transmit descriptors. */ |
4524 | hw->rx_desc_info.alloc = NUM_OF_RX_DESC; |
4525 | hw->tx_desc_info.alloc = NUM_OF_TX_DESC; |
4526 | |
4527 | /* Determine how many descriptors to skip transmit interrupt. */ |
4528 | hw->tx_int_cnt = 0; |
4529 | hw->tx_int_mask = NUM_OF_TX_DESC / 4; |
4530 | if (hw->tx_int_mask > 8) |
4531 | hw->tx_int_mask = 8; |
4532 | while (hw->tx_int_mask) { |
4533 | hw->tx_int_cnt++; |
4534 | hw->tx_int_mask >>= 1; |
4535 | } |
4536 | if (hw->tx_int_cnt) { |
4537 | hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1; |
4538 | hw->tx_int_cnt = 0; |
4539 | } |
4540 | |
4541 | /* Determine the descriptor size. */ |
4542 | hw->rx_desc_info.size = |
4543 | (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) / |
4544 | DESC_ALIGNMENT) * DESC_ALIGNMENT); |
4545 | hw->tx_desc_info.size = |
4546 | (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) / |
4547 | DESC_ALIGNMENT) * DESC_ALIGNMENT); |
4548 | if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc)) |
4549 | printk(KERN_ALERT |
4550 | "Hardware descriptor size not right!\n"); |
4551 | ksz_check_desc_num(&hw->rx_desc_info); |
4552 | ksz_check_desc_num(&hw->tx_desc_info); |
4553 | |
4554 | /* Allocate descriptors. */ |
4555 | if (ksz_alloc_desc(adapter)) |
4556 | return 1; |
4557 | |
4558 | return 0; |
4559 | } |
4560 | |
4561 | /** |
4562 | * ksz_free_desc - free software and hardware descriptors |
4563 | * @adapter: Adapter information structure. |
4564 | * |
4565 | * This local routine frees the software and hardware descriptors allocated by |
4566 | * ksz_alloc_desc(). |
4567 | */ |
4568 | static void ksz_free_desc(struct dev_info *adapter) |
4569 | { |
4570 | struct ksz_hw *hw = &adapter->hw; |
4571 | |
4572 | /* Reset descriptor. */ |
4573 | hw->rx_desc_info.ring_virt = NULL; |
4574 | hw->tx_desc_info.ring_virt = NULL; |
4575 | hw->rx_desc_info.ring_phys = 0; |
4576 | hw->tx_desc_info.ring_phys = 0; |
4577 | |
4578 | /* Free memory. */ |
4579 | if (adapter->desc_pool.alloc_virt) |
4580 | pci_free_consistent( |
4581 | adapter->pdev, |
4582 | adapter->desc_pool.alloc_size, |
4583 | adapter->desc_pool.alloc_virt, |
4584 | adapter->desc_pool.dma_addr); |
4585 | |
4586 | /* Reset resource pool. */ |
4587 | adapter->desc_pool.alloc_size = 0; |
4588 | adapter->desc_pool.alloc_virt = NULL; |
4589 | |
4590 | kfree(hw->rx_desc_info.ring); |
4591 | hw->rx_desc_info.ring = NULL; |
4592 | kfree(hw->tx_desc_info.ring); |
4593 | hw->tx_desc_info.ring = NULL; |
4594 | } |
4595 | |
4596 | /** |
4597 | * ksz_free_buffers - free buffers used in the descriptors |
4598 | * @adapter: Adapter information structure. |
4599 | * @desc_info: Descriptor information structure. |
4600 | * |
4601 | * This local routine frees buffers used in the DMA buffers. |
4602 | */ |
4603 | static void ksz_free_buffers(struct dev_info *adapter, |
4604 | struct ksz_desc_info *desc_info, int direction) |
4605 | { |
4606 | int i; |
4607 | struct ksz_dma_buf *dma_buf; |
4608 | struct ksz_desc *desc = desc_info->ring; |
4609 | |
4610 | for (i = 0; i < desc_info->alloc; i++) { |
4611 | dma_buf = DMA_BUFFER(desc); |
4612 | if (dma_buf->skb) |
4613 | free_dma_buf(adapter, dma_buf, direction); |
4614 | desc++; |
4615 | } |
4616 | } |
4617 | |
4618 | /** |
4619 | * ksz_free_mem - free all resources used by descriptors |
4620 | * @adapter: Adapter information structure. |
4621 | * |
4622 | * This local routine frees all the resources allocated by ksz_alloc_mem(). |
4623 | */ |
4624 | static void ksz_free_mem(struct dev_info *adapter) |
4625 | { |
4626 | /* Free transmit buffers. */ |
4627 | ksz_free_buffers(adapter, &adapter->hw.tx_desc_info, |
4628 | PCI_DMA_TODEVICE); |
4629 | |
4630 | /* Free receive buffers. */ |
4631 | ksz_free_buffers(adapter, &adapter->hw.rx_desc_info, |
4632 | PCI_DMA_FROMDEVICE); |
4633 | |
4634 | /* Free descriptors. */ |
4635 | ksz_free_desc(adapter); |
4636 | } |
4637 | |
4638 | static void get_mib_counters(struct ksz_hw *hw, int first, int cnt, |
4639 | u64 *counter) |
4640 | { |
4641 | int i; |
4642 | int mib; |
4643 | int port; |
4644 | struct ksz_port_mib *port_mib; |
4645 | |
4646 | memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); |
4647 | for (i = 0, port = first; i < cnt; i++, port++) { |
4648 | port_mib = &hw->port_mib[port]; |
4649 | for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++) |
4650 | counter[mib] += port_mib->counter[mib]; |
4651 | } |
4652 | } |
4653 | |
4654 | /** |
4655 | * send_packet - send packet |
4656 | * @skb: Socket buffer. |
4657 | * @dev: Network device. |
4658 | * |
4659 | * This routine is used to send a packet out to the network. |
4660 | */ |
4661 | static void send_packet(struct sk_buff *skb, struct net_device *dev) |
4662 | { |
4663 | struct ksz_desc *desc; |
4664 | struct ksz_desc *first; |
4665 | struct dev_priv *priv = netdev_priv(dev); |
4666 | struct dev_info *hw_priv = priv->adapter; |
4667 | struct ksz_hw *hw = &hw_priv->hw; |
4668 | struct ksz_desc_info *info = &hw->tx_desc_info; |
4669 | struct ksz_dma_buf *dma_buf; |
4670 | int len; |
4671 | int last_frag = skb_shinfo(skb)->nr_frags; |
4672 | |
4673 | /* |
4674 | * KSZ8842 with multiple device interfaces needs to be told which port |
4675 | * to send. |
4676 | */ |
4677 | if (hw->dev_count > 1) |
4678 | hw->dst_ports = 1 << priv->port.first_port; |
4679 | |
4680 | /* Hardware will pad the length to 60. */ |
4681 | len = skb->len; |
4682 | |
4683 | /* Remember the very first descriptor. */ |
4684 | first = info->cur; |
4685 | desc = first; |
4686 | |
4687 | dma_buf = DMA_BUFFER(desc); |
4688 | if (last_frag) { |
4689 | int frag; |
4690 | skb_frag_t *this_frag; |
4691 | |
4692 | dma_buf->len = skb->len - skb->data_len; |
4693 | |
4694 | dma_buf->dma = pci_map_single( |
4695 | hw_priv->pdev, skb->data, dma_buf->len, |
4696 | PCI_DMA_TODEVICE); |
4697 | set_tx_buf(desc, dma_buf->dma); |
4698 | set_tx_len(desc, dma_buf->len); |
4699 | |
4700 | frag = 0; |
4701 | do { |
4702 | this_frag = &skb_shinfo(skb)->frags[frag]; |
4703 | |
4704 | /* Get a new descriptor. */ |
4705 | get_tx_pkt(info, &desc); |
4706 | |
4707 | /* Keep track of descriptors used so far. */ |
4708 | ++hw->tx_int_cnt; |
4709 | |
4710 | dma_buf = DMA_BUFFER(desc); |
4711 | dma_buf->len = this_frag->size; |
4712 | |
4713 | dma_buf->dma = pci_map_single( |
4714 | hw_priv->pdev, |
4715 | page_address(this_frag->page) + |
4716 | this_frag->page_offset, |
4717 | dma_buf->len, |
4718 | PCI_DMA_TODEVICE); |
4719 | set_tx_buf(desc, dma_buf->dma); |
4720 | set_tx_len(desc, dma_buf->len); |
4721 | |
4722 | frag++; |
4723 | if (frag == last_frag) |
4724 | break; |
4725 | |
4726 | /* Do not release the last descriptor here. */ |
4727 | release_desc(desc); |
4728 | } while (1); |
4729 | |
4730 | /* current points to the last descriptor. */ |
4731 | info->cur = desc; |
4732 | |
4733 | /* Release the first descriptor. */ |
4734 | release_desc(first); |
4735 | } else { |
4736 | dma_buf->len = len; |
4737 | |
4738 | dma_buf->dma = pci_map_single( |
4739 | hw_priv->pdev, skb->data, dma_buf->len, |
4740 | PCI_DMA_TODEVICE); |
4741 | set_tx_buf(desc, dma_buf->dma); |
4742 | set_tx_len(desc, dma_buf->len); |
4743 | } |
4744 | |
4745 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
4746 | (desc)->sw.buf.tx.csum_gen_tcp = 1; |
4747 | (desc)->sw.buf.tx.csum_gen_udp = 1; |
4748 | } |
4749 | |
4750 | /* |
4751 | * The last descriptor holds the packet so that it can be returned to |
4752 | * network subsystem after all descriptors are transmitted. |
4753 | */ |
4754 | dma_buf->skb = skb; |
4755 | |
4756 | hw_send_pkt(hw); |
4757 | |
4758 | /* Update transmit statistics. */ |
4759 | priv->stats.tx_packets++; |
4760 | priv->stats.tx_bytes += len; |
4761 | } |
4762 | |
4763 | /** |
4764 | * transmit_cleanup - clean up transmit descriptors |
4765 | * @dev: Network device. |
4766 | * |
4767 | * This routine is called to clean up the transmitted buffers. |
4768 | */ |
4769 | static void transmit_cleanup(struct dev_info *hw_priv, int normal) |
4770 | { |
4771 | int last; |
4772 | union desc_stat status; |
4773 | struct ksz_hw *hw = &hw_priv->hw; |
4774 | struct ksz_desc_info *info = &hw->tx_desc_info; |
4775 | struct ksz_desc *desc; |
4776 | struct ksz_dma_buf *dma_buf; |
4777 | struct net_device *dev = NULL; |
4778 | |
4779 | spin_lock(&hw_priv->hwlock); |
4780 | last = info->last; |
4781 | |
4782 | while (info->avail < info->alloc) { |
4783 | /* Get next descriptor which is not hardware owned. */ |
4784 | desc = &info->ring[last]; |
4785 | status.data = le32_to_cpu(desc->phw->ctrl.data); |
4786 | if (status.tx.hw_owned) { |
4787 | if (normal) |
4788 | break; |
4789 | else |
4790 | reset_desc(desc, status); |
4791 | } |
4792 | |
4793 | dma_buf = DMA_BUFFER(desc); |
4794 | pci_unmap_single( |
4795 | hw_priv->pdev, dma_buf->dma, dma_buf->len, |
4796 | PCI_DMA_TODEVICE); |
4797 | |
4798 | /* This descriptor contains the last buffer in the packet. */ |
4799 | if (dma_buf->skb) { |
4800 | dev = dma_buf->skb->dev; |
4801 | |
4802 | /* Release the packet back to network subsystem. */ |
4803 | dev_kfree_skb_irq(dma_buf->skb); |
4804 | dma_buf->skb = NULL; |
4805 | } |
4806 | |
4807 | /* Free the transmitted descriptor. */ |
4808 | last++; |
4809 | last &= info->mask; |
4810 | info->avail++; |
4811 | } |
4812 | info->last = last; |
4813 | spin_unlock(&hw_priv->hwlock); |
4814 | |
4815 | /* Notify the network subsystem that the packet has been sent. */ |
4816 | if (dev) |
4817 | dev->trans_start = jiffies; |
4818 | } |
4819 | |
4820 | /** |
4821 | * transmit_done - transmit done processing |
4822 | * @dev: Network device. |
4823 | * |
4824 | * This routine is called when the transmit interrupt is triggered, indicating |
4825 | * either a packet is sent successfully or there are transmit errors. |
4826 | */ |
4827 | static void tx_done(struct dev_info *hw_priv) |
4828 | { |
4829 | struct ksz_hw *hw = &hw_priv->hw; |
4830 | int port; |
4831 | |
4832 | transmit_cleanup(hw_priv, 1); |
4833 | |
4834 | for (port = 0; port < hw->dev_count; port++) { |
4835 | struct net_device *dev = hw->port_info[port].pdev; |
4836 | |
4837 | if (netif_running(dev) && netif_queue_stopped(dev)) |
4838 | netif_wake_queue(dev); |
4839 | } |
4840 | } |
4841 | |
4842 | static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb) |
4843 | { |
4844 | skb->dev = old->dev; |
4845 | skb->protocol = old->protocol; |
4846 | skb->ip_summed = old->ip_summed; |
4847 | skb->csum = old->csum; |
4848 | skb_set_network_header(skb, ETH_HLEN); |
4849 | |
4850 | dev_kfree_skb(old); |
4851 | } |
4852 | |
4853 | /** |
4854 | * netdev_tx - send out packet |
4855 | * @skb: Socket buffer. |
4856 | * @dev: Network device. |
4857 | * |
4858 | * This function is used by the upper network layer to send out a packet. |
4859 | * |
4860 | * Return 0 if successful; otherwise an error code indicating failure. |
4861 | */ |
4862 | static int netdev_tx(struct sk_buff *skb, struct net_device *dev) |
4863 | { |
4864 | struct dev_priv *priv = netdev_priv(dev); |
4865 | struct dev_info *hw_priv = priv->adapter; |
4866 | struct ksz_hw *hw = &hw_priv->hw; |
4867 | int left; |
4868 | int num = 1; |
4869 | int rc = 0; |
4870 | |
4871 | if (hw->features & SMALL_PACKET_TX_BUG) { |
4872 | struct sk_buff *org_skb = skb; |
4873 | |
4874 | if (skb->len <= 48) { |
4875 | if (skb_end_pointer(skb) - skb->data >= 50) { |
4876 | memset(&skb->data[skb->len], 0, 50 - skb->len); |
4877 | skb->len = 50; |
4878 | } else { |
4879 | skb = dev_alloc_skb(50); |
4880 | if (!skb) |
4881 | return NETDEV_TX_BUSY; |
4882 | memcpy(skb->data, org_skb->data, org_skb->len); |
4883 | memset(&skb->data[org_skb->len], 0, |
4884 | 50 - org_skb->len); |
4885 | skb->len = 50; |
4886 | copy_old_skb(org_skb, skb); |
4887 | } |
4888 | } |
4889 | } |
4890 | |
4891 | spin_lock_irq(&hw_priv->hwlock); |
4892 | |
4893 | num = skb_shinfo(skb)->nr_frags + 1; |
4894 | left = hw_alloc_pkt(hw, skb->len, num); |
4895 | if (left) { |
4896 | if (left < num || |
4897 | ((hw->features & IPV6_CSUM_GEN_HACK) && |
4898 | (CHECKSUM_PARTIAL == skb->ip_summed) && |
4899 | (ETH_P_IPV6 == htons(skb->protocol)))) { |
4900 | struct sk_buff *org_skb = skb; |
4901 | |
4902 | skb = dev_alloc_skb(org_skb->len); |
4903 | if (!skb) { |
4904 | rc = NETDEV_TX_BUSY; |
4905 | goto unlock; |
4906 | } |
4907 | skb_copy_and_csum_dev(org_skb, skb->data); |
4908 | org_skb->ip_summed = 0; |
4909 | skb->len = org_skb->len; |
4910 | copy_old_skb(org_skb, skb); |
4911 | } |
4912 | send_packet(skb, dev); |
4913 | if (left <= num) |
4914 | netif_stop_queue(dev); |
4915 | } else { |
4916 | /* Stop the transmit queue until packet is allocated. */ |
4917 | netif_stop_queue(dev); |
4918 | rc = NETDEV_TX_BUSY; |
4919 | } |
4920 | unlock: |
4921 | spin_unlock_irq(&hw_priv->hwlock); |
4922 | |
4923 | return rc; |
4924 | } |
4925 | |
4926 | /** |
4927 | * netdev_tx_timeout - transmit timeout processing |
4928 | * @dev: Network device. |
4929 | * |
4930 | * This routine is called when the transmit timer expires. That indicates the |
4931 | * hardware is not running correctly because transmit interrupts are not |
4932 | * triggered to free up resources so that the transmit routine can continue |
4933 | * sending out packets. The hardware is reset to correct the problem. |
4934 | */ |
4935 | static void netdev_tx_timeout(struct net_device *dev) |
4936 | { |
4937 | static unsigned long last_reset; |
4938 | |
4939 | struct dev_priv *priv = netdev_priv(dev); |
4940 | struct dev_info *hw_priv = priv->adapter; |
4941 | struct ksz_hw *hw = &hw_priv->hw; |
4942 | int port; |
4943 | |
4944 | if (hw->dev_count > 1) { |
4945 | /* |
4946 | * Only reset the hardware if time between calls is long |
4947 | * enough. |
4948 | */ |
4949 | if (jiffies - last_reset <= dev->watchdog_timeo) |
4950 | hw_priv = NULL; |
4951 | } |
4952 | |
4953 | last_reset = jiffies; |
4954 | if (hw_priv) { |
4955 | hw_dis_intr(hw); |
4956 | hw_disable(hw); |
4957 | |
4958 | transmit_cleanup(hw_priv, 0); |
4959 | hw_reset_pkts(&hw->rx_desc_info); |
4960 | hw_reset_pkts(&hw->tx_desc_info); |
4961 | ksz_init_rx_buffers(hw_priv); |
4962 | |
4963 | hw_reset(hw); |
4964 | |
4965 | hw_set_desc_base(hw, |
4966 | hw->tx_desc_info.ring_phys, |
4967 | hw->rx_desc_info.ring_phys); |
4968 | hw_set_addr(hw); |
4969 | if (hw->all_multi) |
4970 | hw_set_multicast(hw, hw->all_multi); |
4971 | else if (hw->multi_list_size) |
4972 | hw_set_grp_addr(hw); |
4973 | |
4974 | if (hw->dev_count > 1) { |
4975 | hw_set_add_addr(hw); |
4976 | for (port = 0; port < SWITCH_PORT_NUM; port++) { |
4977 | struct net_device *port_dev; |
4978 | |
4979 | port_set_stp_state(hw, port, |
4980 | STP_STATE_DISABLED); |
4981 | |
4982 | port_dev = hw->port_info[port].pdev; |
4983 | if (netif_running(port_dev)) |
4984 | port_set_stp_state(hw, port, |
4985 | STP_STATE_SIMPLE); |
4986 | } |
4987 | } |
4988 | |
4989 | hw_enable(hw); |
4990 | hw_ena_intr(hw); |
4991 | } |
4992 | |
4993 | dev->trans_start = jiffies; |
4994 | netif_wake_queue(dev); |
4995 | } |
4996 | |
4997 | static inline void csum_verified(struct sk_buff *skb) |
4998 | { |
4999 | unsigned short protocol; |
5000 | struct iphdr *iph; |
5001 | |
5002 | protocol = skb->protocol; |
5003 | skb_reset_network_header(skb); |
5004 | iph = (struct iphdr *) skb_network_header(skb); |
5005 | if (protocol == htons(ETH_P_8021Q)) { |
5006 | protocol = iph->tot_len; |
5007 | skb_set_network_header(skb, VLAN_HLEN); |
5008 | iph = (struct iphdr *) skb_network_header(skb); |
5009 | } |
5010 | if (protocol == htons(ETH_P_IP)) { |
5011 | if (iph->protocol == IPPROTO_TCP) |
5012 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
5013 | } |
5014 | } |
5015 | |
5016 | static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw, |
5017 | struct ksz_desc *desc, union desc_stat status) |
5018 | { |
5019 | int packet_len; |
5020 | struct dev_priv *priv = netdev_priv(dev); |
5021 | struct dev_info *hw_priv = priv->adapter; |
5022 | struct ksz_dma_buf *dma_buf; |
5023 | struct sk_buff *skb; |
5024 | int rx_status; |
5025 | |
5026 | /* Received length includes 4-byte CRC. */ |
5027 | packet_len = status.rx.frame_len - 4; |
5028 | |
5029 | dma_buf = DMA_BUFFER(desc); |
5030 | pci_dma_sync_single_for_cpu( |
5031 | hw_priv->pdev, dma_buf->dma, packet_len + 4, |
5032 | PCI_DMA_FROMDEVICE); |
5033 | |
5034 | do { |
5035 | /* skb->data != skb->head */ |
5036 | skb = dev_alloc_skb(packet_len + 2); |
5037 | if (!skb) { |
5038 | priv->stats.rx_dropped++; |
5039 | return -ENOMEM; |
5040 | } |
5041 | |
5042 | /* |
5043 | * Align socket buffer in 4-byte boundary for better |
5044 | * performance. |
5045 | */ |
5046 | skb_reserve(skb, 2); |
5047 | |
5048 | memcpy(skb_put(skb, packet_len), |
5049 | dma_buf->skb->data, packet_len); |
5050 | } while (0); |
5051 | |
5052 | skb->dev = dev; |
5053 | |
5054 | skb->protocol = eth_type_trans(skb, dev); |
5055 | |
5056 | if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP)) |
5057 | csum_verified(skb); |
5058 | |
5059 | /* Update receive statistics. */ |
5060 | priv->stats.rx_packets++; |
5061 | priv->stats.rx_bytes += packet_len; |
5062 | |
5063 | /* Notify upper layer for received packet. */ |
5064 | dev->last_rx = jiffies; |
5065 | |
5066 | rx_status = netif_rx(skb); |
5067 | |
5068 | return 0; |
5069 | } |
5070 | |
5071 | static int dev_rcv_packets(struct dev_info *hw_priv) |
5072 | { |
5073 | int next; |
5074 | union desc_stat status; |
5075 | struct ksz_hw *hw = &hw_priv->hw; |
5076 | struct net_device *dev = hw->port_info[0].pdev; |
5077 | struct ksz_desc_info *info = &hw->rx_desc_info; |
5078 | int left = info->alloc; |
5079 | struct ksz_desc *desc; |
5080 | int received = 0; |
5081 | |
5082 | next = info->next; |
5083 | while (left--) { |
5084 | /* Get next descriptor which is not hardware owned. */ |
5085 | desc = &info->ring[next]; |
5086 | status.data = le32_to_cpu(desc->phw->ctrl.data); |
5087 | if (status.rx.hw_owned) |
5088 | break; |
5089 | |
5090 | /* Status valid only when last descriptor bit is set. */ |
5091 | if (status.rx.last_desc && status.rx.first_desc) { |
5092 | if (rx_proc(dev, hw, desc, status)) |
5093 | goto release_packet; |
5094 | received++; |
5095 | } |
5096 | |
5097 | release_packet: |
5098 | release_desc(desc); |
5099 | next++; |
5100 | next &= info->mask; |
5101 | } |
5102 | info->next = next; |
5103 | |
5104 | return received; |
5105 | } |
5106 | |
5107 | static int port_rcv_packets(struct dev_info *hw_priv) |
5108 | { |
5109 | int next; |
5110 | union desc_stat status; |
5111 | struct ksz_hw *hw = &hw_priv->hw; |
5112 | struct net_device *dev = hw->port_info[0].pdev; |
5113 | struct ksz_desc_info *info = &hw->rx_desc_info; |
5114 | int left = info->alloc; |
5115 | struct ksz_desc *desc; |
5116 | int received = 0; |
5117 | |
5118 | next = info->next; |
5119 | while (left--) { |
5120 | /* Get next descriptor which is not hardware owned. */ |
5121 | desc = &info->ring[next]; |
5122 | status.data = le32_to_cpu(desc->phw->ctrl.data); |
5123 | if (status.rx.hw_owned) |
5124 | break; |
5125 | |
5126 | if (hw->dev_count > 1) { |
5127 | /* Get received port number. */ |
5128 | int p = HW_TO_DEV_PORT(status.rx.src_port); |
5129 | |
5130 | dev = hw->port_info[p].pdev; |
5131 | if (!netif_running(dev)) |
5132 | goto release_packet; |
5133 | } |
5134 | |
5135 | /* Status valid only when last descriptor bit is set. */ |
5136 | if (status.rx.last_desc && status.rx.first_desc) { |
5137 | if (rx_proc(dev, hw, desc, status)) |
5138 | goto release_packet; |
5139 | received++; |
5140 | } |
5141 | |
5142 | release_packet: |
5143 | release_desc(desc); |
5144 | next++; |
5145 | next &= info->mask; |
5146 | } |
5147 | info->next = next; |
5148 | |
5149 | return received; |
5150 | } |
5151 | |
5152 | static int dev_rcv_special(struct dev_info *hw_priv) |
5153 | { |
5154 | int next; |
5155 | union desc_stat status; |
5156 | struct ksz_hw *hw = &hw_priv->hw; |
5157 | struct net_device *dev = hw->port_info[0].pdev; |
5158 | struct ksz_desc_info *info = &hw->rx_desc_info; |
5159 | int left = info->alloc; |
5160 | struct ksz_desc *desc; |
5161 | int received = 0; |
5162 | |
5163 | next = info->next; |
5164 | while (left--) { |
5165 | /* Get next descriptor which is not hardware owned. */ |
5166 | desc = &info->ring[next]; |
5167 | status.data = le32_to_cpu(desc->phw->ctrl.data); |
5168 | if (status.rx.hw_owned) |
5169 | break; |
5170 | |
5171 | if (hw->dev_count > 1) { |
5172 | /* Get received port number. */ |
5173 | int p = HW_TO_DEV_PORT(status.rx.src_port); |
5174 | |
5175 | dev = hw->port_info[p].pdev; |
5176 | if (!netif_running(dev)) |
5177 | goto release_packet; |
5178 | } |
5179 | |
5180 | /* Status valid only when last descriptor bit is set. */ |
5181 | if (status.rx.last_desc && status.rx.first_desc) { |
5182 | /* |
5183 | * Receive without error. With receive errors |
5184 | * disabled, packets with receive errors will be |
5185 | * dropped, so no need to check the error bit. |
5186 | */ |
5187 | if (!status.rx.error || (status.data & |
5188 | KS_DESC_RX_ERROR_COND) == |
5189 | KS_DESC_RX_ERROR_TOO_LONG) { |
5190 | if (rx_proc(dev, hw, desc, status)) |
5191 | goto release_packet; |
5192 | received++; |
5193 | } else { |
5194 | struct dev_priv *priv = netdev_priv(dev); |
5195 | |
5196 | /* Update receive error statistics. */ |
5197 | priv->port.counter[OID_COUNTER_RCV_ERROR]++; |
5198 | } |
5199 | } |
5200 | |
5201 | release_packet: |
5202 | release_desc(desc); |
5203 | next++; |
5204 | next &= info->mask; |
5205 | } |
5206 | info->next = next; |
5207 | |
5208 | return received; |
5209 | } |
5210 | |
5211 | static void rx_proc_task(unsigned long data) |
5212 | { |
5213 | struct dev_info *hw_priv = (struct dev_info *) data; |
5214 | struct ksz_hw *hw = &hw_priv->hw; |
5215 | |
5216 | if (!hw->enabled) |
5217 | return; |
5218 | if (unlikely(!hw_priv->dev_rcv(hw_priv))) { |
5219 | |
5220 | /* In case receive process is suspended because of overrun. */ |
5221 | hw_resume_rx(hw); |
5222 | |
5223 | /* tasklets are interruptible. */ |
5224 | spin_lock_irq(&hw_priv->hwlock); |
5225 | hw_turn_on_intr(hw, KS884X_INT_RX_MASK); |
5226 | spin_unlock_irq(&hw_priv->hwlock); |
5227 | } else { |
5228 | hw_ack_intr(hw, KS884X_INT_RX); |
5229 | tasklet_schedule(&hw_priv->rx_tasklet); |
5230 | } |
5231 | } |
5232 | |
5233 | static void tx_proc_task(unsigned long data) |
5234 | { |
5235 | struct dev_info *hw_priv = (struct dev_info *) data; |
5236 | struct ksz_hw *hw = &hw_priv->hw; |
5237 | |
5238 | hw_ack_intr(hw, KS884X_INT_TX_MASK); |
5239 | |
5240 | tx_done(hw_priv); |
5241 | |
5242 | /* tasklets are interruptible. */ |
5243 | spin_lock_irq(&hw_priv->hwlock); |
5244 | hw_turn_on_intr(hw, KS884X_INT_TX); |
5245 | spin_unlock_irq(&hw_priv->hwlock); |
5246 | } |
5247 | |
5248 | static inline void handle_rx_stop(struct ksz_hw *hw) |
5249 | { |
5250 | /* Receive just has been stopped. */ |
5251 | if (0 == hw->rx_stop) |
5252 | hw->intr_mask &= ~KS884X_INT_RX_STOPPED; |
5253 | else if (hw->rx_stop > 1) { |
5254 | if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) { |
5255 | hw_start_rx(hw); |
5256 | } else { |
5257 | hw->intr_mask &= ~KS884X_INT_RX_STOPPED; |
5258 | hw->rx_stop = 0; |
5259 | } |
5260 | } else |
5261 | /* Receive just has been started. */ |
5262 | hw->rx_stop++; |
5263 | } |
5264 | |
5265 | /** |
5266 | * netdev_intr - interrupt handling |
5267 | * @irq: Interrupt number. |
5268 | * @dev_id: Network device. |
5269 | * |
5270 | * This function is called by upper network layer to signal interrupt. |
5271 | * |
5272 | * Return IRQ_HANDLED if interrupt is handled. |
5273 | */ |
5274 | static irqreturn_t netdev_intr(int irq, void *dev_id) |
5275 | { |
5276 | uint int_enable = 0; |
5277 | struct net_device *dev = (struct net_device *) dev_id; |
5278 | struct dev_priv *priv = netdev_priv(dev); |
5279 | struct dev_info *hw_priv = priv->adapter; |
5280 | struct ksz_hw *hw = &hw_priv->hw; |
5281 | |
5282 | hw_read_intr(hw, &int_enable); |
5283 | |
5284 | /* Not our interrupt! */ |
5285 | if (!int_enable) |
5286 | return IRQ_NONE; |
5287 | |
5288 | do { |
5289 | hw_ack_intr(hw, int_enable); |
5290 | int_enable &= hw->intr_mask; |
5291 | |
5292 | if (unlikely(int_enable & KS884X_INT_TX_MASK)) { |
5293 | hw_dis_intr_bit(hw, KS884X_INT_TX_MASK); |
5294 | tasklet_schedule(&hw_priv->tx_tasklet); |
5295 | } |
5296 | |
5297 | if (likely(int_enable & KS884X_INT_RX)) { |
5298 | hw_dis_intr_bit(hw, KS884X_INT_RX); |
5299 | tasklet_schedule(&hw_priv->rx_tasklet); |
5300 | } |
5301 | |
5302 | if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) { |
5303 | priv->stats.rx_fifo_errors++; |
5304 | hw_resume_rx(hw); |
5305 | } |
5306 | |
5307 | if (unlikely(int_enable & KS884X_INT_PHY)) { |
5308 | struct ksz_port *port = &priv->port; |
5309 | |
5310 | hw->features |= LINK_INT_WORKING; |
5311 | port_get_link_speed(port); |
5312 | } |
5313 | |
5314 | if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) { |
5315 | handle_rx_stop(hw); |
5316 | break; |
5317 | } |
5318 | |
5319 | if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) { |
5320 | u32 data; |
5321 | |
5322 | hw->intr_mask &= ~KS884X_INT_TX_STOPPED; |
5323 | printk(KERN_INFO "Tx stopped\n"); |
5324 | data = readl(hw->io + KS_DMA_TX_CTRL); |
5325 | if (!(data & DMA_TX_ENABLE)) |
5326 | printk(KERN_INFO "Tx disabled\n"); |
5327 | break; |
5328 | } |
5329 | } while (0); |
5330 | |
5331 | hw_ena_intr(hw); |
5332 | |
5333 | return IRQ_HANDLED; |
5334 | } |
5335 | |
5336 | /* |
5337 | * Linux network device functions |
5338 | */ |
5339 | |
5340 | static unsigned long next_jiffies; |
5341 | |
5342 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5343 | static void netdev_netpoll(struct net_device *dev) |
5344 | { |
5345 | struct dev_priv *priv = netdev_priv(dev); |
5346 | struct dev_info *hw_priv = priv->adapter; |
5347 | |
5348 | hw_dis_intr(&hw_priv->hw); |
5349 | netdev_intr(dev->irq, dev); |
5350 | } |
5351 | #endif |
5352 | |
5353 | static void bridge_change(struct ksz_hw *hw) |
5354 | { |
5355 | int port; |
5356 | u8 member; |
5357 | struct ksz_switch *sw = hw->ksz_switch; |
5358 | |
5359 | /* No ports in forwarding state. */ |
5360 | if (!sw->member) { |
5361 | port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE); |
5362 | sw_block_addr(hw); |
5363 | } |
5364 | for (port = 0; port < SWITCH_PORT_NUM; port++) { |
5365 | if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state) |
5366 | member = HOST_MASK | sw->member; |
5367 | else |
5368 | member = HOST_MASK | (1 << port); |
5369 | if (member != sw->port_cfg[port].member) |
5370 | sw_cfg_port_base_vlan(hw, port, member); |
5371 | } |
5372 | } |
5373 | |
5374 | /** |
5375 | * netdev_close - close network device |
5376 | * @dev: Network device. |
5377 | * |
5378 | * This function process the close operation of network device. This is caused |
5379 | * by the user command "ifconfig ethX down." |
5380 | * |
5381 | * Return 0 if successful; otherwise an error code indicating failure. |
5382 | */ |
5383 | static int netdev_close(struct net_device *dev) |
5384 | { |
5385 | struct dev_priv *priv = netdev_priv(dev); |
5386 | struct dev_info *hw_priv = priv->adapter; |
5387 | struct ksz_port *port = &priv->port; |
5388 | struct ksz_hw *hw = &hw_priv->hw; |
5389 | int pi; |
5390 | |
5391 | netif_stop_queue(dev); |
5392 | |
5393 | ksz_stop_timer(&priv->monitor_timer_info); |
5394 | |
5395 | /* Need to shut the port manually in multiple device interfaces mode. */ |
5396 | if (hw->dev_count > 1) { |
5397 | port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED); |
5398 | |
5399 | /* Port is closed. Need to change bridge setting. */ |
5400 | if (hw->features & STP_SUPPORT) { |
5401 | pi = 1 << port->first_port; |
5402 | if (hw->ksz_switch->member & pi) { |
5403 | hw->ksz_switch->member &= ~pi; |
5404 | bridge_change(hw); |
5405 | } |
5406 | } |
5407 | } |
5408 | if (port->first_port > 0) |
5409 | hw_del_addr(hw, dev->dev_addr); |
5410 | if (!hw_priv->wol_enable) |
5411 | port_set_power_saving(port, true); |
5412 | |
5413 | if (priv->multicast) |
5414 | --hw->all_multi; |
5415 | if (priv->promiscuous) |
5416 | --hw->promiscuous; |
5417 | |
5418 | hw_priv->opened--; |
5419 | if (!(hw_priv->opened)) { |
5420 | ksz_stop_timer(&hw_priv->mib_timer_info); |
5421 | flush_work(&hw_priv->mib_read); |
5422 | |
5423 | hw_dis_intr(hw); |
5424 | hw_disable(hw); |
5425 | hw_clr_multicast(hw); |
5426 | |
5427 | /* Delay for receive task to stop scheduling itself. */ |
5428 | msleep(2000 / HZ); |
5429 | |
5430 | tasklet_disable(&hw_priv->rx_tasklet); |
5431 | tasklet_disable(&hw_priv->tx_tasklet); |
5432 | free_irq(dev->irq, hw_priv->dev); |
5433 | |
5434 | transmit_cleanup(hw_priv, 0); |
5435 | hw_reset_pkts(&hw->rx_desc_info); |
5436 | hw_reset_pkts(&hw->tx_desc_info); |
5437 | |
5438 | /* Clean out static MAC table when the switch is shutdown. */ |
5439 | if (hw->features & STP_SUPPORT) |
5440 | sw_clr_sta_mac_table(hw); |
5441 | } |
5442 | |
5443 | return 0; |
5444 | } |
5445 | |
5446 | static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw) |
5447 | { |
5448 | if (hw->ksz_switch) { |
5449 | u32 data; |
5450 | |
5451 | data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); |
5452 | if (hw->features & RX_HUGE_FRAME) |
5453 | data |= SWITCH_HUGE_PACKET; |
5454 | else |
5455 | data &= ~SWITCH_HUGE_PACKET; |
5456 | writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); |
5457 | } |
5458 | if (hw->features & RX_HUGE_FRAME) { |
5459 | hw->rx_cfg |= DMA_RX_ERROR; |
5460 | hw_priv->dev_rcv = dev_rcv_special; |
5461 | } else { |
5462 | hw->rx_cfg &= ~DMA_RX_ERROR; |
5463 | if (hw->dev_count > 1) |
5464 | hw_priv->dev_rcv = port_rcv_packets; |
5465 | else |
5466 | hw_priv->dev_rcv = dev_rcv_packets; |
5467 | } |
5468 | } |
5469 | |
5470 | static int prepare_hardware(struct net_device *dev) |
5471 | { |
5472 | struct dev_priv *priv = netdev_priv(dev); |
5473 | struct dev_info *hw_priv = priv->adapter; |
5474 | struct ksz_hw *hw = &hw_priv->hw; |
5475 | int rc = 0; |
5476 | |
5477 | /* Remember the network device that requests interrupts. */ |
5478 | hw_priv->dev = dev; |
5479 | rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev); |
5480 | if (rc) |
5481 | return rc; |
5482 | tasklet_enable(&hw_priv->rx_tasklet); |
5483 | tasklet_enable(&hw_priv->tx_tasklet); |
5484 | |
5485 | hw->promiscuous = 0; |
5486 | hw->all_multi = 0; |
5487 | hw->multi_list_size = 0; |
5488 | |
5489 | hw_reset(hw); |
5490 | |
5491 | hw_set_desc_base(hw, |
5492 | hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys); |
5493 | hw_set_addr(hw); |
5494 | hw_cfg_huge_frame(hw_priv, hw); |
5495 | ksz_init_rx_buffers(hw_priv); |
5496 | return 0; |
5497 | } |
5498 | |
5499 | /** |
5500 | * netdev_open - open network device |
5501 | * @dev: Network device. |
5502 | * |
5503 | * This function process the open operation of network device. This is caused |
5504 | * by the user command "ifconfig ethX up." |
5505 | * |
5506 | * Return 0 if successful; otherwise an error code indicating failure. |
5507 | */ |
5508 | static int netdev_open(struct net_device *dev) |
5509 | { |
5510 | struct dev_priv *priv = netdev_priv(dev); |
5511 | struct dev_info *hw_priv = priv->adapter; |
5512 | struct ksz_hw *hw = &hw_priv->hw; |
5513 | struct ksz_port *port = &priv->port; |
5514 | int i; |
5515 | int p; |
5516 | int rc = 0; |
5517 | |
5518 | priv->multicast = 0; |
5519 | priv->promiscuous = 0; |
5520 | |
5521 | /* Reset device statistics. */ |
5522 | memset(&priv->stats, 0, sizeof(struct net_device_stats)); |
5523 | memset((void *) port->counter, 0, |
5524 | (sizeof(u64) * OID_COUNTER_LAST)); |
5525 | |
5526 | if (!(hw_priv->opened)) { |
5527 | rc = prepare_hardware(dev); |
5528 | if (rc) |
5529 | return rc; |
5530 | for (i = 0; i < hw->mib_port_cnt; i++) { |
5531 | if (next_jiffies < jiffies) |
5532 | next_jiffies = jiffies + HZ * 2; |
5533 | else |
5534 | next_jiffies += HZ * 1; |
5535 | hw_priv->counter[i].time = next_jiffies; |
5536 | hw->port_mib[i].state = media_disconnected; |
5537 | port_init_cnt(hw, i); |
5538 | } |
5539 | if (hw->ksz_switch) |
5540 | hw->port_mib[HOST_PORT].state = media_connected; |
5541 | else { |
5542 | hw_add_wol_bcast(hw); |
5543 | hw_cfg_wol_pme(hw, 0); |
5544 | hw_clr_wol_pme_status(&hw_priv->hw); |
5545 | } |
5546 | } |
5547 | port_set_power_saving(port, false); |
5548 | |
5549 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { |
5550 | /* |
5551 | * Initialize to invalid value so that link detection |
5552 | * is done. |
5553 | */ |
5554 | hw->port_info[p].partner = 0xFF; |
5555 | hw->port_info[p].state = media_disconnected; |
5556 | } |
5557 | |
5558 | /* Need to open the port in multiple device interfaces mode. */ |
5559 | if (hw->dev_count > 1) { |
5560 | port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE); |
5561 | if (port->first_port > 0) |
5562 | hw_add_addr(hw, dev->dev_addr); |
5563 | } |
5564 | |
5565 | port_get_link_speed(port); |
5566 | if (port->force_link) |
5567 | port_force_link_speed(port); |
5568 | else |
5569 | port_set_link_speed(port); |
5570 | |
5571 | if (!(hw_priv->opened)) { |
5572 | hw_setup_intr(hw); |
5573 | hw_enable(hw); |
5574 | hw_ena_intr(hw); |
5575 | |
5576 | if (hw->mib_port_cnt) |
5577 | ksz_start_timer(&hw_priv->mib_timer_info, |
5578 | hw_priv->mib_timer_info.period); |
5579 | } |
5580 | |
5581 | hw_priv->opened++; |
5582 | |
5583 | ksz_start_timer(&priv->monitor_timer_info, |
5584 | priv->monitor_timer_info.period); |
5585 | |
5586 | priv->media_state = port->linked->state; |
5587 | |
5588 | if (media_connected == priv->media_state) |
5589 | netif_carrier_on(dev); |
5590 | else |
5591 | netif_carrier_off(dev); |
5592 | if (netif_msg_link(priv)) |
5593 | printk(KERN_INFO "%s link %s\n", dev->name, |
5594 | (media_connected == priv->media_state ? |
5595 | "on" : "off")); |
5596 | |
5597 | netif_start_queue(dev); |
5598 | |
5599 | return 0; |
5600 | } |
5601 | |
5602 | /* RX errors = rx_errors */ |
5603 | /* RX dropped = rx_dropped */ |
5604 | /* RX overruns = rx_fifo_errors */ |
5605 | /* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */ |
5606 | /* TX errors = tx_errors */ |
5607 | /* TX dropped = tx_dropped */ |
5608 | /* TX overruns = tx_fifo_errors */ |
5609 | /* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */ |
5610 | /* collisions = collisions */ |
5611 | |
5612 | /** |
5613 | * netdev_query_statistics - query network device statistics |
5614 | * @dev: Network device. |
5615 | * |
5616 | * This function returns the statistics of the network device. The device |
5617 | * needs not be opened. |
5618 | * |
5619 | * Return network device statistics. |
5620 | */ |
5621 | static struct net_device_stats *netdev_query_statistics(struct net_device *dev) |
5622 | { |
5623 | struct dev_priv *priv = netdev_priv(dev); |
5624 | struct ksz_port *port = &priv->port; |
5625 | struct ksz_hw *hw = &priv->adapter->hw; |
5626 | struct ksz_port_mib *mib; |
5627 | int i; |
5628 | int p; |
5629 | |
5630 | priv->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR]; |
5631 | priv->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR]; |
5632 | |
5633 | /* Reset to zero to add count later. */ |
5634 | priv->stats.multicast = 0; |
5635 | priv->stats.collisions = 0; |
5636 | priv->stats.rx_length_errors = 0; |
5637 | priv->stats.rx_crc_errors = 0; |
5638 | priv->stats.rx_frame_errors = 0; |
5639 | priv->stats.tx_window_errors = 0; |
5640 | |
5641 | for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { |
5642 | mib = &hw->port_mib[p]; |
5643 | |
5644 | priv->stats.multicast += (unsigned long) |
5645 | mib->counter[MIB_COUNTER_RX_MULTICAST]; |
5646 | |
5647 | priv->stats.collisions += (unsigned long) |
5648 | mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION]; |
5649 | |
5650 | priv->stats.rx_length_errors += (unsigned long)( |
5651 | mib->counter[MIB_COUNTER_RX_UNDERSIZE] + |
5652 | mib->counter[MIB_COUNTER_RX_FRAGMENT] + |
5653 | mib->counter[MIB_COUNTER_RX_OVERSIZE] + |
5654 | mib->counter[MIB_COUNTER_RX_JABBER]); |
5655 | priv->stats.rx_crc_errors += (unsigned long) |
5656 | mib->counter[MIB_COUNTER_RX_CRC_ERR]; |
5657 | priv->stats.rx_frame_errors += (unsigned long)( |
5658 | mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] + |
5659 | mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]); |
5660 | |
5661 | priv->stats.tx_window_errors += (unsigned long) |
5662 | mib->counter[MIB_COUNTER_TX_LATE_COLLISION]; |
5663 | } |
5664 | |
5665 | return &priv->stats; |
5666 | } |
5667 | |
5668 | /** |
5669 | * netdev_set_mac_address - set network device MAC address |
5670 | * @dev: Network device. |
5671 | * @addr: Buffer of MAC address. |
5672 | * |
5673 | * This function is used to set the MAC address of the network device. |
5674 | * |
5675 | * Return 0 to indicate success. |
5676 | */ |
5677 | static int netdev_set_mac_address(struct net_device *dev, void *addr) |
5678 | { |
5679 | struct dev_priv *priv = netdev_priv(dev); |
5680 | struct dev_info *hw_priv = priv->adapter; |
5681 | struct ksz_hw *hw = &hw_priv->hw; |
5682 | struct sockaddr *mac = addr; |
5683 | uint interrupt; |
5684 | |
5685 | if (priv->port.first_port > 0) |
5686 | hw_del_addr(hw, dev->dev_addr); |
5687 | else { |
5688 | hw->mac_override = 1; |
5689 | memcpy(hw->override_addr, mac->sa_data, MAC_ADDR_LEN); |
5690 | } |
5691 | |
5692 | memcpy(dev->dev_addr, mac->sa_data, MAX_ADDR_LEN); |
5693 | |
5694 | interrupt = hw_block_intr(hw); |
5695 | |
5696 | if (priv->port.first_port > 0) |
5697 | hw_add_addr(hw, dev->dev_addr); |
5698 | else |
5699 | hw_set_addr(hw); |
5700 | hw_restore_intr(hw, interrupt); |
5701 | |
5702 | return 0; |
5703 | } |
5704 | |
5705 | static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv, |
5706 | struct ksz_hw *hw, int promiscuous) |
5707 | { |
5708 | if (promiscuous != priv->promiscuous) { |
5709 | u8 prev_state = hw->promiscuous; |
5710 | |
5711 | if (promiscuous) |
5712 | ++hw->promiscuous; |
5713 | else |
5714 | --hw->promiscuous; |
5715 | priv->promiscuous = promiscuous; |
5716 | |
5717 | /* Turn on/off promiscuous mode. */ |
5718 | if (hw->promiscuous <= 1 && prev_state <= 1) |
5719 | hw_set_promiscuous(hw, hw->promiscuous); |
5720 | |
5721 | /* |
5722 | * Port is not in promiscuous mode, meaning it is released |
5723 | * from the bridge. |
5724 | */ |
5725 | if ((hw->features & STP_SUPPORT) && !promiscuous && |
5726 | dev->br_port) { |
5727 | struct ksz_switch *sw = hw->ksz_switch; |
5728 | int port = priv->port.first_port; |
5729 | |
5730 | port_set_stp_state(hw, port, STP_STATE_DISABLED); |
5731 | port = 1 << port; |
5732 | if (sw->member & port) { |
5733 | sw->member &= ~port; |
5734 | bridge_change(hw); |
5735 | } |
5736 | } |
5737 | } |
5738 | } |
5739 | |
5740 | static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw, |
5741 | int multicast) |
5742 | { |
5743 | if (multicast != priv->multicast) { |
5744 | u8 all_multi = hw->all_multi; |
5745 | |
5746 | if (multicast) |
5747 | ++hw->all_multi; |
5748 | else |
5749 | --hw->all_multi; |
5750 | priv->multicast = multicast; |
5751 | |
5752 | /* Turn on/off all multicast mode. */ |
5753 | if (hw->all_multi <= 1 && all_multi <= 1) |
5754 | hw_set_multicast(hw, hw->all_multi); |
5755 | } |
5756 | } |
5757 | |
5758 | /** |
5759 | * netdev_set_rx_mode |
5760 | * @dev: Network device. |
5761 | * |
5762 | * This routine is used to set multicast addresses or put the network device |
5763 | * into promiscuous mode. |
5764 | */ |
5765 | static void netdev_set_rx_mode(struct net_device *dev) |
5766 | { |
5767 | struct dev_priv *priv = netdev_priv(dev); |
5768 | struct dev_info *hw_priv = priv->adapter; |
5769 | struct ksz_hw *hw = &hw_priv->hw; |
5770 | struct dev_mc_list *mc_ptr; |
5771 | int multicast = (dev->flags & IFF_ALLMULTI); |
5772 | |
5773 | dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC)); |
5774 | |
5775 | if (hw_priv->hw.dev_count > 1) |
5776 | multicast |= (dev->flags & IFF_MULTICAST); |
5777 | dev_set_multicast(priv, hw, multicast); |
5778 | |
5779 | /* Cannot use different hashes in multiple device interfaces mode. */ |
5780 | if (hw_priv->hw.dev_count > 1) |
5781 | return; |
5782 | |
5783 | if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) { |
5784 | int i = 0; |
5785 | |
5786 | /* List too big to support so turn on all multicast mode. */ |
5787 | if (dev->mc_count > MAX_MULTICAST_LIST) { |
5788 | if (MAX_MULTICAST_LIST != hw->multi_list_size) { |
5789 | hw->multi_list_size = MAX_MULTICAST_LIST; |
5790 | ++hw->all_multi; |
5791 | hw_set_multicast(hw, hw->all_multi); |
5792 | } |
5793 | return; |
5794 | } |
5795 | |
5796 | netdev_for_each_mc_addr(mc_ptr, dev) { |
5797 | if (!(*mc_ptr->dmi_addr & 1)) |
5798 | continue; |
5799 | if (i >= MAX_MULTICAST_LIST) |
5800 | break; |
5801 | memcpy(hw->multi_list[i++], mc_ptr->dmi_addr, |
5802 | MAC_ADDR_LEN); |
5803 | } |
5804 | hw->multi_list_size = (u8) i; |
5805 | hw_set_grp_addr(hw); |
5806 | } else { |
5807 | if (MAX_MULTICAST_LIST == hw->multi_list_size) { |
5808 | --hw->all_multi; |
5809 | hw_set_multicast(hw, hw->all_multi); |
5810 | } |
5811 | hw->multi_list_size = 0; |
5812 | hw_clr_multicast(hw); |
5813 | } |
5814 | } |
5815 | |
5816 | static int netdev_change_mtu(struct net_device *dev, int new_mtu) |
5817 | { |
5818 | struct dev_priv *priv = netdev_priv(dev); |
5819 | struct dev_info *hw_priv = priv->adapter; |
5820 | struct ksz_hw *hw = &hw_priv->hw; |
5821 | int hw_mtu; |
5822 | |
5823 | if (netif_running(dev)) |
5824 | return -EBUSY; |
5825 | |
5826 | /* Cannot use different MTU in multiple device interfaces mode. */ |
5827 | if (hw->dev_count > 1) |
5828 | if (dev != hw_priv->dev) |
5829 | return 0; |
5830 | if (new_mtu < 60) |
5831 | return -EINVAL; |
5832 | |
5833 | if (dev->mtu != new_mtu) { |
5834 | hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4; |
5835 | if (hw_mtu > MAX_RX_BUF_SIZE) |
5836 | return -EINVAL; |
5837 | if (hw_mtu > REGULAR_RX_BUF_SIZE) { |
5838 | hw->features |= RX_HUGE_FRAME; |
5839 | hw_mtu = MAX_RX_BUF_SIZE; |
5840 | } else { |
5841 | hw->features &= ~RX_HUGE_FRAME; |
5842 | hw_mtu = REGULAR_RX_BUF_SIZE; |
5843 | } |
5844 | hw_mtu = (hw_mtu + 3) & ~3; |
5845 | hw_priv->mtu = hw_mtu; |
5846 | dev->mtu = new_mtu; |
5847 | } |
5848 | return 0; |
5849 | } |
5850 | |
5851 | /** |
5852 | * netdev_ioctl - I/O control processing |
5853 | * @dev: Network device. |
5854 | * @ifr: Interface request structure. |
5855 | * @cmd: I/O control code. |
5856 | * |
5857 | * This function is used to process I/O control calls. |
5858 | * |
5859 | * Return 0 to indicate success. |
5860 | */ |
5861 | static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
5862 | { |
5863 | struct dev_priv *priv = netdev_priv(dev); |
5864 | struct dev_info *hw_priv = priv->adapter; |
5865 | struct ksz_hw *hw = &hw_priv->hw; |
5866 | struct ksz_port *port = &priv->port; |
5867 | int rc; |
5868 | int result = 0; |
5869 | struct mii_ioctl_data *data = if_mii(ifr); |
5870 | |
5871 | if (down_interruptible(&priv->proc_sem)) |
5872 | return -ERESTARTSYS; |
5873 | |
5874 | /* assume success */ |
5875 | rc = 0; |
5876 | switch (cmd) { |
5877 | /* Get address of MII PHY in use. */ |
5878 | case SIOCGMIIPHY: |
5879 | data->phy_id = priv->id; |
5880 | |
5881 | /* Fallthrough... */ |
5882 | |
5883 | /* Read MII PHY register. */ |
5884 | case SIOCGMIIREG: |
5885 | if (data->phy_id != priv->id || data->reg_num >= 6) |
5886 | result = -EIO; |
5887 | else |
5888 | hw_r_phy(hw, port->linked->port_id, data->reg_num, |
5889 | &data->val_out); |
5890 | break; |
5891 | |
5892 | /* Write MII PHY register. */ |
5893 | case SIOCSMIIREG: |
5894 | if (!capable(CAP_NET_ADMIN)) |
5895 | result = -EPERM; |
5896 | else if (data->phy_id != priv->id || data->reg_num >= 6) |
5897 | result = -EIO; |
5898 | else |
5899 | hw_w_phy(hw, port->linked->port_id, data->reg_num, |
5900 | data->val_in); |
5901 | break; |
5902 | |
5903 | default: |
5904 | result = -EOPNOTSUPP; |
5905 | } |
5906 | |
5907 | up(&priv->proc_sem); |
5908 | |
5909 | return result; |
5910 | } |
5911 | |
5912 | /* |
5913 | * MII support |
5914 | */ |
5915 | |
5916 | /** |
5917 | * mdio_read - read PHY register |
5918 | * @dev: Network device. |
5919 | * @phy_id: The PHY id. |
5920 | * @reg_num: The register number. |
5921 | * |
5922 | * This function returns the PHY register value. |
5923 | * |
5924 | * Return the register value. |
5925 | */ |
5926 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num) |
5927 | { |
5928 | struct dev_priv *priv = netdev_priv(dev); |
5929 | struct ksz_port *port = &priv->port; |
5930 | struct ksz_hw *hw = port->hw; |
5931 | u16 val_out; |
5932 | |
5933 | hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out); |
5934 | return val_out; |
5935 | } |
5936 | |
5937 | /** |
5938 | * mdio_write - set PHY register |
5939 | * @dev: Network device. |
5940 | * @phy_id: The PHY id. |
5941 | * @reg_num: The register number. |
5942 | * @val: The register value. |
5943 | * |
5944 | * This procedure sets the PHY register value. |
5945 | */ |
5946 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) |
5947 | { |
5948 | struct dev_priv *priv = netdev_priv(dev); |
5949 | struct ksz_port *port = &priv->port; |
5950 | struct ksz_hw *hw = port->hw; |
5951 | int i; |
5952 | int pi; |
5953 | |
5954 | for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++) |
5955 | hw_w_phy(hw, pi, reg_num << 1, val); |
5956 | } |
5957 | |
5958 | /* |
5959 | * ethtool support |
5960 | */ |
5961 | |
5962 | #define EEPROM_SIZE 0x40 |
5963 | |
5964 | static u16 eeprom_data[EEPROM_SIZE] = { 0 }; |
5965 | |
5966 | #define ADVERTISED_ALL \ |
5967 | (ADVERTISED_10baseT_Half | \ |
5968 | ADVERTISED_10baseT_Full | \ |
5969 | ADVERTISED_100baseT_Half | \ |
5970 | ADVERTISED_100baseT_Full) |
5971 | |
5972 | /* These functions use the MII functions in mii.c. */ |
5973 | |
5974 | /** |
5975 | * netdev_get_settings - get network device settings |
5976 | * @dev: Network device. |
5977 | * @cmd: Ethtool command. |
5978 | * |
5979 | * This function queries the PHY and returns its state in the ethtool command. |
5980 | * |
5981 | * Return 0 if successful; otherwise an error code. |
5982 | */ |
5983 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
5984 | { |
5985 | struct dev_priv *priv = netdev_priv(dev); |
5986 | struct dev_info *hw_priv = priv->adapter; |
5987 | |
5988 | mutex_lock(&hw_priv->lock); |
5989 | mii_ethtool_gset(&priv->mii_if, cmd); |
5990 | cmd->advertising |= SUPPORTED_TP; |
5991 | mutex_unlock(&hw_priv->lock); |
5992 | |
5993 | /* Save advertised settings for workaround in next function. */ |
5994 | priv->advertising = cmd->advertising; |
5995 | return 0; |
5996 | } |
5997 | |
5998 | /** |
5999 | * netdev_set_settings - set network device settings |
6000 | * @dev: Network device. |
6001 | * @cmd: Ethtool command. |
6002 | * |
6003 | * This function sets the PHY according to the ethtool command. |
6004 | * |
6005 | * Return 0 if successful; otherwise an error code. |
6006 | */ |
6007 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
6008 | { |
6009 | struct dev_priv *priv = netdev_priv(dev); |
6010 | struct dev_info *hw_priv = priv->adapter; |
6011 | struct ksz_port *port = &priv->port; |
6012 | int rc; |
6013 | |
6014 | /* |
6015 | * ethtool utility does not change advertised setting if auto |
6016 | * negotiation is not specified explicitly. |
6017 | */ |
6018 | if (cmd->autoneg && priv->advertising == cmd->advertising) { |
6019 | cmd->advertising |= ADVERTISED_ALL; |
6020 | if (10 == cmd->speed) |
6021 | cmd->advertising &= |
6022 | ~(ADVERTISED_100baseT_Full | |
6023 | ADVERTISED_100baseT_Half); |
6024 | else if (100 == cmd->speed) |
6025 | cmd->advertising &= |
6026 | ~(ADVERTISED_10baseT_Full | |
6027 | ADVERTISED_10baseT_Half); |
6028 | if (0 == cmd->duplex) |
6029 | cmd->advertising &= |
6030 | ~(ADVERTISED_100baseT_Full | |
6031 | ADVERTISED_10baseT_Full); |
6032 | else if (1 == cmd->duplex) |
6033 | cmd->advertising &= |
6034 | ~(ADVERTISED_100baseT_Half | |
6035 | ADVERTISED_10baseT_Half); |
6036 | } |
6037 | mutex_lock(&hw_priv->lock); |
6038 | if (cmd->autoneg && |
6039 | (cmd->advertising & ADVERTISED_ALL) == |
6040 | ADVERTISED_ALL) { |
6041 | port->duplex = 0; |
6042 | port->speed = 0; |
6043 | port->force_link = 0; |
6044 | } else { |
6045 | port->duplex = cmd->duplex + 1; |
6046 | if (cmd->speed != 1000) |
6047 | port->speed = cmd->speed; |
6048 | if (cmd->autoneg) |
6049 | port->force_link = 0; |
6050 | else |
6051 | port->force_link = 1; |
6052 | } |
6053 | rc = mii_ethtool_sset(&priv->mii_if, cmd); |
6054 | mutex_unlock(&hw_priv->lock); |
6055 | return rc; |
6056 | } |
6057 | |
6058 | /** |
6059 | * netdev_nway_reset - restart auto-negotiation |
6060 | * @dev: Network device. |
6061 | * |
6062 | * This function restarts the PHY for auto-negotiation. |
6063 | * |
6064 | * Return 0 if successful; otherwise an error code. |
6065 | */ |
6066 | static int netdev_nway_reset(struct net_device *dev) |
6067 | { |
6068 | struct dev_priv *priv = netdev_priv(dev); |
6069 | struct dev_info *hw_priv = priv->adapter; |
6070 | int rc; |
6071 | |
6072 | mutex_lock(&hw_priv->lock); |
6073 | rc = mii_nway_restart(&priv->mii_if); |
6074 | mutex_unlock(&hw_priv->lock); |
6075 | return rc; |
6076 | } |
6077 | |
6078 | /** |
6079 | * netdev_get_link - get network device link status |
6080 | * @dev: Network device. |
6081 | * |
6082 | * This function gets the link status from the PHY. |
6083 | * |
6084 | * Return true if PHY is linked and false otherwise. |
6085 | */ |
6086 | static u32 netdev_get_link(struct net_device *dev) |
6087 | { |
6088 | struct dev_priv *priv = netdev_priv(dev); |
6089 | int rc; |
6090 | |
6091 | rc = mii_link_ok(&priv->mii_if); |
6092 | return rc; |
6093 | } |
6094 | |
6095 | /** |
6096 | * netdev_get_drvinfo - get network driver information |
6097 | * @dev: Network device. |
6098 | * @info: Ethtool driver info data structure. |
6099 | * |
6100 | * This procedure returns the driver information. |
6101 | */ |
6102 | static void netdev_get_drvinfo(struct net_device *dev, |
6103 | struct ethtool_drvinfo *info) |
6104 | { |
6105 | struct dev_priv *priv = netdev_priv(dev); |
6106 | struct dev_info *hw_priv = priv->adapter; |
6107 | |
6108 | strcpy(info->driver, DRV_NAME); |
6109 | strcpy(info->version, DRV_VERSION); |
6110 | strcpy(info->bus_info, pci_name(hw_priv->pdev)); |
6111 | } |
6112 | |
6113 | /** |
6114 | * netdev_get_regs_len - get length of register dump |
6115 | * @dev: Network device. |
6116 | * |
6117 | * This function returns the length of the register dump. |
6118 | * |
6119 | * Return length of the register dump. |
6120 | */ |
6121 | static struct hw_regs { |
6122 | int start; |
6123 | int end; |
6124 | } hw_regs_range[] = { |
6125 | { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS }, |
6126 | { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI }, |
6127 | { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET }, |
6128 | { KS884X_SIDER_P, KS8842_SGCR7_P }, |
6129 | { KS8842_MACAR1_P, KS8842_TOSR8_P }, |
6130 | { KS884X_P1MBCR_P, KS8842_P3ERCR_P }, |
6131 | { 0, 0 } |
6132 | }; |
6133 | |
6134 | static int netdev_get_regs_len(struct net_device *dev) |
6135 | { |
6136 | struct hw_regs *range = hw_regs_range; |
6137 | int regs_len = 0x10 * sizeof(u32); |
6138 | |
6139 | while (range->end > range->start) { |
6140 | regs_len += (range->end - range->start + 3) / 4 * 4; |
6141 | range++; |
6142 | } |
6143 | return regs_len; |
6144 | } |
6145 | |
6146 | /** |
6147 | * netdev_get_regs - get register dump |
6148 | * @dev: Network device. |
6149 | * @regs: Ethtool registers data structure. |
6150 | * @ptr: Buffer to store the register values. |
6151 | * |
6152 | * This procedure dumps the register values in the provided buffer. |
6153 | */ |
6154 | static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
6155 | void *ptr) |
6156 | { |
6157 | struct dev_priv *priv = netdev_priv(dev); |
6158 | struct dev_info *hw_priv = priv->adapter; |
6159 | struct ksz_hw *hw = &hw_priv->hw; |
6160 | int *buf = (int *) ptr; |
6161 | struct hw_regs *range = hw_regs_range; |
6162 | int len; |
6163 | |
6164 | mutex_lock(&hw_priv->lock); |
6165 | regs->version = 0; |
6166 | for (len = 0; len < 0x40; len += 4) { |
6167 | pci_read_config_dword(hw_priv->pdev, len, buf); |
6168 | buf++; |
6169 | } |
6170 | while (range->end > range->start) { |
6171 | for (len = range->start; len < range->end; len += 4) { |
6172 | *buf = readl(hw->io + len); |
6173 | buf++; |
6174 | } |
6175 | range++; |
6176 | } |
6177 | mutex_unlock(&hw_priv->lock); |
6178 | } |
6179 | |
6180 | #define WOL_SUPPORT \ |
6181 | (WAKE_PHY | WAKE_MAGIC | \ |
6182 | WAKE_UCAST | WAKE_MCAST | \ |
6183 | WAKE_BCAST | WAKE_ARP) |
6184 | |
6185 | /** |
6186 | * netdev_get_wol - get Wake-on-LAN support |
6187 | * @dev: Network device. |
6188 | * @wol: Ethtool Wake-on-LAN data structure. |
6189 | * |
6190 | * This procedure returns Wake-on-LAN support. |
6191 | */ |
6192 | static void netdev_get_wol(struct net_device *dev, |
6193 | struct ethtool_wolinfo *wol) |
6194 | { |
6195 | struct dev_priv *priv = netdev_priv(dev); |
6196 | struct dev_info *hw_priv = priv->adapter; |
6197 | |
6198 | wol->supported = hw_priv->wol_support; |
6199 | wol->wolopts = hw_priv->wol_enable; |
6200 | memset(&wol->sopass, 0, sizeof(wol->sopass)); |
6201 | } |
6202 | |
6203 | /** |
6204 | * netdev_set_wol - set Wake-on-LAN support |
6205 | * @dev: Network device. |
6206 | * @wol: Ethtool Wake-on-LAN data structure. |
6207 | * |
6208 | * This function sets Wake-on-LAN support. |
6209 | * |
6210 | * Return 0 if successful; otherwise an error code. |
6211 | */ |
6212 | static int netdev_set_wol(struct net_device *dev, |
6213 | struct ethtool_wolinfo *wol) |
6214 | { |
6215 | struct dev_priv *priv = netdev_priv(dev); |
6216 | struct dev_info *hw_priv = priv->adapter; |
6217 | |
6218 | /* Need to find a way to retrieve the device IP address. */ |
6219 | u8 net_addr[] = { 192, 168, 1, 1 }; |
6220 | |
6221 | if (wol->wolopts & ~hw_priv->wol_support) |
6222 | return -EINVAL; |
6223 | |
6224 | hw_priv->wol_enable = wol->wolopts; |
6225 | |
6226 | /* Link wakeup cannot really be disabled. */ |
6227 | if (wol->wolopts) |
6228 | hw_priv->wol_enable |= WAKE_PHY; |
6229 | hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr); |
6230 | return 0; |
6231 | } |
6232 | |
6233 | /** |
6234 | * netdev_get_msglevel - get debug message level |
6235 | * @dev: Network device. |
6236 | * |
6237 | * This function returns current debug message level. |
6238 | * |
6239 | * Return current debug message flags. |
6240 | */ |
6241 | static u32 netdev_get_msglevel(struct net_device *dev) |
6242 | { |
6243 | struct dev_priv *priv = netdev_priv(dev); |
6244 | |
6245 | return priv->msg_enable; |
6246 | } |
6247 | |
6248 | /** |
6249 | * netdev_set_msglevel - set debug message level |
6250 | * @dev: Network device. |
6251 | * @value: Debug message flags. |
6252 | * |
6253 | * This procedure sets debug message level. |
6254 | */ |
6255 | static void netdev_set_msglevel(struct net_device *dev, u32 value) |
6256 | { |
6257 | struct dev_priv *priv = netdev_priv(dev); |
6258 | |
6259 | priv->msg_enable = value; |
6260 | } |
6261 | |
6262 | /** |
6263 | * netdev_get_eeprom_len - get EEPROM length |
6264 | * @dev: Network device. |
6265 | * |
6266 | * This function returns the length of the EEPROM. |
6267 | * |
6268 | * Return length of the EEPROM. |
6269 | */ |
6270 | static int netdev_get_eeprom_len(struct net_device *dev) |
6271 | { |
6272 | return EEPROM_SIZE * 2; |
6273 | } |
6274 | |
6275 | /** |
6276 | * netdev_get_eeprom - get EEPROM data |
6277 | * @dev: Network device. |
6278 | * @eeprom: Ethtool EEPROM data structure. |
6279 | * @data: Buffer to store the EEPROM data. |
6280 | * |
6281 | * This function dumps the EEPROM data in the provided buffer. |
6282 | * |
6283 | * Return 0 if successful; otherwise an error code. |
6284 | */ |
6285 | #define EEPROM_MAGIC 0x10A18842 |
6286 | |
6287 | static int netdev_get_eeprom(struct net_device *dev, |
6288 | struct ethtool_eeprom *eeprom, u8 *data) |
6289 | { |
6290 | struct dev_priv *priv = netdev_priv(dev); |
6291 | struct dev_info *hw_priv = priv->adapter; |
6292 | u8 *eeprom_byte = (u8 *) eeprom_data; |
6293 | int i; |
6294 | int len; |
6295 | |
6296 | len = (eeprom->offset + eeprom->len + 1) / 2; |
6297 | for (i = eeprom->offset / 2; i < len; i++) |
6298 | eeprom_data[i] = eeprom_read(&hw_priv->hw, i); |
6299 | eeprom->magic = EEPROM_MAGIC; |
6300 | memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len); |
6301 | |
6302 | return 0; |
6303 | } |
6304 | |
6305 | /** |
6306 | * netdev_set_eeprom - write EEPROM data |
6307 | * @dev: Network device. |
6308 | * @eeprom: Ethtool EEPROM data structure. |
6309 | * @data: Data buffer. |
6310 | * |
6311 | * This function modifies the EEPROM data one byte at a time. |
6312 | * |
6313 | * Return 0 if successful; otherwise an error code. |
6314 | */ |
6315 | static int netdev_set_eeprom(struct net_device *dev, |
6316 | struct ethtool_eeprom *eeprom, u8 *data) |
6317 | { |
6318 | struct dev_priv *priv = netdev_priv(dev); |
6319 | struct dev_info *hw_priv = priv->adapter; |
6320 | u16 eeprom_word[EEPROM_SIZE]; |
6321 | u8 *eeprom_byte = (u8 *) eeprom_word; |
6322 | int i; |
6323 | int len; |
6324 | |
6325 | if (eeprom->magic != EEPROM_MAGIC) |
6326 | return -EINVAL; |
6327 | |
6328 | len = (eeprom->offset + eeprom->len + 1) / 2; |
6329 | for (i = eeprom->offset / 2; i < len; i++) |
6330 | eeprom_data[i] = eeprom_read(&hw_priv->hw, i); |
6331 | memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2); |
6332 | memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len); |
6333 | for (i = 0; i < EEPROM_SIZE; i++) |
6334 | if (eeprom_word[i] != eeprom_data[i]) { |
6335 | eeprom_data[i] = eeprom_word[i]; |
6336 | eeprom_write(&hw_priv->hw, i, eeprom_data[i]); |
6337 | } |
6338 | |
6339 | return 0; |
6340 | } |
6341 | |
6342 | /** |
6343 | * netdev_get_pauseparam - get flow control parameters |
6344 | * @dev: Network device. |
6345 | * @pause: Ethtool PAUSE settings data structure. |
6346 | * |
6347 | * This procedure returns the PAUSE control flow settings. |
6348 | */ |
6349 | static void netdev_get_pauseparam(struct net_device *dev, |
6350 | struct ethtool_pauseparam *pause) |
6351 | { |
6352 | struct dev_priv *priv = netdev_priv(dev); |
6353 | struct dev_info *hw_priv = priv->adapter; |
6354 | struct ksz_hw *hw = &hw_priv->hw; |
6355 | |
6356 | pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1; |
6357 | if (!hw->ksz_switch) { |
6358 | pause->rx_pause = |
6359 | (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0; |
6360 | pause->tx_pause = |
6361 | (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0; |
6362 | } else { |
6363 | pause->rx_pause = |
6364 | (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, |
6365 | SWITCH_RX_FLOW_CTRL)) ? 1 : 0; |
6366 | pause->tx_pause = |
6367 | (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, |
6368 | SWITCH_TX_FLOW_CTRL)) ? 1 : 0; |
6369 | } |
6370 | } |
6371 | |
6372 | /** |
6373 | * netdev_set_pauseparam - set flow control parameters |
6374 | * @dev: Network device. |
6375 | * @pause: Ethtool PAUSE settings data structure. |
6376 | * |
6377 | * This function sets the PAUSE control flow settings. |
6378 | * Not implemented yet. |
6379 | * |
6380 | * Return 0 if successful; otherwise an error code. |
6381 | */ |
6382 | static int netdev_set_pauseparam(struct net_device *dev, |
6383 | struct ethtool_pauseparam *pause) |
6384 | { |
6385 | struct dev_priv *priv = netdev_priv(dev); |
6386 | struct dev_info *hw_priv = priv->adapter; |
6387 | struct ksz_hw *hw = &hw_priv->hw; |
6388 | struct ksz_port *port = &priv->port; |
6389 | |
6390 | mutex_lock(&hw_priv->lock); |
6391 | if (pause->autoneg) { |
6392 | if (!pause->rx_pause && !pause->tx_pause) |
6393 | port->flow_ctrl = PHY_NO_FLOW_CTRL; |
6394 | else |
6395 | port->flow_ctrl = PHY_FLOW_CTRL; |
6396 | hw->overrides &= ~PAUSE_FLOW_CTRL; |
6397 | port->force_link = 0; |
6398 | if (hw->ksz_switch) { |
6399 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, |
6400 | SWITCH_RX_FLOW_CTRL, 1); |
6401 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, |
6402 | SWITCH_TX_FLOW_CTRL, 1); |
6403 | } |
6404 | port_set_link_speed(port); |
6405 | } else { |
6406 | hw->overrides |= PAUSE_FLOW_CTRL; |
6407 | if (hw->ksz_switch) { |
6408 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, |
6409 | SWITCH_RX_FLOW_CTRL, pause->rx_pause); |
6410 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, |
6411 | SWITCH_TX_FLOW_CTRL, pause->tx_pause); |
6412 | } else |
6413 | set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause); |
6414 | } |
6415 | mutex_unlock(&hw_priv->lock); |
6416 | |
6417 | return 0; |
6418 | } |
6419 | |
6420 | /** |
6421 | * netdev_get_ringparam - get tx/rx ring parameters |
6422 | * @dev: Network device. |
6423 | * @pause: Ethtool RING settings data structure. |
6424 | * |
6425 | * This procedure returns the TX/RX ring settings. |
6426 | */ |
6427 | static void netdev_get_ringparam(struct net_device *dev, |
6428 | struct ethtool_ringparam *ring) |
6429 | { |
6430 | struct dev_priv *priv = netdev_priv(dev); |
6431 | struct dev_info *hw_priv = priv->adapter; |
6432 | struct ksz_hw *hw = &hw_priv->hw; |
6433 | |
6434 | ring->tx_max_pending = (1 << 9); |
6435 | ring->tx_pending = hw->tx_desc_info.alloc; |
6436 | ring->rx_max_pending = (1 << 9); |
6437 | ring->rx_pending = hw->rx_desc_info.alloc; |
6438 | } |
6439 | |
6440 | #define STATS_LEN (TOTAL_PORT_COUNTER_NUM) |
6441 | |
6442 | static struct { |
6443 | char string[ETH_GSTRING_LEN]; |
6444 | } ethtool_stats_keys[STATS_LEN] = { |
6445 | { "rx_lo_priority_octets" }, |
6446 | { "rx_hi_priority_octets" }, |
6447 | { "rx_undersize_packets" }, |
6448 | { "rx_fragments" }, |
6449 | { "rx_oversize_packets" }, |
6450 | { "rx_jabbers" }, |
6451 | { "rx_symbol_errors" }, |
6452 | { "rx_crc_errors" }, |
6453 | { "rx_align_errors" }, |
6454 | { "rx_mac_ctrl_packets" }, |
6455 | { "rx_pause_packets" }, |
6456 | { "rx_bcast_packets" }, |
6457 | { "rx_mcast_packets" }, |
6458 | { "rx_ucast_packets" }, |
6459 | { "rx_64_or_less_octet_packets" }, |
6460 | { "rx_65_to_127_octet_packets" }, |
6461 | { "rx_128_to_255_octet_packets" }, |
6462 | { "rx_256_to_511_octet_packets" }, |
6463 | { "rx_512_to_1023_octet_packets" }, |
6464 | { "rx_1024_to_1522_octet_packets" }, |
6465 | |
6466 | { "tx_lo_priority_octets" }, |
6467 | { "tx_hi_priority_octets" }, |
6468 | { "tx_late_collisions" }, |
6469 | { "tx_pause_packets" }, |
6470 | { "tx_bcast_packets" }, |
6471 | { "tx_mcast_packets" }, |
6472 | { "tx_ucast_packets" }, |
6473 | { "tx_deferred" }, |
6474 | { "tx_total_collisions" }, |
6475 | { "tx_excessive_collisions" }, |
6476 | { "tx_single_collisions" }, |
6477 | { "tx_mult_collisions" }, |
6478 | |
6479 | { "rx_discards" }, |
6480 | { "tx_discards" }, |
6481 | }; |
6482 | |
6483 | /** |
6484 | * netdev_get_strings - get statistics identity strings |
6485 | * @dev: Network device. |
6486 | * @stringset: String set identifier. |
6487 | * @buf: Buffer to store the strings. |
6488 | * |
6489 | * This procedure returns the strings used to identify the statistics. |
6490 | */ |
6491 | static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
6492 | { |
6493 | struct dev_priv *priv = netdev_priv(dev); |
6494 | struct dev_info *hw_priv = priv->adapter; |
6495 | struct ksz_hw *hw = &hw_priv->hw; |
6496 | |
6497 | if (ETH_SS_STATS == stringset) |
6498 | memcpy(buf, ðtool_stats_keys, |
6499 | ETH_GSTRING_LEN * hw->mib_cnt); |
6500 | } |
6501 | |
6502 | /** |
6503 | * netdev_get_sset_count - get statistics size |
6504 | * @dev: Network device. |
6505 | * @sset: The statistics set number. |
6506 | * |
6507 | * This function returns the size of the statistics to be reported. |
6508 | * |
6509 | * Return size of the statistics to be reported. |
6510 | */ |
6511 | static int netdev_get_sset_count(struct net_device *dev, int sset) |
6512 | { |
6513 | struct dev_priv *priv = netdev_priv(dev); |
6514 | struct dev_info *hw_priv = priv->adapter; |
6515 | struct ksz_hw *hw = &hw_priv->hw; |
6516 | |
6517 | switch (sset) { |
6518 | case ETH_SS_STATS: |
6519 | return hw->mib_cnt; |
6520 | default: |
6521 | return -EOPNOTSUPP; |
6522 | } |
6523 | } |
6524 | |
6525 | /** |
6526 | * netdev_get_ethtool_stats - get network device statistics |
6527 | * @dev: Network device. |
6528 | * @stats: Ethtool statistics data structure. |
6529 | * @data: Buffer to store the statistics. |
6530 | * |
6531 | * This procedure returns the statistics. |
6532 | */ |
6533 | static void netdev_get_ethtool_stats(struct net_device *dev, |
6534 | struct ethtool_stats *stats, u64 *data) |
6535 | { |
6536 | struct dev_priv *priv = netdev_priv(dev); |
6537 | struct dev_info *hw_priv = priv->adapter; |
6538 | struct ksz_hw *hw = &hw_priv->hw; |
6539 | struct ksz_port *port = &priv->port; |
6540 | int n_stats = stats->n_stats; |
6541 | int i; |
6542 | int n; |
6543 | int p; |
6544 | int rc; |
6545 | u64 counter[TOTAL_PORT_COUNTER_NUM]; |
6546 | |
6547 | mutex_lock(&hw_priv->lock); |
6548 | n = SWITCH_PORT_NUM; |
6549 | for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { |
6550 | if (media_connected == hw->port_mib[p].state) { |
6551 | hw_priv->counter[p].read = 1; |
6552 | |
6553 | /* Remember first port that requests read. */ |
6554 | if (n == SWITCH_PORT_NUM) |
6555 | n = p; |
6556 | } |
6557 | } |
6558 | mutex_unlock(&hw_priv->lock); |
6559 | |
6560 | if (n < SWITCH_PORT_NUM) |
6561 | schedule_work(&hw_priv->mib_read); |
6562 | |
6563 | if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) { |
6564 | p = n; |
6565 | rc = wait_event_interruptible_timeout( |
6566 | hw_priv->counter[p].counter, |
6567 | 2 == hw_priv->counter[p].read, |
6568 | HZ * 1); |
6569 | } else |
6570 | for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) { |
6571 | if (0 == i) { |
6572 | rc = wait_event_interruptible_timeout( |
6573 | hw_priv->counter[p].counter, |
6574 | 2 == hw_priv->counter[p].read, |
6575 | HZ * 2); |
6576 | } else if (hw->port_mib[p].cnt_ptr) { |
6577 | rc = wait_event_interruptible_timeout( |
6578 | hw_priv->counter[p].counter, |
6579 | 2 == hw_priv->counter[p].read, |
6580 | HZ * 1); |
6581 | } |
6582 | } |
6583 | |
6584 | get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter); |
6585 | n = hw->mib_cnt; |
6586 | if (n > n_stats) |
6587 | n = n_stats; |
6588 | n_stats -= n; |
6589 | for (i = 0; i < n; i++) |
6590 | *data++ = counter[i]; |
6591 | } |
6592 | |
6593 | /** |
6594 | * netdev_get_rx_csum - get receive checksum support |
6595 | * @dev: Network device. |
6596 | * |
6597 | * This function gets receive checksum support setting. |
6598 | * |
6599 | * Return true if receive checksum is enabled; false otherwise. |
6600 | */ |
6601 | static u32 netdev_get_rx_csum(struct net_device *dev) |
6602 | { |
6603 | struct dev_priv *priv = netdev_priv(dev); |
6604 | struct dev_info *hw_priv = priv->adapter; |
6605 | struct ksz_hw *hw = &hw_priv->hw; |
6606 | |
6607 | return hw->rx_cfg & |
6608 | (DMA_RX_CSUM_UDP | |
6609 | DMA_RX_CSUM_TCP | |
6610 | DMA_RX_CSUM_IP); |
6611 | } |
6612 | |
6613 | /** |
6614 | * netdev_set_rx_csum - set receive checksum support |
6615 | * @dev: Network device. |
6616 | * @data: Zero to disable receive checksum support. |
6617 | * |
6618 | * This function sets receive checksum support setting. |
6619 | * |
6620 | * Return 0 if successful; otherwise an error code. |
6621 | */ |
6622 | static int netdev_set_rx_csum(struct net_device *dev, u32 data) |
6623 | { |
6624 | struct dev_priv *priv = netdev_priv(dev); |
6625 | struct dev_info *hw_priv = priv->adapter; |
6626 | struct ksz_hw *hw = &hw_priv->hw; |
6627 | u32 new_setting = hw->rx_cfg; |
6628 | |
6629 | if (data) |
6630 | new_setting |= |
6631 | (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP | |
6632 | DMA_RX_CSUM_IP); |
6633 | else |
6634 | new_setting &= |
6635 | ~(DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP | |
6636 | DMA_RX_CSUM_IP); |
6637 | new_setting &= ~DMA_RX_CSUM_UDP; |
6638 | mutex_lock(&hw_priv->lock); |
6639 | if (new_setting != hw->rx_cfg) { |
6640 | hw->rx_cfg = new_setting; |
6641 | if (hw->enabled) |
6642 | writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); |
6643 | } |
6644 | mutex_unlock(&hw_priv->lock); |
6645 | return 0; |
6646 | } |
6647 | |
6648 | static struct ethtool_ops netdev_ethtool_ops = { |
6649 | .get_settings = netdev_get_settings, |
6650 | .set_settings = netdev_set_settings, |
6651 | .nway_reset = netdev_nway_reset, |
6652 | .get_link = netdev_get_link, |
6653 | .get_drvinfo = netdev_get_drvinfo, |
6654 | .get_regs_len = netdev_get_regs_len, |
6655 | .get_regs = netdev_get_regs, |
6656 | .get_wol = netdev_get_wol, |
6657 | .set_wol = netdev_set_wol, |
6658 | .get_msglevel = netdev_get_msglevel, |
6659 | .set_msglevel = netdev_set_msglevel, |
6660 | .get_eeprom_len = netdev_get_eeprom_len, |
6661 | .get_eeprom = netdev_get_eeprom, |
6662 | .set_eeprom = netdev_set_eeprom, |
6663 | .get_pauseparam = netdev_get_pauseparam, |
6664 | .set_pauseparam = netdev_set_pauseparam, |
6665 | .get_ringparam = netdev_get_ringparam, |
6666 | .get_strings = netdev_get_strings, |
6667 | .get_sset_count = netdev_get_sset_count, |
6668 | .get_ethtool_stats = netdev_get_ethtool_stats, |
6669 | .get_rx_csum = netdev_get_rx_csum, |
6670 | .set_rx_csum = netdev_set_rx_csum, |
6671 | .get_tx_csum = ethtool_op_get_tx_csum, |
6672 | .set_tx_csum = ethtool_op_set_tx_csum, |
6673 | .get_sg = ethtool_op_get_sg, |
6674 | .set_sg = ethtool_op_set_sg, |
6675 | }; |
6676 | |
6677 | /* |
6678 | * Hardware monitoring |
6679 | */ |
6680 | |
6681 | static void update_link(struct net_device *dev, struct dev_priv *priv, |
6682 | struct ksz_port *port) |
6683 | { |
6684 | if (priv->media_state != port->linked->state) { |
6685 | priv->media_state = port->linked->state; |
6686 | if (netif_running(dev)) { |
6687 | if (media_connected == priv->media_state) |
6688 | netif_carrier_on(dev); |
6689 | else |
6690 | netif_carrier_off(dev); |
6691 | if (netif_msg_link(priv)) |
6692 | printk(KERN_INFO "%s link %s\n", dev->name, |
6693 | (media_connected == priv->media_state ? |
6694 | "on" : "off")); |
6695 | } |
6696 | } |
6697 | } |
6698 | |
6699 | static void mib_read_work(struct work_struct *work) |
6700 | { |
6701 | struct dev_info *hw_priv = |
6702 | container_of(work, struct dev_info, mib_read); |
6703 | struct ksz_hw *hw = &hw_priv->hw; |
6704 | struct ksz_port_mib *mib; |
6705 | int i; |
6706 | |
6707 | next_jiffies = jiffies; |
6708 | for (i = 0; i < hw->mib_port_cnt; i++) { |
6709 | mib = &hw->port_mib[i]; |
6710 | |
6711 | /* Reading MIB counters or requested to read. */ |
6712 | if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) { |
6713 | |
6714 | /* Need to process receive interrupt. */ |
6715 | if (port_r_cnt(hw, i)) |
6716 | break; |
6717 | hw_priv->counter[i].read = 0; |
6718 | |
6719 | /* Finish reading counters. */ |
6720 | if (0 == mib->cnt_ptr) { |
6721 | hw_priv->counter[i].read = 2; |
6722 | wake_up_interruptible( |
6723 | &hw_priv->counter[i].counter); |
6724 | } |
6725 | } else if (jiffies >= hw_priv->counter[i].time) { |
6726 | /* Only read MIB counters when the port is connected. */ |
6727 | if (media_connected == mib->state) |
6728 | hw_priv->counter[i].read = 1; |
6729 | next_jiffies += HZ * 1 * hw->mib_port_cnt; |
6730 | hw_priv->counter[i].time = next_jiffies; |
6731 | |
6732 | /* Port is just disconnected. */ |
6733 | } else if (mib->link_down) { |
6734 | mib->link_down = 0; |
6735 | |
6736 | /* Read counters one last time after link is lost. */ |
6737 | hw_priv->counter[i].read = 1; |
6738 | } |
6739 | } |
6740 | } |
6741 | |
6742 | static void mib_monitor(unsigned long ptr) |
6743 | { |
6744 | struct dev_info *hw_priv = (struct dev_info *) ptr; |
6745 | |
6746 | mib_read_work(&hw_priv->mib_read); |
6747 | |
6748 | /* This is used to verify Wake-on-LAN is working. */ |
6749 | if (hw_priv->pme_wait) { |
6750 | if (hw_priv->pme_wait <= jiffies) { |
6751 | hw_clr_wol_pme_status(&hw_priv->hw); |
6752 | hw_priv->pme_wait = 0; |
6753 | } |
6754 | } else if (hw_chk_wol_pme_status(&hw_priv->hw)) { |
6755 | |
6756 | /* PME is asserted. Wait 2 seconds to clear it. */ |
6757 | hw_priv->pme_wait = jiffies + HZ * 2; |
6758 | } |
6759 | |
6760 | ksz_update_timer(&hw_priv->mib_timer_info); |
6761 | } |
6762 | |
6763 | /** |
6764 | * dev_monitor - periodic monitoring |
6765 | * @ptr: Network device pointer. |
6766 | * |
6767 | * This routine is run in a kernel timer to monitor the network device. |
6768 | */ |
6769 | static void dev_monitor(unsigned long ptr) |
6770 | { |
6771 | struct net_device *dev = (struct net_device *) ptr; |
6772 | struct dev_priv *priv = netdev_priv(dev); |
6773 | struct dev_info *hw_priv = priv->adapter; |
6774 | struct ksz_hw *hw = &hw_priv->hw; |
6775 | struct ksz_port *port = &priv->port; |
6776 | |
6777 | if (!(hw->features & LINK_INT_WORKING)) |
6778 | port_get_link_speed(port); |
6779 | update_link(dev, priv, port); |
6780 | |
6781 | ksz_update_timer(&priv->monitor_timer_info); |
6782 | } |
6783 | |
6784 | /* |
6785 | * Linux network device interface functions |
6786 | */ |
6787 | |
6788 | /* Driver exported variables */ |
6789 | |
6790 | static int msg_enable; |
6791 | |
6792 | static char *macaddr = ":"; |
6793 | static char *mac1addr = ":"; |
6794 | |
6795 | /* |
6796 | * This enables multiple network device mode for KSZ8842, which contains a |
6797 | * switch with two physical ports. Some users like to take control of the |
6798 | * ports for running Spanning Tree Protocol. The driver will create an |
6799 | * additional eth? device for the other port. |
6800 | * |
6801 | * Some limitations are the network devices cannot have different MTU and |
6802 | * multicast hash tables. |
6803 | */ |
6804 | static int multi_dev; |
6805 | |
6806 | /* |
6807 | * As most users select multiple network device mode to use Spanning Tree |
6808 | * Protocol, this enables a feature in which most unicast and multicast packets |
6809 | * are forwarded inside the switch and not passed to the host. Only packets |
6810 | * that need the host's attention are passed to it. This prevents the host |
6811 | * wasting CPU time to examine each and every incoming packets and do the |
6812 | * forwarding itself. |
6813 | * |
6814 | * As the hack requires the private bridge header, the driver cannot compile |
6815 | * with just the kernel headers. |
6816 | * |
6817 | * Enabling STP support also turns on multiple network device mode. |
6818 | */ |
6819 | static int stp; |
6820 | |
6821 | /* |
6822 | * This enables fast aging in the KSZ8842 switch. Not sure what situation |
6823 | * needs that. However, fast aging is used to flush the dynamic MAC table when |
6824 | * STP suport is enabled. |
6825 | */ |
6826 | static int fast_aging; |
6827 | |
6828 | /** |
6829 | * netdev_init - initalize network device. |
6830 | * @dev: Network device. |
6831 | * |
6832 | * This function initializes the network device. |
6833 | * |
6834 | * Return 0 if successful; otherwise an error code indicating failure. |
6835 | */ |
6836 | static int __init netdev_init(struct net_device *dev) |
6837 | { |
6838 | struct dev_priv *priv = netdev_priv(dev); |
6839 | |
6840 | /* 500 ms timeout */ |
6841 | ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000, |
6842 | dev_monitor, dev); |
6843 | |
6844 | /* 500 ms timeout */ |
6845 | dev->watchdog_timeo = HZ / 2; |
6846 | |
6847 | dev->features |= NETIF_F_IP_CSUM; |
6848 | |
6849 | /* |
6850 | * Hardware does not really support IPv6 checksum generation, but |
6851 | * driver actually runs faster with this on. Refer IPV6_CSUM_GEN_HACK. |
6852 | */ |
6853 | dev->features |= NETIF_F_IPV6_CSUM; |
6854 | dev->features |= NETIF_F_SG; |
6855 | |
6856 | sema_init(&priv->proc_sem, 1); |
6857 | |
6858 | priv->mii_if.phy_id_mask = 0x1; |
6859 | priv->mii_if.reg_num_mask = 0x7; |
6860 | priv->mii_if.dev = dev; |
6861 | priv->mii_if.mdio_read = mdio_read; |
6862 | priv->mii_if.mdio_write = mdio_write; |
6863 | priv->mii_if.phy_id = priv->port.first_port + 1; |
6864 | |
6865 | priv->msg_enable = netif_msg_init(msg_enable, |
6866 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)); |
6867 | |
6868 | return 0; |
6869 | } |
6870 | |
6871 | static const struct net_device_ops netdev_ops = { |
6872 | .ndo_init = netdev_init, |
6873 | .ndo_open = netdev_open, |
6874 | .ndo_stop = netdev_close, |
6875 | .ndo_get_stats = netdev_query_statistics, |
6876 | .ndo_start_xmit = netdev_tx, |
6877 | .ndo_tx_timeout = netdev_tx_timeout, |
6878 | .ndo_change_mtu = netdev_change_mtu, |
6879 | .ndo_set_mac_address = netdev_set_mac_address, |
6880 | .ndo_do_ioctl = netdev_ioctl, |
6881 | .ndo_set_rx_mode = netdev_set_rx_mode, |
6882 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6883 | .ndo_poll_controller = netdev_netpoll, |
6884 | #endif |
6885 | }; |
6886 | |
6887 | static void netdev_free(struct net_device *dev) |
6888 | { |
6889 | if (dev->watchdog_timeo) |
6890 | unregister_netdev(dev); |
6891 | |
6892 | free_netdev(dev); |
6893 | } |
6894 | |
6895 | struct platform_info { |
6896 | struct dev_info dev_info; |
6897 | struct net_device *netdev[SWITCH_PORT_NUM]; |
6898 | }; |
6899 | |
6900 | static int net_device_present; |
6901 | |
6902 | static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port) |
6903 | { |
6904 | int i; |
6905 | int j; |
6906 | int got_num; |
6907 | int num; |
6908 | |
6909 | i = j = num = got_num = 0; |
6910 | while (j < MAC_ADDR_LEN) { |
6911 | if (macaddr[i]) { |
6912 | got_num = 1; |
6913 | if ('0' <= macaddr[i] && macaddr[i] <= '9') |
6914 | num = num * 16 + macaddr[i] - '0'; |
6915 | else if ('A' <= macaddr[i] && macaddr[i] <= 'F') |
6916 | num = num * 16 + 10 + macaddr[i] - 'A'; |
6917 | else if ('a' <= macaddr[i] && macaddr[i] <= 'f') |
6918 | num = num * 16 + 10 + macaddr[i] - 'a'; |
6919 | else if (':' == macaddr[i]) |
6920 | got_num = 2; |
6921 | else |
6922 | break; |
6923 | } else if (got_num) |
6924 | got_num = 2; |
6925 | else |
6926 | break; |
6927 | if (2 == got_num) { |
6928 | if (MAIN_PORT == port) { |
6929 | hw_priv->hw.override_addr[j++] = (u8) num; |
6930 | hw_priv->hw.override_addr[5] += |
6931 | hw_priv->hw.id; |
6932 | } else { |
6933 | hw_priv->hw.ksz_switch->other_addr[j++] = |
6934 | (u8) num; |
6935 | hw_priv->hw.ksz_switch->other_addr[5] += |
6936 | hw_priv->hw.id; |
6937 | } |
6938 | num = got_num = 0; |
6939 | } |
6940 | i++; |
6941 | } |
6942 | if (MAC_ADDR_LEN == j) { |
6943 | if (MAIN_PORT == port) |
6944 | hw_priv->hw.mac_override = 1; |
6945 | } |
6946 | } |
6947 | |
6948 | #define KS884X_DMA_MASK (~0x0UL) |
6949 | |
6950 | static void read_other_addr(struct ksz_hw *hw) |
6951 | { |
6952 | int i; |
6953 | u16 data[3]; |
6954 | struct ksz_switch *sw = hw->ksz_switch; |
6955 | |
6956 | for (i = 0; i < 3; i++) |
6957 | data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR); |
6958 | if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) { |
6959 | sw->other_addr[5] = (u8) data[0]; |
6960 | sw->other_addr[4] = (u8)(data[0] >> 8); |
6961 | sw->other_addr[3] = (u8) data[1]; |
6962 | sw->other_addr[2] = (u8)(data[1] >> 8); |
6963 | sw->other_addr[1] = (u8) data[2]; |
6964 | sw->other_addr[0] = (u8)(data[2] >> 8); |
6965 | } |
6966 | } |
6967 | |
6968 | #ifndef PCI_VENDOR_ID_MICREL_KS |
6969 | #define PCI_VENDOR_ID_MICREL_KS 0x16c6 |
6970 | #endif |
6971 | |
6972 | static int __init pcidev_init(struct pci_dev *pdev, |
6973 | const struct pci_device_id *id) |
6974 | { |
6975 | struct net_device *dev; |
6976 | struct dev_priv *priv; |
6977 | struct dev_info *hw_priv; |
6978 | struct ksz_hw *hw; |
6979 | struct platform_info *info; |
6980 | struct ksz_port *port; |
6981 | unsigned long reg_base; |
6982 | unsigned long reg_len; |
6983 | int cnt; |
6984 | int i; |
6985 | int mib_port_count; |
6986 | int pi; |
6987 | int port_count; |
6988 | int result; |
6989 | char banner[80]; |
6990 | struct ksz_switch *sw = NULL; |
6991 | |
6992 | result = pci_enable_device(pdev); |
6993 | if (result) |
6994 | return result; |
6995 | |
6996 | result = -ENODEV; |
6997 | |
6998 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) || |
6999 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) |
7000 | return result; |
7001 | |
7002 | reg_base = pci_resource_start(pdev, 0); |
7003 | reg_len = pci_resource_len(pdev, 0); |
7004 | if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) |
7005 | return result; |
7006 | |
7007 | if (!request_mem_region(reg_base, reg_len, DRV_NAME)) |
7008 | return result; |
7009 | pci_set_master(pdev); |
7010 | |
7011 | result = -ENOMEM; |
7012 | |
7013 | info = kmalloc(sizeof(struct platform_info), GFP_KERNEL); |
7014 | if (!info) |
7015 | goto pcidev_init_dev_err; |
7016 | memset(info, 0, sizeof(struct platform_info)); |
7017 | |
7018 | hw_priv = &info->dev_info; |
7019 | hw_priv->pdev = pdev; |
7020 | |
7021 | hw = &hw_priv->hw; |
7022 | |
7023 | hw->io = ioremap(reg_base, reg_len); |
7024 | if (!hw->io) |
7025 | goto pcidev_init_io_err; |
7026 | |
7027 | cnt = hw_init(hw); |
7028 | if (!cnt) { |
7029 | if (msg_enable & NETIF_MSG_PROBE) |
7030 | printk(KERN_ALERT "chip not detected\n"); |
7031 | result = -ENODEV; |
7032 | goto pcidev_init_alloc_err; |
7033 | } |
7034 | |
7035 | sprintf(banner, "%s\n", version); |
7036 | banner[13] = cnt + '0'; |
7037 | ks_info(hw_priv, "%s", banner); |
7038 | ks_dbg(hw_priv, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq); |
7039 | |
7040 | /* Assume device is KSZ8841. */ |
7041 | hw->dev_count = 1; |
7042 | port_count = 1; |
7043 | mib_port_count = 1; |
7044 | hw->addr_list_size = 0; |
7045 | hw->mib_cnt = PORT_COUNTER_NUM; |
7046 | hw->mib_port_cnt = 1; |
7047 | |
7048 | /* KSZ8842 has a switch with multiple ports. */ |
7049 | if (2 == cnt) { |
7050 | if (fast_aging) |
7051 | hw->overrides |= FAST_AGING; |
7052 | |
7053 | hw->mib_cnt = TOTAL_PORT_COUNTER_NUM; |
7054 | |
7055 | /* Multiple network device interfaces are required. */ |
7056 | if (multi_dev) { |
7057 | hw->dev_count = SWITCH_PORT_NUM; |
7058 | hw->addr_list_size = SWITCH_PORT_NUM - 1; |
7059 | } |
7060 | |
7061 | /* Single network device has multiple ports. */ |
7062 | if (1 == hw->dev_count) { |
7063 | port_count = SWITCH_PORT_NUM; |
7064 | mib_port_count = SWITCH_PORT_NUM; |
7065 | } |
7066 | hw->mib_port_cnt = TOTAL_PORT_NUM; |
7067 | hw->ksz_switch = kmalloc(sizeof(struct ksz_switch), GFP_KERNEL); |
7068 | if (!hw->ksz_switch) |
7069 | goto pcidev_init_alloc_err; |
7070 | memset(hw->ksz_switch, 0, sizeof(struct ksz_switch)); |
7071 | |
7072 | sw = hw->ksz_switch; |
7073 | } |
7074 | for (i = 0; i < hw->mib_port_cnt; i++) |
7075 | hw->port_mib[i].mib_start = 0; |
7076 | |
7077 | hw->parent = hw_priv; |
7078 | |
7079 | /* Default MTU is 1500. */ |
7080 | hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3; |
7081 | |
7082 | if (ksz_alloc_mem(hw_priv)) |
7083 | goto pcidev_init_mem_err; |
7084 | |
7085 | hw_priv->hw.id = net_device_present; |
7086 | |
7087 | spin_lock_init(&hw_priv->hwlock); |
7088 | mutex_init(&hw_priv->lock); |
7089 | |
7090 | /* tasklet is enabled. */ |
7091 | tasklet_init(&hw_priv->rx_tasklet, rx_proc_task, |
7092 | (unsigned long) hw_priv); |
7093 | tasklet_init(&hw_priv->tx_tasklet, tx_proc_task, |
7094 | (unsigned long) hw_priv); |
7095 | |
7096 | /* tasklet_enable will decrement the atomic counter. */ |
7097 | tasklet_disable(&hw_priv->rx_tasklet); |
7098 | tasklet_disable(&hw_priv->tx_tasklet); |
7099 | |
7100 | for (i = 0; i < TOTAL_PORT_NUM; i++) |
7101 | init_waitqueue_head(&hw_priv->counter[i].counter); |
7102 | |
7103 | if (macaddr[0] != ':') |
7104 | get_mac_addr(hw_priv, macaddr, MAIN_PORT); |
7105 | |
7106 | /* Read MAC address and initialize override address if not overrided. */ |
7107 | hw_read_addr(hw); |
7108 | |
7109 | /* Multiple device interfaces mode requires a second MAC address. */ |
7110 | if (hw->dev_count > 1) { |
7111 | memcpy(sw->other_addr, hw->override_addr, MAC_ADDR_LEN); |
7112 | read_other_addr(hw); |
7113 | if (mac1addr[0] != ':') |
7114 | get_mac_addr(hw_priv, mac1addr, OTHER_PORT); |
7115 | } |
7116 | |
7117 | hw_setup(hw); |
7118 | if (hw->ksz_switch) |
7119 | sw_setup(hw); |
7120 | else { |
7121 | hw_priv->wol_support = WOL_SUPPORT; |
7122 | hw_priv->wol_enable = 0; |
7123 | } |
7124 | |
7125 | INIT_WORK(&hw_priv->mib_read, mib_read_work); |
7126 | |
7127 | /* 500 ms timeout */ |
7128 | ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000, |
7129 | mib_monitor, hw_priv); |
7130 | |
7131 | for (i = 0; i < hw->dev_count; i++) { |
7132 | dev = alloc_etherdev(sizeof(struct dev_priv)); |
7133 | if (!dev) |
7134 | goto pcidev_init_reg_err; |
7135 | info->netdev[i] = dev; |
7136 | |
7137 | priv = netdev_priv(dev); |
7138 | priv->adapter = hw_priv; |
7139 | priv->id = net_device_present++; |
7140 | |
7141 | port = &priv->port; |
7142 | port->port_cnt = port_count; |
7143 | port->mib_port_cnt = mib_port_count; |
7144 | port->first_port = i; |
7145 | port->flow_ctrl = PHY_FLOW_CTRL; |
7146 | |
7147 | port->hw = hw; |
7148 | port->linked = &hw->port_info[port->first_port]; |
7149 | |
7150 | for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) { |
7151 | hw->port_info[pi].port_id = pi; |
7152 | hw->port_info[pi].pdev = dev; |
7153 | hw->port_info[pi].state = media_disconnected; |
7154 | } |
7155 | |
7156 | dev->mem_start = (unsigned long) hw->io; |
7157 | dev->mem_end = dev->mem_start + reg_len - 1; |
7158 | dev->irq = pdev->irq; |
7159 | if (MAIN_PORT == i) |
7160 | memcpy(dev->dev_addr, hw_priv->hw.override_addr, |
7161 | MAC_ADDR_LEN); |
7162 | else { |
7163 | memcpy(dev->dev_addr, sw->other_addr, |
7164 | MAC_ADDR_LEN); |
7165 | if (!memcmp(sw->other_addr, hw->override_addr, |
7166 | MAC_ADDR_LEN)) |
7167 | dev->dev_addr[5] += port->first_port; |
7168 | } |
7169 | |
7170 | dev->netdev_ops = &netdev_ops; |
7171 | SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); |
7172 | if (register_netdev(dev)) |
7173 | goto pcidev_init_reg_err; |
7174 | port_set_power_saving(port, true); |
7175 | } |
7176 | |
7177 | pci_dev_get(hw_priv->pdev); |
7178 | pci_set_drvdata(pdev, info); |
7179 | return 0; |
7180 | |
7181 | pcidev_init_reg_err: |
7182 | for (i = 0; i < hw->dev_count; i++) { |
7183 | if (info->netdev[i]) { |
7184 | netdev_free(info->netdev[i]); |
7185 | info->netdev[i] = NULL; |
7186 | } |
7187 | } |
7188 | |
7189 | pcidev_init_mem_err: |
7190 | ksz_free_mem(hw_priv); |
7191 | kfree(hw->ksz_switch); |
7192 | |
7193 | pcidev_init_alloc_err: |
7194 | iounmap(hw->io); |
7195 | |
7196 | pcidev_init_io_err: |
7197 | kfree(info); |
7198 | |
7199 | pcidev_init_dev_err: |
7200 | release_mem_region(reg_base, reg_len); |
7201 | |
7202 | return result; |
7203 | } |
7204 | |
7205 | static void pcidev_exit(struct pci_dev *pdev) |
7206 | { |
7207 | int i; |
7208 | struct platform_info *info = pci_get_drvdata(pdev); |
7209 | struct dev_info *hw_priv = &info->dev_info; |
7210 | |
7211 | pci_set_drvdata(pdev, NULL); |
7212 | |
7213 | release_mem_region(pci_resource_start(pdev, 0), |
7214 | pci_resource_len(pdev, 0)); |
7215 | for (i = 0; i < hw_priv->hw.dev_count; i++) { |
7216 | if (info->netdev[i]) |
7217 | netdev_free(info->netdev[i]); |
7218 | } |
7219 | if (hw_priv->hw.io) |
7220 | iounmap(hw_priv->hw.io); |
7221 | ksz_free_mem(hw_priv); |
7222 | kfree(hw_priv->hw.ksz_switch); |
7223 | pci_dev_put(hw_priv->pdev); |
7224 | kfree(info); |
7225 | } |
7226 | |
7227 | #ifdef CONFIG_PM |
7228 | static int pcidev_resume(struct pci_dev *pdev) |
7229 | { |
7230 | int i; |
7231 | struct platform_info *info = pci_get_drvdata(pdev); |
7232 | struct dev_info *hw_priv = &info->dev_info; |
7233 | struct ksz_hw *hw = &hw_priv->hw; |
7234 | |
7235 | pci_set_power_state(pdev, PCI_D0); |
7236 | pci_restore_state(pdev); |
7237 | pci_enable_wake(pdev, PCI_D0, 0); |
7238 | |
7239 | if (hw_priv->wol_enable) |
7240 | hw_cfg_wol_pme(hw, 0); |
7241 | for (i = 0; i < hw->dev_count; i++) { |
7242 | if (info->netdev[i]) { |
7243 | struct net_device *dev = info->netdev[i]; |
7244 | |
7245 | if (netif_running(dev)) { |
7246 | netdev_open(dev); |
7247 | netif_device_attach(dev); |
7248 | } |
7249 | } |
7250 | } |
7251 | return 0; |
7252 | } |
7253 | |
7254 | static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state) |
7255 | { |
7256 | int i; |
7257 | struct platform_info *info = pci_get_drvdata(pdev); |
7258 | struct dev_info *hw_priv = &info->dev_info; |
7259 | struct ksz_hw *hw = &hw_priv->hw; |
7260 | |
7261 | /* Need to find a way to retrieve the device IP address. */ |
7262 | u8 net_addr[] = { 192, 168, 1, 1 }; |
7263 | |
7264 | for (i = 0; i < hw->dev_count; i++) { |
7265 | if (info->netdev[i]) { |
7266 | struct net_device *dev = info->netdev[i]; |
7267 | |
7268 | if (netif_running(dev)) { |
7269 | netif_device_detach(dev); |
7270 | netdev_close(dev); |
7271 | } |
7272 | } |
7273 | } |
7274 | if (hw_priv->wol_enable) { |
7275 | hw_enable_wol(hw, hw_priv->wol_enable, net_addr); |
7276 | hw_cfg_wol_pme(hw, 1); |
7277 | } |
7278 | |
7279 | pci_save_state(pdev); |
7280 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); |
7281 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
7282 | return 0; |
7283 | } |
7284 | #endif |
7285 | |
7286 | static char pcidev_name[] = "ksz884xp"; |
7287 | |
7288 | static struct pci_device_id pcidev_table[] = { |
7289 | { PCI_VENDOR_ID_MICREL_KS, 0x8841, |
7290 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
7291 | { PCI_VENDOR_ID_MICREL_KS, 0x8842, |
7292 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
7293 | { 0 } |
7294 | }; |
7295 | |
7296 | MODULE_DEVICE_TABLE(pci, pcidev_table); |
7297 | |
7298 | static struct pci_driver pci_device_driver = { |
7299 | #ifdef CONFIG_PM |
7300 | .suspend = pcidev_suspend, |
7301 | .resume = pcidev_resume, |
7302 | #endif |
7303 | .name = pcidev_name, |
7304 | .id_table = pcidev_table, |
7305 | .probe = pcidev_init, |
7306 | .remove = pcidev_exit |
7307 | }; |
7308 | |
7309 | static int __init ksz884x_init_module(void) |
7310 | { |
7311 | return pci_register_driver(&pci_device_driver); |
7312 | } |
7313 | |
7314 | static void __exit ksz884x_cleanup_module(void) |
7315 | { |
7316 | pci_unregister_driver(&pci_device_driver); |
7317 | } |
7318 | |
7319 | module_init(ksz884x_init_module); |
7320 | module_exit(ksz884x_cleanup_module); |
7321 | |
7322 | MODULE_DESCRIPTION("KSZ8841/2 PCI network driver"); |
7323 | MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>"); |
7324 | MODULE_LICENSE("GPL"); |
7325 | |
7326 | module_param_named(message, msg_enable, int, 0); |
7327 | MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)"); |
7328 | |
7329 | module_param(macaddr, charp, 0); |
7330 | module_param(mac1addr, charp, 0); |
7331 | module_param(fast_aging, int, 0); |
7332 | module_param(multi_dev, int, 0); |
7333 | module_param(stp, int, 0); |
7334 | MODULE_PARM_DESC(macaddr, "MAC address"); |
7335 | MODULE_PARM_DESC(mac1addr, "Second MAC address"); |
7336 | MODULE_PARM_DESC(fast_aging, "Fast aging"); |
7337 | MODULE_PARM_DESC(multi_dev, "Multiple device interfaces"); |
7338 | MODULE_PARM_DESC(stp, "STP support"); |
7339 |
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Tags:
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v2.6.34-rc5
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