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1 | /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ |
2 | /* |
3 | * Copyright 1996-1999 Thomas Bogendoerfer |
4 | * |
5 | * Derived from the lance driver written 1993,1994,1995 by Donald Becker. |
6 | * |
7 | * Copyright 1993 United States Government as represented by the |
8 | * Director, National Security Agency. |
9 | * |
10 | * This software may be used and distributed according to the terms |
11 | * of the GNU General Public License, incorporated herein by reference. |
12 | * |
13 | * This driver is for PCnet32 and PCnetPCI based ethercards |
14 | */ |
15 | /************************************************************************** |
16 | * 23 Oct, 2000. |
17 | * Fixed a few bugs, related to running the controller in 32bit mode. |
18 | * |
19 | * Carsten Langgaard, carstenl@mips.com |
20 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
21 | * |
22 | *************************************************************************/ |
23 | |
24 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
25 | |
26 | #define DRV_NAME "pcnet32" |
27 | #define DRV_VERSION "1.35" |
28 | #define DRV_RELDATE "21.Apr.2008" |
29 | #define PFX DRV_NAME ": " |
30 | |
31 | static const char *const version = |
32 | DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; |
33 | |
34 | #include <linux/module.h> |
35 | #include <linux/kernel.h> |
36 | #include <linux/sched.h> |
37 | #include <linux/string.h> |
38 | #include <linux/errno.h> |
39 | #include <linux/ioport.h> |
40 | #include <linux/slab.h> |
41 | #include <linux/interrupt.h> |
42 | #include <linux/pci.h> |
43 | #include <linux/delay.h> |
44 | #include <linux/init.h> |
45 | #include <linux/ethtool.h> |
46 | #include <linux/mii.h> |
47 | #include <linux/crc32.h> |
48 | #include <linux/netdevice.h> |
49 | #include <linux/etherdevice.h> |
50 | #include <linux/if_ether.h> |
51 | #include <linux/skbuff.h> |
52 | #include <linux/spinlock.h> |
53 | #include <linux/moduleparam.h> |
54 | #include <linux/bitops.h> |
55 | #include <linux/io.h> |
56 | #include <linux/uaccess.h> |
57 | |
58 | #include <asm/dma.h> |
59 | #include <asm/irq.h> |
60 | |
61 | /* |
62 | * PCI device identifiers for "new style" Linux PCI Device Drivers |
63 | */ |
64 | static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = { |
65 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), }, |
66 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), }, |
67 | |
68 | /* |
69 | * Adapters that were sold with IBM's RS/6000 or pSeries hardware have |
70 | * the incorrect vendor id. |
71 | */ |
72 | { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE), |
73 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, }, |
74 | |
75 | { } /* terminate list */ |
76 | }; |
77 | |
78 | MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); |
79 | |
80 | static int cards_found; |
81 | |
82 | /* |
83 | * VLB I/O addresses |
84 | */ |
85 | static unsigned int pcnet32_portlist[] __initdata = |
86 | { 0x300, 0x320, 0x340, 0x360, 0 }; |
87 | |
88 | static int pcnet32_debug; |
89 | static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ |
90 | static int pcnet32vlb; /* check for VLB cards ? */ |
91 | |
92 | static struct net_device *pcnet32_dev; |
93 | |
94 | static int max_interrupt_work = 2; |
95 | static int rx_copybreak = 200; |
96 | |
97 | #define PCNET32_PORT_AUI 0x00 |
98 | #define PCNET32_PORT_10BT 0x01 |
99 | #define PCNET32_PORT_GPSI 0x02 |
100 | #define PCNET32_PORT_MII 0x03 |
101 | |
102 | #define PCNET32_PORT_PORTSEL 0x03 |
103 | #define PCNET32_PORT_ASEL 0x04 |
104 | #define PCNET32_PORT_100 0x40 |
105 | #define PCNET32_PORT_FD 0x80 |
106 | |
107 | #define PCNET32_DMA_MASK 0xffffffff |
108 | |
109 | #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) |
110 | #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) |
111 | |
112 | /* |
113 | * table to translate option values from tulip |
114 | * to internal options |
115 | */ |
116 | static const unsigned char options_mapping[] = { |
117 | PCNET32_PORT_ASEL, /* 0 Auto-select */ |
118 | PCNET32_PORT_AUI, /* 1 BNC/AUI */ |
119 | PCNET32_PORT_AUI, /* 2 AUI/BNC */ |
120 | PCNET32_PORT_ASEL, /* 3 not supported */ |
121 | PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ |
122 | PCNET32_PORT_ASEL, /* 5 not supported */ |
123 | PCNET32_PORT_ASEL, /* 6 not supported */ |
124 | PCNET32_PORT_ASEL, /* 7 not supported */ |
125 | PCNET32_PORT_ASEL, /* 8 not supported */ |
126 | PCNET32_PORT_MII, /* 9 MII 10baseT */ |
127 | PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ |
128 | PCNET32_PORT_MII, /* 11 MII (autosel) */ |
129 | PCNET32_PORT_10BT, /* 12 10BaseT */ |
130 | PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ |
131 | /* 14 MII 100BaseTx-FD */ |
132 | PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, |
133 | PCNET32_PORT_ASEL /* 15 not supported */ |
134 | }; |
135 | |
136 | static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { |
137 | "Loopback test (offline)" |
138 | }; |
139 | |
140 | #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test) |
141 | |
142 | #define PCNET32_NUM_REGS 136 |
143 | |
144 | #define MAX_UNITS 8 /* More are supported, limit only on options */ |
145 | static int options[MAX_UNITS]; |
146 | static int full_duplex[MAX_UNITS]; |
147 | static int homepna[MAX_UNITS]; |
148 | |
149 | /* |
150 | * Theory of Operation |
151 | * |
152 | * This driver uses the same software structure as the normal lance |
153 | * driver. So look for a verbose description in lance.c. The differences |
154 | * to the normal lance driver is the use of the 32bit mode of PCnet32 |
155 | * and PCnetPCI chips. Because these chips are 32bit chips, there is no |
156 | * 16MB limitation and we don't need bounce buffers. |
157 | */ |
158 | |
159 | /* |
160 | * Set the number of Tx and Rx buffers, using Log_2(# buffers). |
161 | * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. |
162 | * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). |
163 | */ |
164 | #ifndef PCNET32_LOG_TX_BUFFERS |
165 | #define PCNET32_LOG_TX_BUFFERS 4 |
166 | #define PCNET32_LOG_RX_BUFFERS 5 |
167 | #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ |
168 | #define PCNET32_LOG_MAX_RX_BUFFERS 9 |
169 | #endif |
170 | |
171 | #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) |
172 | #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) |
173 | |
174 | #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) |
175 | #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) |
176 | |
177 | #define PKT_BUF_SKB 1544 |
178 | /* actual buffer length after being aligned */ |
179 | #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN) |
180 | /* chip wants twos complement of the (aligned) buffer length */ |
181 | #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB) |
182 | |
183 | /* Offsets from base I/O address. */ |
184 | #define PCNET32_WIO_RDP 0x10 |
185 | #define PCNET32_WIO_RAP 0x12 |
186 | #define PCNET32_WIO_RESET 0x14 |
187 | #define PCNET32_WIO_BDP 0x16 |
188 | |
189 | #define PCNET32_DWIO_RDP 0x10 |
190 | #define PCNET32_DWIO_RAP 0x14 |
191 | #define PCNET32_DWIO_RESET 0x18 |
192 | #define PCNET32_DWIO_BDP 0x1C |
193 | |
194 | #define PCNET32_TOTAL_SIZE 0x20 |
195 | |
196 | #define CSR0 0 |
197 | #define CSR0_INIT 0x1 |
198 | #define CSR0_START 0x2 |
199 | #define CSR0_STOP 0x4 |
200 | #define CSR0_TXPOLL 0x8 |
201 | #define CSR0_INTEN 0x40 |
202 | #define CSR0_IDON 0x0100 |
203 | #define CSR0_NORMAL (CSR0_START | CSR0_INTEN) |
204 | #define PCNET32_INIT_LOW 1 |
205 | #define PCNET32_INIT_HIGH 2 |
206 | #define CSR3 3 |
207 | #define CSR4 4 |
208 | #define CSR5 5 |
209 | #define CSR5_SUSPEND 0x0001 |
210 | #define CSR15 15 |
211 | #define PCNET32_MC_FILTER 8 |
212 | |
213 | #define PCNET32_79C970A 0x2621 |
214 | |
215 | /* The PCNET32 Rx and Tx ring descriptors. */ |
216 | struct pcnet32_rx_head { |
217 | __le32 base; |
218 | __le16 buf_length; /* two`s complement of length */ |
219 | __le16 status; |
220 | __le32 msg_length; |
221 | __le32 reserved; |
222 | }; |
223 | |
224 | struct pcnet32_tx_head { |
225 | __le32 base; |
226 | __le16 length; /* two`s complement of length */ |
227 | __le16 status; |
228 | __le32 misc; |
229 | __le32 reserved; |
230 | }; |
231 | |
232 | /* The PCNET32 32-Bit initialization block, described in databook. */ |
233 | struct pcnet32_init_block { |
234 | __le16 mode; |
235 | __le16 tlen_rlen; |
236 | u8 phys_addr[6]; |
237 | __le16 reserved; |
238 | __le32 filter[2]; |
239 | /* Receive and transmit ring base, along with extra bits. */ |
240 | __le32 rx_ring; |
241 | __le32 tx_ring; |
242 | }; |
243 | |
244 | /* PCnet32 access functions */ |
245 | struct pcnet32_access { |
246 | u16 (*read_csr) (unsigned long, int); |
247 | void (*write_csr) (unsigned long, int, u16); |
248 | u16 (*read_bcr) (unsigned long, int); |
249 | void (*write_bcr) (unsigned long, int, u16); |
250 | u16 (*read_rap) (unsigned long); |
251 | void (*write_rap) (unsigned long, u16); |
252 | void (*reset) (unsigned long); |
253 | }; |
254 | |
255 | /* |
256 | * The first field of pcnet32_private is read by the ethernet device |
257 | * so the structure should be allocated using pci_alloc_consistent(). |
258 | */ |
259 | struct pcnet32_private { |
260 | struct pcnet32_init_block *init_block; |
261 | /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ |
262 | struct pcnet32_rx_head *rx_ring; |
263 | struct pcnet32_tx_head *tx_ring; |
264 | dma_addr_t init_dma_addr;/* DMA address of beginning of the init block, |
265 | returned by pci_alloc_consistent */ |
266 | struct pci_dev *pci_dev; |
267 | const char *name; |
268 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
269 | struct sk_buff **tx_skbuff; |
270 | struct sk_buff **rx_skbuff; |
271 | dma_addr_t *tx_dma_addr; |
272 | dma_addr_t *rx_dma_addr; |
273 | struct pcnet32_access a; |
274 | spinlock_t lock; /* Guard lock */ |
275 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ |
276 | unsigned int rx_ring_size; /* current rx ring size */ |
277 | unsigned int tx_ring_size; /* current tx ring size */ |
278 | unsigned int rx_mod_mask; /* rx ring modular mask */ |
279 | unsigned int tx_mod_mask; /* tx ring modular mask */ |
280 | unsigned short rx_len_bits; |
281 | unsigned short tx_len_bits; |
282 | dma_addr_t rx_ring_dma_addr; |
283 | dma_addr_t tx_ring_dma_addr; |
284 | unsigned int dirty_rx, /* ring entries to be freed. */ |
285 | dirty_tx; |
286 | |
287 | struct net_device *dev; |
288 | struct napi_struct napi; |
289 | char tx_full; |
290 | char phycount; /* number of phys found */ |
291 | int options; |
292 | unsigned int shared_irq:1, /* shared irq possible */ |
293 | dxsuflo:1, /* disable transmit stop on uflo */ |
294 | mii:1; /* mii port available */ |
295 | struct net_device *next; |
296 | struct mii_if_info mii_if; |
297 | struct timer_list watchdog_timer; |
298 | struct timer_list blink_timer; |
299 | u32 msg_enable; /* debug message level */ |
300 | |
301 | /* each bit indicates an available PHY */ |
302 | u32 phymask; |
303 | unsigned short chip_version; /* which variant this is */ |
304 | }; |
305 | |
306 | static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); |
307 | static int pcnet32_probe1(unsigned long, int, struct pci_dev *); |
308 | static int pcnet32_open(struct net_device *); |
309 | static int pcnet32_init_ring(struct net_device *); |
310 | static netdev_tx_t pcnet32_start_xmit(struct sk_buff *, |
311 | struct net_device *); |
312 | static void pcnet32_tx_timeout(struct net_device *dev); |
313 | static irqreturn_t pcnet32_interrupt(int, void *); |
314 | static int pcnet32_close(struct net_device *); |
315 | static struct net_device_stats *pcnet32_get_stats(struct net_device *); |
316 | static void pcnet32_load_multicast(struct net_device *dev); |
317 | static void pcnet32_set_multicast_list(struct net_device *); |
318 | static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); |
319 | static void pcnet32_watchdog(struct net_device *); |
320 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num); |
321 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, |
322 | int val); |
323 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); |
324 | static void pcnet32_ethtool_test(struct net_device *dev, |
325 | struct ethtool_test *eth_test, u64 * data); |
326 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); |
327 | static int pcnet32_phys_id(struct net_device *dev, u32 data); |
328 | static void pcnet32_led_blink_callback(struct net_device *dev); |
329 | static int pcnet32_get_regs_len(struct net_device *dev); |
330 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
331 | void *ptr); |
332 | static void pcnet32_purge_tx_ring(struct net_device *dev); |
333 | static int pcnet32_alloc_ring(struct net_device *dev, const char *name); |
334 | static void pcnet32_free_ring(struct net_device *dev); |
335 | static void pcnet32_check_media(struct net_device *dev, int verbose); |
336 | |
337 | static u16 pcnet32_wio_read_csr(unsigned long addr, int index) |
338 | { |
339 | outw(index, addr + PCNET32_WIO_RAP); |
340 | return inw(addr + PCNET32_WIO_RDP); |
341 | } |
342 | |
343 | static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) |
344 | { |
345 | outw(index, addr + PCNET32_WIO_RAP); |
346 | outw(val, addr + PCNET32_WIO_RDP); |
347 | } |
348 | |
349 | static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) |
350 | { |
351 | outw(index, addr + PCNET32_WIO_RAP); |
352 | return inw(addr + PCNET32_WIO_BDP); |
353 | } |
354 | |
355 | static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) |
356 | { |
357 | outw(index, addr + PCNET32_WIO_RAP); |
358 | outw(val, addr + PCNET32_WIO_BDP); |
359 | } |
360 | |
361 | static u16 pcnet32_wio_read_rap(unsigned long addr) |
362 | { |
363 | return inw(addr + PCNET32_WIO_RAP); |
364 | } |
365 | |
366 | static void pcnet32_wio_write_rap(unsigned long addr, u16 val) |
367 | { |
368 | outw(val, addr + PCNET32_WIO_RAP); |
369 | } |
370 | |
371 | static void pcnet32_wio_reset(unsigned long addr) |
372 | { |
373 | inw(addr + PCNET32_WIO_RESET); |
374 | } |
375 | |
376 | static int pcnet32_wio_check(unsigned long addr) |
377 | { |
378 | outw(88, addr + PCNET32_WIO_RAP); |
379 | return (inw(addr + PCNET32_WIO_RAP) == 88); |
380 | } |
381 | |
382 | static struct pcnet32_access pcnet32_wio = { |
383 | .read_csr = pcnet32_wio_read_csr, |
384 | .write_csr = pcnet32_wio_write_csr, |
385 | .read_bcr = pcnet32_wio_read_bcr, |
386 | .write_bcr = pcnet32_wio_write_bcr, |
387 | .read_rap = pcnet32_wio_read_rap, |
388 | .write_rap = pcnet32_wio_write_rap, |
389 | .reset = pcnet32_wio_reset |
390 | }; |
391 | |
392 | static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) |
393 | { |
394 | outl(index, addr + PCNET32_DWIO_RAP); |
395 | return inl(addr + PCNET32_DWIO_RDP) & 0xffff; |
396 | } |
397 | |
398 | static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) |
399 | { |
400 | outl(index, addr + PCNET32_DWIO_RAP); |
401 | outl(val, addr + PCNET32_DWIO_RDP); |
402 | } |
403 | |
404 | static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) |
405 | { |
406 | outl(index, addr + PCNET32_DWIO_RAP); |
407 | return inl(addr + PCNET32_DWIO_BDP) & 0xffff; |
408 | } |
409 | |
410 | static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) |
411 | { |
412 | outl(index, addr + PCNET32_DWIO_RAP); |
413 | outl(val, addr + PCNET32_DWIO_BDP); |
414 | } |
415 | |
416 | static u16 pcnet32_dwio_read_rap(unsigned long addr) |
417 | { |
418 | return inl(addr + PCNET32_DWIO_RAP) & 0xffff; |
419 | } |
420 | |
421 | static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) |
422 | { |
423 | outl(val, addr + PCNET32_DWIO_RAP); |
424 | } |
425 | |
426 | static void pcnet32_dwio_reset(unsigned long addr) |
427 | { |
428 | inl(addr + PCNET32_DWIO_RESET); |
429 | } |
430 | |
431 | static int pcnet32_dwio_check(unsigned long addr) |
432 | { |
433 | outl(88, addr + PCNET32_DWIO_RAP); |
434 | return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88); |
435 | } |
436 | |
437 | static struct pcnet32_access pcnet32_dwio = { |
438 | .read_csr = pcnet32_dwio_read_csr, |
439 | .write_csr = pcnet32_dwio_write_csr, |
440 | .read_bcr = pcnet32_dwio_read_bcr, |
441 | .write_bcr = pcnet32_dwio_write_bcr, |
442 | .read_rap = pcnet32_dwio_read_rap, |
443 | .write_rap = pcnet32_dwio_write_rap, |
444 | .reset = pcnet32_dwio_reset |
445 | }; |
446 | |
447 | static void pcnet32_netif_stop(struct net_device *dev) |
448 | { |
449 | struct pcnet32_private *lp = netdev_priv(dev); |
450 | |
451 | dev->trans_start = jiffies; |
452 | napi_disable(&lp->napi); |
453 | netif_tx_disable(dev); |
454 | } |
455 | |
456 | static void pcnet32_netif_start(struct net_device *dev) |
457 | { |
458 | struct pcnet32_private *lp = netdev_priv(dev); |
459 | ulong ioaddr = dev->base_addr; |
460 | u16 val; |
461 | |
462 | netif_wake_queue(dev); |
463 | val = lp->a.read_csr(ioaddr, CSR3); |
464 | val &= 0x00ff; |
465 | lp->a.write_csr(ioaddr, CSR3, val); |
466 | napi_enable(&lp->napi); |
467 | } |
468 | |
469 | /* |
470 | * Allocate space for the new sized tx ring. |
471 | * Free old resources |
472 | * Save new resources. |
473 | * Any failure keeps old resources. |
474 | * Must be called with lp->lock held. |
475 | */ |
476 | static void pcnet32_realloc_tx_ring(struct net_device *dev, |
477 | struct pcnet32_private *lp, |
478 | unsigned int size) |
479 | { |
480 | dma_addr_t new_ring_dma_addr; |
481 | dma_addr_t *new_dma_addr_list; |
482 | struct pcnet32_tx_head *new_tx_ring; |
483 | struct sk_buff **new_skb_list; |
484 | |
485 | pcnet32_purge_tx_ring(dev); |
486 | |
487 | new_tx_ring = pci_alloc_consistent(lp->pci_dev, |
488 | sizeof(struct pcnet32_tx_head) * |
489 | (1 << size), |
490 | &new_ring_dma_addr); |
491 | if (new_tx_ring == NULL) { |
492 | netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); |
493 | return; |
494 | } |
495 | memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size)); |
496 | |
497 | new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t), |
498 | GFP_ATOMIC); |
499 | if (!new_dma_addr_list) { |
500 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
501 | goto free_new_tx_ring; |
502 | } |
503 | |
504 | new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *), |
505 | GFP_ATOMIC); |
506 | if (!new_skb_list) { |
507 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
508 | goto free_new_lists; |
509 | } |
510 | |
511 | kfree(lp->tx_skbuff); |
512 | kfree(lp->tx_dma_addr); |
513 | pci_free_consistent(lp->pci_dev, |
514 | sizeof(struct pcnet32_tx_head) * |
515 | lp->tx_ring_size, lp->tx_ring, |
516 | lp->tx_ring_dma_addr); |
517 | |
518 | lp->tx_ring_size = (1 << size); |
519 | lp->tx_mod_mask = lp->tx_ring_size - 1; |
520 | lp->tx_len_bits = (size << 12); |
521 | lp->tx_ring = new_tx_ring; |
522 | lp->tx_ring_dma_addr = new_ring_dma_addr; |
523 | lp->tx_dma_addr = new_dma_addr_list; |
524 | lp->tx_skbuff = new_skb_list; |
525 | return; |
526 | |
527 | free_new_lists: |
528 | kfree(new_dma_addr_list); |
529 | free_new_tx_ring: |
530 | pci_free_consistent(lp->pci_dev, |
531 | sizeof(struct pcnet32_tx_head) * |
532 | (1 << size), |
533 | new_tx_ring, |
534 | new_ring_dma_addr); |
535 | } |
536 | |
537 | /* |
538 | * Allocate space for the new sized rx ring. |
539 | * Re-use old receive buffers. |
540 | * alloc extra buffers |
541 | * free unneeded buffers |
542 | * free unneeded buffers |
543 | * Save new resources. |
544 | * Any failure keeps old resources. |
545 | * Must be called with lp->lock held. |
546 | */ |
547 | static void pcnet32_realloc_rx_ring(struct net_device *dev, |
548 | struct pcnet32_private *lp, |
549 | unsigned int size) |
550 | { |
551 | dma_addr_t new_ring_dma_addr; |
552 | dma_addr_t *new_dma_addr_list; |
553 | struct pcnet32_rx_head *new_rx_ring; |
554 | struct sk_buff **new_skb_list; |
555 | int new, overlap; |
556 | |
557 | new_rx_ring = pci_alloc_consistent(lp->pci_dev, |
558 | sizeof(struct pcnet32_rx_head) * |
559 | (1 << size), |
560 | &new_ring_dma_addr); |
561 | if (new_rx_ring == NULL) { |
562 | netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); |
563 | return; |
564 | } |
565 | memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size)); |
566 | |
567 | new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t), |
568 | GFP_ATOMIC); |
569 | if (!new_dma_addr_list) { |
570 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
571 | goto free_new_rx_ring; |
572 | } |
573 | |
574 | new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *), |
575 | GFP_ATOMIC); |
576 | if (!new_skb_list) { |
577 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
578 | goto free_new_lists; |
579 | } |
580 | |
581 | /* first copy the current receive buffers */ |
582 | overlap = min(size, lp->rx_ring_size); |
583 | for (new = 0; new < overlap; new++) { |
584 | new_rx_ring[new] = lp->rx_ring[new]; |
585 | new_dma_addr_list[new] = lp->rx_dma_addr[new]; |
586 | new_skb_list[new] = lp->rx_skbuff[new]; |
587 | } |
588 | /* now allocate any new buffers needed */ |
589 | for (; new < size; new++) { |
590 | struct sk_buff *rx_skbuff; |
591 | new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB); |
592 | rx_skbuff = new_skb_list[new]; |
593 | if (!rx_skbuff) { |
594 | /* keep the original lists and buffers */ |
595 | netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n", |
596 | __func__); |
597 | goto free_all_new; |
598 | } |
599 | skb_reserve(rx_skbuff, NET_IP_ALIGN); |
600 | |
601 | new_dma_addr_list[new] = |
602 | pci_map_single(lp->pci_dev, rx_skbuff->data, |
603 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
604 | new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); |
605 | new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE); |
606 | new_rx_ring[new].status = cpu_to_le16(0x8000); |
607 | } |
608 | /* and free any unneeded buffers */ |
609 | for (; new < lp->rx_ring_size; new++) { |
610 | if (lp->rx_skbuff[new]) { |
611 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new], |
612 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
613 | dev_kfree_skb(lp->rx_skbuff[new]); |
614 | } |
615 | } |
616 | |
617 | kfree(lp->rx_skbuff); |
618 | kfree(lp->rx_dma_addr); |
619 | pci_free_consistent(lp->pci_dev, |
620 | sizeof(struct pcnet32_rx_head) * |
621 | lp->rx_ring_size, lp->rx_ring, |
622 | lp->rx_ring_dma_addr); |
623 | |
624 | lp->rx_ring_size = (1 << size); |
625 | lp->rx_mod_mask = lp->rx_ring_size - 1; |
626 | lp->rx_len_bits = (size << 4); |
627 | lp->rx_ring = new_rx_ring; |
628 | lp->rx_ring_dma_addr = new_ring_dma_addr; |
629 | lp->rx_dma_addr = new_dma_addr_list; |
630 | lp->rx_skbuff = new_skb_list; |
631 | return; |
632 | |
633 | free_all_new: |
634 | while (--new >= lp->rx_ring_size) { |
635 | if (new_skb_list[new]) { |
636 | pci_unmap_single(lp->pci_dev, new_dma_addr_list[new], |
637 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
638 | dev_kfree_skb(new_skb_list[new]); |
639 | } |
640 | } |
641 | kfree(new_skb_list); |
642 | free_new_lists: |
643 | kfree(new_dma_addr_list); |
644 | free_new_rx_ring: |
645 | pci_free_consistent(lp->pci_dev, |
646 | sizeof(struct pcnet32_rx_head) * |
647 | (1 << size), |
648 | new_rx_ring, |
649 | new_ring_dma_addr); |
650 | return; |
651 | } |
652 | |
653 | static void pcnet32_purge_rx_ring(struct net_device *dev) |
654 | { |
655 | struct pcnet32_private *lp = netdev_priv(dev); |
656 | int i; |
657 | |
658 | /* free all allocated skbuffs */ |
659 | for (i = 0; i < lp->rx_ring_size; i++) { |
660 | lp->rx_ring[i].status = 0; /* CPU owns buffer */ |
661 | wmb(); /* Make sure adapter sees owner change */ |
662 | if (lp->rx_skbuff[i]) { |
663 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], |
664 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
665 | dev_kfree_skb_any(lp->rx_skbuff[i]); |
666 | } |
667 | lp->rx_skbuff[i] = NULL; |
668 | lp->rx_dma_addr[i] = 0; |
669 | } |
670 | } |
671 | |
672 | #ifdef CONFIG_NET_POLL_CONTROLLER |
673 | static void pcnet32_poll_controller(struct net_device *dev) |
674 | { |
675 | disable_irq(dev->irq); |
676 | pcnet32_interrupt(0, dev); |
677 | enable_irq(dev->irq); |
678 | } |
679 | #endif |
680 | |
681 | static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
682 | { |
683 | struct pcnet32_private *lp = netdev_priv(dev); |
684 | unsigned long flags; |
685 | int r = -EOPNOTSUPP; |
686 | |
687 | if (lp->mii) { |
688 | spin_lock_irqsave(&lp->lock, flags); |
689 | mii_ethtool_gset(&lp->mii_if, cmd); |
690 | spin_unlock_irqrestore(&lp->lock, flags); |
691 | r = 0; |
692 | } |
693 | return r; |
694 | } |
695 | |
696 | static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
697 | { |
698 | struct pcnet32_private *lp = netdev_priv(dev); |
699 | unsigned long flags; |
700 | int r = -EOPNOTSUPP; |
701 | |
702 | if (lp->mii) { |
703 | spin_lock_irqsave(&lp->lock, flags); |
704 | r = mii_ethtool_sset(&lp->mii_if, cmd); |
705 | spin_unlock_irqrestore(&lp->lock, flags); |
706 | } |
707 | return r; |
708 | } |
709 | |
710 | static void pcnet32_get_drvinfo(struct net_device *dev, |
711 | struct ethtool_drvinfo *info) |
712 | { |
713 | struct pcnet32_private *lp = netdev_priv(dev); |
714 | |
715 | strcpy(info->driver, DRV_NAME); |
716 | strcpy(info->version, DRV_VERSION); |
717 | if (lp->pci_dev) |
718 | strcpy(info->bus_info, pci_name(lp->pci_dev)); |
719 | else |
720 | sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr); |
721 | } |
722 | |
723 | static u32 pcnet32_get_link(struct net_device *dev) |
724 | { |
725 | struct pcnet32_private *lp = netdev_priv(dev); |
726 | unsigned long flags; |
727 | int r; |
728 | |
729 | spin_lock_irqsave(&lp->lock, flags); |
730 | if (lp->mii) { |
731 | r = mii_link_ok(&lp->mii_if); |
732 | } else if (lp->chip_version >= PCNET32_79C970A) { |
733 | ulong ioaddr = dev->base_addr; /* card base I/O address */ |
734 | r = (lp->a.read_bcr(ioaddr, 4) != 0xc0); |
735 | } else { /* can not detect link on really old chips */ |
736 | r = 1; |
737 | } |
738 | spin_unlock_irqrestore(&lp->lock, flags); |
739 | |
740 | return r; |
741 | } |
742 | |
743 | static u32 pcnet32_get_msglevel(struct net_device *dev) |
744 | { |
745 | struct pcnet32_private *lp = netdev_priv(dev); |
746 | return lp->msg_enable; |
747 | } |
748 | |
749 | static void pcnet32_set_msglevel(struct net_device *dev, u32 value) |
750 | { |
751 | struct pcnet32_private *lp = netdev_priv(dev); |
752 | lp->msg_enable = value; |
753 | } |
754 | |
755 | static int pcnet32_nway_reset(struct net_device *dev) |
756 | { |
757 | struct pcnet32_private *lp = netdev_priv(dev); |
758 | unsigned long flags; |
759 | int r = -EOPNOTSUPP; |
760 | |
761 | if (lp->mii) { |
762 | spin_lock_irqsave(&lp->lock, flags); |
763 | r = mii_nway_restart(&lp->mii_if); |
764 | spin_unlock_irqrestore(&lp->lock, flags); |
765 | } |
766 | return r; |
767 | } |
768 | |
769 | static void pcnet32_get_ringparam(struct net_device *dev, |
770 | struct ethtool_ringparam *ering) |
771 | { |
772 | struct pcnet32_private *lp = netdev_priv(dev); |
773 | |
774 | ering->tx_max_pending = TX_MAX_RING_SIZE; |
775 | ering->tx_pending = lp->tx_ring_size; |
776 | ering->rx_max_pending = RX_MAX_RING_SIZE; |
777 | ering->rx_pending = lp->rx_ring_size; |
778 | } |
779 | |
780 | static int pcnet32_set_ringparam(struct net_device *dev, |
781 | struct ethtool_ringparam *ering) |
782 | { |
783 | struct pcnet32_private *lp = netdev_priv(dev); |
784 | unsigned long flags; |
785 | unsigned int size; |
786 | ulong ioaddr = dev->base_addr; |
787 | int i; |
788 | |
789 | if (ering->rx_mini_pending || ering->rx_jumbo_pending) |
790 | return -EINVAL; |
791 | |
792 | if (netif_running(dev)) |
793 | pcnet32_netif_stop(dev); |
794 | |
795 | spin_lock_irqsave(&lp->lock, flags); |
796 | lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ |
797 | |
798 | size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); |
799 | |
800 | /* set the minimum ring size to 4, to allow the loopback test to work |
801 | * unchanged. |
802 | */ |
803 | for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { |
804 | if (size <= (1 << i)) |
805 | break; |
806 | } |
807 | if ((1 << i) != lp->tx_ring_size) |
808 | pcnet32_realloc_tx_ring(dev, lp, i); |
809 | |
810 | size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); |
811 | for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { |
812 | if (size <= (1 << i)) |
813 | break; |
814 | } |
815 | if ((1 << i) != lp->rx_ring_size) |
816 | pcnet32_realloc_rx_ring(dev, lp, i); |
817 | |
818 | lp->napi.weight = lp->rx_ring_size / 2; |
819 | |
820 | if (netif_running(dev)) { |
821 | pcnet32_netif_start(dev); |
822 | pcnet32_restart(dev, CSR0_NORMAL); |
823 | } |
824 | |
825 | spin_unlock_irqrestore(&lp->lock, flags); |
826 | |
827 | netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n", |
828 | lp->rx_ring_size, lp->tx_ring_size); |
829 | |
830 | return 0; |
831 | } |
832 | |
833 | static void pcnet32_get_strings(struct net_device *dev, u32 stringset, |
834 | u8 *data) |
835 | { |
836 | memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); |
837 | } |
838 | |
839 | static int pcnet32_get_sset_count(struct net_device *dev, int sset) |
840 | { |
841 | switch (sset) { |
842 | case ETH_SS_TEST: |
843 | return PCNET32_TEST_LEN; |
844 | default: |
845 | return -EOPNOTSUPP; |
846 | } |
847 | } |
848 | |
849 | static void pcnet32_ethtool_test(struct net_device *dev, |
850 | struct ethtool_test *test, u64 * data) |
851 | { |
852 | struct pcnet32_private *lp = netdev_priv(dev); |
853 | int rc; |
854 | |
855 | if (test->flags == ETH_TEST_FL_OFFLINE) { |
856 | rc = pcnet32_loopback_test(dev, data); |
857 | if (rc) { |
858 | netif_printk(lp, hw, KERN_DEBUG, dev, |
859 | "Loopback test failed\n"); |
860 | test->flags |= ETH_TEST_FL_FAILED; |
861 | } else |
862 | netif_printk(lp, hw, KERN_DEBUG, dev, |
863 | "Loopback test passed\n"); |
864 | } else |
865 | netif_printk(lp, hw, KERN_DEBUG, dev, |
866 | "No tests to run (specify 'Offline' on ethtool)\n"); |
867 | } /* end pcnet32_ethtool_test */ |
868 | |
869 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) |
870 | { |
871 | struct pcnet32_private *lp = netdev_priv(dev); |
872 | struct pcnet32_access *a = &lp->a; /* access to registers */ |
873 | ulong ioaddr = dev->base_addr; /* card base I/O address */ |
874 | struct sk_buff *skb; /* sk buff */ |
875 | int x, i; /* counters */ |
876 | int numbuffs = 4; /* number of TX/RX buffers and descs */ |
877 | u16 status = 0x8300; /* TX ring status */ |
878 | __le16 teststatus; /* test of ring status */ |
879 | int rc; /* return code */ |
880 | int size; /* size of packets */ |
881 | unsigned char *packet; /* source packet data */ |
882 | static const int data_len = 60; /* length of source packets */ |
883 | unsigned long flags; |
884 | unsigned long ticks; |
885 | |
886 | rc = 1; /* default to fail */ |
887 | |
888 | if (netif_running(dev)) |
889 | pcnet32_netif_stop(dev); |
890 | |
891 | spin_lock_irqsave(&lp->lock, flags); |
892 | lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ |
893 | |
894 | numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size)); |
895 | |
896 | /* Reset the PCNET32 */ |
897 | lp->a.reset(ioaddr); |
898 | lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ |
899 | |
900 | /* switch pcnet32 to 32bit mode */ |
901 | lp->a.write_bcr(ioaddr, 20, 2); |
902 | |
903 | /* purge & init rings but don't actually restart */ |
904 | pcnet32_restart(dev, 0x0000); |
905 | |
906 | lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ |
907 | |
908 | /* Initialize Transmit buffers. */ |
909 | size = data_len + 15; |
910 | for (x = 0; x < numbuffs; x++) { |
911 | skb = dev_alloc_skb(size); |
912 | if (!skb) { |
913 | netif_printk(lp, hw, KERN_DEBUG, dev, |
914 | "Cannot allocate skb at line: %d!\n", |
915 | __LINE__); |
916 | goto clean_up; |
917 | } |
918 | packet = skb->data; |
919 | skb_put(skb, size); /* create space for data */ |
920 | lp->tx_skbuff[x] = skb; |
921 | lp->tx_ring[x].length = cpu_to_le16(-skb->len); |
922 | lp->tx_ring[x].misc = 0; |
923 | |
924 | /* put DA and SA into the skb */ |
925 | for (i = 0; i < 6; i++) |
926 | *packet++ = dev->dev_addr[i]; |
927 | for (i = 0; i < 6; i++) |
928 | *packet++ = dev->dev_addr[i]; |
929 | /* type */ |
930 | *packet++ = 0x08; |
931 | *packet++ = 0x06; |
932 | /* packet number */ |
933 | *packet++ = x; |
934 | /* fill packet with data */ |
935 | for (i = 0; i < data_len; i++) |
936 | *packet++ = i; |
937 | |
938 | lp->tx_dma_addr[x] = |
939 | pci_map_single(lp->pci_dev, skb->data, skb->len, |
940 | PCI_DMA_TODEVICE); |
941 | lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); |
942 | wmb(); /* Make sure owner changes after all others are visible */ |
943 | lp->tx_ring[x].status = cpu_to_le16(status); |
944 | } |
945 | |
946 | x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */ |
947 | a->write_bcr(ioaddr, 32, x | 0x0002); |
948 | |
949 | /* set int loopback in CSR15 */ |
950 | x = a->read_csr(ioaddr, CSR15) & 0xfffc; |
951 | lp->a.write_csr(ioaddr, CSR15, x | 0x0044); |
952 | |
953 | teststatus = cpu_to_le16(0x8000); |
954 | lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ |
955 | |
956 | /* Check status of descriptors */ |
957 | for (x = 0; x < numbuffs; x++) { |
958 | ticks = 0; |
959 | rmb(); |
960 | while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { |
961 | spin_unlock_irqrestore(&lp->lock, flags); |
962 | msleep(1); |
963 | spin_lock_irqsave(&lp->lock, flags); |
964 | rmb(); |
965 | ticks++; |
966 | } |
967 | if (ticks == 200) { |
968 | netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x); |
969 | break; |
970 | } |
971 | } |
972 | |
973 | lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ |
974 | wmb(); |
975 | if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { |
976 | netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n"); |
977 | |
978 | for (x = 0; x < numbuffs; x++) { |
979 | netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x); |
980 | skb = lp->rx_skbuff[x]; |
981 | for (i = 0; i < size; i++) |
982 | pr_cont(" %02x", *(skb->data + i)); |
983 | pr_cont("\n"); |
984 | } |
985 | } |
986 | |
987 | x = 0; |
988 | rc = 0; |
989 | while (x < numbuffs && !rc) { |
990 | skb = lp->rx_skbuff[x]; |
991 | packet = lp->tx_skbuff[x]->data; |
992 | for (i = 0; i < size; i++) { |
993 | if (*(skb->data + i) != packet[i]) { |
994 | netif_printk(lp, hw, KERN_DEBUG, dev, |
995 | "Error in compare! %2x - %02x %02x\n", |
996 | i, *(skb->data + i), packet[i]); |
997 | rc = 1; |
998 | break; |
999 | } |
1000 | } |
1001 | x++; |
1002 | } |
1003 | |
1004 | clean_up: |
1005 | *data1 = rc; |
1006 | pcnet32_purge_tx_ring(dev); |
1007 | |
1008 | x = a->read_csr(ioaddr, CSR15); |
1009 | a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ |
1010 | |
1011 | x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ |
1012 | a->write_bcr(ioaddr, 32, (x & ~0x0002)); |
1013 | |
1014 | if (netif_running(dev)) { |
1015 | pcnet32_netif_start(dev); |
1016 | pcnet32_restart(dev, CSR0_NORMAL); |
1017 | } else { |
1018 | pcnet32_purge_rx_ring(dev); |
1019 | lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ |
1020 | } |
1021 | spin_unlock_irqrestore(&lp->lock, flags); |
1022 | |
1023 | return rc; |
1024 | } /* end pcnet32_loopback_test */ |
1025 | |
1026 | static void pcnet32_led_blink_callback(struct net_device *dev) |
1027 | { |
1028 | struct pcnet32_private *lp = netdev_priv(dev); |
1029 | struct pcnet32_access *a = &lp->a; |
1030 | ulong ioaddr = dev->base_addr; |
1031 | unsigned long flags; |
1032 | int i; |
1033 | |
1034 | spin_lock_irqsave(&lp->lock, flags); |
1035 | for (i = 4; i < 8; i++) |
1036 | a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); |
1037 | spin_unlock_irqrestore(&lp->lock, flags); |
1038 | |
1039 | mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT); |
1040 | } |
1041 | |
1042 | static int pcnet32_phys_id(struct net_device *dev, u32 data) |
1043 | { |
1044 | struct pcnet32_private *lp = netdev_priv(dev); |
1045 | struct pcnet32_access *a = &lp->a; |
1046 | ulong ioaddr = dev->base_addr; |
1047 | unsigned long flags; |
1048 | int i, regs[4]; |
1049 | |
1050 | if (!lp->blink_timer.function) { |
1051 | init_timer(&lp->blink_timer); |
1052 | lp->blink_timer.function = (void *)pcnet32_led_blink_callback; |
1053 | lp->blink_timer.data = (unsigned long)dev; |
1054 | } |
1055 | |
1056 | /* Save the current value of the bcrs */ |
1057 | spin_lock_irqsave(&lp->lock, flags); |
1058 | for (i = 4; i < 8; i++) |
1059 | regs[i - 4] = a->read_bcr(ioaddr, i); |
1060 | spin_unlock_irqrestore(&lp->lock, flags); |
1061 | |
1062 | mod_timer(&lp->blink_timer, jiffies); |
1063 | set_current_state(TASK_INTERRUPTIBLE); |
1064 | |
1065 | /* AV: the limit here makes no sense whatsoever */ |
1066 | if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))) |
1067 | data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ); |
1068 | |
1069 | msleep_interruptible(data * 1000); |
1070 | del_timer_sync(&lp->blink_timer); |
1071 | |
1072 | /* Restore the original value of the bcrs */ |
1073 | spin_lock_irqsave(&lp->lock, flags); |
1074 | for (i = 4; i < 8; i++) |
1075 | a->write_bcr(ioaddr, i, regs[i - 4]); |
1076 | spin_unlock_irqrestore(&lp->lock, flags); |
1077 | |
1078 | return 0; |
1079 | } |
1080 | |
1081 | /* |
1082 | * lp->lock must be held. |
1083 | */ |
1084 | static int pcnet32_suspend(struct net_device *dev, unsigned long *flags, |
1085 | int can_sleep) |
1086 | { |
1087 | int csr5; |
1088 | struct pcnet32_private *lp = netdev_priv(dev); |
1089 | struct pcnet32_access *a = &lp->a; |
1090 | ulong ioaddr = dev->base_addr; |
1091 | int ticks; |
1092 | |
1093 | /* really old chips have to be stopped. */ |
1094 | if (lp->chip_version < PCNET32_79C970A) |
1095 | return 0; |
1096 | |
1097 | /* set SUSPEND (SPND) - CSR5 bit 0 */ |
1098 | csr5 = a->read_csr(ioaddr, CSR5); |
1099 | a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); |
1100 | |
1101 | /* poll waiting for bit to be set */ |
1102 | ticks = 0; |
1103 | while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { |
1104 | spin_unlock_irqrestore(&lp->lock, *flags); |
1105 | if (can_sleep) |
1106 | msleep(1); |
1107 | else |
1108 | mdelay(1); |
1109 | spin_lock_irqsave(&lp->lock, *flags); |
1110 | ticks++; |
1111 | if (ticks > 200) { |
1112 | netif_printk(lp, hw, KERN_DEBUG, dev, |
1113 | "Error getting into suspend!\n"); |
1114 | return 0; |
1115 | } |
1116 | } |
1117 | return 1; |
1118 | } |
1119 | |
1120 | /* |
1121 | * process one receive descriptor entry |
1122 | */ |
1123 | |
1124 | static void pcnet32_rx_entry(struct net_device *dev, |
1125 | struct pcnet32_private *lp, |
1126 | struct pcnet32_rx_head *rxp, |
1127 | int entry) |
1128 | { |
1129 | int status = (short)le16_to_cpu(rxp->status) >> 8; |
1130 | int rx_in_place = 0; |
1131 | struct sk_buff *skb; |
1132 | short pkt_len; |
1133 | |
1134 | if (status != 0x03) { /* There was an error. */ |
1135 | /* |
1136 | * There is a tricky error noted by John Murphy, |
1137 | * <murf@perftech.com> to Russ Nelson: Even with full-sized |
1138 | * buffers it's possible for a jabber packet to use two |
1139 | * buffers, with only the last correctly noting the error. |
1140 | */ |
1141 | if (status & 0x01) /* Only count a general error at the */ |
1142 | dev->stats.rx_errors++; /* end of a packet. */ |
1143 | if (status & 0x20) |
1144 | dev->stats.rx_frame_errors++; |
1145 | if (status & 0x10) |
1146 | dev->stats.rx_over_errors++; |
1147 | if (status & 0x08) |
1148 | dev->stats.rx_crc_errors++; |
1149 | if (status & 0x04) |
1150 | dev->stats.rx_fifo_errors++; |
1151 | return; |
1152 | } |
1153 | |
1154 | pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4; |
1155 | |
1156 | /* Discard oversize frames. */ |
1157 | if (unlikely(pkt_len > PKT_BUF_SIZE)) { |
1158 | netif_err(lp, drv, dev, "Impossible packet size %d!\n", |
1159 | pkt_len); |
1160 | dev->stats.rx_errors++; |
1161 | return; |
1162 | } |
1163 | if (pkt_len < 60) { |
1164 | netif_err(lp, rx_err, dev, "Runt packet!\n"); |
1165 | dev->stats.rx_errors++; |
1166 | return; |
1167 | } |
1168 | |
1169 | if (pkt_len > rx_copybreak) { |
1170 | struct sk_buff *newskb; |
1171 | |
1172 | newskb = dev_alloc_skb(PKT_BUF_SKB); |
1173 | if (newskb) { |
1174 | skb_reserve(newskb, NET_IP_ALIGN); |
1175 | skb = lp->rx_skbuff[entry]; |
1176 | pci_unmap_single(lp->pci_dev, |
1177 | lp->rx_dma_addr[entry], |
1178 | PKT_BUF_SIZE, |
1179 | PCI_DMA_FROMDEVICE); |
1180 | skb_put(skb, pkt_len); |
1181 | lp->rx_skbuff[entry] = newskb; |
1182 | lp->rx_dma_addr[entry] = |
1183 | pci_map_single(lp->pci_dev, |
1184 | newskb->data, |
1185 | PKT_BUF_SIZE, |
1186 | PCI_DMA_FROMDEVICE); |
1187 | rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]); |
1188 | rx_in_place = 1; |
1189 | } else |
1190 | skb = NULL; |
1191 | } else |
1192 | skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN); |
1193 | |
1194 | if (skb == NULL) { |
1195 | netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n"); |
1196 | dev->stats.rx_dropped++; |
1197 | return; |
1198 | } |
1199 | if (!rx_in_place) { |
1200 | skb_reserve(skb, NET_IP_ALIGN); |
1201 | skb_put(skb, pkt_len); /* Make room */ |
1202 | pci_dma_sync_single_for_cpu(lp->pci_dev, |
1203 | lp->rx_dma_addr[entry], |
1204 | pkt_len, |
1205 | PCI_DMA_FROMDEVICE); |
1206 | skb_copy_to_linear_data(skb, |
1207 | (unsigned char *)(lp->rx_skbuff[entry]->data), |
1208 | pkt_len); |
1209 | pci_dma_sync_single_for_device(lp->pci_dev, |
1210 | lp->rx_dma_addr[entry], |
1211 | pkt_len, |
1212 | PCI_DMA_FROMDEVICE); |
1213 | } |
1214 | dev->stats.rx_bytes += skb->len; |
1215 | skb->protocol = eth_type_trans(skb, dev); |
1216 | netif_receive_skb(skb); |
1217 | dev->stats.rx_packets++; |
1218 | return; |
1219 | } |
1220 | |
1221 | static int pcnet32_rx(struct net_device *dev, int budget) |
1222 | { |
1223 | struct pcnet32_private *lp = netdev_priv(dev); |
1224 | int entry = lp->cur_rx & lp->rx_mod_mask; |
1225 | struct pcnet32_rx_head *rxp = &lp->rx_ring[entry]; |
1226 | int npackets = 0; |
1227 | |
1228 | /* If we own the next entry, it's a new packet. Send it up. */ |
1229 | while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) { |
1230 | pcnet32_rx_entry(dev, lp, rxp, entry); |
1231 | npackets += 1; |
1232 | /* |
1233 | * The docs say that the buffer length isn't touched, but Andrew |
1234 | * Boyd of QNX reports that some revs of the 79C965 clear it. |
1235 | */ |
1236 | rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE); |
1237 | wmb(); /* Make sure owner changes after others are visible */ |
1238 | rxp->status = cpu_to_le16(0x8000); |
1239 | entry = (++lp->cur_rx) & lp->rx_mod_mask; |
1240 | rxp = &lp->rx_ring[entry]; |
1241 | } |
1242 | |
1243 | return npackets; |
1244 | } |
1245 | |
1246 | static int pcnet32_tx(struct net_device *dev) |
1247 | { |
1248 | struct pcnet32_private *lp = netdev_priv(dev); |
1249 | unsigned int dirty_tx = lp->dirty_tx; |
1250 | int delta; |
1251 | int must_restart = 0; |
1252 | |
1253 | while (dirty_tx != lp->cur_tx) { |
1254 | int entry = dirty_tx & lp->tx_mod_mask; |
1255 | int status = (short)le16_to_cpu(lp->tx_ring[entry].status); |
1256 | |
1257 | if (status < 0) |
1258 | break; /* It still hasn't been Txed */ |
1259 | |
1260 | lp->tx_ring[entry].base = 0; |
1261 | |
1262 | if (status & 0x4000) { |
1263 | /* There was a major error, log it. */ |
1264 | int err_status = le32_to_cpu(lp->tx_ring[entry].misc); |
1265 | dev->stats.tx_errors++; |
1266 | netif_err(lp, tx_err, dev, |
1267 | "Tx error status=%04x err_status=%08x\n", |
1268 | status, err_status); |
1269 | if (err_status & 0x04000000) |
1270 | dev->stats.tx_aborted_errors++; |
1271 | if (err_status & 0x08000000) |
1272 | dev->stats.tx_carrier_errors++; |
1273 | if (err_status & 0x10000000) |
1274 | dev->stats.tx_window_errors++; |
1275 | #ifndef DO_DXSUFLO |
1276 | if (err_status & 0x40000000) { |
1277 | dev->stats.tx_fifo_errors++; |
1278 | /* Ackk! On FIFO errors the Tx unit is turned off! */ |
1279 | /* Remove this verbosity later! */ |
1280 | netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); |
1281 | must_restart = 1; |
1282 | } |
1283 | #else |
1284 | if (err_status & 0x40000000) { |
1285 | dev->stats.tx_fifo_errors++; |
1286 | if (!lp->dxsuflo) { /* If controller doesn't recover ... */ |
1287 | /* Ackk! On FIFO errors the Tx unit is turned off! */ |
1288 | /* Remove this verbosity later! */ |
1289 | netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); |
1290 | must_restart = 1; |
1291 | } |
1292 | } |
1293 | #endif |
1294 | } else { |
1295 | if (status & 0x1800) |
1296 | dev->stats.collisions++; |
1297 | dev->stats.tx_packets++; |
1298 | } |
1299 | |
1300 | /* We must free the original skb */ |
1301 | if (lp->tx_skbuff[entry]) { |
1302 | pci_unmap_single(lp->pci_dev, |
1303 | lp->tx_dma_addr[entry], |
1304 | lp->tx_skbuff[entry]-> |
1305 | len, PCI_DMA_TODEVICE); |
1306 | dev_kfree_skb_any(lp->tx_skbuff[entry]); |
1307 | lp->tx_skbuff[entry] = NULL; |
1308 | lp->tx_dma_addr[entry] = 0; |
1309 | } |
1310 | dirty_tx++; |
1311 | } |
1312 | |
1313 | delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); |
1314 | if (delta > lp->tx_ring_size) { |
1315 | netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n", |
1316 | dirty_tx, lp->cur_tx, lp->tx_full); |
1317 | dirty_tx += lp->tx_ring_size; |
1318 | delta -= lp->tx_ring_size; |
1319 | } |
1320 | |
1321 | if (lp->tx_full && |
1322 | netif_queue_stopped(dev) && |
1323 | delta < lp->tx_ring_size - 2) { |
1324 | /* The ring is no longer full, clear tbusy. */ |
1325 | lp->tx_full = 0; |
1326 | netif_wake_queue(dev); |
1327 | } |
1328 | lp->dirty_tx = dirty_tx; |
1329 | |
1330 | return must_restart; |
1331 | } |
1332 | |
1333 | static int pcnet32_poll(struct napi_struct *napi, int budget) |
1334 | { |
1335 | struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); |
1336 | struct net_device *dev = lp->dev; |
1337 | unsigned long ioaddr = dev->base_addr; |
1338 | unsigned long flags; |
1339 | int work_done; |
1340 | u16 val; |
1341 | |
1342 | work_done = pcnet32_rx(dev, budget); |
1343 | |
1344 | spin_lock_irqsave(&lp->lock, flags); |
1345 | if (pcnet32_tx(dev)) { |
1346 | /* reset the chip to clear the error condition, then restart */ |
1347 | lp->a.reset(ioaddr); |
1348 | lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ |
1349 | pcnet32_restart(dev, CSR0_START); |
1350 | netif_wake_queue(dev); |
1351 | } |
1352 | spin_unlock_irqrestore(&lp->lock, flags); |
1353 | |
1354 | if (work_done < budget) { |
1355 | spin_lock_irqsave(&lp->lock, flags); |
1356 | |
1357 | __napi_complete(napi); |
1358 | |
1359 | /* clear interrupt masks */ |
1360 | val = lp->a.read_csr(ioaddr, CSR3); |
1361 | val &= 0x00ff; |
1362 | lp->a.write_csr(ioaddr, CSR3, val); |
1363 | |
1364 | /* Set interrupt enable. */ |
1365 | lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN); |
1366 | |
1367 | spin_unlock_irqrestore(&lp->lock, flags); |
1368 | } |
1369 | return work_done; |
1370 | } |
1371 | |
1372 | #define PCNET32_REGS_PER_PHY 32 |
1373 | #define PCNET32_MAX_PHYS 32 |
1374 | static int pcnet32_get_regs_len(struct net_device *dev) |
1375 | { |
1376 | struct pcnet32_private *lp = netdev_priv(dev); |
1377 | int j = lp->phycount * PCNET32_REGS_PER_PHY; |
1378 | |
1379 | return (PCNET32_NUM_REGS + j) * sizeof(u16); |
1380 | } |
1381 | |
1382 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
1383 | void *ptr) |
1384 | { |
1385 | int i, csr0; |
1386 | u16 *buff = ptr; |
1387 | struct pcnet32_private *lp = netdev_priv(dev); |
1388 | struct pcnet32_access *a = &lp->a; |
1389 | ulong ioaddr = dev->base_addr; |
1390 | unsigned long flags; |
1391 | |
1392 | spin_lock_irqsave(&lp->lock, flags); |
1393 | |
1394 | csr0 = a->read_csr(ioaddr, CSR0); |
1395 | if (!(csr0 & CSR0_STOP)) /* If not stopped */ |
1396 | pcnet32_suspend(dev, &flags, 1); |
1397 | |
1398 | /* read address PROM */ |
1399 | for (i = 0; i < 16; i += 2) |
1400 | *buff++ = inw(ioaddr + i); |
1401 | |
1402 | /* read control and status registers */ |
1403 | for (i = 0; i < 90; i++) |
1404 | *buff++ = a->read_csr(ioaddr, i); |
1405 | |
1406 | *buff++ = a->read_csr(ioaddr, 112); |
1407 | *buff++ = a->read_csr(ioaddr, 114); |
1408 | |
1409 | /* read bus configuration registers */ |
1410 | for (i = 0; i < 30; i++) |
1411 | *buff++ = a->read_bcr(ioaddr, i); |
1412 | |
1413 | *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ |
1414 | |
1415 | for (i = 31; i < 36; i++) |
1416 | *buff++ = a->read_bcr(ioaddr, i); |
1417 | |
1418 | /* read mii phy registers */ |
1419 | if (lp->mii) { |
1420 | int j; |
1421 | for (j = 0; j < PCNET32_MAX_PHYS; j++) { |
1422 | if (lp->phymask & (1 << j)) { |
1423 | for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { |
1424 | lp->a.write_bcr(ioaddr, 33, |
1425 | (j << 5) | i); |
1426 | *buff++ = lp->a.read_bcr(ioaddr, 34); |
1427 | } |
1428 | } |
1429 | } |
1430 | } |
1431 | |
1432 | if (!(csr0 & CSR0_STOP)) { /* If not stopped */ |
1433 | int csr5; |
1434 | |
1435 | /* clear SUSPEND (SPND) - CSR5 bit 0 */ |
1436 | csr5 = a->read_csr(ioaddr, CSR5); |
1437 | a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); |
1438 | } |
1439 | |
1440 | spin_unlock_irqrestore(&lp->lock, flags); |
1441 | } |
1442 | |
1443 | static const struct ethtool_ops pcnet32_ethtool_ops = { |
1444 | .get_settings = pcnet32_get_settings, |
1445 | .set_settings = pcnet32_set_settings, |
1446 | .get_drvinfo = pcnet32_get_drvinfo, |
1447 | .get_msglevel = pcnet32_get_msglevel, |
1448 | .set_msglevel = pcnet32_set_msglevel, |
1449 | .nway_reset = pcnet32_nway_reset, |
1450 | .get_link = pcnet32_get_link, |
1451 | .get_ringparam = pcnet32_get_ringparam, |
1452 | .set_ringparam = pcnet32_set_ringparam, |
1453 | .get_strings = pcnet32_get_strings, |
1454 | .self_test = pcnet32_ethtool_test, |
1455 | .phys_id = pcnet32_phys_id, |
1456 | .get_regs_len = pcnet32_get_regs_len, |
1457 | .get_regs = pcnet32_get_regs, |
1458 | .get_sset_count = pcnet32_get_sset_count, |
1459 | }; |
1460 | |
1461 | /* only probes for non-PCI devices, the rest are handled by |
1462 | * pci_register_driver via pcnet32_probe_pci */ |
1463 | |
1464 | static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) |
1465 | { |
1466 | unsigned int *port, ioaddr; |
1467 | |
1468 | /* search for PCnet32 VLB cards at known addresses */ |
1469 | for (port = pcnet32_portlist; (ioaddr = *port); port++) { |
1470 | if (request_region |
1471 | (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { |
1472 | /* check if there is really a pcnet chip on that ioaddr */ |
1473 | if ((inb(ioaddr + 14) == 0x57) && |
1474 | (inb(ioaddr + 15) == 0x57)) { |
1475 | pcnet32_probe1(ioaddr, 0, NULL); |
1476 | } else { |
1477 | release_region(ioaddr, PCNET32_TOTAL_SIZE); |
1478 | } |
1479 | } |
1480 | } |
1481 | } |
1482 | |
1483 | static int __devinit |
1484 | pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) |
1485 | { |
1486 | unsigned long ioaddr; |
1487 | int err; |
1488 | |
1489 | err = pci_enable_device(pdev); |
1490 | if (err < 0) { |
1491 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1492 | pr_err("failed to enable device -- err=%d\n", err); |
1493 | return err; |
1494 | } |
1495 | pci_set_master(pdev); |
1496 | |
1497 | ioaddr = pci_resource_start(pdev, 0); |
1498 | if (!ioaddr) { |
1499 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1500 | pr_err("card has no PCI IO resources, aborting\n"); |
1501 | return -ENODEV; |
1502 | } |
1503 | |
1504 | if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) { |
1505 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1506 | pr_err("architecture does not support 32bit PCI busmaster DMA\n"); |
1507 | return -ENODEV; |
1508 | } |
1509 | if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) { |
1510 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1511 | pr_err("io address range already allocated\n"); |
1512 | return -EBUSY; |
1513 | } |
1514 | |
1515 | err = pcnet32_probe1(ioaddr, 1, pdev); |
1516 | if (err < 0) |
1517 | pci_disable_device(pdev); |
1518 | |
1519 | return err; |
1520 | } |
1521 | |
1522 | static const struct net_device_ops pcnet32_netdev_ops = { |
1523 | .ndo_open = pcnet32_open, |
1524 | .ndo_stop = pcnet32_close, |
1525 | .ndo_start_xmit = pcnet32_start_xmit, |
1526 | .ndo_tx_timeout = pcnet32_tx_timeout, |
1527 | .ndo_get_stats = pcnet32_get_stats, |
1528 | .ndo_set_multicast_list = pcnet32_set_multicast_list, |
1529 | .ndo_do_ioctl = pcnet32_ioctl, |
1530 | .ndo_change_mtu = eth_change_mtu, |
1531 | .ndo_set_mac_address = eth_mac_addr, |
1532 | .ndo_validate_addr = eth_validate_addr, |
1533 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1534 | .ndo_poll_controller = pcnet32_poll_controller, |
1535 | #endif |
1536 | }; |
1537 | |
1538 | /* pcnet32_probe1 |
1539 | * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. |
1540 | * pdev will be NULL when called from pcnet32_probe_vlbus. |
1541 | */ |
1542 | static int __devinit |
1543 | pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) |
1544 | { |
1545 | struct pcnet32_private *lp; |
1546 | int i, media; |
1547 | int fdx, mii, fset, dxsuflo; |
1548 | int chip_version; |
1549 | char *chipname; |
1550 | struct net_device *dev; |
1551 | struct pcnet32_access *a = NULL; |
1552 | u8 promaddr[6]; |
1553 | int ret = -ENODEV; |
1554 | |
1555 | /* reset the chip */ |
1556 | pcnet32_wio_reset(ioaddr); |
1557 | |
1558 | /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ |
1559 | if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { |
1560 | a = &pcnet32_wio; |
1561 | } else { |
1562 | pcnet32_dwio_reset(ioaddr); |
1563 | if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && |
1564 | pcnet32_dwio_check(ioaddr)) { |
1565 | a = &pcnet32_dwio; |
1566 | } else { |
1567 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1568 | pr_err("No access methods\n"); |
1569 | goto err_release_region; |
1570 | } |
1571 | } |
1572 | |
1573 | chip_version = |
1574 | a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); |
1575 | if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) |
1576 | pr_info(" PCnet chip version is %#x\n", chip_version); |
1577 | if ((chip_version & 0xfff) != 0x003) { |
1578 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1579 | pr_info("Unsupported chip version\n"); |
1580 | goto err_release_region; |
1581 | } |
1582 | |
1583 | /* initialize variables */ |
1584 | fdx = mii = fset = dxsuflo = 0; |
1585 | chip_version = (chip_version >> 12) & 0xffff; |
1586 | |
1587 | switch (chip_version) { |
1588 | case 0x2420: |
1589 | chipname = "PCnet/PCI 79C970"; /* PCI */ |
1590 | break; |
1591 | case 0x2430: |
1592 | if (shared) |
1593 | chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ |
1594 | else |
1595 | chipname = "PCnet/32 79C965"; /* 486/VL bus */ |
1596 | break; |
1597 | case 0x2621: |
1598 | chipname = "PCnet/PCI II 79C970A"; /* PCI */ |
1599 | fdx = 1; |
1600 | break; |
1601 | case 0x2623: |
1602 | chipname = "PCnet/FAST 79C971"; /* PCI */ |
1603 | fdx = 1; |
1604 | mii = 1; |
1605 | fset = 1; |
1606 | break; |
1607 | case 0x2624: |
1608 | chipname = "PCnet/FAST+ 79C972"; /* PCI */ |
1609 | fdx = 1; |
1610 | mii = 1; |
1611 | fset = 1; |
1612 | break; |
1613 | case 0x2625: |
1614 | chipname = "PCnet/FAST III 79C973"; /* PCI */ |
1615 | fdx = 1; |
1616 | mii = 1; |
1617 | break; |
1618 | case 0x2626: |
1619 | chipname = "PCnet/Home 79C978"; /* PCI */ |
1620 | fdx = 1; |
1621 | /* |
1622 | * This is based on specs published at www.amd.com. This section |
1623 | * assumes that a card with a 79C978 wants to go into standard |
1624 | * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, |
1625 | * and the module option homepna=1 can select this instead. |
1626 | */ |
1627 | media = a->read_bcr(ioaddr, 49); |
1628 | media &= ~3; /* default to 10Mb ethernet */ |
1629 | if (cards_found < MAX_UNITS && homepna[cards_found]) |
1630 | media |= 1; /* switch to home wiring mode */ |
1631 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1632 | printk(KERN_DEBUG PFX "media set to %sMbit mode\n", |
1633 | (media & 1) ? "1" : "10"); |
1634 | a->write_bcr(ioaddr, 49, media); |
1635 | break; |
1636 | case 0x2627: |
1637 | chipname = "PCnet/FAST III 79C975"; /* PCI */ |
1638 | fdx = 1; |
1639 | mii = 1; |
1640 | break; |
1641 | case 0x2628: |
1642 | chipname = "PCnet/PRO 79C976"; |
1643 | fdx = 1; |
1644 | mii = 1; |
1645 | break; |
1646 | default: |
1647 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1648 | pr_info("PCnet version %#x, no PCnet32 chip\n", |
1649 | chip_version); |
1650 | goto err_release_region; |
1651 | } |
1652 | |
1653 | /* |
1654 | * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit |
1655 | * starting until the packet is loaded. Strike one for reliability, lose |
1656 | * one for latency - although on PCI this isnt a big loss. Older chips |
1657 | * have FIFO's smaller than a packet, so you can't do this. |
1658 | * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. |
1659 | */ |
1660 | |
1661 | if (fset) { |
1662 | a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); |
1663 | a->write_csr(ioaddr, 80, |
1664 | (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); |
1665 | dxsuflo = 1; |
1666 | } |
1667 | |
1668 | dev = alloc_etherdev(sizeof(*lp)); |
1669 | if (!dev) { |
1670 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1671 | pr_err("Memory allocation failed\n"); |
1672 | ret = -ENOMEM; |
1673 | goto err_release_region; |
1674 | } |
1675 | |
1676 | if (pdev) |
1677 | SET_NETDEV_DEV(dev, &pdev->dev); |
1678 | |
1679 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1680 | pr_info("%s at %#3lx,", chipname, ioaddr); |
1681 | |
1682 | /* In most chips, after a chip reset, the ethernet address is read from the |
1683 | * station address PROM at the base address and programmed into the |
1684 | * "Physical Address Registers" CSR12-14. |
1685 | * As a precautionary measure, we read the PROM values and complain if |
1686 | * they disagree with the CSRs. If they miscompare, and the PROM addr |
1687 | * is valid, then the PROM addr is used. |
1688 | */ |
1689 | for (i = 0; i < 3; i++) { |
1690 | unsigned int val; |
1691 | val = a->read_csr(ioaddr, i + 12) & 0x0ffff; |
1692 | /* There may be endianness issues here. */ |
1693 | dev->dev_addr[2 * i] = val & 0x0ff; |
1694 | dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; |
1695 | } |
1696 | |
1697 | /* read PROM address and compare with CSR address */ |
1698 | for (i = 0; i < 6; i++) |
1699 | promaddr[i] = inb(ioaddr + i); |
1700 | |
1701 | if (memcmp(promaddr, dev->dev_addr, 6) || |
1702 | !is_valid_ether_addr(dev->dev_addr)) { |
1703 | if (is_valid_ether_addr(promaddr)) { |
1704 | if (pcnet32_debug & NETIF_MSG_PROBE) { |
1705 | pr_cont(" warning: CSR address invalid,\n"); |
1706 | pr_info(" using instead PROM address of"); |
1707 | } |
1708 | memcpy(dev->dev_addr, promaddr, 6); |
1709 | } |
1710 | } |
1711 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1712 | |
1713 | /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ |
1714 | if (!is_valid_ether_addr(dev->perm_addr)) |
1715 | memset(dev->dev_addr, 0, ETH_ALEN); |
1716 | |
1717 | if (pcnet32_debug & NETIF_MSG_PROBE) { |
1718 | pr_cont(" %pM", dev->dev_addr); |
1719 | |
1720 | /* Version 0x2623 and 0x2624 */ |
1721 | if (((chip_version + 1) & 0xfffe) == 0x2624) { |
1722 | i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ |
1723 | pr_info(" tx_start_pt(0x%04x):", i); |
1724 | switch (i >> 10) { |
1725 | case 0: |
1726 | pr_cont(" 20 bytes,"); |
1727 | break; |
1728 | case 1: |
1729 | pr_cont(" 64 bytes,"); |
1730 | break; |
1731 | case 2: |
1732 | pr_cont(" 128 bytes,"); |
1733 | break; |
1734 | case 3: |
1735 | pr_cont("~220 bytes,"); |
1736 | break; |
1737 | } |
1738 | i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ |
1739 | pr_cont(" BCR18(%x):", i & 0xffff); |
1740 | if (i & (1 << 5)) |
1741 | pr_cont("BurstWrEn "); |
1742 | if (i & (1 << 6)) |
1743 | pr_cont("BurstRdEn "); |
1744 | if (i & (1 << 7)) |
1745 | pr_cont("DWordIO "); |
1746 | if (i & (1 << 11)) |
1747 | pr_cont("NoUFlow "); |
1748 | i = a->read_bcr(ioaddr, 25); |
1749 | pr_info(" SRAMSIZE=0x%04x,", i << 8); |
1750 | i = a->read_bcr(ioaddr, 26); |
1751 | pr_cont(" SRAM_BND=0x%04x,", i << 8); |
1752 | i = a->read_bcr(ioaddr, 27); |
1753 | if (i & (1 << 14)) |
1754 | pr_cont("LowLatRx"); |
1755 | } |
1756 | } |
1757 | |
1758 | dev->base_addr = ioaddr; |
1759 | lp = netdev_priv(dev); |
1760 | /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ |
1761 | lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block), |
1762 | &lp->init_dma_addr); |
1763 | if (!lp->init_block) { |
1764 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1765 | pr_err("Consistent memory allocation failed\n"); |
1766 | ret = -ENOMEM; |
1767 | goto err_free_netdev; |
1768 | } |
1769 | lp->pci_dev = pdev; |
1770 | |
1771 | lp->dev = dev; |
1772 | |
1773 | spin_lock_init(&lp->lock); |
1774 | |
1775 | lp->name = chipname; |
1776 | lp->shared_irq = shared; |
1777 | lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ |
1778 | lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ |
1779 | lp->tx_mod_mask = lp->tx_ring_size - 1; |
1780 | lp->rx_mod_mask = lp->rx_ring_size - 1; |
1781 | lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); |
1782 | lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); |
1783 | lp->mii_if.full_duplex = fdx; |
1784 | lp->mii_if.phy_id_mask = 0x1f; |
1785 | lp->mii_if.reg_num_mask = 0x1f; |
1786 | lp->dxsuflo = dxsuflo; |
1787 | lp->mii = mii; |
1788 | lp->chip_version = chip_version; |
1789 | lp->msg_enable = pcnet32_debug; |
1790 | if ((cards_found >= MAX_UNITS) || |
1791 | (options[cards_found] >= sizeof(options_mapping))) |
1792 | lp->options = PCNET32_PORT_ASEL; |
1793 | else |
1794 | lp->options = options_mapping[options[cards_found]]; |
1795 | lp->mii_if.dev = dev; |
1796 | lp->mii_if.mdio_read = mdio_read; |
1797 | lp->mii_if.mdio_write = mdio_write; |
1798 | |
1799 | /* napi.weight is used in both the napi and non-napi cases */ |
1800 | lp->napi.weight = lp->rx_ring_size / 2; |
1801 | |
1802 | netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2); |
1803 | |
1804 | if (fdx && !(lp->options & PCNET32_PORT_ASEL) && |
1805 | ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) |
1806 | lp->options |= PCNET32_PORT_FD; |
1807 | |
1808 | lp->a = *a; |
1809 | |
1810 | /* prior to register_netdev, dev->name is not yet correct */ |
1811 | if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { |
1812 | ret = -ENOMEM; |
1813 | goto err_free_ring; |
1814 | } |
1815 | /* detect special T1/E1 WAN card by checking for MAC address */ |
1816 | if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && |
1817 | dev->dev_addr[2] == 0x75) |
1818 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; |
1819 | |
1820 | lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */ |
1821 | lp->init_block->tlen_rlen = |
1822 | cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); |
1823 | for (i = 0; i < 6; i++) |
1824 | lp->init_block->phys_addr[i] = dev->dev_addr[i]; |
1825 | lp->init_block->filter[0] = 0x00000000; |
1826 | lp->init_block->filter[1] = 0x00000000; |
1827 | lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); |
1828 | lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); |
1829 | |
1830 | /* switch pcnet32 to 32bit mode */ |
1831 | a->write_bcr(ioaddr, 20, 2); |
1832 | |
1833 | a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); |
1834 | a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); |
1835 | |
1836 | if (pdev) { /* use the IRQ provided by PCI */ |
1837 | dev->irq = pdev->irq; |
1838 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1839 | pr_cont(" assigned IRQ %d\n", dev->irq); |
1840 | } else { |
1841 | unsigned long irq_mask = probe_irq_on(); |
1842 | |
1843 | /* |
1844 | * To auto-IRQ we enable the initialization-done and DMA error |
1845 | * interrupts. For ISA boards we get a DMA error, but VLB and PCI |
1846 | * boards will work. |
1847 | */ |
1848 | /* Trigger an initialization just for the interrupt. */ |
1849 | a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); |
1850 | mdelay(1); |
1851 | |
1852 | dev->irq = probe_irq_off(irq_mask); |
1853 | if (!dev->irq) { |
1854 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1855 | pr_cont(", failed to detect IRQ line\n"); |
1856 | ret = -ENODEV; |
1857 | goto err_free_ring; |
1858 | } |
1859 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1860 | pr_cont(", probed IRQ %d\n", dev->irq); |
1861 | } |
1862 | |
1863 | /* Set the mii phy_id so that we can query the link state */ |
1864 | if (lp->mii) { |
1865 | /* lp->phycount and lp->phymask are set to 0 by memset above */ |
1866 | |
1867 | lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f; |
1868 | /* scan for PHYs */ |
1869 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { |
1870 | unsigned short id1, id2; |
1871 | |
1872 | id1 = mdio_read(dev, i, MII_PHYSID1); |
1873 | if (id1 == 0xffff) |
1874 | continue; |
1875 | id2 = mdio_read(dev, i, MII_PHYSID2); |
1876 | if (id2 == 0xffff) |
1877 | continue; |
1878 | if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) |
1879 | continue; /* 79C971 & 79C972 have phantom phy at id 31 */ |
1880 | lp->phycount++; |
1881 | lp->phymask |= (1 << i); |
1882 | lp->mii_if.phy_id = i; |
1883 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1884 | pr_info("Found PHY %04x:%04x at address %d\n", |
1885 | id1, id2, i); |
1886 | } |
1887 | lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); |
1888 | if (lp->phycount > 1) |
1889 | lp->options |= PCNET32_PORT_MII; |
1890 | } |
1891 | |
1892 | init_timer(&lp->watchdog_timer); |
1893 | lp->watchdog_timer.data = (unsigned long)dev; |
1894 | lp->watchdog_timer.function = (void *)&pcnet32_watchdog; |
1895 | |
1896 | /* The PCNET32-specific entries in the device structure. */ |
1897 | dev->netdev_ops = &pcnet32_netdev_ops; |
1898 | dev->ethtool_ops = &pcnet32_ethtool_ops; |
1899 | dev->watchdog_timeo = (5 * HZ); |
1900 | |
1901 | /* Fill in the generic fields of the device structure. */ |
1902 | if (register_netdev(dev)) |
1903 | goto err_free_ring; |
1904 | |
1905 | if (pdev) { |
1906 | pci_set_drvdata(pdev, dev); |
1907 | } else { |
1908 | lp->next = pcnet32_dev; |
1909 | pcnet32_dev = dev; |
1910 | } |
1911 | |
1912 | if (pcnet32_debug & NETIF_MSG_PROBE) |
1913 | pr_info("%s: registered as %s\n", dev->name, lp->name); |
1914 | cards_found++; |
1915 | |
1916 | /* enable LED writes */ |
1917 | a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); |
1918 | |
1919 | return 0; |
1920 | |
1921 | err_free_ring: |
1922 | pcnet32_free_ring(dev); |
1923 | pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), |
1924 | lp->init_block, lp->init_dma_addr); |
1925 | err_free_netdev: |
1926 | free_netdev(dev); |
1927 | err_release_region: |
1928 | release_region(ioaddr, PCNET32_TOTAL_SIZE); |
1929 | return ret; |
1930 | } |
1931 | |
1932 | /* if any allocation fails, caller must also call pcnet32_free_ring */ |
1933 | static int pcnet32_alloc_ring(struct net_device *dev, const char *name) |
1934 | { |
1935 | struct pcnet32_private *lp = netdev_priv(dev); |
1936 | |
1937 | lp->tx_ring = pci_alloc_consistent(lp->pci_dev, |
1938 | sizeof(struct pcnet32_tx_head) * |
1939 | lp->tx_ring_size, |
1940 | &lp->tx_ring_dma_addr); |
1941 | if (lp->tx_ring == NULL) { |
1942 | netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); |
1943 | return -ENOMEM; |
1944 | } |
1945 | |
1946 | lp->rx_ring = pci_alloc_consistent(lp->pci_dev, |
1947 | sizeof(struct pcnet32_rx_head) * |
1948 | lp->rx_ring_size, |
1949 | &lp->rx_ring_dma_addr); |
1950 | if (lp->rx_ring == NULL) { |
1951 | netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); |
1952 | return -ENOMEM; |
1953 | } |
1954 | |
1955 | lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t), |
1956 | GFP_ATOMIC); |
1957 | if (!lp->tx_dma_addr) { |
1958 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
1959 | return -ENOMEM; |
1960 | } |
1961 | |
1962 | lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t), |
1963 | GFP_ATOMIC); |
1964 | if (!lp->rx_dma_addr) { |
1965 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
1966 | return -ENOMEM; |
1967 | } |
1968 | |
1969 | lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *), |
1970 | GFP_ATOMIC); |
1971 | if (!lp->tx_skbuff) { |
1972 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
1973 | return -ENOMEM; |
1974 | } |
1975 | |
1976 | lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *), |
1977 | GFP_ATOMIC); |
1978 | if (!lp->rx_skbuff) { |
1979 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
1980 | return -ENOMEM; |
1981 | } |
1982 | |
1983 | return 0; |
1984 | } |
1985 | |
1986 | static void pcnet32_free_ring(struct net_device *dev) |
1987 | { |
1988 | struct pcnet32_private *lp = netdev_priv(dev); |
1989 | |
1990 | kfree(lp->tx_skbuff); |
1991 | lp->tx_skbuff = NULL; |
1992 | |
1993 | kfree(lp->rx_skbuff); |
1994 | lp->rx_skbuff = NULL; |
1995 | |
1996 | kfree(lp->tx_dma_addr); |
1997 | lp->tx_dma_addr = NULL; |
1998 | |
1999 | kfree(lp->rx_dma_addr); |
2000 | lp->rx_dma_addr = NULL; |
2001 | |
2002 | if (lp->tx_ring) { |
2003 | pci_free_consistent(lp->pci_dev, |
2004 | sizeof(struct pcnet32_tx_head) * |
2005 | lp->tx_ring_size, lp->tx_ring, |
2006 | lp->tx_ring_dma_addr); |
2007 | lp->tx_ring = NULL; |
2008 | } |
2009 | |
2010 | if (lp->rx_ring) { |
2011 | pci_free_consistent(lp->pci_dev, |
2012 | sizeof(struct pcnet32_rx_head) * |
2013 | lp->rx_ring_size, lp->rx_ring, |
2014 | lp->rx_ring_dma_addr); |
2015 | lp->rx_ring = NULL; |
2016 | } |
2017 | } |
2018 | |
2019 | static int pcnet32_open(struct net_device *dev) |
2020 | { |
2021 | struct pcnet32_private *lp = netdev_priv(dev); |
2022 | struct pci_dev *pdev = lp->pci_dev; |
2023 | unsigned long ioaddr = dev->base_addr; |
2024 | u16 val; |
2025 | int i; |
2026 | int rc; |
2027 | unsigned long flags; |
2028 | |
2029 | if (request_irq(dev->irq, pcnet32_interrupt, |
2030 | lp->shared_irq ? IRQF_SHARED : 0, dev->name, |
2031 | (void *)dev)) { |
2032 | return -EAGAIN; |
2033 | } |
2034 | |
2035 | spin_lock_irqsave(&lp->lock, flags); |
2036 | /* Check for a valid station address */ |
2037 | if (!is_valid_ether_addr(dev->dev_addr)) { |
2038 | rc = -EINVAL; |
2039 | goto err_free_irq; |
2040 | } |
2041 | |
2042 | /* Reset the PCNET32 */ |
2043 | lp->a.reset(ioaddr); |
2044 | |
2045 | /* switch pcnet32 to 32bit mode */ |
2046 | lp->a.write_bcr(ioaddr, 20, 2); |
2047 | |
2048 | netif_printk(lp, ifup, KERN_DEBUG, dev, |
2049 | "%s() irq %d tx/rx rings %#x/%#x init %#x\n", |
2050 | __func__, dev->irq, (u32) (lp->tx_ring_dma_addr), |
2051 | (u32) (lp->rx_ring_dma_addr), |
2052 | (u32) (lp->init_dma_addr)); |
2053 | |
2054 | /* set/reset autoselect bit */ |
2055 | val = lp->a.read_bcr(ioaddr, 2) & ~2; |
2056 | if (lp->options & PCNET32_PORT_ASEL) |
2057 | val |= 2; |
2058 | lp->a.write_bcr(ioaddr, 2, val); |
2059 | |
2060 | /* handle full duplex setting */ |
2061 | if (lp->mii_if.full_duplex) { |
2062 | val = lp->a.read_bcr(ioaddr, 9) & ~3; |
2063 | if (lp->options & PCNET32_PORT_FD) { |
2064 | val |= 1; |
2065 | if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) |
2066 | val |= 2; |
2067 | } else if (lp->options & PCNET32_PORT_ASEL) { |
2068 | /* workaround of xSeries250, turn on for 79C975 only */ |
2069 | if (lp->chip_version == 0x2627) |
2070 | val |= 3; |
2071 | } |
2072 | lp->a.write_bcr(ioaddr, 9, val); |
2073 | } |
2074 | |
2075 | /* set/reset GPSI bit in test register */ |
2076 | val = lp->a.read_csr(ioaddr, 124) & ~0x10; |
2077 | if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) |
2078 | val |= 0x10; |
2079 | lp->a.write_csr(ioaddr, 124, val); |
2080 | |
2081 | /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ |
2082 | if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT && |
2083 | (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || |
2084 | pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { |
2085 | if (lp->options & PCNET32_PORT_ASEL) { |
2086 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; |
2087 | netif_printk(lp, link, KERN_DEBUG, dev, |
2088 | "Setting 100Mb-Full Duplex\n"); |
2089 | } |
2090 | } |
2091 | if (lp->phycount < 2) { |
2092 | /* |
2093 | * 24 Jun 2004 according AMD, in order to change the PHY, |
2094 | * DANAS (or DISPM for 79C976) must be set; then select the speed, |
2095 | * duplex, and/or enable auto negotiation, and clear DANAS |
2096 | */ |
2097 | if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { |
2098 | lp->a.write_bcr(ioaddr, 32, |
2099 | lp->a.read_bcr(ioaddr, 32) | 0x0080); |
2100 | /* disable Auto Negotiation, set 10Mpbs, HD */ |
2101 | val = lp->a.read_bcr(ioaddr, 32) & ~0xb8; |
2102 | if (lp->options & PCNET32_PORT_FD) |
2103 | val |= 0x10; |
2104 | if (lp->options & PCNET32_PORT_100) |
2105 | val |= 0x08; |
2106 | lp->a.write_bcr(ioaddr, 32, val); |
2107 | } else { |
2108 | if (lp->options & PCNET32_PORT_ASEL) { |
2109 | lp->a.write_bcr(ioaddr, 32, |
2110 | lp->a.read_bcr(ioaddr, |
2111 | 32) | 0x0080); |
2112 | /* enable auto negotiate, setup, disable fd */ |
2113 | val = lp->a.read_bcr(ioaddr, 32) & ~0x98; |
2114 | val |= 0x20; |
2115 | lp->a.write_bcr(ioaddr, 32, val); |
2116 | } |
2117 | } |
2118 | } else { |
2119 | int first_phy = -1; |
2120 | u16 bmcr; |
2121 | u32 bcr9; |
2122 | struct ethtool_cmd ecmd; |
2123 | |
2124 | /* |
2125 | * There is really no good other way to handle multiple PHYs |
2126 | * other than turning off all automatics |
2127 | */ |
2128 | val = lp->a.read_bcr(ioaddr, 2); |
2129 | lp->a.write_bcr(ioaddr, 2, val & ~2); |
2130 | val = lp->a.read_bcr(ioaddr, 32); |
2131 | lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ |
2132 | |
2133 | if (!(lp->options & PCNET32_PORT_ASEL)) { |
2134 | /* setup ecmd */ |
2135 | ecmd.port = PORT_MII; |
2136 | ecmd.transceiver = XCVR_INTERNAL; |
2137 | ecmd.autoneg = AUTONEG_DISABLE; |
2138 | ecmd.speed = |
2139 | lp-> |
2140 | options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10; |
2141 | bcr9 = lp->a.read_bcr(ioaddr, 9); |
2142 | |
2143 | if (lp->options & PCNET32_PORT_FD) { |
2144 | ecmd.duplex = DUPLEX_FULL; |
2145 | bcr9 |= (1 << 0); |
2146 | } else { |
2147 | ecmd.duplex = DUPLEX_HALF; |
2148 | bcr9 |= ~(1 << 0); |
2149 | } |
2150 | lp->a.write_bcr(ioaddr, 9, bcr9); |
2151 | } |
2152 | |
2153 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { |
2154 | if (lp->phymask & (1 << i)) { |
2155 | /* isolate all but the first PHY */ |
2156 | bmcr = mdio_read(dev, i, MII_BMCR); |
2157 | if (first_phy == -1) { |
2158 | first_phy = i; |
2159 | mdio_write(dev, i, MII_BMCR, |
2160 | bmcr & ~BMCR_ISOLATE); |
2161 | } else { |
2162 | mdio_write(dev, i, MII_BMCR, |
2163 | bmcr | BMCR_ISOLATE); |
2164 | } |
2165 | /* use mii_ethtool_sset to setup PHY */ |
2166 | lp->mii_if.phy_id = i; |
2167 | ecmd.phy_address = i; |
2168 | if (lp->options & PCNET32_PORT_ASEL) { |
2169 | mii_ethtool_gset(&lp->mii_if, &ecmd); |
2170 | ecmd.autoneg = AUTONEG_ENABLE; |
2171 | } |
2172 | mii_ethtool_sset(&lp->mii_if, &ecmd); |
2173 | } |
2174 | } |
2175 | lp->mii_if.phy_id = first_phy; |
2176 | netif_info(lp, link, dev, "Using PHY number %d\n", first_phy); |
2177 | } |
2178 | |
2179 | #ifdef DO_DXSUFLO |
2180 | if (lp->dxsuflo) { /* Disable transmit stop on underflow */ |
2181 | val = lp->a.read_csr(ioaddr, CSR3); |
2182 | val |= 0x40; |
2183 | lp->a.write_csr(ioaddr, CSR3, val); |
2184 | } |
2185 | #endif |
2186 | |
2187 | lp->init_block->mode = |
2188 | cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); |
2189 | pcnet32_load_multicast(dev); |
2190 | |
2191 | if (pcnet32_init_ring(dev)) { |
2192 | rc = -ENOMEM; |
2193 | goto err_free_ring; |
2194 | } |
2195 | |
2196 | napi_enable(&lp->napi); |
2197 | |
2198 | /* Re-initialize the PCNET32, and start it when done. */ |
2199 | lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); |
2200 | lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); |
2201 | |
2202 | lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ |
2203 | lp->a.write_csr(ioaddr, CSR0, CSR0_INIT); |
2204 | |
2205 | netif_start_queue(dev); |
2206 | |
2207 | if (lp->chip_version >= PCNET32_79C970A) { |
2208 | /* Print the link status and start the watchdog */ |
2209 | pcnet32_check_media(dev, 1); |
2210 | mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT); |
2211 | } |
2212 | |
2213 | i = 0; |
2214 | while (i++ < 100) |
2215 | if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON) |
2216 | break; |
2217 | /* |
2218 | * We used to clear the InitDone bit, 0x0100, here but Mark Stockton |
2219 | * reports that doing so triggers a bug in the '974. |
2220 | */ |
2221 | lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL); |
2222 | |
2223 | netif_printk(lp, ifup, KERN_DEBUG, dev, |
2224 | "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", |
2225 | i, |
2226 | (u32) (lp->init_dma_addr), |
2227 | lp->a.read_csr(ioaddr, CSR0)); |
2228 | |
2229 | spin_unlock_irqrestore(&lp->lock, flags); |
2230 | |
2231 | return 0; /* Always succeed */ |
2232 | |
2233 | err_free_ring: |
2234 | /* free any allocated skbuffs */ |
2235 | pcnet32_purge_rx_ring(dev); |
2236 | |
2237 | /* |
2238 | * Switch back to 16bit mode to avoid problems with dumb |
2239 | * DOS packet driver after a warm reboot |
2240 | */ |
2241 | lp->a.write_bcr(ioaddr, 20, 4); |
2242 | |
2243 | err_free_irq: |
2244 | spin_unlock_irqrestore(&lp->lock, flags); |
2245 | free_irq(dev->irq, dev); |
2246 | return rc; |
2247 | } |
2248 | |
2249 | /* |
2250 | * The LANCE has been halted for one reason or another (busmaster memory |
2251 | * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, |
2252 | * etc.). Modern LANCE variants always reload their ring-buffer |
2253 | * configuration when restarted, so we must reinitialize our ring |
2254 | * context before restarting. As part of this reinitialization, |
2255 | * find all packets still on the Tx ring and pretend that they had been |
2256 | * sent (in effect, drop the packets on the floor) - the higher-level |
2257 | * protocols will time out and retransmit. It'd be better to shuffle |
2258 | * these skbs to a temp list and then actually re-Tx them after |
2259 | * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com |
2260 | */ |
2261 | |
2262 | static void pcnet32_purge_tx_ring(struct net_device *dev) |
2263 | { |
2264 | struct pcnet32_private *lp = netdev_priv(dev); |
2265 | int i; |
2266 | |
2267 | for (i = 0; i < lp->tx_ring_size; i++) { |
2268 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ |
2269 | wmb(); /* Make sure adapter sees owner change */ |
2270 | if (lp->tx_skbuff[i]) { |
2271 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], |
2272 | lp->tx_skbuff[i]->len, |
2273 | PCI_DMA_TODEVICE); |
2274 | dev_kfree_skb_any(lp->tx_skbuff[i]); |
2275 | } |
2276 | lp->tx_skbuff[i] = NULL; |
2277 | lp->tx_dma_addr[i] = 0; |
2278 | } |
2279 | } |
2280 | |
2281 | /* Initialize the PCNET32 Rx and Tx rings. */ |
2282 | static int pcnet32_init_ring(struct net_device *dev) |
2283 | { |
2284 | struct pcnet32_private *lp = netdev_priv(dev); |
2285 | int i; |
2286 | |
2287 | lp->tx_full = 0; |
2288 | lp->cur_rx = lp->cur_tx = 0; |
2289 | lp->dirty_rx = lp->dirty_tx = 0; |
2290 | |
2291 | for (i = 0; i < lp->rx_ring_size; i++) { |
2292 | struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; |
2293 | if (rx_skbuff == NULL) { |
2294 | lp->rx_skbuff[i] = dev_alloc_skb(PKT_BUF_SKB); |
2295 | rx_skbuff = lp->rx_skbuff[i]; |
2296 | if (!rx_skbuff) { |
2297 | /* there is not much we can do at this point */ |
2298 | netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n", |
2299 | __func__); |
2300 | return -1; |
2301 | } |
2302 | skb_reserve(rx_skbuff, NET_IP_ALIGN); |
2303 | } |
2304 | |
2305 | rmb(); |
2306 | if (lp->rx_dma_addr[i] == 0) |
2307 | lp->rx_dma_addr[i] = |
2308 | pci_map_single(lp->pci_dev, rx_skbuff->data, |
2309 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
2310 | lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); |
2311 | lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE); |
2312 | wmb(); /* Make sure owner changes after all others are visible */ |
2313 | lp->rx_ring[i].status = cpu_to_le16(0x8000); |
2314 | } |
2315 | /* The Tx buffer address is filled in as needed, but we do need to clear |
2316 | * the upper ownership bit. */ |
2317 | for (i = 0; i < lp->tx_ring_size; i++) { |
2318 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ |
2319 | wmb(); /* Make sure adapter sees owner change */ |
2320 | lp->tx_ring[i].base = 0; |
2321 | lp->tx_dma_addr[i] = 0; |
2322 | } |
2323 | |
2324 | lp->init_block->tlen_rlen = |
2325 | cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); |
2326 | for (i = 0; i < 6; i++) |
2327 | lp->init_block->phys_addr[i] = dev->dev_addr[i]; |
2328 | lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); |
2329 | lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); |
2330 | wmb(); /* Make sure all changes are visible */ |
2331 | return 0; |
2332 | } |
2333 | |
2334 | /* the pcnet32 has been issued a stop or reset. Wait for the stop bit |
2335 | * then flush the pending transmit operations, re-initialize the ring, |
2336 | * and tell the chip to initialize. |
2337 | */ |
2338 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) |
2339 | { |
2340 | struct pcnet32_private *lp = netdev_priv(dev); |
2341 | unsigned long ioaddr = dev->base_addr; |
2342 | int i; |
2343 | |
2344 | /* wait for stop */ |
2345 | for (i = 0; i < 100; i++) |
2346 | if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP) |
2347 | break; |
2348 | |
2349 | if (i >= 100) |
2350 | netif_err(lp, drv, dev, "%s timed out waiting for stop\n", |
2351 | __func__); |
2352 | |
2353 | pcnet32_purge_tx_ring(dev); |
2354 | if (pcnet32_init_ring(dev)) |
2355 | return; |
2356 | |
2357 | /* ReInit Ring */ |
2358 | lp->a.write_csr(ioaddr, CSR0, CSR0_INIT); |
2359 | i = 0; |
2360 | while (i++ < 1000) |
2361 | if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON) |
2362 | break; |
2363 | |
2364 | lp->a.write_csr(ioaddr, CSR0, csr0_bits); |
2365 | } |
2366 | |
2367 | static void pcnet32_tx_timeout(struct net_device *dev) |
2368 | { |
2369 | struct pcnet32_private *lp = netdev_priv(dev); |
2370 | unsigned long ioaddr = dev->base_addr, flags; |
2371 | |
2372 | spin_lock_irqsave(&lp->lock, flags); |
2373 | /* Transmitter timeout, serious problems. */ |
2374 | if (pcnet32_debug & NETIF_MSG_DRV) |
2375 | pr_err("%s: transmit timed out, status %4.4x, resetting\n", |
2376 | dev->name, lp->a.read_csr(ioaddr, CSR0)); |
2377 | lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); |
2378 | dev->stats.tx_errors++; |
2379 | if (netif_msg_tx_err(lp)) { |
2380 | int i; |
2381 | printk(KERN_DEBUG |
2382 | " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", |
2383 | lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", |
2384 | lp->cur_rx); |
2385 | for (i = 0; i < lp->rx_ring_size; i++) |
2386 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", |
2387 | le32_to_cpu(lp->rx_ring[i].base), |
2388 | (-le16_to_cpu(lp->rx_ring[i].buf_length)) & |
2389 | 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), |
2390 | le16_to_cpu(lp->rx_ring[i].status)); |
2391 | for (i = 0; i < lp->tx_ring_size; i++) |
2392 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", |
2393 | le32_to_cpu(lp->tx_ring[i].base), |
2394 | (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, |
2395 | le32_to_cpu(lp->tx_ring[i].misc), |
2396 | le16_to_cpu(lp->tx_ring[i].status)); |
2397 | printk("\n"); |
2398 | } |
2399 | pcnet32_restart(dev, CSR0_NORMAL); |
2400 | |
2401 | dev->trans_start = jiffies; |
2402 | netif_wake_queue(dev); |
2403 | |
2404 | spin_unlock_irqrestore(&lp->lock, flags); |
2405 | } |
2406 | |
2407 | static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb, |
2408 | struct net_device *dev) |
2409 | { |
2410 | struct pcnet32_private *lp = netdev_priv(dev); |
2411 | unsigned long ioaddr = dev->base_addr; |
2412 | u16 status; |
2413 | int entry; |
2414 | unsigned long flags; |
2415 | |
2416 | spin_lock_irqsave(&lp->lock, flags); |
2417 | |
2418 | netif_printk(lp, tx_queued, KERN_DEBUG, dev, |
2419 | "%s() called, csr0 %4.4x\n", |
2420 | __func__, lp->a.read_csr(ioaddr, CSR0)); |
2421 | |
2422 | /* Default status -- will not enable Successful-TxDone |
2423 | * interrupt when that option is available to us. |
2424 | */ |
2425 | status = 0x8300; |
2426 | |
2427 | /* Fill in a Tx ring entry */ |
2428 | |
2429 | /* Mask to ring buffer boundary. */ |
2430 | entry = lp->cur_tx & lp->tx_mod_mask; |
2431 | |
2432 | /* Caution: the write order is important here, set the status |
2433 | * with the "ownership" bits last. */ |
2434 | |
2435 | lp->tx_ring[entry].length = cpu_to_le16(-skb->len); |
2436 | |
2437 | lp->tx_ring[entry].misc = 0x00000000; |
2438 | |
2439 | lp->tx_skbuff[entry] = skb; |
2440 | lp->tx_dma_addr[entry] = |
2441 | pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); |
2442 | lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); |
2443 | wmb(); /* Make sure owner changes after all others are visible */ |
2444 | lp->tx_ring[entry].status = cpu_to_le16(status); |
2445 | |
2446 | lp->cur_tx++; |
2447 | dev->stats.tx_bytes += skb->len; |
2448 | |
2449 | /* Trigger an immediate send poll. */ |
2450 | lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); |
2451 | |
2452 | dev->trans_start = jiffies; |
2453 | |
2454 | if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { |
2455 | lp->tx_full = 1; |
2456 | netif_stop_queue(dev); |
2457 | } |
2458 | spin_unlock_irqrestore(&lp->lock, flags); |
2459 | return NETDEV_TX_OK; |
2460 | } |
2461 | |
2462 | /* The PCNET32 interrupt handler. */ |
2463 | static irqreturn_t |
2464 | pcnet32_interrupt(int irq, void *dev_id) |
2465 | { |
2466 | struct net_device *dev = dev_id; |
2467 | struct pcnet32_private *lp; |
2468 | unsigned long ioaddr; |
2469 | u16 csr0; |
2470 | int boguscnt = max_interrupt_work; |
2471 | |
2472 | ioaddr = dev->base_addr; |
2473 | lp = netdev_priv(dev); |
2474 | |
2475 | spin_lock(&lp->lock); |
2476 | |
2477 | csr0 = lp->a.read_csr(ioaddr, CSR0); |
2478 | while ((csr0 & 0x8f00) && --boguscnt >= 0) { |
2479 | if (csr0 == 0xffff) |
2480 | break; /* PCMCIA remove happened */ |
2481 | /* Acknowledge all of the current interrupt sources ASAP. */ |
2482 | lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f); |
2483 | |
2484 | netif_printk(lp, intr, KERN_DEBUG, dev, |
2485 | "interrupt csr0=%#2.2x new csr=%#2.2x\n", |
2486 | csr0, lp->a.read_csr(ioaddr, CSR0)); |
2487 | |
2488 | /* Log misc errors. */ |
2489 | if (csr0 & 0x4000) |
2490 | dev->stats.tx_errors++; /* Tx babble. */ |
2491 | if (csr0 & 0x1000) { |
2492 | /* |
2493 | * This happens when our receive ring is full. This |
2494 | * shouldn't be a problem as we will see normal rx |
2495 | * interrupts for the frames in the receive ring. But |
2496 | * there are some PCI chipsets (I can reproduce this |
2497 | * on SP3G with Intel saturn chipset) which have |
2498 | * sometimes problems and will fill up the receive |
2499 | * ring with error descriptors. In this situation we |
2500 | * don't get a rx interrupt, but a missed frame |
2501 | * interrupt sooner or later. |
2502 | */ |
2503 | dev->stats.rx_errors++; /* Missed a Rx frame. */ |
2504 | } |
2505 | if (csr0 & 0x0800) { |
2506 | netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n", |
2507 | csr0); |
2508 | /* unlike for the lance, there is no restart needed */ |
2509 | } |
2510 | if (napi_schedule_prep(&lp->napi)) { |
2511 | u16 val; |
2512 | /* set interrupt masks */ |
2513 | val = lp->a.read_csr(ioaddr, CSR3); |
2514 | val |= 0x5f00; |
2515 | lp->a.write_csr(ioaddr, CSR3, val); |
2516 | |
2517 | __napi_schedule(&lp->napi); |
2518 | break; |
2519 | } |
2520 | csr0 = lp->a.read_csr(ioaddr, CSR0); |
2521 | } |
2522 | |
2523 | netif_printk(lp, intr, KERN_DEBUG, dev, |
2524 | "exiting interrupt, csr0=%#4.4x\n", |
2525 | lp->a.read_csr(ioaddr, CSR0)); |
2526 | |
2527 | spin_unlock(&lp->lock); |
2528 | |
2529 | return IRQ_HANDLED; |
2530 | } |
2531 | |
2532 | static int pcnet32_close(struct net_device *dev) |
2533 | { |
2534 | unsigned long ioaddr = dev->base_addr; |
2535 | struct pcnet32_private *lp = netdev_priv(dev); |
2536 | unsigned long flags; |
2537 | |
2538 | del_timer_sync(&lp->watchdog_timer); |
2539 | |
2540 | netif_stop_queue(dev); |
2541 | napi_disable(&lp->napi); |
2542 | |
2543 | spin_lock_irqsave(&lp->lock, flags); |
2544 | |
2545 | dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112); |
2546 | |
2547 | netif_printk(lp, ifdown, KERN_DEBUG, dev, |
2548 | "Shutting down ethercard, status was %2.2x\n", |
2549 | lp->a.read_csr(ioaddr, CSR0)); |
2550 | |
2551 | /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ |
2552 | lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); |
2553 | |
2554 | /* |
2555 | * Switch back to 16bit mode to avoid problems with dumb |
2556 | * DOS packet driver after a warm reboot |
2557 | */ |
2558 | lp->a.write_bcr(ioaddr, 20, 4); |
2559 | |
2560 | spin_unlock_irqrestore(&lp->lock, flags); |
2561 | |
2562 | free_irq(dev->irq, dev); |
2563 | |
2564 | spin_lock_irqsave(&lp->lock, flags); |
2565 | |
2566 | pcnet32_purge_rx_ring(dev); |
2567 | pcnet32_purge_tx_ring(dev); |
2568 | |
2569 | spin_unlock_irqrestore(&lp->lock, flags); |
2570 | |
2571 | return 0; |
2572 | } |
2573 | |
2574 | static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) |
2575 | { |
2576 | struct pcnet32_private *lp = netdev_priv(dev); |
2577 | unsigned long ioaddr = dev->base_addr; |
2578 | unsigned long flags; |
2579 | |
2580 | spin_lock_irqsave(&lp->lock, flags); |
2581 | dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112); |
2582 | spin_unlock_irqrestore(&lp->lock, flags); |
2583 | |
2584 | return &dev->stats; |
2585 | } |
2586 | |
2587 | /* taken from the sunlance driver, which it took from the depca driver */ |
2588 | static void pcnet32_load_multicast(struct net_device *dev) |
2589 | { |
2590 | struct pcnet32_private *lp = netdev_priv(dev); |
2591 | volatile struct pcnet32_init_block *ib = lp->init_block; |
2592 | volatile __le16 *mcast_table = (__le16 *)ib->filter; |
2593 | struct dev_mc_list *dmi; |
2594 | unsigned long ioaddr = dev->base_addr; |
2595 | char *addrs; |
2596 | int i; |
2597 | u32 crc; |
2598 | |
2599 | /* set all multicast bits */ |
2600 | if (dev->flags & IFF_ALLMULTI) { |
2601 | ib->filter[0] = cpu_to_le32(~0U); |
2602 | ib->filter[1] = cpu_to_le32(~0U); |
2603 | lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); |
2604 | lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); |
2605 | lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); |
2606 | lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); |
2607 | return; |
2608 | } |
2609 | /* clear the multicast filter */ |
2610 | ib->filter[0] = 0; |
2611 | ib->filter[1] = 0; |
2612 | |
2613 | /* Add addresses */ |
2614 | netdev_for_each_mc_addr(dmi, dev) { |
2615 | addrs = dmi->dmi_addr; |
2616 | |
2617 | /* multicast address? */ |
2618 | if (!(*addrs & 1)) |
2619 | continue; |
2620 | |
2621 | crc = ether_crc_le(6, addrs); |
2622 | crc = crc >> 26; |
2623 | mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf)); |
2624 | } |
2625 | for (i = 0; i < 4; i++) |
2626 | lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i, |
2627 | le16_to_cpu(mcast_table[i])); |
2628 | return; |
2629 | } |
2630 | |
2631 | /* |
2632 | * Set or clear the multicast filter for this adaptor. |
2633 | */ |
2634 | static void pcnet32_set_multicast_list(struct net_device *dev) |
2635 | { |
2636 | unsigned long ioaddr = dev->base_addr, flags; |
2637 | struct pcnet32_private *lp = netdev_priv(dev); |
2638 | int csr15, suspended; |
2639 | |
2640 | spin_lock_irqsave(&lp->lock, flags); |
2641 | suspended = pcnet32_suspend(dev, &flags, 0); |
2642 | csr15 = lp->a.read_csr(ioaddr, CSR15); |
2643 | if (dev->flags & IFF_PROMISC) { |
2644 | /* Log any net taps. */ |
2645 | netif_info(lp, hw, dev, "Promiscuous mode enabled\n"); |
2646 | lp->init_block->mode = |
2647 | cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << |
2648 | 7); |
2649 | lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000); |
2650 | } else { |
2651 | lp->init_block->mode = |
2652 | cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); |
2653 | lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff); |
2654 | pcnet32_load_multicast(dev); |
2655 | } |
2656 | |
2657 | if (suspended) { |
2658 | int csr5; |
2659 | /* clear SUSPEND (SPND) - CSR5 bit 0 */ |
2660 | csr5 = lp->a.read_csr(ioaddr, CSR5); |
2661 | lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); |
2662 | } else { |
2663 | lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); |
2664 | pcnet32_restart(dev, CSR0_NORMAL); |
2665 | netif_wake_queue(dev); |
2666 | } |
2667 | |
2668 | spin_unlock_irqrestore(&lp->lock, flags); |
2669 | } |
2670 | |
2671 | /* This routine assumes that the lp->lock is held */ |
2672 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num) |
2673 | { |
2674 | struct pcnet32_private *lp = netdev_priv(dev); |
2675 | unsigned long ioaddr = dev->base_addr; |
2676 | u16 val_out; |
2677 | |
2678 | if (!lp->mii) |
2679 | return 0; |
2680 | |
2681 | lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); |
2682 | val_out = lp->a.read_bcr(ioaddr, 34); |
2683 | |
2684 | return val_out; |
2685 | } |
2686 | |
2687 | /* This routine assumes that the lp->lock is held */ |
2688 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) |
2689 | { |
2690 | struct pcnet32_private *lp = netdev_priv(dev); |
2691 | unsigned long ioaddr = dev->base_addr; |
2692 | |
2693 | if (!lp->mii) |
2694 | return; |
2695 | |
2696 | lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); |
2697 | lp->a.write_bcr(ioaddr, 34, val); |
2698 | } |
2699 | |
2700 | static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
2701 | { |
2702 | struct pcnet32_private *lp = netdev_priv(dev); |
2703 | int rc; |
2704 | unsigned long flags; |
2705 | |
2706 | /* SIOC[GS]MIIxxx ioctls */ |
2707 | if (lp->mii) { |
2708 | spin_lock_irqsave(&lp->lock, flags); |
2709 | rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); |
2710 | spin_unlock_irqrestore(&lp->lock, flags); |
2711 | } else { |
2712 | rc = -EOPNOTSUPP; |
2713 | } |
2714 | |
2715 | return rc; |
2716 | } |
2717 | |
2718 | static int pcnet32_check_otherphy(struct net_device *dev) |
2719 | { |
2720 | struct pcnet32_private *lp = netdev_priv(dev); |
2721 | struct mii_if_info mii = lp->mii_if; |
2722 | u16 bmcr; |
2723 | int i; |
2724 | |
2725 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { |
2726 | if (i == lp->mii_if.phy_id) |
2727 | continue; /* skip active phy */ |
2728 | if (lp->phymask & (1 << i)) { |
2729 | mii.phy_id = i; |
2730 | if (mii_link_ok(&mii)) { |
2731 | /* found PHY with active link */ |
2732 | netif_info(lp, link, dev, "Using PHY number %d\n", |
2733 | i); |
2734 | |
2735 | /* isolate inactive phy */ |
2736 | bmcr = |
2737 | mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); |
2738 | mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, |
2739 | bmcr | BMCR_ISOLATE); |
2740 | |
2741 | /* de-isolate new phy */ |
2742 | bmcr = mdio_read(dev, i, MII_BMCR); |
2743 | mdio_write(dev, i, MII_BMCR, |
2744 | bmcr & ~BMCR_ISOLATE); |
2745 | |
2746 | /* set new phy address */ |
2747 | lp->mii_if.phy_id = i; |
2748 | return 1; |
2749 | } |
2750 | } |
2751 | } |
2752 | return 0; |
2753 | } |
2754 | |
2755 | /* |
2756 | * Show the status of the media. Similar to mii_check_media however it |
2757 | * correctly shows the link speed for all (tested) pcnet32 variants. |
2758 | * Devices with no mii just report link state without speed. |
2759 | * |
2760 | * Caller is assumed to hold and release the lp->lock. |
2761 | */ |
2762 | |
2763 | static void pcnet32_check_media(struct net_device *dev, int verbose) |
2764 | { |
2765 | struct pcnet32_private *lp = netdev_priv(dev); |
2766 | int curr_link; |
2767 | int prev_link = netif_carrier_ok(dev) ? 1 : 0; |
2768 | u32 bcr9; |
2769 | |
2770 | if (lp->mii) { |
2771 | curr_link = mii_link_ok(&lp->mii_if); |
2772 | } else { |
2773 | ulong ioaddr = dev->base_addr; /* card base I/O address */ |
2774 | curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0); |
2775 | } |
2776 | if (!curr_link) { |
2777 | if (prev_link || verbose) { |
2778 | netif_carrier_off(dev); |
2779 | netif_info(lp, link, dev, "link down\n"); |
2780 | } |
2781 | if (lp->phycount > 1) { |
2782 | curr_link = pcnet32_check_otherphy(dev); |
2783 | prev_link = 0; |
2784 | } |
2785 | } else if (verbose || !prev_link) { |
2786 | netif_carrier_on(dev); |
2787 | if (lp->mii) { |
2788 | if (netif_msg_link(lp)) { |
2789 | struct ethtool_cmd ecmd; |
2790 | mii_ethtool_gset(&lp->mii_if, &ecmd); |
2791 | netdev_info(dev, "link up, %sMbps, %s-duplex\n", |
2792 | (ecmd.speed == SPEED_100) |
2793 | ? "100" : "10", |
2794 | (ecmd.duplex == DUPLEX_FULL) |
2795 | ? "full" : "half"); |
2796 | } |
2797 | bcr9 = lp->a.read_bcr(dev->base_addr, 9); |
2798 | if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { |
2799 | if (lp->mii_if.full_duplex) |
2800 | bcr9 |= (1 << 0); |
2801 | else |
2802 | bcr9 &= ~(1 << 0); |
2803 | lp->a.write_bcr(dev->base_addr, 9, bcr9); |
2804 | } |
2805 | } else { |
2806 | netif_info(lp, link, dev, "link up\n"); |
2807 | } |
2808 | } |
2809 | } |
2810 | |
2811 | /* |
2812 | * Check for loss of link and link establishment. |
2813 | * Can not use mii_check_media because it does nothing if mode is forced. |
2814 | */ |
2815 | |
2816 | static void pcnet32_watchdog(struct net_device *dev) |
2817 | { |
2818 | struct pcnet32_private *lp = netdev_priv(dev); |
2819 | unsigned long flags; |
2820 | |
2821 | /* Print the link status if it has changed */ |
2822 | spin_lock_irqsave(&lp->lock, flags); |
2823 | pcnet32_check_media(dev, 0); |
2824 | spin_unlock_irqrestore(&lp->lock, flags); |
2825 | |
2826 | mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT)); |
2827 | } |
2828 | |
2829 | static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state) |
2830 | { |
2831 | struct net_device *dev = pci_get_drvdata(pdev); |
2832 | |
2833 | if (netif_running(dev)) { |
2834 | netif_device_detach(dev); |
2835 | pcnet32_close(dev); |
2836 | } |
2837 | pci_save_state(pdev); |
2838 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
2839 | return 0; |
2840 | } |
2841 | |
2842 | static int pcnet32_pm_resume(struct pci_dev *pdev) |
2843 | { |
2844 | struct net_device *dev = pci_get_drvdata(pdev); |
2845 | |
2846 | pci_set_power_state(pdev, PCI_D0); |
2847 | pci_restore_state(pdev); |
2848 | |
2849 | if (netif_running(dev)) { |
2850 | pcnet32_open(dev); |
2851 | netif_device_attach(dev); |
2852 | } |
2853 | return 0; |
2854 | } |
2855 | |
2856 | static void __devexit pcnet32_remove_one(struct pci_dev *pdev) |
2857 | { |
2858 | struct net_device *dev = pci_get_drvdata(pdev); |
2859 | |
2860 | if (dev) { |
2861 | struct pcnet32_private *lp = netdev_priv(dev); |
2862 | |
2863 | unregister_netdev(dev); |
2864 | pcnet32_free_ring(dev); |
2865 | release_region(dev->base_addr, PCNET32_TOTAL_SIZE); |
2866 | pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), |
2867 | lp->init_block, lp->init_dma_addr); |
2868 | free_netdev(dev); |
2869 | pci_disable_device(pdev); |
2870 | pci_set_drvdata(pdev, NULL); |
2871 | } |
2872 | } |
2873 | |
2874 | static struct pci_driver pcnet32_driver = { |
2875 | .name = DRV_NAME, |
2876 | .probe = pcnet32_probe_pci, |
2877 | .remove = __devexit_p(pcnet32_remove_one), |
2878 | .id_table = pcnet32_pci_tbl, |
2879 | .suspend = pcnet32_pm_suspend, |
2880 | .resume = pcnet32_pm_resume, |
2881 | }; |
2882 | |
2883 | /* An additional parameter that may be passed in... */ |
2884 | static int debug = -1; |
2885 | static int tx_start_pt = -1; |
2886 | static int pcnet32_have_pci; |
2887 | |
2888 | module_param(debug, int, 0); |
2889 | MODULE_PARM_DESC(debug, DRV_NAME " debug level"); |
2890 | module_param(max_interrupt_work, int, 0); |
2891 | MODULE_PARM_DESC(max_interrupt_work, |
2892 | DRV_NAME " maximum events handled per interrupt"); |
2893 | module_param(rx_copybreak, int, 0); |
2894 | MODULE_PARM_DESC(rx_copybreak, |
2895 | DRV_NAME " copy breakpoint for copy-only-tiny-frames"); |
2896 | module_param(tx_start_pt, int, 0); |
2897 | MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); |
2898 | module_param(pcnet32vlb, int, 0); |
2899 | MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); |
2900 | module_param_array(options, int, NULL, 0); |
2901 | MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); |
2902 | module_param_array(full_duplex, int, NULL, 0); |
2903 | MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); |
2904 | /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ |
2905 | module_param_array(homepna, int, NULL, 0); |
2906 | MODULE_PARM_DESC(homepna, |
2907 | DRV_NAME |
2908 | " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); |
2909 | |
2910 | MODULE_AUTHOR("Thomas Bogendoerfer"); |
2911 | MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); |
2912 | MODULE_LICENSE("GPL"); |
2913 | |
2914 | #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) |
2915 | |
2916 | static int __init pcnet32_init_module(void) |
2917 | { |
2918 | pr_info("%s", version); |
2919 | |
2920 | pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); |
2921 | |
2922 | if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) |
2923 | tx_start = tx_start_pt; |
2924 | |
2925 | /* find the PCI devices */ |
2926 | if (!pci_register_driver(&pcnet32_driver)) |
2927 | pcnet32_have_pci = 1; |
2928 | |
2929 | /* should we find any remaining VLbus devices ? */ |
2930 | if (pcnet32vlb) |
2931 | pcnet32_probe_vlbus(pcnet32_portlist); |
2932 | |
2933 | if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) |
2934 | pr_info("%d cards_found\n", cards_found); |
2935 | |
2936 | return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; |
2937 | } |
2938 | |
2939 | static void __exit pcnet32_cleanup_module(void) |
2940 | { |
2941 | struct net_device *next_dev; |
2942 | |
2943 | while (pcnet32_dev) { |
2944 | struct pcnet32_private *lp = netdev_priv(pcnet32_dev); |
2945 | next_dev = lp->next; |
2946 | unregister_netdev(pcnet32_dev); |
2947 | pcnet32_free_ring(pcnet32_dev); |
2948 | release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); |
2949 | pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), |
2950 | lp->init_block, lp->init_dma_addr); |
2951 | free_netdev(pcnet32_dev); |
2952 | pcnet32_dev = next_dev; |
2953 | } |
2954 | |
2955 | if (pcnet32_have_pci) |
2956 | pci_unregister_driver(&pcnet32_driver); |
2957 | } |
2958 | |
2959 | module_init(pcnet32_init_module); |
2960 | module_exit(pcnet32_cleanup_module); |
2961 | |
2962 | /* |
2963 | * Local variables: |
2964 | * c-indent-level: 4 |
2965 | * tab-width: 8 |
2966 | * End: |
2967 | */ |
2968 |
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