Root/
1 | /*************************************************************************** |
2 | * |
3 | * Copyright (C) 2004-2008 SMSC |
4 | * Copyright (C) 2005-2008 ARM |
5 | * |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License |
8 | * as published by the Free Software Foundation; either version 2 |
9 | * of the License, or (at your option) any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
19 | * |
20 | *************************************************************************** |
21 | * Rewritten, heavily based on smsc911x simple driver by SMSC. |
22 | * Partly uses io macros from smc91x.c by Nicolas Pitre |
23 | * |
24 | * Supported devices: |
25 | * LAN9115, LAN9116, LAN9117, LAN9118 |
26 | * LAN9215, LAN9216, LAN9217, LAN9218 |
27 | * LAN9210, LAN9211 |
28 | * LAN9220, LAN9221 |
29 | * |
30 | */ |
31 | |
32 | #include <linux/crc32.h> |
33 | #include <linux/delay.h> |
34 | #include <linux/errno.h> |
35 | #include <linux/etherdevice.h> |
36 | #include <linux/ethtool.h> |
37 | #include <linux/init.h> |
38 | #include <linux/ioport.h> |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> |
41 | #include <linux/netdevice.h> |
42 | #include <linux/platform_device.h> |
43 | #include <linux/sched.h> |
44 | #include <linux/timer.h> |
45 | #include <linux/bug.h> |
46 | #include <linux/bitops.h> |
47 | #include <linux/irq.h> |
48 | #include <linux/io.h> |
49 | #include <linux/swab.h> |
50 | #include <linux/phy.h> |
51 | #include <linux/smsc911x.h> |
52 | #include <linux/device.h> |
53 | #include "smsc911x.h" |
54 | |
55 | #define SMSC_CHIPNAME "smsc911x" |
56 | #define SMSC_MDIONAME "smsc911x-mdio" |
57 | #define SMSC_DRV_VERSION "2008-10-21" |
58 | |
59 | MODULE_LICENSE("GPL"); |
60 | MODULE_VERSION(SMSC_DRV_VERSION); |
61 | |
62 | #if USE_DEBUG > 0 |
63 | static int debug = 16; |
64 | #else |
65 | static int debug = 3; |
66 | #endif |
67 | |
68 | module_param(debug, int, 0); |
69 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); |
70 | |
71 | struct smsc911x_data { |
72 | void __iomem *ioaddr; |
73 | |
74 | unsigned int idrev; |
75 | |
76 | /* used to decide which workarounds apply */ |
77 | unsigned int generation; |
78 | |
79 | /* device configuration (copied from platform_data during probe) */ |
80 | struct smsc911x_platform_config config; |
81 | |
82 | /* This needs to be acquired before calling any of below: |
83 | * smsc911x_mac_read(), smsc911x_mac_write() |
84 | */ |
85 | spinlock_t mac_lock; |
86 | |
87 | /* spinlock to ensure 16-bit accesses are serialised. |
88 | * unused with a 32-bit bus */ |
89 | spinlock_t dev_lock; |
90 | |
91 | struct phy_device *phy_dev; |
92 | struct mii_bus *mii_bus; |
93 | int phy_irq[PHY_MAX_ADDR]; |
94 | unsigned int using_extphy; |
95 | int last_duplex; |
96 | int last_carrier; |
97 | |
98 | u32 msg_enable; |
99 | unsigned int gpio_setting; |
100 | unsigned int gpio_orig_setting; |
101 | struct net_device *dev; |
102 | struct napi_struct napi; |
103 | |
104 | unsigned int software_irq_signal; |
105 | |
106 | #ifdef USE_PHY_WORK_AROUND |
107 | #define MIN_PACKET_SIZE (64) |
108 | char loopback_tx_pkt[MIN_PACKET_SIZE]; |
109 | char loopback_rx_pkt[MIN_PACKET_SIZE]; |
110 | unsigned int resetcount; |
111 | #endif |
112 | |
113 | /* Members for Multicast filter workaround */ |
114 | unsigned int multicast_update_pending; |
115 | unsigned int set_bits_mask; |
116 | unsigned int clear_bits_mask; |
117 | unsigned int hashhi; |
118 | unsigned int hashlo; |
119 | }; |
120 | |
121 | /* The 16-bit access functions are significantly slower, due to the locking |
122 | * necessary. If your bus hardware can be configured to do this for you |
123 | * (in response to a single 32-bit operation from software), you should use |
124 | * the 32-bit access functions instead. */ |
125 | |
126 | static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
127 | { |
128 | if (pdata->config.flags & SMSC911X_USE_32BIT) |
129 | return readl(pdata->ioaddr + reg); |
130 | |
131 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
132 | u32 data; |
133 | unsigned long flags; |
134 | |
135 | /* these two 16-bit reads must be performed consecutively, so |
136 | * must not be interrupted by our own ISR (which would start |
137 | * another read operation) */ |
138 | spin_lock_irqsave(&pdata->dev_lock, flags); |
139 | data = ((readw(pdata->ioaddr + reg) & 0xFFFF) | |
140 | ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16)); |
141 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
142 | |
143 | return data; |
144 | } |
145 | |
146 | BUG(); |
147 | return 0; |
148 | } |
149 | |
150 | static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, |
151 | u32 val) |
152 | { |
153 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
154 | writel(val, pdata->ioaddr + reg); |
155 | return; |
156 | } |
157 | |
158 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
159 | unsigned long flags; |
160 | |
161 | /* these two 16-bit writes must be performed consecutively, so |
162 | * must not be interrupted by our own ISR (which would start |
163 | * another read operation) */ |
164 | spin_lock_irqsave(&pdata->dev_lock, flags); |
165 | writew(val & 0xFFFF, pdata->ioaddr + reg); |
166 | writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); |
167 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
168 | return; |
169 | } |
170 | |
171 | BUG(); |
172 | } |
173 | |
174 | /* Writes a packet to the TX_DATA_FIFO */ |
175 | static inline void |
176 | smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf, |
177 | unsigned int wordcount) |
178 | { |
179 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
180 | while (wordcount--) |
181 | smsc911x_reg_write(pdata, TX_DATA_FIFO, swab32(*buf++)); |
182 | return; |
183 | } |
184 | |
185 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
186 | writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount); |
187 | return; |
188 | } |
189 | |
190 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
191 | while (wordcount--) |
192 | smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++); |
193 | return; |
194 | } |
195 | |
196 | BUG(); |
197 | } |
198 | |
199 | /* Reads a packet out of the RX_DATA_FIFO */ |
200 | static inline void |
201 | smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf, |
202 | unsigned int wordcount) |
203 | { |
204 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
205 | while (wordcount--) |
206 | *buf++ = swab32(smsc911x_reg_read(pdata, RX_DATA_FIFO)); |
207 | return; |
208 | } |
209 | |
210 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
211 | readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount); |
212 | return; |
213 | } |
214 | |
215 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
216 | while (wordcount--) |
217 | *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO); |
218 | return; |
219 | } |
220 | |
221 | BUG(); |
222 | } |
223 | |
224 | /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read |
225 | * and smsc911x_mac_write, so assumes mac_lock is held */ |
226 | static int smsc911x_mac_complete(struct smsc911x_data *pdata) |
227 | { |
228 | int i; |
229 | u32 val; |
230 | |
231 | SMSC_ASSERT_MAC_LOCK(pdata); |
232 | |
233 | for (i = 0; i < 40; i++) { |
234 | val = smsc911x_reg_read(pdata, MAC_CSR_CMD); |
235 | if (!(val & MAC_CSR_CMD_CSR_BUSY_)) |
236 | return 0; |
237 | } |
238 | SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. " |
239 | "MAC_CSR_CMD: 0x%08X", val); |
240 | return -EIO; |
241 | } |
242 | |
243 | /* Fetches a MAC register value. Assumes mac_lock is acquired */ |
244 | static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset) |
245 | { |
246 | unsigned int temp; |
247 | |
248 | SMSC_ASSERT_MAC_LOCK(pdata); |
249 | |
250 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); |
251 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { |
252 | SMSC_WARNING(HW, "MAC busy at entry"); |
253 | return 0xFFFFFFFF; |
254 | } |
255 | |
256 | /* Send the MAC cmd */ |
257 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | |
258 | MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_)); |
259 | |
260 | /* Workaround for hardware read-after-write restriction */ |
261 | temp = smsc911x_reg_read(pdata, BYTE_TEST); |
262 | |
263 | /* Wait for the read to complete */ |
264 | if (likely(smsc911x_mac_complete(pdata) == 0)) |
265 | return smsc911x_reg_read(pdata, MAC_CSR_DATA); |
266 | |
267 | SMSC_WARNING(HW, "MAC busy after read"); |
268 | return 0xFFFFFFFF; |
269 | } |
270 | |
271 | /* Set a mac register, mac_lock must be acquired before calling */ |
272 | static void smsc911x_mac_write(struct smsc911x_data *pdata, |
273 | unsigned int offset, u32 val) |
274 | { |
275 | unsigned int temp; |
276 | |
277 | SMSC_ASSERT_MAC_LOCK(pdata); |
278 | |
279 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); |
280 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { |
281 | SMSC_WARNING(HW, |
282 | "smsc911x_mac_write failed, MAC busy at entry"); |
283 | return; |
284 | } |
285 | |
286 | /* Send data to write */ |
287 | smsc911x_reg_write(pdata, MAC_CSR_DATA, val); |
288 | |
289 | /* Write the actual data */ |
290 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | |
291 | MAC_CSR_CMD_CSR_BUSY_)); |
292 | |
293 | /* Workaround for hardware read-after-write restriction */ |
294 | temp = smsc911x_reg_read(pdata, BYTE_TEST); |
295 | |
296 | /* Wait for the write to complete */ |
297 | if (likely(smsc911x_mac_complete(pdata) == 0)) |
298 | return; |
299 | |
300 | SMSC_WARNING(HW, |
301 | "smsc911x_mac_write failed, MAC busy after write"); |
302 | } |
303 | |
304 | /* Get a phy register */ |
305 | static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx) |
306 | { |
307 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; |
308 | unsigned long flags; |
309 | unsigned int addr; |
310 | int i, reg; |
311 | |
312 | spin_lock_irqsave(&pdata->mac_lock, flags); |
313 | |
314 | /* Confirm MII not busy */ |
315 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { |
316 | SMSC_WARNING(HW, |
317 | "MII is busy in smsc911x_mii_read???"); |
318 | reg = -EIO; |
319 | goto out; |
320 | } |
321 | |
322 | /* Set the address, index & direction (read from PHY) */ |
323 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6); |
324 | smsc911x_mac_write(pdata, MII_ACC, addr); |
325 | |
326 | /* Wait for read to complete w/ timeout */ |
327 | for (i = 0; i < 100; i++) |
328 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { |
329 | reg = smsc911x_mac_read(pdata, MII_DATA); |
330 | goto out; |
331 | } |
332 | |
333 | SMSC_WARNING(HW, "Timed out waiting for MII read to finish"); |
334 | reg = -EIO; |
335 | |
336 | out: |
337 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
338 | return reg; |
339 | } |
340 | |
341 | /* Set a phy register */ |
342 | static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx, |
343 | u16 val) |
344 | { |
345 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; |
346 | unsigned long flags; |
347 | unsigned int addr; |
348 | int i, reg; |
349 | |
350 | spin_lock_irqsave(&pdata->mac_lock, flags); |
351 | |
352 | /* Confirm MII not busy */ |
353 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { |
354 | SMSC_WARNING(HW, |
355 | "MII is busy in smsc911x_mii_write???"); |
356 | reg = -EIO; |
357 | goto out; |
358 | } |
359 | |
360 | /* Put the data to write in the MAC */ |
361 | smsc911x_mac_write(pdata, MII_DATA, val); |
362 | |
363 | /* Set the address, index & direction (write to PHY) */ |
364 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | |
365 | MII_ACC_MII_WRITE_; |
366 | smsc911x_mac_write(pdata, MII_ACC, addr); |
367 | |
368 | /* Wait for write to complete w/ timeout */ |
369 | for (i = 0; i < 100; i++) |
370 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { |
371 | reg = 0; |
372 | goto out; |
373 | } |
374 | |
375 | SMSC_WARNING(HW, "Timed out waiting for MII write to finish"); |
376 | reg = -EIO; |
377 | |
378 | out: |
379 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
380 | return reg; |
381 | } |
382 | |
383 | /* Switch to external phy. Assumes tx and rx are stopped. */ |
384 | static void smsc911x_phy_enable_external(struct smsc911x_data *pdata) |
385 | { |
386 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); |
387 | |
388 | /* Disable phy clocks to the MAC */ |
389 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); |
390 | hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; |
391 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); |
392 | udelay(10); /* Enough time for clocks to stop */ |
393 | |
394 | /* Switch to external phy */ |
395 | hwcfg |= HW_CFG_EXT_PHY_EN_; |
396 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); |
397 | |
398 | /* Enable phy clocks to the MAC */ |
399 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); |
400 | hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; |
401 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); |
402 | udelay(10); /* Enough time for clocks to restart */ |
403 | |
404 | hwcfg |= HW_CFG_SMI_SEL_; |
405 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); |
406 | } |
407 | |
408 | /* Autodetects and enables external phy if present on supported chips. |
409 | * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY |
410 | * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */ |
411 | static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata) |
412 | { |
413 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); |
414 | |
415 | if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) { |
416 | SMSC_TRACE(HW, "Forcing internal PHY"); |
417 | pdata->using_extphy = 0; |
418 | } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) { |
419 | SMSC_TRACE(HW, "Forcing external PHY"); |
420 | smsc911x_phy_enable_external(pdata); |
421 | pdata->using_extphy = 1; |
422 | } else if (hwcfg & HW_CFG_EXT_PHY_DET_) { |
423 | SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY"); |
424 | smsc911x_phy_enable_external(pdata); |
425 | pdata->using_extphy = 1; |
426 | } else { |
427 | SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY"); |
428 | pdata->using_extphy = 0; |
429 | } |
430 | } |
431 | |
432 | /* Fetches a tx status out of the status fifo */ |
433 | static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata) |
434 | { |
435 | unsigned int result = |
436 | smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_; |
437 | |
438 | if (result != 0) |
439 | result = smsc911x_reg_read(pdata, TX_STATUS_FIFO); |
440 | |
441 | return result; |
442 | } |
443 | |
444 | /* Fetches the next rx status */ |
445 | static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata) |
446 | { |
447 | unsigned int result = |
448 | smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_; |
449 | |
450 | if (result != 0) |
451 | result = smsc911x_reg_read(pdata, RX_STATUS_FIFO); |
452 | |
453 | return result; |
454 | } |
455 | |
456 | #ifdef USE_PHY_WORK_AROUND |
457 | static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata) |
458 | { |
459 | unsigned int tries; |
460 | u32 wrsz; |
461 | u32 rdsz; |
462 | ulong bufp; |
463 | |
464 | for (tries = 0; tries < 10; tries++) { |
465 | unsigned int txcmd_a; |
466 | unsigned int txcmd_b; |
467 | unsigned int status; |
468 | unsigned int pktlength; |
469 | unsigned int i; |
470 | |
471 | /* Zero-out rx packet memory */ |
472 | memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE); |
473 | |
474 | /* Write tx packet to 118 */ |
475 | txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16; |
476 | txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; |
477 | txcmd_a |= MIN_PACKET_SIZE; |
478 | |
479 | txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE; |
480 | |
481 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a); |
482 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b); |
483 | |
484 | bufp = (ulong)pdata->loopback_tx_pkt & (~0x3); |
485 | wrsz = MIN_PACKET_SIZE + 3; |
486 | wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3); |
487 | wrsz >>= 2; |
488 | |
489 | smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
490 | |
491 | /* Wait till transmit is done */ |
492 | i = 60; |
493 | do { |
494 | udelay(5); |
495 | status = smsc911x_tx_get_txstatus(pdata); |
496 | } while ((i--) && (!status)); |
497 | |
498 | if (!status) { |
499 | SMSC_WARNING(HW, "Failed to transmit " |
500 | "during loopback test"); |
501 | continue; |
502 | } |
503 | if (status & TX_STS_ES_) { |
504 | SMSC_WARNING(HW, "Transmit encountered " |
505 | "errors during loopback test"); |
506 | continue; |
507 | } |
508 | |
509 | /* Wait till receive is done */ |
510 | i = 60; |
511 | do { |
512 | udelay(5); |
513 | status = smsc911x_rx_get_rxstatus(pdata); |
514 | } while ((i--) && (!status)); |
515 | |
516 | if (!status) { |
517 | SMSC_WARNING(HW, |
518 | "Failed to receive during loopback test"); |
519 | continue; |
520 | } |
521 | if (status & RX_STS_ES_) { |
522 | SMSC_WARNING(HW, "Receive encountered " |
523 | "errors during loopback test"); |
524 | continue; |
525 | } |
526 | |
527 | pktlength = ((status & 0x3FFF0000UL) >> 16); |
528 | bufp = (ulong)pdata->loopback_rx_pkt; |
529 | rdsz = pktlength + 3; |
530 | rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3); |
531 | rdsz >>= 2; |
532 | |
533 | smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz); |
534 | |
535 | if (pktlength != (MIN_PACKET_SIZE + 4)) { |
536 | SMSC_WARNING(HW, "Unexpected packet size " |
537 | "during loop back test, size=%d, will retry", |
538 | pktlength); |
539 | } else { |
540 | unsigned int j; |
541 | int mismatch = 0; |
542 | for (j = 0; j < MIN_PACKET_SIZE; j++) { |
543 | if (pdata->loopback_tx_pkt[j] |
544 | != pdata->loopback_rx_pkt[j]) { |
545 | mismatch = 1; |
546 | break; |
547 | } |
548 | } |
549 | if (!mismatch) { |
550 | SMSC_TRACE(HW, "Successfully verified " |
551 | "loopback packet"); |
552 | return 0; |
553 | } else { |
554 | SMSC_WARNING(HW, "Data mismatch " |
555 | "during loop back test, will retry"); |
556 | } |
557 | } |
558 | } |
559 | |
560 | return -EIO; |
561 | } |
562 | |
563 | static int smsc911x_phy_reset(struct smsc911x_data *pdata) |
564 | { |
565 | struct phy_device *phy_dev = pdata->phy_dev; |
566 | unsigned int temp; |
567 | unsigned int i = 100000; |
568 | |
569 | BUG_ON(!phy_dev); |
570 | BUG_ON(!phy_dev->bus); |
571 | |
572 | SMSC_TRACE(HW, "Performing PHY BCR Reset"); |
573 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET); |
574 | do { |
575 | msleep(1); |
576 | temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, |
577 | MII_BMCR); |
578 | } while ((i--) && (temp & BMCR_RESET)); |
579 | |
580 | if (temp & BMCR_RESET) { |
581 | SMSC_WARNING(HW, "PHY reset failed to complete."); |
582 | return -EIO; |
583 | } |
584 | /* Extra delay required because the phy may not be completed with |
585 | * its reset when BMCR_RESET is cleared. Specs say 256 uS is |
586 | * enough delay but using 1ms here to be safe */ |
587 | msleep(1); |
588 | |
589 | return 0; |
590 | } |
591 | |
592 | static int smsc911x_phy_loopbacktest(struct net_device *dev) |
593 | { |
594 | struct smsc911x_data *pdata = netdev_priv(dev); |
595 | struct phy_device *phy_dev = pdata->phy_dev; |
596 | int result = -EIO; |
597 | unsigned int i, val; |
598 | unsigned long flags; |
599 | |
600 | /* Initialise tx packet using broadcast destination address */ |
601 | memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN); |
602 | |
603 | /* Use incrementing source address */ |
604 | for (i = 6; i < 12; i++) |
605 | pdata->loopback_tx_pkt[i] = (char)i; |
606 | |
607 | /* Set length type field */ |
608 | pdata->loopback_tx_pkt[12] = 0x00; |
609 | pdata->loopback_tx_pkt[13] = 0x00; |
610 | |
611 | for (i = 14; i < MIN_PACKET_SIZE; i++) |
612 | pdata->loopback_tx_pkt[i] = (char)i; |
613 | |
614 | val = smsc911x_reg_read(pdata, HW_CFG); |
615 | val &= HW_CFG_TX_FIF_SZ_; |
616 | val |= HW_CFG_SF_; |
617 | smsc911x_reg_write(pdata, HW_CFG, val); |
618 | |
619 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); |
620 | smsc911x_reg_write(pdata, RX_CFG, |
621 | (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8); |
622 | |
623 | for (i = 0; i < 10; i++) { |
624 | /* Set PHY to 10/FD, no ANEG, and loopback mode */ |
625 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, |
626 | BMCR_LOOPBACK | BMCR_FULLDPLX); |
627 | |
628 | /* Enable MAC tx/rx, FD */ |
629 | spin_lock_irqsave(&pdata->mac_lock, flags); |
630 | smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_ |
631 | | MAC_CR_TXEN_ | MAC_CR_RXEN_); |
632 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
633 | |
634 | if (smsc911x_phy_check_loopbackpkt(pdata) == 0) { |
635 | result = 0; |
636 | break; |
637 | } |
638 | pdata->resetcount++; |
639 | |
640 | /* Disable MAC rx */ |
641 | spin_lock_irqsave(&pdata->mac_lock, flags); |
642 | smsc911x_mac_write(pdata, MAC_CR, 0); |
643 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
644 | |
645 | smsc911x_phy_reset(pdata); |
646 | } |
647 | |
648 | /* Disable MAC */ |
649 | spin_lock_irqsave(&pdata->mac_lock, flags); |
650 | smsc911x_mac_write(pdata, MAC_CR, 0); |
651 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
652 | |
653 | /* Cancel PHY loopback mode */ |
654 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0); |
655 | |
656 | smsc911x_reg_write(pdata, TX_CFG, 0); |
657 | smsc911x_reg_write(pdata, RX_CFG, 0); |
658 | |
659 | return result; |
660 | } |
661 | #endif /* USE_PHY_WORK_AROUND */ |
662 | |
663 | static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata) |
664 | { |
665 | struct phy_device *phy_dev = pdata->phy_dev; |
666 | u32 afc = smsc911x_reg_read(pdata, AFC_CFG); |
667 | u32 flow; |
668 | unsigned long flags; |
669 | |
670 | if (phy_dev->duplex == DUPLEX_FULL) { |
671 | u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); |
672 | u16 rmtadv = phy_read(phy_dev, MII_LPA); |
673 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
674 | |
675 | if (cap & FLOW_CTRL_RX) |
676 | flow = 0xFFFF0002; |
677 | else |
678 | flow = 0; |
679 | |
680 | if (cap & FLOW_CTRL_TX) |
681 | afc |= 0xF; |
682 | else |
683 | afc &= ~0xF; |
684 | |
685 | SMSC_TRACE(HW, "rx pause %s, tx pause %s", |
686 | (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), |
687 | (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); |
688 | } else { |
689 | SMSC_TRACE(HW, "half duplex"); |
690 | flow = 0; |
691 | afc |= 0xF; |
692 | } |
693 | |
694 | spin_lock_irqsave(&pdata->mac_lock, flags); |
695 | smsc911x_mac_write(pdata, FLOW, flow); |
696 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
697 | |
698 | smsc911x_reg_write(pdata, AFC_CFG, afc); |
699 | } |
700 | |
701 | /* Update link mode if anything has changed. Called periodically when the |
702 | * PHY is in polling mode, even if nothing has changed. */ |
703 | static void smsc911x_phy_adjust_link(struct net_device *dev) |
704 | { |
705 | struct smsc911x_data *pdata = netdev_priv(dev); |
706 | struct phy_device *phy_dev = pdata->phy_dev; |
707 | unsigned long flags; |
708 | int carrier; |
709 | |
710 | if (phy_dev->duplex != pdata->last_duplex) { |
711 | unsigned int mac_cr; |
712 | SMSC_TRACE(HW, "duplex state has changed"); |
713 | |
714 | spin_lock_irqsave(&pdata->mac_lock, flags); |
715 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); |
716 | if (phy_dev->duplex) { |
717 | SMSC_TRACE(HW, |
718 | "configuring for full duplex mode"); |
719 | mac_cr |= MAC_CR_FDPX_; |
720 | } else { |
721 | SMSC_TRACE(HW, |
722 | "configuring for half duplex mode"); |
723 | mac_cr &= ~MAC_CR_FDPX_; |
724 | } |
725 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); |
726 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
727 | |
728 | smsc911x_phy_update_flowcontrol(pdata); |
729 | pdata->last_duplex = phy_dev->duplex; |
730 | } |
731 | |
732 | carrier = netif_carrier_ok(dev); |
733 | if (carrier != pdata->last_carrier) { |
734 | SMSC_TRACE(HW, "carrier state has changed"); |
735 | if (carrier) { |
736 | SMSC_TRACE(HW, "configuring for carrier OK"); |
737 | if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) && |
738 | (!pdata->using_extphy)) { |
739 | /* Restore orginal GPIO configuration */ |
740 | pdata->gpio_setting = pdata->gpio_orig_setting; |
741 | smsc911x_reg_write(pdata, GPIO_CFG, |
742 | pdata->gpio_setting); |
743 | } |
744 | } else { |
745 | SMSC_TRACE(HW, "configuring for no carrier"); |
746 | /* Check global setting that LED1 |
747 | * usage is 10/100 indicator */ |
748 | pdata->gpio_setting = smsc911x_reg_read(pdata, |
749 | GPIO_CFG); |
750 | if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) && |
751 | (!pdata->using_extphy)) { |
752 | /* Force 10/100 LED off, after saving |
753 | * orginal GPIO configuration */ |
754 | pdata->gpio_orig_setting = pdata->gpio_setting; |
755 | |
756 | pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_; |
757 | pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_ |
758 | | GPIO_CFG_GPIODIR0_ |
759 | | GPIO_CFG_GPIOD0_); |
760 | smsc911x_reg_write(pdata, GPIO_CFG, |
761 | pdata->gpio_setting); |
762 | } |
763 | } |
764 | pdata->last_carrier = carrier; |
765 | } |
766 | } |
767 | |
768 | static int smsc911x_mii_probe(struct net_device *dev) |
769 | { |
770 | struct smsc911x_data *pdata = netdev_priv(dev); |
771 | struct phy_device *phydev = NULL; |
772 | int ret; |
773 | |
774 | /* find the first phy */ |
775 | phydev = phy_find_first(pdata->mii_bus); |
776 | if (!phydev) { |
777 | pr_err("%s: no PHY found\n", dev->name); |
778 | return -ENODEV; |
779 | } |
780 | |
781 | SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X", |
782 | phy_addr, phydev->addr, phydev->phy_id); |
783 | |
784 | ret = phy_connect_direct(dev, phydev, |
785 | &smsc911x_phy_adjust_link, 0, |
786 | pdata->config.phy_interface); |
787 | |
788 | if (ret) { |
789 | pr_err("%s: Could not attach to PHY\n", dev->name); |
790 | return ret; |
791 | } |
792 | |
793 | pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
794 | dev->name, phydev->drv->name, |
795 | dev_name(&phydev->dev), phydev->irq); |
796 | |
797 | /* mask with MAC supported features */ |
798 | phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | |
799 | SUPPORTED_Asym_Pause); |
800 | phydev->advertising = phydev->supported; |
801 | |
802 | pdata->phy_dev = phydev; |
803 | pdata->last_duplex = -1; |
804 | pdata->last_carrier = -1; |
805 | |
806 | #ifdef USE_PHY_WORK_AROUND |
807 | if (smsc911x_phy_loopbacktest(dev) < 0) { |
808 | SMSC_WARNING(HW, "Failed Loop Back Test"); |
809 | return -ENODEV; |
810 | } |
811 | SMSC_TRACE(HW, "Passed Loop Back Test"); |
812 | #endif /* USE_PHY_WORK_AROUND */ |
813 | |
814 | SMSC_TRACE(HW, "phy initialised successfully"); |
815 | return 0; |
816 | } |
817 | |
818 | static int __devinit smsc911x_mii_init(struct platform_device *pdev, |
819 | struct net_device *dev) |
820 | { |
821 | struct smsc911x_data *pdata = netdev_priv(dev); |
822 | int err = -ENXIO, i; |
823 | |
824 | pdata->mii_bus = mdiobus_alloc(); |
825 | if (!pdata->mii_bus) { |
826 | err = -ENOMEM; |
827 | goto err_out_1; |
828 | } |
829 | |
830 | pdata->mii_bus->name = SMSC_MDIONAME; |
831 | snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id); |
832 | pdata->mii_bus->priv = pdata; |
833 | pdata->mii_bus->read = smsc911x_mii_read; |
834 | pdata->mii_bus->write = smsc911x_mii_write; |
835 | pdata->mii_bus->irq = pdata->phy_irq; |
836 | for (i = 0; i < PHY_MAX_ADDR; ++i) |
837 | pdata->mii_bus->irq[i] = PHY_POLL; |
838 | |
839 | pdata->mii_bus->parent = &pdev->dev; |
840 | |
841 | switch (pdata->idrev & 0xFFFF0000) { |
842 | case 0x01170000: |
843 | case 0x01150000: |
844 | case 0x117A0000: |
845 | case 0x115A0000: |
846 | /* External PHY supported, try to autodetect */ |
847 | smsc911x_phy_initialise_external(pdata); |
848 | break; |
849 | default: |
850 | SMSC_TRACE(HW, "External PHY is not supported, " |
851 | "using internal PHY"); |
852 | pdata->using_extphy = 0; |
853 | break; |
854 | } |
855 | |
856 | if (!pdata->using_extphy) { |
857 | /* Mask all PHYs except ID 1 (internal) */ |
858 | pdata->mii_bus->phy_mask = ~(1 << 1); |
859 | } |
860 | |
861 | if (mdiobus_register(pdata->mii_bus)) { |
862 | SMSC_WARNING(PROBE, "Error registering mii bus"); |
863 | goto err_out_free_bus_2; |
864 | } |
865 | |
866 | if (smsc911x_mii_probe(dev) < 0) { |
867 | SMSC_WARNING(PROBE, "Error registering mii bus"); |
868 | goto err_out_unregister_bus_3; |
869 | } |
870 | |
871 | return 0; |
872 | |
873 | err_out_unregister_bus_3: |
874 | mdiobus_unregister(pdata->mii_bus); |
875 | err_out_free_bus_2: |
876 | mdiobus_free(pdata->mii_bus); |
877 | err_out_1: |
878 | return err; |
879 | } |
880 | |
881 | /* Gets the number of tx statuses in the fifo */ |
882 | static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata) |
883 | { |
884 | return (smsc911x_reg_read(pdata, TX_FIFO_INF) |
885 | & TX_FIFO_INF_TSUSED_) >> 16; |
886 | } |
887 | |
888 | /* Reads tx statuses and increments counters where necessary */ |
889 | static void smsc911x_tx_update_txcounters(struct net_device *dev) |
890 | { |
891 | struct smsc911x_data *pdata = netdev_priv(dev); |
892 | unsigned int tx_stat; |
893 | |
894 | while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) { |
895 | if (unlikely(tx_stat & 0x80000000)) { |
896 | /* In this driver the packet tag is used as the packet |
897 | * length. Since a packet length can never reach the |
898 | * size of 0x8000, this bit is reserved. It is worth |
899 | * noting that the "reserved bit" in the warning above |
900 | * does not reference a hardware defined reserved bit |
901 | * but rather a driver defined one. |
902 | */ |
903 | SMSC_WARNING(HW, |
904 | "Packet tag reserved bit is high"); |
905 | } else { |
906 | if (unlikely(tx_stat & TX_STS_ES_)) { |
907 | dev->stats.tx_errors++; |
908 | } else { |
909 | dev->stats.tx_packets++; |
910 | dev->stats.tx_bytes += (tx_stat >> 16); |
911 | } |
912 | if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) { |
913 | dev->stats.collisions += 16; |
914 | dev->stats.tx_aborted_errors += 1; |
915 | } else { |
916 | dev->stats.collisions += |
917 | ((tx_stat >> 3) & 0xF); |
918 | } |
919 | if (unlikely(tx_stat & TX_STS_LOST_CARRIER_)) |
920 | dev->stats.tx_carrier_errors += 1; |
921 | if (unlikely(tx_stat & TX_STS_LATE_COL_)) { |
922 | dev->stats.collisions++; |
923 | dev->stats.tx_aborted_errors++; |
924 | } |
925 | } |
926 | } |
927 | } |
928 | |
929 | /* Increments the Rx error counters */ |
930 | static void |
931 | smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat) |
932 | { |
933 | int crc_err = 0; |
934 | |
935 | if (unlikely(rxstat & RX_STS_ES_)) { |
936 | dev->stats.rx_errors++; |
937 | if (unlikely(rxstat & RX_STS_CRC_ERR_)) { |
938 | dev->stats.rx_crc_errors++; |
939 | crc_err = 1; |
940 | } |
941 | } |
942 | if (likely(!crc_err)) { |
943 | if (unlikely((rxstat & RX_STS_FRAME_TYPE_) && |
944 | (rxstat & RX_STS_LENGTH_ERR_))) |
945 | dev->stats.rx_length_errors++; |
946 | if (rxstat & RX_STS_MCAST_) |
947 | dev->stats.multicast++; |
948 | } |
949 | } |
950 | |
951 | /* Quickly dumps bad packets */ |
952 | static void |
953 | smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes) |
954 | { |
955 | unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2; |
956 | |
957 | if (likely(pktwords >= 4)) { |
958 | unsigned int timeout = 500; |
959 | unsigned int val; |
960 | smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_); |
961 | do { |
962 | udelay(1); |
963 | val = smsc911x_reg_read(pdata, RX_DP_CTRL); |
964 | } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout); |
965 | |
966 | if (unlikely(timeout == 0)) |
967 | SMSC_WARNING(HW, "Timed out waiting for " |
968 | "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val); |
969 | } else { |
970 | unsigned int temp; |
971 | while (pktwords--) |
972 | temp = smsc911x_reg_read(pdata, RX_DATA_FIFO); |
973 | } |
974 | } |
975 | |
976 | /* NAPI poll function */ |
977 | static int smsc911x_poll(struct napi_struct *napi, int budget) |
978 | { |
979 | struct smsc911x_data *pdata = |
980 | container_of(napi, struct smsc911x_data, napi); |
981 | struct net_device *dev = pdata->dev; |
982 | int npackets = 0; |
983 | |
984 | while (npackets < budget) { |
985 | unsigned int pktlength; |
986 | unsigned int pktwords; |
987 | struct sk_buff *skb; |
988 | unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata); |
989 | |
990 | if (!rxstat) { |
991 | unsigned int temp; |
992 | /* We processed all packets available. Tell NAPI it can |
993 | * stop polling then re-enable rx interrupts */ |
994 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_); |
995 | napi_complete(napi); |
996 | temp = smsc911x_reg_read(pdata, INT_EN); |
997 | temp |= INT_EN_RSFL_EN_; |
998 | smsc911x_reg_write(pdata, INT_EN, temp); |
999 | break; |
1000 | } |
1001 | |
1002 | /* Count packet for NAPI scheduling, even if it has an error. |
1003 | * Error packets still require cycles to discard */ |
1004 | npackets++; |
1005 | |
1006 | pktlength = ((rxstat & 0x3FFF0000) >> 16); |
1007 | pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2; |
1008 | smsc911x_rx_counterrors(dev, rxstat); |
1009 | |
1010 | if (unlikely(rxstat & RX_STS_ES_)) { |
1011 | SMSC_WARNING(RX_ERR, |
1012 | "Discarding packet with error bit set"); |
1013 | /* Packet has an error, discard it and continue with |
1014 | * the next */ |
1015 | smsc911x_rx_fastforward(pdata, pktwords); |
1016 | dev->stats.rx_dropped++; |
1017 | continue; |
1018 | } |
1019 | |
1020 | skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN); |
1021 | if (unlikely(!skb)) { |
1022 | SMSC_WARNING(RX_ERR, |
1023 | "Unable to allocate skb for rx packet"); |
1024 | /* Drop the packet and stop this polling iteration */ |
1025 | smsc911x_rx_fastforward(pdata, pktwords); |
1026 | dev->stats.rx_dropped++; |
1027 | break; |
1028 | } |
1029 | |
1030 | skb->data = skb->head; |
1031 | skb_reset_tail_pointer(skb); |
1032 | |
1033 | /* Align IP on 16B boundary */ |
1034 | skb_reserve(skb, NET_IP_ALIGN); |
1035 | skb_put(skb, pktlength - 4); |
1036 | smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head, |
1037 | pktwords); |
1038 | skb->protocol = eth_type_trans(skb, dev); |
1039 | skb->ip_summed = CHECKSUM_NONE; |
1040 | netif_receive_skb(skb); |
1041 | |
1042 | /* Update counters */ |
1043 | dev->stats.rx_packets++; |
1044 | dev->stats.rx_bytes += (pktlength - 4); |
1045 | } |
1046 | |
1047 | /* Return total received packets */ |
1048 | return npackets; |
1049 | } |
1050 | |
1051 | /* Returns hash bit number for given MAC address |
1052 | * Example: |
1053 | * 01 00 5E 00 00 01 -> returns bit number 31 */ |
1054 | static unsigned int smsc911x_hash(char addr[ETH_ALEN]) |
1055 | { |
1056 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; |
1057 | } |
1058 | |
1059 | static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata) |
1060 | { |
1061 | /* Performs the multicast & mac_cr update. This is called when |
1062 | * safe on the current hardware, and with the mac_lock held */ |
1063 | unsigned int mac_cr; |
1064 | |
1065 | SMSC_ASSERT_MAC_LOCK(pdata); |
1066 | |
1067 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); |
1068 | mac_cr |= pdata->set_bits_mask; |
1069 | mac_cr &= ~(pdata->clear_bits_mask); |
1070 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); |
1071 | smsc911x_mac_write(pdata, HASHH, pdata->hashhi); |
1072 | smsc911x_mac_write(pdata, HASHL, pdata->hashlo); |
1073 | SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X", |
1074 | mac_cr, pdata->hashhi, pdata->hashlo); |
1075 | } |
1076 | |
1077 | static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata) |
1078 | { |
1079 | unsigned int mac_cr; |
1080 | |
1081 | /* This function is only called for older LAN911x devices |
1082 | * (revA or revB), where MAC_CR, HASHH and HASHL should not |
1083 | * be modified during Rx - newer devices immediately update the |
1084 | * registers. |
1085 | * |
1086 | * This is called from interrupt context */ |
1087 | |
1088 | spin_lock(&pdata->mac_lock); |
1089 | |
1090 | /* Check Rx has stopped */ |
1091 | if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_) |
1092 | SMSC_WARNING(DRV, "Rx not stopped"); |
1093 | |
1094 | /* Perform the update - safe to do now Rx has stopped */ |
1095 | smsc911x_rx_multicast_update(pdata); |
1096 | |
1097 | /* Re-enable Rx */ |
1098 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); |
1099 | mac_cr |= MAC_CR_RXEN_; |
1100 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); |
1101 | |
1102 | pdata->multicast_update_pending = 0; |
1103 | |
1104 | spin_unlock(&pdata->mac_lock); |
1105 | } |
1106 | |
1107 | static int smsc911x_soft_reset(struct smsc911x_data *pdata) |
1108 | { |
1109 | unsigned int timeout; |
1110 | unsigned int temp; |
1111 | |
1112 | /* Reset the LAN911x */ |
1113 | smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_); |
1114 | timeout = 10; |
1115 | do { |
1116 | udelay(10); |
1117 | temp = smsc911x_reg_read(pdata, HW_CFG); |
1118 | } while ((--timeout) && (temp & HW_CFG_SRST_)); |
1119 | |
1120 | if (unlikely(temp & HW_CFG_SRST_)) { |
1121 | SMSC_WARNING(DRV, "Failed to complete reset"); |
1122 | return -EIO; |
1123 | } |
1124 | return 0; |
1125 | } |
1126 | |
1127 | /* Sets the device MAC address to dev_addr, called with mac_lock held */ |
1128 | static void |
1129 | smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6]) |
1130 | { |
1131 | u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; |
1132 | u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | |
1133 | (dev_addr[1] << 8) | dev_addr[0]; |
1134 | |
1135 | SMSC_ASSERT_MAC_LOCK(pdata); |
1136 | |
1137 | smsc911x_mac_write(pdata, ADDRH, mac_high16); |
1138 | smsc911x_mac_write(pdata, ADDRL, mac_low32); |
1139 | } |
1140 | |
1141 | static int smsc911x_open(struct net_device *dev) |
1142 | { |
1143 | struct smsc911x_data *pdata = netdev_priv(dev); |
1144 | unsigned int timeout; |
1145 | unsigned int temp; |
1146 | unsigned int intcfg; |
1147 | |
1148 | /* if the phy is not yet registered, retry later*/ |
1149 | if (!pdata->phy_dev) { |
1150 | SMSC_WARNING(HW, "phy_dev is NULL"); |
1151 | return -EAGAIN; |
1152 | } |
1153 | |
1154 | if (!is_valid_ether_addr(dev->dev_addr)) { |
1155 | SMSC_WARNING(HW, "dev_addr is not a valid MAC address"); |
1156 | return -EADDRNOTAVAIL; |
1157 | } |
1158 | |
1159 | /* Reset the LAN911x */ |
1160 | if (smsc911x_soft_reset(pdata)) { |
1161 | SMSC_WARNING(HW, "soft reset failed"); |
1162 | return -EIO; |
1163 | } |
1164 | |
1165 | smsc911x_reg_write(pdata, HW_CFG, 0x00050000); |
1166 | smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740); |
1167 | |
1168 | /* Make sure EEPROM has finished loading before setting GPIO_CFG */ |
1169 | timeout = 50; |
1170 | while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) && |
1171 | --timeout) { |
1172 | udelay(10); |
1173 | } |
1174 | |
1175 | if (unlikely(timeout == 0)) |
1176 | SMSC_WARNING(IFUP, |
1177 | "Timed out waiting for EEPROM busy bit to clear"); |
1178 | |
1179 | smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000); |
1180 | |
1181 | /* The soft reset above cleared the device's MAC address, |
1182 | * restore it from local copy (set in probe) */ |
1183 | spin_lock_irq(&pdata->mac_lock); |
1184 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
1185 | spin_unlock_irq(&pdata->mac_lock); |
1186 | |
1187 | /* Initialise irqs, but leave all sources disabled */ |
1188 | smsc911x_reg_write(pdata, INT_EN, 0); |
1189 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); |
1190 | |
1191 | /* Set interrupt deassertion to 100uS */ |
1192 | intcfg = ((10 << 24) | INT_CFG_IRQ_EN_); |
1193 | |
1194 | if (pdata->config.irq_polarity) { |
1195 | SMSC_TRACE(IFUP, "irq polarity: active high"); |
1196 | intcfg |= INT_CFG_IRQ_POL_; |
1197 | } else { |
1198 | SMSC_TRACE(IFUP, "irq polarity: active low"); |
1199 | } |
1200 | |
1201 | if (pdata->config.irq_type) { |
1202 | SMSC_TRACE(IFUP, "irq type: push-pull"); |
1203 | intcfg |= INT_CFG_IRQ_TYPE_; |
1204 | } else { |
1205 | SMSC_TRACE(IFUP, "irq type: open drain"); |
1206 | } |
1207 | |
1208 | smsc911x_reg_write(pdata, INT_CFG, intcfg); |
1209 | |
1210 | SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq); |
1211 | pdata->software_irq_signal = 0; |
1212 | smp_wmb(); |
1213 | |
1214 | temp = smsc911x_reg_read(pdata, INT_EN); |
1215 | temp |= INT_EN_SW_INT_EN_; |
1216 | smsc911x_reg_write(pdata, INT_EN, temp); |
1217 | |
1218 | timeout = 1000; |
1219 | while (timeout--) { |
1220 | if (pdata->software_irq_signal) |
1221 | break; |
1222 | msleep(1); |
1223 | } |
1224 | |
1225 | if (!pdata->software_irq_signal) { |
1226 | dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n", |
1227 | dev->irq); |
1228 | return -ENODEV; |
1229 | } |
1230 | SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq); |
1231 | |
1232 | dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n", |
1233 | (unsigned long)pdata->ioaddr, dev->irq); |
1234 | |
1235 | /* Reset the last known duplex and carrier */ |
1236 | pdata->last_duplex = -1; |
1237 | pdata->last_carrier = -1; |
1238 | |
1239 | /* Bring the PHY up */ |
1240 | phy_start(pdata->phy_dev); |
1241 | |
1242 | temp = smsc911x_reg_read(pdata, HW_CFG); |
1243 | /* Preserve TX FIFO size and external PHY configuration */ |
1244 | temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF); |
1245 | temp |= HW_CFG_SF_; |
1246 | smsc911x_reg_write(pdata, HW_CFG, temp); |
1247 | |
1248 | temp = smsc911x_reg_read(pdata, FIFO_INT); |
1249 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; |
1250 | temp &= ~(FIFO_INT_RX_STS_LEVEL_); |
1251 | smsc911x_reg_write(pdata, FIFO_INT, temp); |
1252 | |
1253 | /* set RX Data offset to 2 bytes for alignment */ |
1254 | smsc911x_reg_write(pdata, RX_CFG, (2 << 8)); |
1255 | |
1256 | /* enable NAPI polling before enabling RX interrupts */ |
1257 | napi_enable(&pdata->napi); |
1258 | |
1259 | temp = smsc911x_reg_read(pdata, INT_EN); |
1260 | temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_); |
1261 | smsc911x_reg_write(pdata, INT_EN, temp); |
1262 | |
1263 | spin_lock_irq(&pdata->mac_lock); |
1264 | temp = smsc911x_mac_read(pdata, MAC_CR); |
1265 | temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); |
1266 | smsc911x_mac_write(pdata, MAC_CR, temp); |
1267 | spin_unlock_irq(&pdata->mac_lock); |
1268 | |
1269 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); |
1270 | |
1271 | netif_start_queue(dev); |
1272 | return 0; |
1273 | } |
1274 | |
1275 | /* Entry point for stopping the interface */ |
1276 | static int smsc911x_stop(struct net_device *dev) |
1277 | { |
1278 | struct smsc911x_data *pdata = netdev_priv(dev); |
1279 | unsigned int temp; |
1280 | |
1281 | /* Disable all device interrupts */ |
1282 | temp = smsc911x_reg_read(pdata, INT_CFG); |
1283 | temp &= ~INT_CFG_IRQ_EN_; |
1284 | smsc911x_reg_write(pdata, INT_CFG, temp); |
1285 | |
1286 | /* Stop Tx and Rx polling */ |
1287 | netif_stop_queue(dev); |
1288 | napi_disable(&pdata->napi); |
1289 | |
1290 | /* At this point all Rx and Tx activity is stopped */ |
1291 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); |
1292 | smsc911x_tx_update_txcounters(dev); |
1293 | |
1294 | /* Bring the PHY down */ |
1295 | if (pdata->phy_dev) |
1296 | phy_stop(pdata->phy_dev); |
1297 | |
1298 | SMSC_TRACE(IFDOWN, "Interface stopped"); |
1299 | return 0; |
1300 | } |
1301 | |
1302 | /* Entry point for transmitting a packet */ |
1303 | static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1304 | { |
1305 | struct smsc911x_data *pdata = netdev_priv(dev); |
1306 | unsigned int freespace; |
1307 | unsigned int tx_cmd_a; |
1308 | unsigned int tx_cmd_b; |
1309 | unsigned int temp; |
1310 | u32 wrsz; |
1311 | ulong bufp; |
1312 | |
1313 | freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_; |
1314 | |
1315 | if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD)) |
1316 | SMSC_WARNING(TX_ERR, |
1317 | "Tx data fifo low, space available: %d", freespace); |
1318 | |
1319 | /* Word alignment adjustment */ |
1320 | tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16; |
1321 | tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; |
1322 | tx_cmd_a |= (unsigned int)skb->len; |
1323 | |
1324 | tx_cmd_b = ((unsigned int)skb->len) << 16; |
1325 | tx_cmd_b |= (unsigned int)skb->len; |
1326 | |
1327 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a); |
1328 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b); |
1329 | |
1330 | bufp = (ulong)skb->data & (~0x3); |
1331 | wrsz = (u32)skb->len + 3; |
1332 | wrsz += (u32)((ulong)skb->data & 0x3); |
1333 | wrsz >>= 2; |
1334 | |
1335 | smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
1336 | freespace -= (skb->len + 32); |
1337 | dev_kfree_skb(skb); |
1338 | dev->trans_start = jiffies; |
1339 | |
1340 | if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30)) |
1341 | smsc911x_tx_update_txcounters(dev); |
1342 | |
1343 | if (freespace < TX_FIFO_LOW_THRESHOLD) { |
1344 | netif_stop_queue(dev); |
1345 | temp = smsc911x_reg_read(pdata, FIFO_INT); |
1346 | temp &= 0x00FFFFFF; |
1347 | temp |= 0x32000000; |
1348 | smsc911x_reg_write(pdata, FIFO_INT, temp); |
1349 | } |
1350 | |
1351 | return NETDEV_TX_OK; |
1352 | } |
1353 | |
1354 | /* Entry point for getting status counters */ |
1355 | static struct net_device_stats *smsc911x_get_stats(struct net_device *dev) |
1356 | { |
1357 | struct smsc911x_data *pdata = netdev_priv(dev); |
1358 | smsc911x_tx_update_txcounters(dev); |
1359 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); |
1360 | return &dev->stats; |
1361 | } |
1362 | |
1363 | /* Entry point for setting addressing modes */ |
1364 | static void smsc911x_set_multicast_list(struct net_device *dev) |
1365 | { |
1366 | struct smsc911x_data *pdata = netdev_priv(dev); |
1367 | unsigned long flags; |
1368 | |
1369 | if (dev->flags & IFF_PROMISC) { |
1370 | /* Enabling promiscuous mode */ |
1371 | pdata->set_bits_mask = MAC_CR_PRMS_; |
1372 | pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); |
1373 | pdata->hashhi = 0; |
1374 | pdata->hashlo = 0; |
1375 | } else if (dev->flags & IFF_ALLMULTI) { |
1376 | /* Enabling all multicast mode */ |
1377 | pdata->set_bits_mask = MAC_CR_MCPAS_; |
1378 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); |
1379 | pdata->hashhi = 0; |
1380 | pdata->hashlo = 0; |
1381 | } else if (!netdev_mc_empty(dev)) { |
1382 | /* Enabling specific multicast addresses */ |
1383 | unsigned int hash_high = 0; |
1384 | unsigned int hash_low = 0; |
1385 | struct dev_mc_list *mc_list; |
1386 | |
1387 | pdata->set_bits_mask = MAC_CR_HPFILT_; |
1388 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); |
1389 | |
1390 | netdev_for_each_mc_addr(mc_list, dev) { |
1391 | unsigned int bitnum = smsc911x_hash(mc_list->dmi_addr); |
1392 | unsigned int mask = 0x01 << (bitnum & 0x1F); |
1393 | |
1394 | if (bitnum & 0x20) |
1395 | hash_high |= mask; |
1396 | else |
1397 | hash_low |= mask; |
1398 | } |
1399 | |
1400 | pdata->hashhi = hash_high; |
1401 | pdata->hashlo = hash_low; |
1402 | } else { |
1403 | /* Enabling local MAC address only */ |
1404 | pdata->set_bits_mask = 0; |
1405 | pdata->clear_bits_mask = |
1406 | (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); |
1407 | pdata->hashhi = 0; |
1408 | pdata->hashlo = 0; |
1409 | } |
1410 | |
1411 | spin_lock_irqsave(&pdata->mac_lock, flags); |
1412 | |
1413 | if (pdata->generation <= 1) { |
1414 | /* Older hardware revision - cannot change these flags while |
1415 | * receiving data */ |
1416 | if (!pdata->multicast_update_pending) { |
1417 | unsigned int temp; |
1418 | SMSC_TRACE(HW, "scheduling mcast update"); |
1419 | pdata->multicast_update_pending = 1; |
1420 | |
1421 | /* Request the hardware to stop, then perform the |
1422 | * update when we get an RX_STOP interrupt */ |
1423 | temp = smsc911x_mac_read(pdata, MAC_CR); |
1424 | temp &= ~(MAC_CR_RXEN_); |
1425 | smsc911x_mac_write(pdata, MAC_CR, temp); |
1426 | } else { |
1427 | /* There is another update pending, this should now |
1428 | * use the newer values */ |
1429 | } |
1430 | } else { |
1431 | /* Newer hardware revision - can write immediately */ |
1432 | smsc911x_rx_multicast_update(pdata); |
1433 | } |
1434 | |
1435 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
1436 | } |
1437 | |
1438 | static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id) |
1439 | { |
1440 | struct net_device *dev = dev_id; |
1441 | struct smsc911x_data *pdata = netdev_priv(dev); |
1442 | u32 intsts = smsc911x_reg_read(pdata, INT_STS); |
1443 | u32 inten = smsc911x_reg_read(pdata, INT_EN); |
1444 | int serviced = IRQ_NONE; |
1445 | u32 temp; |
1446 | |
1447 | if (unlikely(intsts & inten & INT_STS_SW_INT_)) { |
1448 | temp = smsc911x_reg_read(pdata, INT_EN); |
1449 | temp &= (~INT_EN_SW_INT_EN_); |
1450 | smsc911x_reg_write(pdata, INT_EN, temp); |
1451 | smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_); |
1452 | pdata->software_irq_signal = 1; |
1453 | smp_wmb(); |
1454 | serviced = IRQ_HANDLED; |
1455 | } |
1456 | |
1457 | if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) { |
1458 | /* Called when there is a multicast update scheduled and |
1459 | * it is now safe to complete the update */ |
1460 | SMSC_TRACE(INTR, "RX Stop interrupt"); |
1461 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_); |
1462 | if (pdata->multicast_update_pending) |
1463 | smsc911x_rx_multicast_update_workaround(pdata); |
1464 | serviced = IRQ_HANDLED; |
1465 | } |
1466 | |
1467 | if (intsts & inten & INT_STS_TDFA_) { |
1468 | temp = smsc911x_reg_read(pdata, FIFO_INT); |
1469 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; |
1470 | smsc911x_reg_write(pdata, FIFO_INT, temp); |
1471 | smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_); |
1472 | netif_wake_queue(dev); |
1473 | serviced = IRQ_HANDLED; |
1474 | } |
1475 | |
1476 | if (unlikely(intsts & inten & INT_STS_RXE_)) { |
1477 | SMSC_TRACE(INTR, "RX Error interrupt"); |
1478 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_); |
1479 | serviced = IRQ_HANDLED; |
1480 | } |
1481 | |
1482 | if (likely(intsts & inten & INT_STS_RSFL_)) { |
1483 | if (likely(napi_schedule_prep(&pdata->napi))) { |
1484 | /* Disable Rx interrupts */ |
1485 | temp = smsc911x_reg_read(pdata, INT_EN); |
1486 | temp &= (~INT_EN_RSFL_EN_); |
1487 | smsc911x_reg_write(pdata, INT_EN, temp); |
1488 | /* Schedule a NAPI poll */ |
1489 | __napi_schedule(&pdata->napi); |
1490 | } else { |
1491 | SMSC_WARNING(RX_ERR, |
1492 | "napi_schedule_prep failed"); |
1493 | } |
1494 | serviced = IRQ_HANDLED; |
1495 | } |
1496 | |
1497 | return serviced; |
1498 | } |
1499 | |
1500 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1501 | static void smsc911x_poll_controller(struct net_device *dev) |
1502 | { |
1503 | disable_irq(dev->irq); |
1504 | smsc911x_irqhandler(0, dev); |
1505 | enable_irq(dev->irq); |
1506 | } |
1507 | #endif /* CONFIG_NET_POLL_CONTROLLER */ |
1508 | |
1509 | static int smsc911x_set_mac_address(struct net_device *dev, void *p) |
1510 | { |
1511 | struct smsc911x_data *pdata = netdev_priv(dev); |
1512 | struct sockaddr *addr = p; |
1513 | |
1514 | /* On older hardware revisions we cannot change the mac address |
1515 | * registers while receiving data. Newer devices can safely change |
1516 | * this at any time. */ |
1517 | if (pdata->generation <= 1 && netif_running(dev)) |
1518 | return -EBUSY; |
1519 | |
1520 | if (!is_valid_ether_addr(addr->sa_data)) |
1521 | return -EADDRNOTAVAIL; |
1522 | |
1523 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
1524 | |
1525 | spin_lock_irq(&pdata->mac_lock); |
1526 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
1527 | spin_unlock_irq(&pdata->mac_lock); |
1528 | |
1529 | dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr); |
1530 | |
1531 | return 0; |
1532 | } |
1533 | |
1534 | /* Standard ioctls for mii-tool */ |
1535 | static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1536 | { |
1537 | struct smsc911x_data *pdata = netdev_priv(dev); |
1538 | |
1539 | if (!netif_running(dev) || !pdata->phy_dev) |
1540 | return -EINVAL; |
1541 | |
1542 | return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd); |
1543 | } |
1544 | |
1545 | static int |
1546 | smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) |
1547 | { |
1548 | struct smsc911x_data *pdata = netdev_priv(dev); |
1549 | |
1550 | cmd->maxtxpkt = 1; |
1551 | cmd->maxrxpkt = 1; |
1552 | return phy_ethtool_gset(pdata->phy_dev, cmd); |
1553 | } |
1554 | |
1555 | static int |
1556 | smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) |
1557 | { |
1558 | struct smsc911x_data *pdata = netdev_priv(dev); |
1559 | |
1560 | return phy_ethtool_sset(pdata->phy_dev, cmd); |
1561 | } |
1562 | |
1563 | static void smsc911x_ethtool_getdrvinfo(struct net_device *dev, |
1564 | struct ethtool_drvinfo *info) |
1565 | { |
1566 | strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver)); |
1567 | strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version)); |
1568 | strlcpy(info->bus_info, dev_name(dev->dev.parent), |
1569 | sizeof(info->bus_info)); |
1570 | } |
1571 | |
1572 | static int smsc911x_ethtool_nwayreset(struct net_device *dev) |
1573 | { |
1574 | struct smsc911x_data *pdata = netdev_priv(dev); |
1575 | |
1576 | return phy_start_aneg(pdata->phy_dev); |
1577 | } |
1578 | |
1579 | static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev) |
1580 | { |
1581 | struct smsc911x_data *pdata = netdev_priv(dev); |
1582 | return pdata->msg_enable; |
1583 | } |
1584 | |
1585 | static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level) |
1586 | { |
1587 | struct smsc911x_data *pdata = netdev_priv(dev); |
1588 | pdata->msg_enable = level; |
1589 | } |
1590 | |
1591 | static int smsc911x_ethtool_getregslen(struct net_device *dev) |
1592 | { |
1593 | return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) * |
1594 | sizeof(u32); |
1595 | } |
1596 | |
1597 | static void |
1598 | smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, |
1599 | void *buf) |
1600 | { |
1601 | struct smsc911x_data *pdata = netdev_priv(dev); |
1602 | struct phy_device *phy_dev = pdata->phy_dev; |
1603 | unsigned long flags; |
1604 | unsigned int i; |
1605 | unsigned int j = 0; |
1606 | u32 *data = buf; |
1607 | |
1608 | regs->version = pdata->idrev; |
1609 | for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32))) |
1610 | data[j++] = smsc911x_reg_read(pdata, i); |
1611 | |
1612 | for (i = MAC_CR; i <= WUCSR; i++) { |
1613 | spin_lock_irqsave(&pdata->mac_lock, flags); |
1614 | data[j++] = smsc911x_mac_read(pdata, i); |
1615 | spin_unlock_irqrestore(&pdata->mac_lock, flags); |
1616 | } |
1617 | |
1618 | for (i = 0; i <= 31; i++) |
1619 | data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i); |
1620 | } |
1621 | |
1622 | static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata) |
1623 | { |
1624 | unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG); |
1625 | temp &= ~GPIO_CFG_EEPR_EN_; |
1626 | smsc911x_reg_write(pdata, GPIO_CFG, temp); |
1627 | msleep(1); |
1628 | } |
1629 | |
1630 | static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op) |
1631 | { |
1632 | int timeout = 100; |
1633 | u32 e2cmd; |
1634 | |
1635 | SMSC_TRACE(DRV, "op 0x%08x", op); |
1636 | if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) { |
1637 | SMSC_WARNING(DRV, "Busy at start"); |
1638 | return -EBUSY; |
1639 | } |
1640 | |
1641 | e2cmd = op | E2P_CMD_EPC_BUSY_; |
1642 | smsc911x_reg_write(pdata, E2P_CMD, e2cmd); |
1643 | |
1644 | do { |
1645 | msleep(1); |
1646 | e2cmd = smsc911x_reg_read(pdata, E2P_CMD); |
1647 | } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); |
1648 | |
1649 | if (!timeout) { |
1650 | SMSC_TRACE(DRV, "TIMED OUT"); |
1651 | return -EAGAIN; |
1652 | } |
1653 | |
1654 | if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { |
1655 | SMSC_TRACE(DRV, "Error occured during eeprom operation"); |
1656 | return -EINVAL; |
1657 | } |
1658 | |
1659 | return 0; |
1660 | } |
1661 | |
1662 | static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata, |
1663 | u8 address, u8 *data) |
1664 | { |
1665 | u32 op = E2P_CMD_EPC_CMD_READ_ | address; |
1666 | int ret; |
1667 | |
1668 | SMSC_TRACE(DRV, "address 0x%x", address); |
1669 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
1670 | |
1671 | if (!ret) |
1672 | data[address] = smsc911x_reg_read(pdata, E2P_DATA); |
1673 | |
1674 | return ret; |
1675 | } |
1676 | |
1677 | static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, |
1678 | u8 address, u8 data) |
1679 | { |
1680 | u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; |
1681 | u32 temp; |
1682 | int ret; |
1683 | |
1684 | SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data); |
1685 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
1686 | |
1687 | if (!ret) { |
1688 | op = E2P_CMD_EPC_CMD_WRITE_ | address; |
1689 | smsc911x_reg_write(pdata, E2P_DATA, (u32)data); |
1690 | |
1691 | /* Workaround for hardware read-after-write restriction */ |
1692 | temp = smsc911x_reg_read(pdata, BYTE_TEST); |
1693 | |
1694 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
1695 | } |
1696 | |
1697 | return ret; |
1698 | } |
1699 | |
1700 | static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev) |
1701 | { |
1702 | return SMSC911X_EEPROM_SIZE; |
1703 | } |
1704 | |
1705 | static int smsc911x_ethtool_get_eeprom(struct net_device *dev, |
1706 | struct ethtool_eeprom *eeprom, u8 *data) |
1707 | { |
1708 | struct smsc911x_data *pdata = netdev_priv(dev); |
1709 | u8 eeprom_data[SMSC911X_EEPROM_SIZE]; |
1710 | int len; |
1711 | int i; |
1712 | |
1713 | smsc911x_eeprom_enable_access(pdata); |
1714 | |
1715 | len = min(eeprom->len, SMSC911X_EEPROM_SIZE); |
1716 | for (i = 0; i < len; i++) { |
1717 | int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data); |
1718 | if (ret < 0) { |
1719 | eeprom->len = 0; |
1720 | return ret; |
1721 | } |
1722 | } |
1723 | |
1724 | memcpy(data, &eeprom_data[eeprom->offset], len); |
1725 | eeprom->len = len; |
1726 | return 0; |
1727 | } |
1728 | |
1729 | static int smsc911x_ethtool_set_eeprom(struct net_device *dev, |
1730 | struct ethtool_eeprom *eeprom, u8 *data) |
1731 | { |
1732 | int ret; |
1733 | struct smsc911x_data *pdata = netdev_priv(dev); |
1734 | |
1735 | smsc911x_eeprom_enable_access(pdata); |
1736 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_); |
1737 | ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data); |
1738 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_); |
1739 | |
1740 | /* Single byte write, according to man page */ |
1741 | eeprom->len = 1; |
1742 | |
1743 | return ret; |
1744 | } |
1745 | |
1746 | static const struct ethtool_ops smsc911x_ethtool_ops = { |
1747 | .get_settings = smsc911x_ethtool_getsettings, |
1748 | .set_settings = smsc911x_ethtool_setsettings, |
1749 | .get_link = ethtool_op_get_link, |
1750 | .get_drvinfo = smsc911x_ethtool_getdrvinfo, |
1751 | .nway_reset = smsc911x_ethtool_nwayreset, |
1752 | .get_msglevel = smsc911x_ethtool_getmsglevel, |
1753 | .set_msglevel = smsc911x_ethtool_setmsglevel, |
1754 | .get_regs_len = smsc911x_ethtool_getregslen, |
1755 | .get_regs = smsc911x_ethtool_getregs, |
1756 | .get_eeprom_len = smsc911x_ethtool_get_eeprom_len, |
1757 | .get_eeprom = smsc911x_ethtool_get_eeprom, |
1758 | .set_eeprom = smsc911x_ethtool_set_eeprom, |
1759 | }; |
1760 | |
1761 | static const struct net_device_ops smsc911x_netdev_ops = { |
1762 | .ndo_open = smsc911x_open, |
1763 | .ndo_stop = smsc911x_stop, |
1764 | .ndo_start_xmit = smsc911x_hard_start_xmit, |
1765 | .ndo_get_stats = smsc911x_get_stats, |
1766 | .ndo_set_multicast_list = smsc911x_set_multicast_list, |
1767 | .ndo_do_ioctl = smsc911x_do_ioctl, |
1768 | .ndo_change_mtu = eth_change_mtu, |
1769 | .ndo_validate_addr = eth_validate_addr, |
1770 | .ndo_set_mac_address = smsc911x_set_mac_address, |
1771 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1772 | .ndo_poll_controller = smsc911x_poll_controller, |
1773 | #endif |
1774 | }; |
1775 | |
1776 | /* copies the current mac address from hardware to dev->dev_addr */ |
1777 | static void __devinit smsc911x_read_mac_address(struct net_device *dev) |
1778 | { |
1779 | struct smsc911x_data *pdata = netdev_priv(dev); |
1780 | u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH); |
1781 | u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL); |
1782 | |
1783 | dev->dev_addr[0] = (u8)(mac_low32); |
1784 | dev->dev_addr[1] = (u8)(mac_low32 >> 8); |
1785 | dev->dev_addr[2] = (u8)(mac_low32 >> 16); |
1786 | dev->dev_addr[3] = (u8)(mac_low32 >> 24); |
1787 | dev->dev_addr[4] = (u8)(mac_high16); |
1788 | dev->dev_addr[5] = (u8)(mac_high16 >> 8); |
1789 | } |
1790 | |
1791 | /* Initializing private device structures, only called from probe */ |
1792 | static int __devinit smsc911x_init(struct net_device *dev) |
1793 | { |
1794 | struct smsc911x_data *pdata = netdev_priv(dev); |
1795 | unsigned int byte_test; |
1796 | |
1797 | SMSC_TRACE(PROBE, "Driver Parameters:"); |
1798 | SMSC_TRACE(PROBE, "LAN base: 0x%08lX", |
1799 | (unsigned long)pdata->ioaddr); |
1800 | SMSC_TRACE(PROBE, "IRQ: %d", dev->irq); |
1801 | SMSC_TRACE(PROBE, "PHY will be autodetected."); |
1802 | |
1803 | spin_lock_init(&pdata->dev_lock); |
1804 | |
1805 | if (pdata->ioaddr == 0) { |
1806 | SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000"); |
1807 | return -ENODEV; |
1808 | } |
1809 | |
1810 | /* Check byte ordering */ |
1811 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); |
1812 | SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test); |
1813 | if (byte_test == 0x43218765) { |
1814 | SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, " |
1815 | "applying WORD_SWAP"); |
1816 | smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff); |
1817 | |
1818 | /* 1 dummy read of BYTE_TEST is needed after a write to |
1819 | * WORD_SWAP before its contents are valid */ |
1820 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); |
1821 | |
1822 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); |
1823 | } |
1824 | |
1825 | if (byte_test != 0x87654321) { |
1826 | SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test); |
1827 | if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) { |
1828 | SMSC_WARNING(PROBE, |
1829 | "top 16 bits equal to bottom 16 bits"); |
1830 | SMSC_TRACE(PROBE, "This may mean the chip is set " |
1831 | "for 32 bit while the bus is reading 16 bit"); |
1832 | } |
1833 | return -ENODEV; |
1834 | } |
1835 | |
1836 | /* Default generation to zero (all workarounds apply) */ |
1837 | pdata->generation = 0; |
1838 | |
1839 | pdata->idrev = smsc911x_reg_read(pdata, ID_REV); |
1840 | switch (pdata->idrev & 0xFFFF0000) { |
1841 | case 0x01180000: |
1842 | case 0x01170000: |
1843 | case 0x01160000: |
1844 | case 0x01150000: |
1845 | /* LAN911[5678] family */ |
1846 | pdata->generation = pdata->idrev & 0x0000FFFF; |
1847 | break; |
1848 | |
1849 | case 0x118A0000: |
1850 | case 0x117A0000: |
1851 | case 0x116A0000: |
1852 | case 0x115A0000: |
1853 | /* LAN921[5678] family */ |
1854 | pdata->generation = 3; |
1855 | break; |
1856 | |
1857 | case 0x92100000: |
1858 | case 0x92110000: |
1859 | case 0x92200000: |
1860 | case 0x92210000: |
1861 | /* LAN9210/LAN9211/LAN9220/LAN9221 */ |
1862 | pdata->generation = 4; |
1863 | break; |
1864 | |
1865 | default: |
1866 | SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X", |
1867 | pdata->idrev); |
1868 | return -ENODEV; |
1869 | } |
1870 | |
1871 | SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d", |
1872 | pdata->idrev, pdata->generation); |
1873 | |
1874 | if (pdata->generation == 0) |
1875 | SMSC_WARNING(PROBE, |
1876 | "This driver is not intended for this chip revision"); |
1877 | |
1878 | /* workaround for platforms without an eeprom, where the mac address |
1879 | * is stored elsewhere and set by the bootloader. This saves the |
1880 | * mac address before resetting the device */ |
1881 | if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) |
1882 | smsc911x_read_mac_address(dev); |
1883 | |
1884 | /* Reset the LAN911x */ |
1885 | if (smsc911x_soft_reset(pdata)) |
1886 | return -ENODEV; |
1887 | |
1888 | /* Disable all interrupt sources until we bring the device up */ |
1889 | smsc911x_reg_write(pdata, INT_EN, 0); |
1890 | |
1891 | ether_setup(dev); |
1892 | dev->flags |= IFF_MULTICAST; |
1893 | netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT); |
1894 | dev->netdev_ops = &smsc911x_netdev_ops; |
1895 | dev->ethtool_ops = &smsc911x_ethtool_ops; |
1896 | |
1897 | return 0; |
1898 | } |
1899 | |
1900 | static int __devexit smsc911x_drv_remove(struct platform_device *pdev) |
1901 | { |
1902 | struct net_device *dev; |
1903 | struct smsc911x_data *pdata; |
1904 | struct resource *res; |
1905 | |
1906 | dev = platform_get_drvdata(pdev); |
1907 | BUG_ON(!dev); |
1908 | pdata = netdev_priv(dev); |
1909 | BUG_ON(!pdata); |
1910 | BUG_ON(!pdata->ioaddr); |
1911 | BUG_ON(!pdata->phy_dev); |
1912 | |
1913 | SMSC_TRACE(IFDOWN, "Stopping driver."); |
1914 | |
1915 | phy_disconnect(pdata->phy_dev); |
1916 | pdata->phy_dev = NULL; |
1917 | mdiobus_unregister(pdata->mii_bus); |
1918 | mdiobus_free(pdata->mii_bus); |
1919 | |
1920 | platform_set_drvdata(pdev, NULL); |
1921 | unregister_netdev(dev); |
1922 | free_irq(dev->irq, dev); |
1923 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
1924 | "smsc911x-memory"); |
1925 | if (!res) |
1926 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1927 | |
1928 | release_mem_region(res->start, resource_size(res)); |
1929 | |
1930 | iounmap(pdata->ioaddr); |
1931 | |
1932 | free_netdev(dev); |
1933 | |
1934 | return 0; |
1935 | } |
1936 | |
1937 | static int __devinit smsc911x_drv_probe(struct platform_device *pdev) |
1938 | { |
1939 | struct net_device *dev; |
1940 | struct smsc911x_data *pdata; |
1941 | struct smsc911x_platform_config *config = pdev->dev.platform_data; |
1942 | struct resource *res, *irq_res; |
1943 | unsigned int intcfg = 0; |
1944 | int res_size, irq_flags; |
1945 | int retval; |
1946 | |
1947 | pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION); |
1948 | |
1949 | /* platform data specifies irq & dynamic bus configuration */ |
1950 | if (!pdev->dev.platform_data) { |
1951 | pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME); |
1952 | retval = -ENODEV; |
1953 | goto out_0; |
1954 | } |
1955 | |
1956 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
1957 | "smsc911x-memory"); |
1958 | if (!res) |
1959 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1960 | if (!res) { |
1961 | pr_warning("%s: Could not allocate resource.\n", |
1962 | SMSC_CHIPNAME); |
1963 | retval = -ENODEV; |
1964 | goto out_0; |
1965 | } |
1966 | res_size = resource_size(res); |
1967 | |
1968 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1969 | if (!irq_res) { |
1970 | pr_warning("%s: Could not allocate irq resource.\n", |
1971 | SMSC_CHIPNAME); |
1972 | retval = -ENODEV; |
1973 | goto out_0; |
1974 | } |
1975 | |
1976 | if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) { |
1977 | retval = -EBUSY; |
1978 | goto out_0; |
1979 | } |
1980 | |
1981 | dev = alloc_etherdev(sizeof(struct smsc911x_data)); |
1982 | if (!dev) { |
1983 | pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME); |
1984 | retval = -ENOMEM; |
1985 | goto out_release_io_1; |
1986 | } |
1987 | |
1988 | SET_NETDEV_DEV(dev, &pdev->dev); |
1989 | |
1990 | pdata = netdev_priv(dev); |
1991 | |
1992 | dev->irq = irq_res->start; |
1993 | irq_flags = irq_res->flags & IRQF_TRIGGER_MASK; |
1994 | pdata->ioaddr = ioremap_nocache(res->start, res_size); |
1995 | |
1996 | /* copy config parameters across to pdata */ |
1997 | memcpy(&pdata->config, config, sizeof(pdata->config)); |
1998 | |
1999 | pdata->dev = dev; |
2000 | pdata->msg_enable = ((1 << debug) - 1); |
2001 | |
2002 | if (pdata->ioaddr == NULL) { |
2003 | SMSC_WARNING(PROBE, |
2004 | "Error smsc911x base address invalid"); |
2005 | retval = -ENOMEM; |
2006 | goto out_free_netdev_2; |
2007 | } |
2008 | |
2009 | retval = smsc911x_init(dev); |
2010 | if (retval < 0) |
2011 | goto out_unmap_io_3; |
2012 | |
2013 | /* configure irq polarity and type before connecting isr */ |
2014 | if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH) |
2015 | intcfg |= INT_CFG_IRQ_POL_; |
2016 | |
2017 | if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL) |
2018 | intcfg |= INT_CFG_IRQ_TYPE_; |
2019 | |
2020 | smsc911x_reg_write(pdata, INT_CFG, intcfg); |
2021 | |
2022 | /* Ensure interrupts are globally disabled before connecting ISR */ |
2023 | smsc911x_reg_write(pdata, INT_EN, 0); |
2024 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); |
2025 | |
2026 | retval = request_irq(dev->irq, smsc911x_irqhandler, |
2027 | irq_flags | IRQF_SHARED, dev->name, dev); |
2028 | if (retval) { |
2029 | SMSC_WARNING(PROBE, |
2030 | "Unable to claim requested irq: %d", dev->irq); |
2031 | goto out_unmap_io_3; |
2032 | } |
2033 | |
2034 | platform_set_drvdata(pdev, dev); |
2035 | |
2036 | retval = register_netdev(dev); |
2037 | if (retval) { |
2038 | SMSC_WARNING(PROBE, |
2039 | "Error %i registering device", retval); |
2040 | goto out_unset_drvdata_4; |
2041 | } else { |
2042 | SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name); |
2043 | } |
2044 | |
2045 | spin_lock_init(&pdata->mac_lock); |
2046 | |
2047 | retval = smsc911x_mii_init(pdev, dev); |
2048 | if (retval) { |
2049 | SMSC_WARNING(PROBE, |
2050 | "Error %i initialising mii", retval); |
2051 | goto out_unregister_netdev_5; |
2052 | } |
2053 | |
2054 | spin_lock_irq(&pdata->mac_lock); |
2055 | |
2056 | /* Check if mac address has been specified when bringing interface up */ |
2057 | if (is_valid_ether_addr(dev->dev_addr)) { |
2058 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
2059 | SMSC_TRACE(PROBE, "MAC Address is specified by configuration"); |
2060 | } else if (is_valid_ether_addr(pdata->config.mac)) { |
2061 | memcpy(dev->dev_addr, pdata->config.mac, 6); |
2062 | SMSC_TRACE(PROBE, "MAC Address specified by platform data"); |
2063 | } else { |
2064 | /* Try reading mac address from device. if EEPROM is present |
2065 | * it will already have been set */ |
2066 | smsc911x_read_mac_address(dev); |
2067 | |
2068 | if (is_valid_ether_addr(dev->dev_addr)) { |
2069 | /* eeprom values are valid so use them */ |
2070 | SMSC_TRACE(PROBE, |
2071 | "Mac Address is read from LAN911x EEPROM"); |
2072 | } else { |
2073 | /* eeprom values are invalid, generate random MAC */ |
2074 | random_ether_addr(dev->dev_addr); |
2075 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
2076 | SMSC_TRACE(PROBE, |
2077 | "MAC Address is set to random_ether_addr"); |
2078 | } |
2079 | } |
2080 | |
2081 | spin_unlock_irq(&pdata->mac_lock); |
2082 | |
2083 | dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr); |
2084 | |
2085 | return 0; |
2086 | |
2087 | out_unregister_netdev_5: |
2088 | unregister_netdev(dev); |
2089 | out_unset_drvdata_4: |
2090 | platform_set_drvdata(pdev, NULL); |
2091 | free_irq(dev->irq, dev); |
2092 | out_unmap_io_3: |
2093 | iounmap(pdata->ioaddr); |
2094 | out_free_netdev_2: |
2095 | free_netdev(dev); |
2096 | out_release_io_1: |
2097 | release_mem_region(res->start, resource_size(res)); |
2098 | out_0: |
2099 | return retval; |
2100 | } |
2101 | |
2102 | #ifdef CONFIG_PM |
2103 | /* This implementation assumes the devices remains powered on its VDDVARIO |
2104 | * pins during suspend. */ |
2105 | |
2106 | /* TODO: implement freeze/thaw callbacks for hibernation.*/ |
2107 | |
2108 | static int smsc911x_suspend(struct device *dev) |
2109 | { |
2110 | struct net_device *ndev = dev_get_drvdata(dev); |
2111 | struct smsc911x_data *pdata = netdev_priv(ndev); |
2112 | |
2113 | /* enable wake on LAN, energy detection and the external PME |
2114 | * signal. */ |
2115 | smsc911x_reg_write(pdata, PMT_CTRL, |
2116 | PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ | |
2117 | PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_); |
2118 | |
2119 | return 0; |
2120 | } |
2121 | |
2122 | static int smsc911x_resume(struct device *dev) |
2123 | { |
2124 | struct net_device *ndev = dev_get_drvdata(dev); |
2125 | struct smsc911x_data *pdata = netdev_priv(ndev); |
2126 | unsigned int to = 100; |
2127 | |
2128 | /* Note 3.11 from the datasheet: |
2129 | * "When the LAN9220 is in a power saving state, a write of any |
2130 | * data to the BYTE_TEST register will wake-up the device." |
2131 | */ |
2132 | smsc911x_reg_write(pdata, BYTE_TEST, 0); |
2133 | |
2134 | /* poll the READY bit in PMT_CTRL. Any other access to the device is |
2135 | * forbidden while this bit isn't set. Try for 100ms and return -EIO |
2136 | * if it failed. */ |
2137 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) |
2138 | udelay(1000); |
2139 | |
2140 | return (to == 0) ? -EIO : 0; |
2141 | } |
2142 | |
2143 | static const struct dev_pm_ops smsc911x_pm_ops = { |
2144 | .suspend = smsc911x_suspend, |
2145 | .resume = smsc911x_resume, |
2146 | }; |
2147 | |
2148 | #define SMSC911X_PM_OPS (&smsc911x_pm_ops) |
2149 | |
2150 | #else |
2151 | #define SMSC911X_PM_OPS NULL |
2152 | #endif |
2153 | |
2154 | static struct platform_driver smsc911x_driver = { |
2155 | .probe = smsc911x_drv_probe, |
2156 | .remove = __devexit_p(smsc911x_drv_remove), |
2157 | .driver = { |
2158 | .name = SMSC_CHIPNAME, |
2159 | .owner = THIS_MODULE, |
2160 | .pm = SMSC911X_PM_OPS, |
2161 | }, |
2162 | }; |
2163 | |
2164 | /* Entry point for loading the module */ |
2165 | static int __init smsc911x_init_module(void) |
2166 | { |
2167 | return platform_driver_register(&smsc911x_driver); |
2168 | } |
2169 | |
2170 | /* entry point for unloading the module */ |
2171 | static void __exit smsc911x_cleanup_module(void) |
2172 | { |
2173 | platform_driver_unregister(&smsc911x_driver); |
2174 | } |
2175 | |
2176 | module_init(smsc911x_init_module); |
2177 | module_exit(smsc911x_cleanup_module); |
2178 |
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javiroman/ks7010
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jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9