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1 | /* |
2 | * drivers/pci/setup-res.c |
3 | * |
4 | * Extruded from code written by |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) |
6 | * David Mosberger (davidm@cs.arizona.edu) |
7 | * David Miller (davem@redhat.com) |
8 | * |
9 | * Support routines for initializing a PCI subsystem. |
10 | */ |
11 | |
12 | /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ |
13 | |
14 | /* |
15 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
16 | * Resource sorting |
17 | */ |
18 | |
19 | #include <linux/init.h> |
20 | #include <linux/kernel.h> |
21 | #include <linux/pci.h> |
22 | #include <linux/errno.h> |
23 | #include <linux/ioport.h> |
24 | #include <linux/cache.h> |
25 | #include <linux/slab.h> |
26 | #include "pci.h" |
27 | |
28 | |
29 | void pci_update_resource(struct pci_dev *dev, int resno) |
30 | { |
31 | struct pci_bus_region region; |
32 | u32 new, check, mask; |
33 | int reg; |
34 | enum pci_bar_type type; |
35 | struct resource *res = dev->resource + resno; |
36 | |
37 | /* |
38 | * Ignore resources for unimplemented BARs and unused resource slots |
39 | * for 64 bit BARs. |
40 | */ |
41 | if (!res->flags) |
42 | return; |
43 | |
44 | /* |
45 | * Ignore non-moveable resources. This might be legacy resources for |
46 | * which no functional BAR register exists or another important |
47 | * system resource we shouldn't move around. |
48 | */ |
49 | if (res->flags & IORESOURCE_PCI_FIXED) |
50 | return; |
51 | |
52 | pcibios_resource_to_bus(dev, ®ion, res); |
53 | |
54 | new = region.start | (res->flags & PCI_REGION_FLAG_MASK); |
55 | if (res->flags & IORESOURCE_IO) |
56 | mask = (u32)PCI_BASE_ADDRESS_IO_MASK; |
57 | else |
58 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
59 | |
60 | reg = pci_resource_bar(dev, resno, &type); |
61 | if (!reg) |
62 | return; |
63 | if (type != pci_bar_unknown) { |
64 | if (!(res->flags & IORESOURCE_ROM_ENABLE)) |
65 | return; |
66 | new |= PCI_ROM_ADDRESS_ENABLE; |
67 | } |
68 | |
69 | pci_write_config_dword(dev, reg, new); |
70 | pci_read_config_dword(dev, reg, &check); |
71 | |
72 | if ((new ^ check) & mask) { |
73 | dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", |
74 | resno, new, check); |
75 | } |
76 | |
77 | if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
78 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) { |
79 | new = region.start >> 16 >> 16; |
80 | pci_write_config_dword(dev, reg + 4, new); |
81 | pci_read_config_dword(dev, reg + 4, &check); |
82 | if (check != new) { |
83 | dev_err(&dev->dev, "BAR %d: error updating " |
84 | "(high %#08x != %#08x)\n", resno, new, check); |
85 | } |
86 | } |
87 | res->flags &= ~IORESOURCE_UNSET; |
88 | dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx]\n", |
89 | resno, res, (unsigned long long)region.start, |
90 | (unsigned long long)region.end); |
91 | } |
92 | |
93 | int pci_claim_resource(struct pci_dev *dev, int resource) |
94 | { |
95 | struct resource *res = &dev->resource[resource]; |
96 | struct resource *root, *conflict; |
97 | |
98 | root = pci_find_parent_resource(dev, res); |
99 | if (!root) { |
100 | dev_err(&dev->dev, "no compatible bridge window for %pR\n", |
101 | res); |
102 | return -EINVAL; |
103 | } |
104 | |
105 | conflict = request_resource_conflict(root, res); |
106 | if (conflict) { |
107 | dev_err(&dev->dev, |
108 | "address space collision: %pR conflicts with %s %pR\n", |
109 | res, conflict->name, conflict); |
110 | return -EBUSY; |
111 | } |
112 | |
113 | return 0; |
114 | } |
115 | EXPORT_SYMBOL(pci_claim_resource); |
116 | |
117 | #ifdef CONFIG_PCI_QUIRKS |
118 | void pci_disable_bridge_window(struct pci_dev *dev) |
119 | { |
120 | dev_info(&dev->dev, "disabling bridge mem windows\n"); |
121 | |
122 | /* MMIO Base/Limit */ |
123 | pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); |
124 | |
125 | /* Prefetchable MMIO Base/Limit */ |
126 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); |
127 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); |
128 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); |
129 | } |
130 | #endif /* CONFIG_PCI_QUIRKS */ |
131 | |
132 | static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, |
133 | int resno) |
134 | { |
135 | struct resource *res = dev->resource + resno; |
136 | resource_size_t size, min, align; |
137 | int ret; |
138 | |
139 | size = resource_size(res); |
140 | min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; |
141 | align = pci_resource_alignment(dev, res); |
142 | |
143 | /* First, try exact prefetching match.. */ |
144 | ret = pci_bus_alloc_resource(bus, res, size, align, min, |
145 | IORESOURCE_PREFETCH, |
146 | pcibios_align_resource, dev); |
147 | |
148 | if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) { |
149 | /* |
150 | * That failed. |
151 | * |
152 | * But a prefetching area can handle a non-prefetching |
153 | * window (it will just not perform as well). |
154 | */ |
155 | ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, |
156 | pcibios_align_resource, dev); |
157 | } |
158 | |
159 | if (!ret) { |
160 | res->flags &= ~IORESOURCE_STARTALIGN; |
161 | dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); |
162 | if (resno < PCI_BRIDGE_RESOURCES) |
163 | pci_update_resource(dev, resno); |
164 | } |
165 | |
166 | return ret; |
167 | } |
168 | |
169 | int pci_assign_resource(struct pci_dev *dev, int resno) |
170 | { |
171 | struct resource *res = dev->resource + resno; |
172 | resource_size_t align; |
173 | struct pci_bus *bus; |
174 | int ret; |
175 | char *type; |
176 | |
177 | align = pci_resource_alignment(dev, res); |
178 | if (!align) { |
179 | dev_info(&dev->dev, "BAR %d: can't assign %pR " |
180 | "(bogus alignment)\n", resno, res); |
181 | return -EINVAL; |
182 | } |
183 | |
184 | bus = dev->bus; |
185 | while ((ret = __pci_assign_resource(bus, dev, resno))) { |
186 | if (bus->parent && bus->self->transparent) |
187 | bus = bus->parent; |
188 | else |
189 | bus = NULL; |
190 | if (bus) |
191 | continue; |
192 | break; |
193 | } |
194 | |
195 | if (ret) { |
196 | if (res->flags & IORESOURCE_MEM) |
197 | if (res->flags & IORESOURCE_PREFETCH) |
198 | type = "mem pref"; |
199 | else |
200 | type = "mem"; |
201 | else if (res->flags & IORESOURCE_IO) |
202 | type = "io"; |
203 | else |
204 | type = "unknown"; |
205 | dev_info(&dev->dev, |
206 | "BAR %d: can't assign %s (size %#llx)\n", |
207 | resno, type, (unsigned long long) resource_size(res)); |
208 | } |
209 | |
210 | return ret; |
211 | } |
212 | |
213 | /* Sort resources by alignment */ |
214 | void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head) |
215 | { |
216 | int i; |
217 | |
218 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
219 | struct resource *r; |
220 | struct resource_list *list, *tmp; |
221 | resource_size_t r_align; |
222 | |
223 | r = &dev->resource[i]; |
224 | |
225 | if (r->flags & IORESOURCE_PCI_FIXED) |
226 | continue; |
227 | |
228 | if (!(r->flags) || r->parent) |
229 | continue; |
230 | |
231 | r_align = pci_resource_alignment(dev, r); |
232 | if (!r_align) { |
233 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", |
234 | i, r); |
235 | continue; |
236 | } |
237 | for (list = head; ; list = list->next) { |
238 | resource_size_t align = 0; |
239 | struct resource_list *ln = list->next; |
240 | |
241 | if (ln) |
242 | align = pci_resource_alignment(ln->dev, ln->res); |
243 | |
244 | if (r_align > align) { |
245 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); |
246 | if (!tmp) |
247 | panic("pdev_sort_resources(): " |
248 | "kmalloc() failed!\n"); |
249 | tmp->next = ln; |
250 | tmp->res = r; |
251 | tmp->dev = dev; |
252 | list->next = tmp; |
253 | break; |
254 | } |
255 | } |
256 | } |
257 | } |
258 | |
259 | int pci_enable_resources(struct pci_dev *dev, int mask) |
260 | { |
261 | u16 cmd, old_cmd; |
262 | int i; |
263 | struct resource *r; |
264 | |
265 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
266 | old_cmd = cmd; |
267 | |
268 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
269 | if (!(mask & (1 << i))) |
270 | continue; |
271 | |
272 | r = &dev->resource[i]; |
273 | |
274 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) |
275 | continue; |
276 | if ((i == PCI_ROM_RESOURCE) && |
277 | (!(r->flags & IORESOURCE_ROM_ENABLE))) |
278 | continue; |
279 | |
280 | if (!r->parent) { |
281 | dev_err(&dev->dev, "device not available " |
282 | "(can't reserve %pR)\n", r); |
283 | return -EINVAL; |
284 | } |
285 | |
286 | if (r->flags & IORESOURCE_IO) |
287 | cmd |= PCI_COMMAND_IO; |
288 | if (r->flags & IORESOURCE_MEM) |
289 | cmd |= PCI_COMMAND_MEMORY; |
290 | } |
291 | |
292 | if (cmd != old_cmd) { |
293 | dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", |
294 | old_cmd, cmd); |
295 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
296 | } |
297 | return 0; |
298 | } |
299 |
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