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1 | /* linux/drivers/serial/samsuing.c |
2 | * |
3 | * Driver core for Samsung SoC onboard UARTs. |
4 | * |
5 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
6 | * http://armlinux.simtec.co.uk/ |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as |
10 | * published by the Free Software Foundation. |
11 | */ |
12 | |
13 | /* Hote on 2410 error handling |
14 | * |
15 | * The s3c2410 manual has a love/hate affair with the contents of the |
16 | * UERSTAT register in the UART blocks, and keeps marking some of the |
17 | * error bits as reserved. Having checked with the s3c2410x01, |
18 | * it copes with BREAKs properly, so I am happy to ignore the RESERVED |
19 | * feature from the latter versions of the manual. |
20 | * |
21 | * If it becomes aparrent that latter versions of the 2410 remove these |
22 | * bits, then action will have to be taken to differentiate the versions |
23 | * and change the policy on BREAK |
24 | * |
25 | * BJD, 04-Nov-2004 |
26 | */ |
27 | |
28 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
29 | #define SUPPORT_SYSRQ |
30 | #endif |
31 | |
32 | #include <linux/module.h> |
33 | #include <linux/ioport.h> |
34 | #include <linux/io.h> |
35 | #include <linux/platform_device.h> |
36 | #include <linux/init.h> |
37 | #include <linux/sysrq.h> |
38 | #include <linux/console.h> |
39 | #include <linux/tty.h> |
40 | #include <linux/tty_flip.h> |
41 | #include <linux/serial_core.h> |
42 | #include <linux/serial.h> |
43 | #include <linux/delay.h> |
44 | #include <linux/clk.h> |
45 | #include <linux/cpufreq.h> |
46 | |
47 | #include <asm/irq.h> |
48 | |
49 | #include <mach/hardware.h> |
50 | #include <mach/map.h> |
51 | |
52 | #include <plat/regs-serial.h> |
53 | |
54 | #include "samsung.h" |
55 | |
56 | /* UART name and device definitions */ |
57 | |
58 | #define S3C24XX_SERIAL_NAME "ttySAC" |
59 | #define S3C24XX_SERIAL_MAJOR 204 |
60 | #define S3C24XX_SERIAL_MINOR 64 |
61 | |
62 | /* macros to change one thing to another */ |
63 | |
64 | #define tx_enabled(port) ((port)->unused[0]) |
65 | #define rx_enabled(port) ((port)->unused[1]) |
66 | |
67 | /* flag to ignore all characters comming in */ |
68 | #define RXSTAT_DUMMY_READ (0x10000000) |
69 | |
70 | static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) |
71 | { |
72 | return container_of(port, struct s3c24xx_uart_port, port); |
73 | } |
74 | |
75 | /* translate a port to the device name */ |
76 | |
77 | static inline const char *s3c24xx_serial_portname(struct uart_port *port) |
78 | { |
79 | return to_platform_device(port->dev)->name; |
80 | } |
81 | |
82 | static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) |
83 | { |
84 | return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE); |
85 | } |
86 | |
87 | static void s3c24xx_serial_rx_enable(struct uart_port *port) |
88 | { |
89 | unsigned long flags; |
90 | unsigned int ucon, ufcon; |
91 | int count = 10000; |
92 | |
93 | spin_lock_irqsave(&port->lock, flags); |
94 | |
95 | while (--count && !s3c24xx_serial_txempty_nofifo(port)) |
96 | udelay(100); |
97 | |
98 | ufcon = rd_regl(port, S3C2410_UFCON); |
99 | ufcon |= S3C2410_UFCON_RESETRX; |
100 | wr_regl(port, S3C2410_UFCON, ufcon); |
101 | |
102 | ucon = rd_regl(port, S3C2410_UCON); |
103 | ucon |= S3C2410_UCON_RXIRQMODE; |
104 | wr_regl(port, S3C2410_UCON, ucon); |
105 | |
106 | rx_enabled(port) = 1; |
107 | spin_unlock_irqrestore(&port->lock, flags); |
108 | } |
109 | |
110 | static void s3c24xx_serial_rx_disable(struct uart_port *port) |
111 | { |
112 | unsigned long flags; |
113 | unsigned int ucon; |
114 | |
115 | spin_lock_irqsave(&port->lock, flags); |
116 | |
117 | ucon = rd_regl(port, S3C2410_UCON); |
118 | ucon &= ~S3C2410_UCON_RXIRQMODE; |
119 | wr_regl(port, S3C2410_UCON, ucon); |
120 | |
121 | rx_enabled(port) = 0; |
122 | spin_unlock_irqrestore(&port->lock, flags); |
123 | } |
124 | |
125 | static void s3c24xx_serial_stop_tx(struct uart_port *port) |
126 | { |
127 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
128 | |
129 | if (tx_enabled(port)) { |
130 | disable_irq_nosync(ourport->tx_irq); |
131 | tx_enabled(port) = 0; |
132 | if (port->flags & UPF_CONS_FLOW) |
133 | s3c24xx_serial_rx_enable(port); |
134 | } |
135 | } |
136 | |
137 | static void s3c24xx_serial_start_tx(struct uart_port *port) |
138 | { |
139 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
140 | |
141 | if (!tx_enabled(port)) { |
142 | if (port->flags & UPF_CONS_FLOW) |
143 | s3c24xx_serial_rx_disable(port); |
144 | |
145 | enable_irq(ourport->tx_irq); |
146 | tx_enabled(port) = 1; |
147 | } |
148 | } |
149 | |
150 | |
151 | static void s3c24xx_serial_stop_rx(struct uart_port *port) |
152 | { |
153 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
154 | |
155 | if (rx_enabled(port)) { |
156 | dbg("s3c24xx_serial_stop_rx: port=%p\n", port); |
157 | disable_irq_nosync(ourport->rx_irq); |
158 | rx_enabled(port) = 0; |
159 | } |
160 | } |
161 | |
162 | static void s3c24xx_serial_enable_ms(struct uart_port *port) |
163 | { |
164 | } |
165 | |
166 | static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port) |
167 | { |
168 | return to_ourport(port)->info; |
169 | } |
170 | |
171 | static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port) |
172 | { |
173 | if (port->dev == NULL) |
174 | return NULL; |
175 | |
176 | return (struct s3c2410_uartcfg *)port->dev->platform_data; |
177 | } |
178 | |
179 | static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, |
180 | unsigned long ufstat) |
181 | { |
182 | struct s3c24xx_uart_info *info = ourport->info; |
183 | |
184 | if (ufstat & info->rx_fifofull) |
185 | return info->fifosize; |
186 | |
187 | return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; |
188 | } |
189 | |
190 | |
191 | /* ? - where has parity gone?? */ |
192 | #define S3C2410_UERSTAT_PARITY (0x1000) |
193 | |
194 | static irqreturn_t |
195 | s3c24xx_serial_rx_chars(int irq, void *dev_id) |
196 | { |
197 | struct s3c24xx_uart_port *ourport = dev_id; |
198 | struct uart_port *port = &ourport->port; |
199 | struct tty_struct *tty = port->state->port.tty; |
200 | unsigned int ufcon, ch, flag, ufstat, uerstat; |
201 | int max_count = 64; |
202 | |
203 | while (max_count-- > 0) { |
204 | ufcon = rd_regl(port, S3C2410_UFCON); |
205 | ufstat = rd_regl(port, S3C2410_UFSTAT); |
206 | |
207 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) |
208 | break; |
209 | |
210 | uerstat = rd_regl(port, S3C2410_UERSTAT); |
211 | ch = rd_regb(port, S3C2410_URXH); |
212 | |
213 | if (port->flags & UPF_CONS_FLOW) { |
214 | int txe = s3c24xx_serial_txempty_nofifo(port); |
215 | |
216 | if (rx_enabled(port)) { |
217 | if (!txe) { |
218 | rx_enabled(port) = 0; |
219 | continue; |
220 | } |
221 | } else { |
222 | if (txe) { |
223 | ufcon |= S3C2410_UFCON_RESETRX; |
224 | wr_regl(port, S3C2410_UFCON, ufcon); |
225 | rx_enabled(port) = 1; |
226 | goto out; |
227 | } |
228 | continue; |
229 | } |
230 | } |
231 | |
232 | /* insert the character into the buffer */ |
233 | |
234 | flag = TTY_NORMAL; |
235 | port->icount.rx++; |
236 | |
237 | if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { |
238 | dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", |
239 | ch, uerstat); |
240 | |
241 | /* check for break */ |
242 | if (uerstat & S3C2410_UERSTAT_BREAK) { |
243 | dbg("break!\n"); |
244 | port->icount.brk++; |
245 | if (uart_handle_break(port)) |
246 | goto ignore_char; |
247 | } |
248 | |
249 | if (uerstat & S3C2410_UERSTAT_FRAME) |
250 | port->icount.frame++; |
251 | if (uerstat & S3C2410_UERSTAT_OVERRUN) |
252 | port->icount.overrun++; |
253 | |
254 | uerstat &= port->read_status_mask; |
255 | |
256 | if (uerstat & S3C2410_UERSTAT_BREAK) |
257 | flag = TTY_BREAK; |
258 | else if (uerstat & S3C2410_UERSTAT_PARITY) |
259 | flag = TTY_PARITY; |
260 | else if (uerstat & (S3C2410_UERSTAT_FRAME | |
261 | S3C2410_UERSTAT_OVERRUN)) |
262 | flag = TTY_FRAME; |
263 | } |
264 | |
265 | if (uart_handle_sysrq_char(port, ch)) |
266 | goto ignore_char; |
267 | |
268 | uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, |
269 | ch, flag); |
270 | |
271 | ignore_char: |
272 | continue; |
273 | } |
274 | tty_flip_buffer_push(tty); |
275 | |
276 | out: |
277 | return IRQ_HANDLED; |
278 | } |
279 | |
280 | static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) |
281 | { |
282 | struct s3c24xx_uart_port *ourport = id; |
283 | struct uart_port *port = &ourport->port; |
284 | struct circ_buf *xmit = &port->state->xmit; |
285 | int count = 256; |
286 | |
287 | if (port->x_char) { |
288 | wr_regb(port, S3C2410_UTXH, port->x_char); |
289 | port->icount.tx++; |
290 | port->x_char = 0; |
291 | goto out; |
292 | } |
293 | |
294 | /* if there isnt anything more to transmit, or the uart is now |
295 | * stopped, disable the uart and exit |
296 | */ |
297 | |
298 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { |
299 | s3c24xx_serial_stop_tx(port); |
300 | goto out; |
301 | } |
302 | |
303 | /* try and drain the buffer... */ |
304 | |
305 | while (!uart_circ_empty(xmit) && count-- > 0) { |
306 | if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) |
307 | break; |
308 | |
309 | wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); |
310 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
311 | port->icount.tx++; |
312 | } |
313 | |
314 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
315 | uart_write_wakeup(port); |
316 | |
317 | if (uart_circ_empty(xmit)) |
318 | s3c24xx_serial_stop_tx(port); |
319 | |
320 | out: |
321 | return IRQ_HANDLED; |
322 | } |
323 | |
324 | static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) |
325 | { |
326 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
327 | unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); |
328 | unsigned long ufcon = rd_regl(port, S3C2410_UFCON); |
329 | |
330 | if (ufcon & S3C2410_UFCON_FIFOMODE) { |
331 | if ((ufstat & info->tx_fifomask) != 0 || |
332 | (ufstat & info->tx_fifofull)) |
333 | return 0; |
334 | |
335 | return 1; |
336 | } |
337 | |
338 | return s3c24xx_serial_txempty_nofifo(port); |
339 | } |
340 | |
341 | /* no modem control lines */ |
342 | static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) |
343 | { |
344 | unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); |
345 | |
346 | if (umstat & S3C2410_UMSTAT_CTS) |
347 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; |
348 | else |
349 | return TIOCM_CAR | TIOCM_DSR; |
350 | } |
351 | |
352 | static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) |
353 | { |
354 | /* todo - possibly remove AFC and do manual CTS */ |
355 | } |
356 | |
357 | static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) |
358 | { |
359 | unsigned long flags; |
360 | unsigned int ucon; |
361 | |
362 | spin_lock_irqsave(&port->lock, flags); |
363 | |
364 | ucon = rd_regl(port, S3C2410_UCON); |
365 | |
366 | if (break_state) |
367 | ucon |= S3C2410_UCON_SBREAK; |
368 | else |
369 | ucon &= ~S3C2410_UCON_SBREAK; |
370 | |
371 | wr_regl(port, S3C2410_UCON, ucon); |
372 | |
373 | spin_unlock_irqrestore(&port->lock, flags); |
374 | } |
375 | |
376 | static void s3c24xx_serial_shutdown(struct uart_port *port) |
377 | { |
378 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
379 | |
380 | if (ourport->tx_claimed) { |
381 | free_irq(ourport->tx_irq, ourport); |
382 | tx_enabled(port) = 0; |
383 | ourport->tx_claimed = 0; |
384 | } |
385 | |
386 | if (ourport->rx_claimed) { |
387 | free_irq(ourport->rx_irq, ourport); |
388 | ourport->rx_claimed = 0; |
389 | rx_enabled(port) = 0; |
390 | } |
391 | } |
392 | |
393 | |
394 | static int s3c24xx_serial_startup(struct uart_port *port) |
395 | { |
396 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
397 | int ret; |
398 | |
399 | dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n", |
400 | port->mapbase, port->membase); |
401 | |
402 | rx_enabled(port) = 1; |
403 | |
404 | ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0, |
405 | s3c24xx_serial_portname(port), ourport); |
406 | |
407 | if (ret != 0) { |
408 | printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq); |
409 | return ret; |
410 | } |
411 | |
412 | ourport->rx_claimed = 1; |
413 | |
414 | dbg("requesting tx irq...\n"); |
415 | |
416 | tx_enabled(port) = 1; |
417 | |
418 | ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0, |
419 | s3c24xx_serial_portname(port), ourport); |
420 | |
421 | if (ret) { |
422 | printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq); |
423 | goto err; |
424 | } |
425 | |
426 | ourport->tx_claimed = 1; |
427 | |
428 | dbg("s3c24xx_serial_startup ok\n"); |
429 | |
430 | /* the port reset code should have done the correct |
431 | * register setup for the port controls */ |
432 | |
433 | return ret; |
434 | |
435 | err: |
436 | s3c24xx_serial_shutdown(port); |
437 | return ret; |
438 | } |
439 | |
440 | /* power power management control */ |
441 | |
442 | static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, |
443 | unsigned int old) |
444 | { |
445 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
446 | |
447 | ourport->pm_level = level; |
448 | |
449 | switch (level) { |
450 | case 3: |
451 | if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) |
452 | clk_disable(ourport->baudclk); |
453 | |
454 | clk_disable(ourport->clk); |
455 | break; |
456 | |
457 | case 0: |
458 | clk_enable(ourport->clk); |
459 | |
460 | if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) |
461 | clk_enable(ourport->baudclk); |
462 | |
463 | break; |
464 | default: |
465 | printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level); |
466 | } |
467 | } |
468 | |
469 | /* baud rate calculation |
470 | * |
471 | * The UARTs on the S3C2410/S3C2440 can take their clocks from a number |
472 | * of different sources, including the peripheral clock ("pclk") and an |
473 | * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") |
474 | * with a programmable extra divisor. |
475 | * |
476 | * The following code goes through the clock sources, and calculates the |
477 | * baud clocks (and the resultant actual baud rates) and then tries to |
478 | * pick the closest one and select that. |
479 | * |
480 | */ |
481 | |
482 | |
483 | #define MAX_CLKS (8) |
484 | |
485 | static struct s3c24xx_uart_clksrc tmp_clksrc = { |
486 | .name = "pclk", |
487 | .min_baud = 0, |
488 | .max_baud = 0, |
489 | .divisor = 1, |
490 | }; |
491 | |
492 | static inline int |
493 | s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) |
494 | { |
495 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
496 | |
497 | return (info->get_clksrc)(port, c); |
498 | } |
499 | |
500 | static inline int |
501 | s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) |
502 | { |
503 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
504 | |
505 | return (info->set_clksrc)(port, c); |
506 | } |
507 | |
508 | struct baud_calc { |
509 | struct s3c24xx_uart_clksrc *clksrc; |
510 | unsigned int calc; |
511 | unsigned int divslot; |
512 | unsigned int quot; |
513 | struct clk *src; |
514 | }; |
515 | |
516 | static int s3c24xx_serial_calcbaud(struct baud_calc *calc, |
517 | struct uart_port *port, |
518 | struct s3c24xx_uart_clksrc *clksrc, |
519 | unsigned int baud) |
520 | { |
521 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
522 | unsigned long rate; |
523 | |
524 | calc->src = clk_get(port->dev, clksrc->name); |
525 | if (calc->src == NULL || IS_ERR(calc->src)) |
526 | return 0; |
527 | |
528 | rate = clk_get_rate(calc->src); |
529 | rate /= clksrc->divisor; |
530 | |
531 | calc->clksrc = clksrc; |
532 | |
533 | if (ourport->info->has_divslot) { |
534 | unsigned long div = rate / baud; |
535 | |
536 | /* The UDIVSLOT register on the newer UARTs allows us to |
537 | * get a divisor adjustment of 1/16th on the baud clock. |
538 | * |
539 | * We don't keep the UDIVSLOT value (the 16ths we calculated |
540 | * by not multiplying the baud by 16) as it is easy enough |
541 | * to recalculate. |
542 | */ |
543 | |
544 | calc->quot = div / 16; |
545 | calc->calc = rate / div; |
546 | } else { |
547 | calc->quot = (rate + (8 * baud)) / (16 * baud); |
548 | calc->calc = (rate / (calc->quot * 16)); |
549 | } |
550 | |
551 | calc->quot--; |
552 | return 1; |
553 | } |
554 | |
555 | static unsigned int s3c24xx_serial_getclk(struct uart_port *port, |
556 | struct s3c24xx_uart_clksrc **clksrc, |
557 | struct clk **clk, |
558 | unsigned int baud) |
559 | { |
560 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); |
561 | struct s3c24xx_uart_clksrc *clkp; |
562 | struct baud_calc res[MAX_CLKS]; |
563 | struct baud_calc *resptr, *best, *sptr; |
564 | int i; |
565 | |
566 | clkp = cfg->clocks; |
567 | best = NULL; |
568 | |
569 | if (cfg->clocks_size < 2) { |
570 | if (cfg->clocks_size == 0) |
571 | clkp = &tmp_clksrc; |
572 | |
573 | /* check to see if we're sourcing fclk, and if so we're |
574 | * going to have to update the clock source |
575 | */ |
576 | |
577 | if (strcmp(clkp->name, "fclk") == 0) { |
578 | struct s3c24xx_uart_clksrc src; |
579 | |
580 | s3c24xx_serial_getsource(port, &src); |
581 | |
582 | /* check that the port already using fclk, and if |
583 | * not, then re-select fclk |
584 | */ |
585 | |
586 | if (strcmp(src.name, clkp->name) == 0) { |
587 | s3c24xx_serial_setsource(port, clkp); |
588 | s3c24xx_serial_getsource(port, &src); |
589 | } |
590 | |
591 | clkp->divisor = src.divisor; |
592 | } |
593 | |
594 | s3c24xx_serial_calcbaud(res, port, clkp, baud); |
595 | best = res; |
596 | resptr = best + 1; |
597 | } else { |
598 | resptr = res; |
599 | |
600 | for (i = 0; i < cfg->clocks_size; i++, clkp++) { |
601 | if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud)) |
602 | resptr++; |
603 | } |
604 | } |
605 | |
606 | /* ok, we now need to select the best clock we found */ |
607 | |
608 | if (!best) { |
609 | unsigned int deviation = (1<<30)|((1<<30)-1); |
610 | int calc_deviation; |
611 | |
612 | for (sptr = res; sptr < resptr; sptr++) { |
613 | calc_deviation = baud - sptr->calc; |
614 | if (calc_deviation < 0) |
615 | calc_deviation = -calc_deviation; |
616 | |
617 | if (calc_deviation < deviation) { |
618 | best = sptr; |
619 | deviation = calc_deviation; |
620 | } |
621 | } |
622 | } |
623 | |
624 | /* store results to pass back */ |
625 | |
626 | *clksrc = best->clksrc; |
627 | *clk = best->src; |
628 | |
629 | return best->quot; |
630 | } |
631 | |
632 | /* udivslot_table[] |
633 | * |
634 | * This table takes the fractional value of the baud divisor and gives |
635 | * the recommended setting for the UDIVSLOT register. |
636 | */ |
637 | static u16 udivslot_table[16] = { |
638 | [0] = 0x0000, |
639 | [1] = 0x0080, |
640 | [2] = 0x0808, |
641 | [3] = 0x0888, |
642 | [4] = 0x2222, |
643 | [5] = 0x4924, |
644 | [6] = 0x4A52, |
645 | [7] = 0x54AA, |
646 | [8] = 0x5555, |
647 | [9] = 0xD555, |
648 | [10] = 0xD5D5, |
649 | [11] = 0xDDD5, |
650 | [12] = 0xDDDD, |
651 | [13] = 0xDFDD, |
652 | [14] = 0xDFDF, |
653 | [15] = 0xFFDF, |
654 | }; |
655 | |
656 | static void s3c24xx_serial_set_termios(struct uart_port *port, |
657 | struct ktermios *termios, |
658 | struct ktermios *old) |
659 | { |
660 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); |
661 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
662 | struct s3c24xx_uart_clksrc *clksrc = NULL; |
663 | struct clk *clk = NULL; |
664 | unsigned long flags; |
665 | unsigned int baud, quot; |
666 | unsigned int ulcon; |
667 | unsigned int umcon; |
668 | unsigned int udivslot = 0; |
669 | |
670 | /* |
671 | * We don't support modem control lines. |
672 | */ |
673 | termios->c_cflag &= ~(HUPCL | CMSPAR); |
674 | termios->c_cflag |= CLOCAL; |
675 | |
676 | /* |
677 | * Ask the core to calculate the divisor for us. |
678 | */ |
679 | |
680 | baud = uart_get_baud_rate(port, termios, old, 0, 115200*8); |
681 | |
682 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) |
683 | quot = port->custom_divisor; |
684 | else |
685 | quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud); |
686 | |
687 | /* check to see if we need to change clock source */ |
688 | |
689 | if (ourport->clksrc != clksrc || ourport->baudclk != clk) { |
690 | dbg("selecting clock %p\n", clk); |
691 | s3c24xx_serial_setsource(port, clksrc); |
692 | |
693 | if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) { |
694 | clk_disable(ourport->baudclk); |
695 | ourport->baudclk = NULL; |
696 | } |
697 | |
698 | clk_enable(clk); |
699 | |
700 | ourport->clksrc = clksrc; |
701 | ourport->baudclk = clk; |
702 | ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; |
703 | } |
704 | |
705 | if (ourport->info->has_divslot) { |
706 | unsigned int div = ourport->baudclk_rate / baud; |
707 | |
708 | udivslot = udivslot_table[div & 15]; |
709 | dbg("udivslot = %04x (div %d)\n", udivslot, div & 15); |
710 | } |
711 | |
712 | switch (termios->c_cflag & CSIZE) { |
713 | case CS5: |
714 | dbg("config: 5bits/char\n"); |
715 | ulcon = S3C2410_LCON_CS5; |
716 | break; |
717 | case CS6: |
718 | dbg("config: 6bits/char\n"); |
719 | ulcon = S3C2410_LCON_CS6; |
720 | break; |
721 | case CS7: |
722 | dbg("config: 7bits/char\n"); |
723 | ulcon = S3C2410_LCON_CS7; |
724 | break; |
725 | case CS8: |
726 | default: |
727 | dbg("config: 8bits/char\n"); |
728 | ulcon = S3C2410_LCON_CS8; |
729 | break; |
730 | } |
731 | |
732 | /* preserve original lcon IR settings */ |
733 | ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); |
734 | |
735 | if (termios->c_cflag & CSTOPB) |
736 | ulcon |= S3C2410_LCON_STOPB; |
737 | |
738 | umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0; |
739 | |
740 | if (termios->c_cflag & PARENB) { |
741 | if (termios->c_cflag & PARODD) |
742 | ulcon |= S3C2410_LCON_PODD; |
743 | else |
744 | ulcon |= S3C2410_LCON_PEVEN; |
745 | } else { |
746 | ulcon |= S3C2410_LCON_PNONE; |
747 | } |
748 | |
749 | spin_lock_irqsave(&port->lock, flags); |
750 | |
751 | dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n", |
752 | ulcon, quot, udivslot); |
753 | |
754 | wr_regl(port, S3C2410_ULCON, ulcon); |
755 | wr_regl(port, S3C2410_UBRDIV, quot); |
756 | wr_regl(port, S3C2410_UMCON, umcon); |
757 | |
758 | if (ourport->info->has_divslot) |
759 | wr_regl(port, S3C2443_DIVSLOT, udivslot); |
760 | |
761 | dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", |
762 | rd_regl(port, S3C2410_ULCON), |
763 | rd_regl(port, S3C2410_UCON), |
764 | rd_regl(port, S3C2410_UFCON)); |
765 | |
766 | /* |
767 | * Update the per-port timeout. |
768 | */ |
769 | uart_update_timeout(port, termios->c_cflag, baud); |
770 | |
771 | /* |
772 | * Which character status flags are we interested in? |
773 | */ |
774 | port->read_status_mask = S3C2410_UERSTAT_OVERRUN; |
775 | if (termios->c_iflag & INPCK) |
776 | port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY; |
777 | |
778 | /* |
779 | * Which character status flags should we ignore? |
780 | */ |
781 | port->ignore_status_mask = 0; |
782 | if (termios->c_iflag & IGNPAR) |
783 | port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; |
784 | if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) |
785 | port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; |
786 | |
787 | /* |
788 | * Ignore all characters if CREAD is not set. |
789 | */ |
790 | if ((termios->c_cflag & CREAD) == 0) |
791 | port->ignore_status_mask |= RXSTAT_DUMMY_READ; |
792 | |
793 | spin_unlock_irqrestore(&port->lock, flags); |
794 | } |
795 | |
796 | static const char *s3c24xx_serial_type(struct uart_port *port) |
797 | { |
798 | switch (port->type) { |
799 | case PORT_S3C2410: |
800 | return "S3C2410"; |
801 | case PORT_S3C2440: |
802 | return "S3C2440"; |
803 | case PORT_S3C2412: |
804 | return "S3C2412"; |
805 | case PORT_S3C6400: |
806 | return "S3C6400/10"; |
807 | default: |
808 | return NULL; |
809 | } |
810 | } |
811 | |
812 | #define MAP_SIZE (0x100) |
813 | |
814 | static void s3c24xx_serial_release_port(struct uart_port *port) |
815 | { |
816 | release_mem_region(port->mapbase, MAP_SIZE); |
817 | } |
818 | |
819 | static int s3c24xx_serial_request_port(struct uart_port *port) |
820 | { |
821 | const char *name = s3c24xx_serial_portname(port); |
822 | return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY; |
823 | } |
824 | |
825 | static void s3c24xx_serial_config_port(struct uart_port *port, int flags) |
826 | { |
827 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
828 | |
829 | if (flags & UART_CONFIG_TYPE && |
830 | s3c24xx_serial_request_port(port) == 0) |
831 | port->type = info->type; |
832 | } |
833 | |
834 | /* |
835 | * verify the new serial_struct (for TIOCSSERIAL). |
836 | */ |
837 | static int |
838 | s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) |
839 | { |
840 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
841 | |
842 | if (ser->type != PORT_UNKNOWN && ser->type != info->type) |
843 | return -EINVAL; |
844 | |
845 | return 0; |
846 | } |
847 | |
848 | |
849 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE |
850 | |
851 | static struct console s3c24xx_serial_console; |
852 | |
853 | #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console |
854 | #else |
855 | #define S3C24XX_SERIAL_CONSOLE NULL |
856 | #endif |
857 | |
858 | static struct uart_ops s3c24xx_serial_ops = { |
859 | .pm = s3c24xx_serial_pm, |
860 | .tx_empty = s3c24xx_serial_tx_empty, |
861 | .get_mctrl = s3c24xx_serial_get_mctrl, |
862 | .set_mctrl = s3c24xx_serial_set_mctrl, |
863 | .stop_tx = s3c24xx_serial_stop_tx, |
864 | .start_tx = s3c24xx_serial_start_tx, |
865 | .stop_rx = s3c24xx_serial_stop_rx, |
866 | .enable_ms = s3c24xx_serial_enable_ms, |
867 | .break_ctl = s3c24xx_serial_break_ctl, |
868 | .startup = s3c24xx_serial_startup, |
869 | .shutdown = s3c24xx_serial_shutdown, |
870 | .set_termios = s3c24xx_serial_set_termios, |
871 | .type = s3c24xx_serial_type, |
872 | .release_port = s3c24xx_serial_release_port, |
873 | .request_port = s3c24xx_serial_request_port, |
874 | .config_port = s3c24xx_serial_config_port, |
875 | .verify_port = s3c24xx_serial_verify_port, |
876 | }; |
877 | |
878 | |
879 | static struct uart_driver s3c24xx_uart_drv = { |
880 | .owner = THIS_MODULE, |
881 | .dev_name = "s3c2410_serial", |
882 | .nr = CONFIG_SERIAL_SAMSUNG_UARTS, |
883 | .cons = S3C24XX_SERIAL_CONSOLE, |
884 | .driver_name = S3C24XX_SERIAL_NAME, |
885 | .major = S3C24XX_SERIAL_MAJOR, |
886 | .minor = S3C24XX_SERIAL_MINOR, |
887 | }; |
888 | |
889 | static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { |
890 | [0] = { |
891 | .port = { |
892 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock), |
893 | .iotype = UPIO_MEM, |
894 | .irq = IRQ_S3CUART_RX0, |
895 | .uartclk = 0, |
896 | .fifosize = 16, |
897 | .ops = &s3c24xx_serial_ops, |
898 | .flags = UPF_BOOT_AUTOCONF, |
899 | .line = 0, |
900 | } |
901 | }, |
902 | [1] = { |
903 | .port = { |
904 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock), |
905 | .iotype = UPIO_MEM, |
906 | .irq = IRQ_S3CUART_RX1, |
907 | .uartclk = 0, |
908 | .fifosize = 16, |
909 | .ops = &s3c24xx_serial_ops, |
910 | .flags = UPF_BOOT_AUTOCONF, |
911 | .line = 1, |
912 | } |
913 | }, |
914 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 2 |
915 | |
916 | [2] = { |
917 | .port = { |
918 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock), |
919 | .iotype = UPIO_MEM, |
920 | .irq = IRQ_S3CUART_RX2, |
921 | .uartclk = 0, |
922 | .fifosize = 16, |
923 | .ops = &s3c24xx_serial_ops, |
924 | .flags = UPF_BOOT_AUTOCONF, |
925 | .line = 2, |
926 | } |
927 | }, |
928 | #endif |
929 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 |
930 | [3] = { |
931 | .port = { |
932 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock), |
933 | .iotype = UPIO_MEM, |
934 | .irq = IRQ_S3CUART_RX3, |
935 | .uartclk = 0, |
936 | .fifosize = 16, |
937 | .ops = &s3c24xx_serial_ops, |
938 | .flags = UPF_BOOT_AUTOCONF, |
939 | .line = 3, |
940 | } |
941 | } |
942 | #endif |
943 | }; |
944 | |
945 | /* s3c24xx_serial_resetport |
946 | * |
947 | * wrapper to call the specific reset for this port (reset the fifos |
948 | * and the settings) |
949 | */ |
950 | |
951 | static inline int s3c24xx_serial_resetport(struct uart_port *port, |
952 | struct s3c2410_uartcfg *cfg) |
953 | { |
954 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
955 | |
956 | return (info->reset_port)(port, cfg); |
957 | } |
958 | |
959 | |
960 | #ifdef CONFIG_CPU_FREQ |
961 | |
962 | static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, |
963 | unsigned long val, void *data) |
964 | { |
965 | struct s3c24xx_uart_port *port; |
966 | struct uart_port *uport; |
967 | |
968 | port = container_of(nb, struct s3c24xx_uart_port, freq_transition); |
969 | uport = &port->port; |
970 | |
971 | /* check to see if port is enabled */ |
972 | |
973 | if (port->pm_level != 0) |
974 | return 0; |
975 | |
976 | /* try and work out if the baudrate is changing, we can detect |
977 | * a change in rate, but we do not have support for detecting |
978 | * a disturbance in the clock-rate over the change. |
979 | */ |
980 | |
981 | if (IS_ERR(port->clk)) |
982 | goto exit; |
983 | |
984 | if (port->baudclk_rate == clk_get_rate(port->clk)) |
985 | goto exit; |
986 | |
987 | if (val == CPUFREQ_PRECHANGE) { |
988 | /* we should really shut the port down whilst the |
989 | * frequency change is in progress. */ |
990 | |
991 | } else if (val == CPUFREQ_POSTCHANGE) { |
992 | struct ktermios *termios; |
993 | struct tty_struct *tty; |
994 | |
995 | if (uport->state == NULL) |
996 | goto exit; |
997 | |
998 | tty = uport->state->port.tty; |
999 | |
1000 | if (tty == NULL) |
1001 | goto exit; |
1002 | |
1003 | termios = tty->termios; |
1004 | |
1005 | if (termios == NULL) { |
1006 | printk(KERN_WARNING "%s: no termios?\n", __func__); |
1007 | goto exit; |
1008 | } |
1009 | |
1010 | s3c24xx_serial_set_termios(uport, termios, NULL); |
1011 | } |
1012 | |
1013 | exit: |
1014 | return 0; |
1015 | } |
1016 | |
1017 | static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) |
1018 | { |
1019 | port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; |
1020 | |
1021 | return cpufreq_register_notifier(&port->freq_transition, |
1022 | CPUFREQ_TRANSITION_NOTIFIER); |
1023 | } |
1024 | |
1025 | static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) |
1026 | { |
1027 | cpufreq_unregister_notifier(&port->freq_transition, |
1028 | CPUFREQ_TRANSITION_NOTIFIER); |
1029 | } |
1030 | |
1031 | #else |
1032 | static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) |
1033 | { |
1034 | return 0; |
1035 | } |
1036 | |
1037 | static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) |
1038 | { |
1039 | } |
1040 | #endif |
1041 | |
1042 | /* s3c24xx_serial_init_port |
1043 | * |
1044 | * initialise a single serial port from the platform device given |
1045 | */ |
1046 | |
1047 | static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, |
1048 | struct s3c24xx_uart_info *info, |
1049 | struct platform_device *platdev) |
1050 | { |
1051 | struct uart_port *port = &ourport->port; |
1052 | struct s3c2410_uartcfg *cfg; |
1053 | struct resource *res; |
1054 | int ret; |
1055 | |
1056 | dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev); |
1057 | |
1058 | if (platdev == NULL) |
1059 | return -ENODEV; |
1060 | |
1061 | cfg = s3c24xx_dev_to_cfg(&platdev->dev); |
1062 | |
1063 | if (port->mapbase != 0) |
1064 | return 0; |
1065 | |
1066 | if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) { |
1067 | printk(KERN_ERR "%s: port %d bigger than %d\n", __func__, |
1068 | cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS); |
1069 | return -ERANGE; |
1070 | } |
1071 | |
1072 | /* setup info for port */ |
1073 | port->dev = &platdev->dev; |
1074 | ourport->info = info; |
1075 | |
1076 | /* copy the info in from provided structure */ |
1077 | ourport->port.fifosize = info->fifosize; |
1078 | |
1079 | dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport); |
1080 | |
1081 | port->uartclk = 1; |
1082 | |
1083 | if (cfg->uart_flags & UPF_CONS_FLOW) { |
1084 | dbg("s3c24xx_serial_init_port: enabling flow control\n"); |
1085 | port->flags |= UPF_CONS_FLOW; |
1086 | } |
1087 | |
1088 | /* sort our the physical and virtual addresses for each UART */ |
1089 | |
1090 | res = platform_get_resource(platdev, IORESOURCE_MEM, 0); |
1091 | if (res == NULL) { |
1092 | printk(KERN_ERR "failed to find memory resource for uart\n"); |
1093 | return -EINVAL; |
1094 | } |
1095 | |
1096 | dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); |
1097 | |
1098 | port->mapbase = res->start; |
1099 | port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000); |
1100 | ret = platform_get_irq(platdev, 0); |
1101 | if (ret < 0) |
1102 | port->irq = 0; |
1103 | else { |
1104 | port->irq = ret; |
1105 | ourport->rx_irq = ret; |
1106 | ourport->tx_irq = ret + 1; |
1107 | } |
1108 | |
1109 | ret = platform_get_irq(platdev, 1); |
1110 | if (ret > 0) |
1111 | ourport->tx_irq = ret; |
1112 | |
1113 | ourport->clk = clk_get(&platdev->dev, "uart"); |
1114 | |
1115 | dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n", |
1116 | port->mapbase, port->membase, port->irq, |
1117 | ourport->rx_irq, ourport->tx_irq, port->uartclk); |
1118 | |
1119 | /* reset the fifos (and setup the uart) */ |
1120 | s3c24xx_serial_resetport(port, cfg); |
1121 | return 0; |
1122 | } |
1123 | |
1124 | static ssize_t s3c24xx_serial_show_clksrc(struct device *dev, |
1125 | struct device_attribute *attr, |
1126 | char *buf) |
1127 | { |
1128 | struct uart_port *port = s3c24xx_dev_to_port(dev); |
1129 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
1130 | |
1131 | return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name); |
1132 | } |
1133 | |
1134 | static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL); |
1135 | |
1136 | /* Device driver serial port probe */ |
1137 | |
1138 | static int probe_index; |
1139 | |
1140 | int s3c24xx_serial_probe(struct platform_device *dev, |
1141 | struct s3c24xx_uart_info *info) |
1142 | { |
1143 | struct s3c24xx_uart_port *ourport; |
1144 | int ret; |
1145 | |
1146 | dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index); |
1147 | |
1148 | ourport = &s3c24xx_serial_ports[probe_index]; |
1149 | probe_index++; |
1150 | |
1151 | dbg("%s: initialising port %p...\n", __func__, ourport); |
1152 | |
1153 | ret = s3c24xx_serial_init_port(ourport, info, dev); |
1154 | if (ret < 0) |
1155 | goto probe_err; |
1156 | |
1157 | dbg("%s: adding port\n", __func__); |
1158 | uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); |
1159 | platform_set_drvdata(dev, &ourport->port); |
1160 | |
1161 | ret = device_create_file(&dev->dev, &dev_attr_clock_source); |
1162 | if (ret < 0) |
1163 | printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__); |
1164 | |
1165 | ret = s3c24xx_serial_cpufreq_register(ourport); |
1166 | if (ret < 0) |
1167 | dev_err(&dev->dev, "failed to add cpufreq notifier\n"); |
1168 | |
1169 | return 0; |
1170 | |
1171 | probe_err: |
1172 | return ret; |
1173 | } |
1174 | |
1175 | EXPORT_SYMBOL_GPL(s3c24xx_serial_probe); |
1176 | |
1177 | int __devexit s3c24xx_serial_remove(struct platform_device *dev) |
1178 | { |
1179 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); |
1180 | |
1181 | if (port) { |
1182 | s3c24xx_serial_cpufreq_deregister(to_ourport(port)); |
1183 | device_remove_file(&dev->dev, &dev_attr_clock_source); |
1184 | uart_remove_one_port(&s3c24xx_uart_drv, port); |
1185 | } |
1186 | |
1187 | return 0; |
1188 | } |
1189 | |
1190 | EXPORT_SYMBOL_GPL(s3c24xx_serial_remove); |
1191 | |
1192 | /* UART power management code */ |
1193 | |
1194 | #ifdef CONFIG_PM |
1195 | |
1196 | static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state) |
1197 | { |
1198 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); |
1199 | |
1200 | if (port) |
1201 | uart_suspend_port(&s3c24xx_uart_drv, port); |
1202 | |
1203 | return 0; |
1204 | } |
1205 | |
1206 | static int s3c24xx_serial_resume(struct platform_device *dev) |
1207 | { |
1208 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); |
1209 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
1210 | |
1211 | if (port) { |
1212 | clk_enable(ourport->clk); |
1213 | s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); |
1214 | clk_disable(ourport->clk); |
1215 | |
1216 | uart_resume_port(&s3c24xx_uart_drv, port); |
1217 | } |
1218 | |
1219 | return 0; |
1220 | } |
1221 | #endif |
1222 | |
1223 | int s3c24xx_serial_init(struct platform_driver *drv, |
1224 | struct s3c24xx_uart_info *info) |
1225 | { |
1226 | dbg("s3c24xx_serial_init(%p,%p)\n", drv, info); |
1227 | |
1228 | #ifdef CONFIG_PM |
1229 | drv->suspend = s3c24xx_serial_suspend; |
1230 | drv->resume = s3c24xx_serial_resume; |
1231 | #endif |
1232 | |
1233 | return platform_driver_register(drv); |
1234 | } |
1235 | |
1236 | EXPORT_SYMBOL_GPL(s3c24xx_serial_init); |
1237 | |
1238 | /* module initialisation code */ |
1239 | |
1240 | static int __init s3c24xx_serial_modinit(void) |
1241 | { |
1242 | int ret; |
1243 | |
1244 | ret = uart_register_driver(&s3c24xx_uart_drv); |
1245 | if (ret < 0) { |
1246 | printk(KERN_ERR "failed to register UART driver\n"); |
1247 | return -1; |
1248 | } |
1249 | |
1250 | return 0; |
1251 | } |
1252 | |
1253 | static void __exit s3c24xx_serial_modexit(void) |
1254 | { |
1255 | uart_unregister_driver(&s3c24xx_uart_drv); |
1256 | } |
1257 | |
1258 | module_init(s3c24xx_serial_modinit); |
1259 | module_exit(s3c24xx_serial_modexit); |
1260 | |
1261 | /* Console code */ |
1262 | |
1263 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE |
1264 | |
1265 | static struct uart_port *cons_uart; |
1266 | |
1267 | static int |
1268 | s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) |
1269 | { |
1270 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
1271 | unsigned long ufstat, utrstat; |
1272 | |
1273 | if (ufcon & S3C2410_UFCON_FIFOMODE) { |
1274 | /* fifo mode - check amount of data in fifo registers... */ |
1275 | |
1276 | ufstat = rd_regl(port, S3C2410_UFSTAT); |
1277 | return (ufstat & info->tx_fifofull) ? 0 : 1; |
1278 | } |
1279 | |
1280 | /* in non-fifo mode, we go and use the tx buffer empty */ |
1281 | |
1282 | utrstat = rd_regl(port, S3C2410_UTRSTAT); |
1283 | return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; |
1284 | } |
1285 | |
1286 | static void |
1287 | s3c24xx_serial_console_putchar(struct uart_port *port, int ch) |
1288 | { |
1289 | unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON); |
1290 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) |
1291 | barrier(); |
1292 | wr_regb(cons_uart, S3C2410_UTXH, ch); |
1293 | } |
1294 | |
1295 | static void |
1296 | s3c24xx_serial_console_write(struct console *co, const char *s, |
1297 | unsigned int count) |
1298 | { |
1299 | uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); |
1300 | } |
1301 | |
1302 | static void __init |
1303 | s3c24xx_serial_get_options(struct uart_port *port, int *baud, |
1304 | int *parity, int *bits) |
1305 | { |
1306 | struct s3c24xx_uart_clksrc clksrc; |
1307 | struct clk *clk; |
1308 | unsigned int ulcon; |
1309 | unsigned int ucon; |
1310 | unsigned int ubrdiv; |
1311 | unsigned long rate; |
1312 | |
1313 | ulcon = rd_regl(port, S3C2410_ULCON); |
1314 | ucon = rd_regl(port, S3C2410_UCON); |
1315 | ubrdiv = rd_regl(port, S3C2410_UBRDIV); |
1316 | |
1317 | dbg("s3c24xx_serial_get_options: port=%p\n" |
1318 | "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n", |
1319 | port, ulcon, ucon, ubrdiv); |
1320 | |
1321 | if ((ucon & 0xf) != 0) { |
1322 | /* consider the serial port configured if the tx/rx mode set */ |
1323 | |
1324 | switch (ulcon & S3C2410_LCON_CSMASK) { |
1325 | case S3C2410_LCON_CS5: |
1326 | *bits = 5; |
1327 | break; |
1328 | case S3C2410_LCON_CS6: |
1329 | *bits = 6; |
1330 | break; |
1331 | case S3C2410_LCON_CS7: |
1332 | *bits = 7; |
1333 | break; |
1334 | default: |
1335 | case S3C2410_LCON_CS8: |
1336 | *bits = 8; |
1337 | break; |
1338 | } |
1339 | |
1340 | switch (ulcon & S3C2410_LCON_PMASK) { |
1341 | case S3C2410_LCON_PEVEN: |
1342 | *parity = 'e'; |
1343 | break; |
1344 | |
1345 | case S3C2410_LCON_PODD: |
1346 | *parity = 'o'; |
1347 | break; |
1348 | |
1349 | case S3C2410_LCON_PNONE: |
1350 | default: |
1351 | *parity = 'n'; |
1352 | } |
1353 | |
1354 | /* now calculate the baud rate */ |
1355 | |
1356 | s3c24xx_serial_getsource(port, &clksrc); |
1357 | |
1358 | clk = clk_get(port->dev, clksrc.name); |
1359 | if (!IS_ERR(clk) && clk != NULL) |
1360 | rate = clk_get_rate(clk) / clksrc.divisor; |
1361 | else |
1362 | rate = 1; |
1363 | |
1364 | |
1365 | *baud = rate / (16 * (ubrdiv + 1)); |
1366 | dbg("calculated baud %d\n", *baud); |
1367 | } |
1368 | |
1369 | } |
1370 | |
1371 | /* s3c24xx_serial_init_ports |
1372 | * |
1373 | * initialise the serial ports from the machine provided initialisation |
1374 | * data. |
1375 | */ |
1376 | |
1377 | static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info) |
1378 | { |
1379 | struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports; |
1380 | struct platform_device **platdev_ptr; |
1381 | int i; |
1382 | |
1383 | dbg("s3c24xx_serial_init_ports: initialising ports...\n"); |
1384 | |
1385 | platdev_ptr = s3c24xx_uart_devs; |
1386 | |
1387 | for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) { |
1388 | s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr); |
1389 | } |
1390 | |
1391 | return 0; |
1392 | } |
1393 | |
1394 | static int __init |
1395 | s3c24xx_serial_console_setup(struct console *co, char *options) |
1396 | { |
1397 | struct uart_port *port; |
1398 | int baud = 9600; |
1399 | int bits = 8; |
1400 | int parity = 'n'; |
1401 | int flow = 'n'; |
1402 | |
1403 | dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n", |
1404 | co, co->index, options); |
1405 | |
1406 | /* is this a valid port */ |
1407 | |
1408 | if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) |
1409 | co->index = 0; |
1410 | |
1411 | port = &s3c24xx_serial_ports[co->index].port; |
1412 | |
1413 | /* is the port configured? */ |
1414 | |
1415 | if (port->mapbase == 0x0) { |
1416 | co->index = 0; |
1417 | port = &s3c24xx_serial_ports[co->index].port; |
1418 | } |
1419 | |
1420 | cons_uart = port; |
1421 | |
1422 | dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index); |
1423 | |
1424 | /* |
1425 | * Check whether an invalid uart number has been specified, and |
1426 | * if so, search for the first available port that does have |
1427 | * console support. |
1428 | */ |
1429 | if (options) |
1430 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
1431 | else |
1432 | s3c24xx_serial_get_options(port, &baud, &parity, &bits); |
1433 | |
1434 | dbg("s3c24xx_serial_console_setup: baud %d\n", baud); |
1435 | |
1436 | return uart_set_options(port, co, baud, parity, bits, flow); |
1437 | } |
1438 | |
1439 | /* s3c24xx_serial_initconsole |
1440 | * |
1441 | * initialise the console from one of the uart drivers |
1442 | */ |
1443 | |
1444 | static struct console s3c24xx_serial_console = { |
1445 | .name = S3C24XX_SERIAL_NAME, |
1446 | .device = uart_console_device, |
1447 | .flags = CON_PRINTBUFFER, |
1448 | .index = -1, |
1449 | .write = s3c24xx_serial_console_write, |
1450 | .setup = s3c24xx_serial_console_setup |
1451 | }; |
1452 | |
1453 | int s3c24xx_serial_initconsole(struct platform_driver *drv, |
1454 | struct s3c24xx_uart_info **info) |
1455 | |
1456 | { |
1457 | struct platform_device *dev = s3c24xx_uart_devs[0]; |
1458 | |
1459 | dbg("s3c24xx_serial_initconsole\n"); |
1460 | |
1461 | /* select driver based on the cpu */ |
1462 | |
1463 | if (dev == NULL) { |
1464 | printk(KERN_ERR "s3c24xx: no devices for console init\n"); |
1465 | return 0; |
1466 | } |
1467 | |
1468 | if (strcmp(dev->name, drv->driver.name) != 0) |
1469 | return 0; |
1470 | |
1471 | s3c24xx_serial_console.data = &s3c24xx_uart_drv; |
1472 | s3c24xx_serial_init_ports(info); |
1473 | |
1474 | register_console(&s3c24xx_serial_console); |
1475 | return 0; |
1476 | } |
1477 | |
1478 | #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ |
1479 | |
1480 | MODULE_DESCRIPTION("Samsung SoC Serial port driver"); |
1481 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); |
1482 | MODULE_LICENSE("GPL v2"); |
1483 |
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