Root/
1 | /* |
2 | * zs.c: Serial port driver for IOASIC DECstations. |
3 | * |
4 | * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras. |
5 | * Derived from drivers/macintosh/macserial.c by Harald Koerfgen. |
6 | * |
7 | * DECstation changes |
8 | * Copyright (C) 1998-2000 Harald Koerfgen |
9 | * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
10 | * |
11 | * For the rest of the code the original Copyright applies: |
12 | * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) |
13 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) |
14 | * |
15 | * |
16 | * Note: for IOASIC systems the wiring is as follows: |
17 | * |
18 | * mouse/keyboard: |
19 | * DIN-7 MJ-4 signal SCC |
20 | * 2 1 TxD <- A.TxD |
21 | * 3 4 RxD -> A.RxD |
22 | * |
23 | * EIA-232/EIA-423: |
24 | * DB-25 MMJ-6 signal SCC |
25 | * 2 2 TxD <- B.TxD |
26 | * 3 5 RxD -> B.RxD |
27 | * 4 RTS <- ~A.RTS |
28 | * 5 CTS -> ~B.CTS |
29 | * 6 6 DSR -> ~A.SYNC |
30 | * 8 CD -> ~B.DCD |
31 | * 12 DSRS(DCE) -> ~A.CTS (*) |
32 | * 15 TxC -> B.TxC |
33 | * 17 RxC -> B.RxC |
34 | * 20 1 DTR <- ~A.DTR |
35 | * 22 RI -> ~A.DCD |
36 | * 23 DSRS(DTE) <- ~B.RTS |
37 | * |
38 | * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE) |
39 | * is shared with DSRS(DTE) at pin 23. |
40 | * |
41 | * As you can immediately notice the wiring of the RTS, DTR and DSR signals |
42 | * is a bit odd. This makes the handling of port B unnecessarily |
43 | * complicated and prevents the use of some automatic modes of operation. |
44 | */ |
45 | |
46 | #if defined(CONFIG_SERIAL_ZS_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
47 | #define SUPPORT_SYSRQ |
48 | #endif |
49 | |
50 | #include <linux/bug.h> |
51 | #include <linux/console.h> |
52 | #include <linux/delay.h> |
53 | #include <linux/errno.h> |
54 | #include <linux/init.h> |
55 | #include <linux/interrupt.h> |
56 | #include <linux/io.h> |
57 | #include <linux/ioport.h> |
58 | #include <linux/irqflags.h> |
59 | #include <linux/kernel.h> |
60 | #include <linux/major.h> |
61 | #include <linux/serial.h> |
62 | #include <linux/serial_core.h> |
63 | #include <linux/spinlock.h> |
64 | #include <linux/sysrq.h> |
65 | #include <linux/tty.h> |
66 | #include <linux/types.h> |
67 | |
68 | #include <asm/atomic.h> |
69 | #include <asm/system.h> |
70 | |
71 | #include <asm/dec/interrupts.h> |
72 | #include <asm/dec/ioasic_addrs.h> |
73 | #include <asm/dec/system.h> |
74 | |
75 | #include "zs.h" |
76 | |
77 | |
78 | MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>"); |
79 | MODULE_DESCRIPTION("DECstation Z85C30 serial driver"); |
80 | MODULE_LICENSE("GPL"); |
81 | |
82 | |
83 | static char zs_name[] __initdata = "DECstation Z85C30 serial driver version "; |
84 | static char zs_version[] __initdata = "0.10"; |
85 | |
86 | /* |
87 | * It would be nice to dynamically allocate everything that |
88 | * depends on ZS_NUM_SCCS, so we could support any number of |
89 | * Z85C30s, but for now... |
90 | */ |
91 | #define ZS_NUM_SCCS 2 /* Max # of ZS chips supported. */ |
92 | #define ZS_NUM_CHAN 2 /* 2 channels per chip. */ |
93 | #define ZS_CHAN_A 0 /* Index of the channel A. */ |
94 | #define ZS_CHAN_B 1 /* Index of the channel B. */ |
95 | #define ZS_CHAN_IO_SIZE 8 /* IOMEM space size. */ |
96 | #define ZS_CHAN_IO_STRIDE 4 /* Register alignment. */ |
97 | #define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte |
98 | of the 16-bit IOBUS. */ |
99 | #define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */ |
100 | |
101 | #define to_zport(uport) container_of(uport, struct zs_port, port) |
102 | |
103 | struct zs_parms { |
104 | resource_size_t scc[ZS_NUM_SCCS]; |
105 | int irq[ZS_NUM_SCCS]; |
106 | }; |
107 | |
108 | static struct zs_scc zs_sccs[ZS_NUM_SCCS]; |
109 | |
110 | static u8 zs_init_regs[ZS_NUM_REGS] __initdata = { |
111 | 0, /* write 0 */ |
112 | PAR_SPEC, /* write 1 */ |
113 | 0, /* write 2 */ |
114 | 0, /* write 3 */ |
115 | X16CLK | SB1, /* write 4 */ |
116 | 0, /* write 5 */ |
117 | 0, 0, 0, /* write 6, 7, 8 */ |
118 | MIE | DLC | NV, /* write 9 */ |
119 | NRZ, /* write 10 */ |
120 | TCBR | RCBR, /* write 11 */ |
121 | 0, 0, /* BRG time constant, write 12 + 13 */ |
122 | BRSRC | BRENABL, /* write 14 */ |
123 | 0, /* write 15 */ |
124 | }; |
125 | |
126 | /* |
127 | * Debugging. |
128 | */ |
129 | #undef ZS_DEBUG_REGS |
130 | |
131 | |
132 | /* |
133 | * Reading and writing Z85C30 registers. |
134 | */ |
135 | static void recovery_delay(void) |
136 | { |
137 | udelay(2); |
138 | } |
139 | |
140 | static u8 read_zsreg(struct zs_port *zport, int reg) |
141 | { |
142 | void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; |
143 | u8 retval; |
144 | |
145 | if (reg != 0) { |
146 | writeb(reg & 0xf, control); |
147 | fast_iob(); |
148 | recovery_delay(); |
149 | } |
150 | retval = readb(control); |
151 | recovery_delay(); |
152 | return retval; |
153 | } |
154 | |
155 | static void write_zsreg(struct zs_port *zport, int reg, u8 value) |
156 | { |
157 | void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; |
158 | |
159 | if (reg != 0) { |
160 | writeb(reg & 0xf, control); |
161 | fast_iob(); recovery_delay(); |
162 | } |
163 | writeb(value, control); |
164 | fast_iob(); |
165 | recovery_delay(); |
166 | return; |
167 | } |
168 | |
169 | static u8 read_zsdata(struct zs_port *zport) |
170 | { |
171 | void __iomem *data = zport->port.membase + |
172 | ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET; |
173 | u8 retval; |
174 | |
175 | retval = readb(data); |
176 | recovery_delay(); |
177 | return retval; |
178 | } |
179 | |
180 | static void write_zsdata(struct zs_port *zport, u8 value) |
181 | { |
182 | void __iomem *data = zport->port.membase + |
183 | ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET; |
184 | |
185 | writeb(value, data); |
186 | fast_iob(); |
187 | recovery_delay(); |
188 | return; |
189 | } |
190 | |
191 | #ifdef ZS_DEBUG_REGS |
192 | void zs_dump(void) |
193 | { |
194 | struct zs_port *zport; |
195 | int i, j; |
196 | |
197 | for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) { |
198 | zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN]; |
199 | |
200 | if (!zport->scc) |
201 | continue; |
202 | |
203 | for (j = 0; j < 16; j++) |
204 | printk("W%-2d = 0x%02x\t", j, zport->regs[j]); |
205 | printk("\n"); |
206 | for (j = 0; j < 16; j++) |
207 | printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j)); |
208 | printk("\n\n"); |
209 | } |
210 | } |
211 | #endif |
212 | |
213 | |
214 | static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq) |
215 | { |
216 | if (irq) |
217 | spin_lock_irq(lock); |
218 | else |
219 | spin_lock(lock); |
220 | } |
221 | |
222 | static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq) |
223 | { |
224 | if (irq) |
225 | spin_unlock_irq(lock); |
226 | else |
227 | spin_unlock(lock); |
228 | } |
229 | |
230 | static int zs_receive_drain(struct zs_port *zport) |
231 | { |
232 | int loops = 10000; |
233 | |
234 | while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops) |
235 | read_zsdata(zport); |
236 | return loops; |
237 | } |
238 | |
239 | static int zs_transmit_drain(struct zs_port *zport, int irq) |
240 | { |
241 | struct zs_scc *scc = zport->scc; |
242 | int loops = 10000; |
243 | |
244 | while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) { |
245 | zs_spin_unlock_cond_irq(&scc->zlock, irq); |
246 | udelay(2); |
247 | zs_spin_lock_cond_irq(&scc->zlock, irq); |
248 | } |
249 | return loops; |
250 | } |
251 | |
252 | static int zs_line_drain(struct zs_port *zport, int irq) |
253 | { |
254 | struct zs_scc *scc = zport->scc; |
255 | int loops = 10000; |
256 | |
257 | while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) { |
258 | zs_spin_unlock_cond_irq(&scc->zlock, irq); |
259 | udelay(2); |
260 | zs_spin_lock_cond_irq(&scc->zlock, irq); |
261 | } |
262 | return loops; |
263 | } |
264 | |
265 | |
266 | static void load_zsregs(struct zs_port *zport, u8 *regs, int irq) |
267 | { |
268 | /* Let the current transmission finish. */ |
269 | zs_line_drain(zport, irq); |
270 | /* Load 'em up. */ |
271 | write_zsreg(zport, R3, regs[3] & ~RxENABLE); |
272 | write_zsreg(zport, R5, regs[5] & ~TxENAB); |
273 | write_zsreg(zport, R4, regs[4]); |
274 | write_zsreg(zport, R9, regs[9]); |
275 | write_zsreg(zport, R1, regs[1]); |
276 | write_zsreg(zport, R2, regs[2]); |
277 | write_zsreg(zport, R10, regs[10]); |
278 | write_zsreg(zport, R14, regs[14] & ~BRENABL); |
279 | write_zsreg(zport, R11, regs[11]); |
280 | write_zsreg(zport, R12, regs[12]); |
281 | write_zsreg(zport, R13, regs[13]); |
282 | write_zsreg(zport, R14, regs[14]); |
283 | write_zsreg(zport, R15, regs[15]); |
284 | if (regs[3] & RxENABLE) |
285 | write_zsreg(zport, R3, regs[3]); |
286 | if (regs[5] & TxENAB) |
287 | write_zsreg(zport, R5, regs[5]); |
288 | return; |
289 | } |
290 | |
291 | |
292 | /* |
293 | * Status handling routines. |
294 | */ |
295 | |
296 | /* |
297 | * zs_tx_empty() -- get the transmitter empty status |
298 | * |
299 | * Purpose: Let user call ioctl() to get info when the UART physically |
300 | * is emptied. On bus types like RS485, the transmitter must |
301 | * release the bus after transmitting. This must be done when |
302 | * the transmit shift register is empty, not be done when the |
303 | * transmit holding register is empty. This functionality |
304 | * allows an RS485 driver to be written in user space. |
305 | */ |
306 | static unsigned int zs_tx_empty(struct uart_port *uport) |
307 | { |
308 | struct zs_port *zport = to_zport(uport); |
309 | struct zs_scc *scc = zport->scc; |
310 | unsigned long flags; |
311 | u8 status; |
312 | |
313 | spin_lock_irqsave(&scc->zlock, flags); |
314 | status = read_zsreg(zport, R1); |
315 | spin_unlock_irqrestore(&scc->zlock, flags); |
316 | |
317 | return status & ALL_SNT ? TIOCSER_TEMT : 0; |
318 | } |
319 | |
320 | static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a, |
321 | struct zs_port *zport_b) |
322 | { |
323 | u8 status_a, status_b; |
324 | unsigned int mctrl; |
325 | |
326 | status_a = read_zsreg(zport_a, R0); |
327 | status_b = read_zsreg(zport_b, R0); |
328 | |
329 | mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) | |
330 | ((status_b & DCD) ? TIOCM_CAR : 0) | |
331 | ((status_a & DCD) ? TIOCM_RNG : 0) | |
332 | ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0); |
333 | |
334 | return mctrl; |
335 | } |
336 | |
337 | static unsigned int zs_raw_get_mctrl(struct zs_port *zport) |
338 | { |
339 | struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A]; |
340 | |
341 | return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0; |
342 | } |
343 | |
344 | static unsigned int zs_raw_xor_mctrl(struct zs_port *zport) |
345 | { |
346 | struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A]; |
347 | unsigned int mmask, mctrl, delta; |
348 | u8 mask_a, mask_b; |
349 | |
350 | if (zport == zport_a) |
351 | return 0; |
352 | |
353 | mask_a = zport_a->regs[15]; |
354 | mask_b = zport->regs[15]; |
355 | |
356 | mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) | |
357 | ((mask_b & DCDIE) ? TIOCM_CAR : 0) | |
358 | ((mask_a & DCDIE) ? TIOCM_RNG : 0) | |
359 | ((mask_a & SYNCIE) ? TIOCM_DSR : 0); |
360 | |
361 | mctrl = zport->mctrl; |
362 | if (mmask) { |
363 | mctrl &= ~mmask; |
364 | mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask; |
365 | } |
366 | |
367 | delta = mctrl ^ zport->mctrl; |
368 | if (delta) |
369 | zport->mctrl = mctrl; |
370 | |
371 | return delta; |
372 | } |
373 | |
374 | static unsigned int zs_get_mctrl(struct uart_port *uport) |
375 | { |
376 | struct zs_port *zport = to_zport(uport); |
377 | struct zs_scc *scc = zport->scc; |
378 | unsigned int mctrl; |
379 | |
380 | spin_lock(&scc->zlock); |
381 | mctrl = zs_raw_get_mctrl(zport); |
382 | spin_unlock(&scc->zlock); |
383 | |
384 | return mctrl; |
385 | } |
386 | |
387 | static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl) |
388 | { |
389 | struct zs_port *zport = to_zport(uport); |
390 | struct zs_scc *scc = zport->scc; |
391 | struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; |
392 | u8 oldloop, newloop; |
393 | |
394 | spin_lock(&scc->zlock); |
395 | if (zport != zport_a) { |
396 | if (mctrl & TIOCM_DTR) |
397 | zport_a->regs[5] |= DTR; |
398 | else |
399 | zport_a->regs[5] &= ~DTR; |
400 | if (mctrl & TIOCM_RTS) |
401 | zport_a->regs[5] |= RTS; |
402 | else |
403 | zport_a->regs[5] &= ~RTS; |
404 | write_zsreg(zport_a, R5, zport_a->regs[5]); |
405 | } |
406 | |
407 | /* Rarely modified, so don't poke at hardware unless necessary. */ |
408 | oldloop = zport->regs[14]; |
409 | newloop = oldloop; |
410 | if (mctrl & TIOCM_LOOP) |
411 | newloop |= LOOPBAK; |
412 | else |
413 | newloop &= ~LOOPBAK; |
414 | if (newloop != oldloop) { |
415 | zport->regs[14] = newloop; |
416 | write_zsreg(zport, R14, zport->regs[14]); |
417 | } |
418 | spin_unlock(&scc->zlock); |
419 | } |
420 | |
421 | static void zs_raw_stop_tx(struct zs_port *zport) |
422 | { |
423 | write_zsreg(zport, R0, RES_Tx_P); |
424 | zport->tx_stopped = 1; |
425 | } |
426 | |
427 | static void zs_stop_tx(struct uart_port *uport) |
428 | { |
429 | struct zs_port *zport = to_zport(uport); |
430 | struct zs_scc *scc = zport->scc; |
431 | |
432 | spin_lock(&scc->zlock); |
433 | zs_raw_stop_tx(zport); |
434 | spin_unlock(&scc->zlock); |
435 | } |
436 | |
437 | static void zs_raw_transmit_chars(struct zs_port *); |
438 | |
439 | static void zs_start_tx(struct uart_port *uport) |
440 | { |
441 | struct zs_port *zport = to_zport(uport); |
442 | struct zs_scc *scc = zport->scc; |
443 | |
444 | spin_lock(&scc->zlock); |
445 | if (zport->tx_stopped) { |
446 | zs_transmit_drain(zport, 0); |
447 | zport->tx_stopped = 0; |
448 | zs_raw_transmit_chars(zport); |
449 | } |
450 | spin_unlock(&scc->zlock); |
451 | } |
452 | |
453 | static void zs_stop_rx(struct uart_port *uport) |
454 | { |
455 | struct zs_port *zport = to_zport(uport); |
456 | struct zs_scc *scc = zport->scc; |
457 | struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; |
458 | |
459 | spin_lock(&scc->zlock); |
460 | zport->regs[15] &= ~BRKIE; |
461 | zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB); |
462 | zport->regs[1] |= RxINT_DISAB; |
463 | |
464 | if (zport != zport_a) { |
465 | /* A-side DCD tracks RI and SYNC tracks DSR. */ |
466 | zport_a->regs[15] &= ~(DCDIE | SYNCIE); |
467 | write_zsreg(zport_a, R15, zport_a->regs[15]); |
468 | if (!(zport_a->regs[15] & BRKIE)) { |
469 | zport_a->regs[1] &= ~EXT_INT_ENAB; |
470 | write_zsreg(zport_a, R1, zport_a->regs[1]); |
471 | } |
472 | |
473 | /* This-side DCD tracks DCD and CTS tracks CTS. */ |
474 | zport->regs[15] &= ~(DCDIE | CTSIE); |
475 | zport->regs[1] &= ~EXT_INT_ENAB; |
476 | } else { |
477 | /* DCD tracks RI and SYNC tracks DSR for the B side. */ |
478 | if (!(zport->regs[15] & (DCDIE | SYNCIE))) |
479 | zport->regs[1] &= ~EXT_INT_ENAB; |
480 | } |
481 | |
482 | write_zsreg(zport, R15, zport->regs[15]); |
483 | write_zsreg(zport, R1, zport->regs[1]); |
484 | spin_unlock(&scc->zlock); |
485 | } |
486 | |
487 | static void zs_enable_ms(struct uart_port *uport) |
488 | { |
489 | struct zs_port *zport = to_zport(uport); |
490 | struct zs_scc *scc = zport->scc; |
491 | struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; |
492 | |
493 | if (zport == zport_a) |
494 | return; |
495 | |
496 | spin_lock(&scc->zlock); |
497 | |
498 | /* Clear Ext interrupts if not being handled already. */ |
499 | if (!(zport_a->regs[1] & EXT_INT_ENAB)) |
500 | write_zsreg(zport_a, R0, RES_EXT_INT); |
501 | |
502 | /* A-side DCD tracks RI and SYNC tracks DSR. */ |
503 | zport_a->regs[1] |= EXT_INT_ENAB; |
504 | zport_a->regs[15] |= DCDIE | SYNCIE; |
505 | |
506 | /* This-side DCD tracks DCD and CTS tracks CTS. */ |
507 | zport->regs[15] |= DCDIE | CTSIE; |
508 | |
509 | zs_raw_xor_mctrl(zport); |
510 | |
511 | write_zsreg(zport_a, R1, zport_a->regs[1]); |
512 | write_zsreg(zport_a, R15, zport_a->regs[15]); |
513 | write_zsreg(zport, R15, zport->regs[15]); |
514 | spin_unlock(&scc->zlock); |
515 | } |
516 | |
517 | static void zs_break_ctl(struct uart_port *uport, int break_state) |
518 | { |
519 | struct zs_port *zport = to_zport(uport); |
520 | struct zs_scc *scc = zport->scc; |
521 | unsigned long flags; |
522 | |
523 | spin_lock_irqsave(&scc->zlock, flags); |
524 | if (break_state == -1) |
525 | zport->regs[5] |= SND_BRK; |
526 | else |
527 | zport->regs[5] &= ~SND_BRK; |
528 | write_zsreg(zport, R5, zport->regs[5]); |
529 | spin_unlock_irqrestore(&scc->zlock, flags); |
530 | } |
531 | |
532 | |
533 | /* |
534 | * Interrupt handling routines. |
535 | */ |
536 | #define Rx_BRK 0x0100 /* BREAK event software flag. */ |
537 | #define Rx_SYS 0x0200 /* SysRq event software flag. */ |
538 | |
539 | static void zs_receive_chars(struct zs_port *zport) |
540 | { |
541 | struct uart_port *uport = &zport->port; |
542 | struct zs_scc *scc = zport->scc; |
543 | struct uart_icount *icount; |
544 | unsigned int avail, status, ch, flag; |
545 | int count; |
546 | |
547 | for (count = 16; count; count--) { |
548 | spin_lock(&scc->zlock); |
549 | avail = read_zsreg(zport, R0) & Rx_CH_AV; |
550 | spin_unlock(&scc->zlock); |
551 | if (!avail) |
552 | break; |
553 | |
554 | spin_lock(&scc->zlock); |
555 | status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR); |
556 | ch = read_zsdata(zport); |
557 | spin_unlock(&scc->zlock); |
558 | |
559 | flag = TTY_NORMAL; |
560 | |
561 | icount = &uport->icount; |
562 | icount->rx++; |
563 | |
564 | /* Handle the null char got when BREAK is removed. */ |
565 | if (!ch) |
566 | status |= zport->tty_break; |
567 | if (unlikely(status & |
568 | (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) { |
569 | zport->tty_break = 0; |
570 | |
571 | /* Reset the error indication. */ |
572 | if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) { |
573 | spin_lock(&scc->zlock); |
574 | write_zsreg(zport, R0, ERR_RES); |
575 | spin_unlock(&scc->zlock); |
576 | } |
577 | |
578 | if (status & (Rx_SYS | Rx_BRK)) { |
579 | icount->brk++; |
580 | /* SysRq discards the null char. */ |
581 | if (status & Rx_SYS) |
582 | continue; |
583 | } else if (status & FRM_ERR) |
584 | icount->frame++; |
585 | else if (status & PAR_ERR) |
586 | icount->parity++; |
587 | if (status & Rx_OVR) |
588 | icount->overrun++; |
589 | |
590 | status &= uport->read_status_mask; |
591 | if (status & Rx_BRK) |
592 | flag = TTY_BREAK; |
593 | else if (status & FRM_ERR) |
594 | flag = TTY_FRAME; |
595 | else if (status & PAR_ERR) |
596 | flag = TTY_PARITY; |
597 | } |
598 | |
599 | if (uart_handle_sysrq_char(uport, ch)) |
600 | continue; |
601 | |
602 | uart_insert_char(uport, status, Rx_OVR, ch, flag); |
603 | } |
604 | |
605 | tty_flip_buffer_push(uport->state->port.tty); |
606 | } |
607 | |
608 | static void zs_raw_transmit_chars(struct zs_port *zport) |
609 | { |
610 | struct circ_buf *xmit = &zport->port.state->xmit; |
611 | |
612 | /* XON/XOFF chars. */ |
613 | if (zport->port.x_char) { |
614 | write_zsdata(zport, zport->port.x_char); |
615 | zport->port.icount.tx++; |
616 | zport->port.x_char = 0; |
617 | return; |
618 | } |
619 | |
620 | /* If nothing to do or stopped or hardware stopped. */ |
621 | if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) { |
622 | zs_raw_stop_tx(zport); |
623 | return; |
624 | } |
625 | |
626 | /* Send char. */ |
627 | write_zsdata(zport, xmit->buf[xmit->tail]); |
628 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
629 | zport->port.icount.tx++; |
630 | |
631 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
632 | uart_write_wakeup(&zport->port); |
633 | |
634 | /* Are we are done? */ |
635 | if (uart_circ_empty(xmit)) |
636 | zs_raw_stop_tx(zport); |
637 | } |
638 | |
639 | static void zs_transmit_chars(struct zs_port *zport) |
640 | { |
641 | struct zs_scc *scc = zport->scc; |
642 | |
643 | spin_lock(&scc->zlock); |
644 | zs_raw_transmit_chars(zport); |
645 | spin_unlock(&scc->zlock); |
646 | } |
647 | |
648 | static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a) |
649 | { |
650 | struct uart_port *uport = &zport->port; |
651 | struct zs_scc *scc = zport->scc; |
652 | unsigned int delta; |
653 | u8 status, brk; |
654 | |
655 | spin_lock(&scc->zlock); |
656 | |
657 | /* Get status from Read Register 0. */ |
658 | status = read_zsreg(zport, R0); |
659 | |
660 | if (zport->regs[15] & BRKIE) { |
661 | brk = status & BRK_ABRT; |
662 | if (brk && !zport->brk) { |
663 | spin_unlock(&scc->zlock); |
664 | if (uart_handle_break(uport)) |
665 | zport->tty_break = Rx_SYS; |
666 | else |
667 | zport->tty_break = Rx_BRK; |
668 | spin_lock(&scc->zlock); |
669 | } |
670 | zport->brk = brk; |
671 | } |
672 | |
673 | if (zport != zport_a) { |
674 | delta = zs_raw_xor_mctrl(zport); |
675 | spin_unlock(&scc->zlock); |
676 | |
677 | if (delta & TIOCM_CTS) |
678 | uart_handle_cts_change(uport, |
679 | zport->mctrl & TIOCM_CTS); |
680 | if (delta & TIOCM_CAR) |
681 | uart_handle_dcd_change(uport, |
682 | zport->mctrl & TIOCM_CAR); |
683 | if (delta & TIOCM_RNG) |
684 | uport->icount.dsr++; |
685 | if (delta & TIOCM_DSR) |
686 | uport->icount.rng++; |
687 | |
688 | if (delta) |
689 | wake_up_interruptible(&uport->state->port.delta_msr_wait); |
690 | |
691 | spin_lock(&scc->zlock); |
692 | } |
693 | |
694 | /* Clear the status condition... */ |
695 | write_zsreg(zport, R0, RES_EXT_INT); |
696 | |
697 | spin_unlock(&scc->zlock); |
698 | } |
699 | |
700 | /* |
701 | * This is the Z85C30 driver's generic interrupt routine. |
702 | */ |
703 | static irqreturn_t zs_interrupt(int irq, void *dev_id) |
704 | { |
705 | struct zs_scc *scc = dev_id; |
706 | struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; |
707 | struct zs_port *zport_b = &scc->zport[ZS_CHAN_B]; |
708 | irqreturn_t status = IRQ_NONE; |
709 | u8 zs_intreg; |
710 | int count; |
711 | |
712 | /* |
713 | * NOTE: The read register 3, which holds the irq status, |
714 | * does so for both channels on each chip. Although |
715 | * the status value itself must be read from the A |
716 | * channel and is only valid when read from channel A. |
717 | * Yes... broken hardware... |
718 | */ |
719 | for (count = 16; count; count--) { |
720 | spin_lock(&scc->zlock); |
721 | zs_intreg = read_zsreg(zport_a, R3); |
722 | spin_unlock(&scc->zlock); |
723 | if (!zs_intreg) |
724 | break; |
725 | |
726 | /* |
727 | * We do not like losing characters, so we prioritise |
728 | * interrupt sources a little bit differently than |
729 | * the SCC would, was it allowed to. |
730 | */ |
731 | if (zs_intreg & CHBRxIP) |
732 | zs_receive_chars(zport_b); |
733 | if (zs_intreg & CHARxIP) |
734 | zs_receive_chars(zport_a); |
735 | if (zs_intreg & CHBEXT) |
736 | zs_status_handle(zport_b, zport_a); |
737 | if (zs_intreg & CHAEXT) |
738 | zs_status_handle(zport_a, zport_a); |
739 | if (zs_intreg & CHBTxIP) |
740 | zs_transmit_chars(zport_b); |
741 | if (zs_intreg & CHATxIP) |
742 | zs_transmit_chars(zport_a); |
743 | |
744 | status = IRQ_HANDLED; |
745 | } |
746 | |
747 | return status; |
748 | } |
749 | |
750 | |
751 | /* |
752 | * Finally, routines used to initialize the serial port. |
753 | */ |
754 | static int zs_startup(struct uart_port *uport) |
755 | { |
756 | struct zs_port *zport = to_zport(uport); |
757 | struct zs_scc *scc = zport->scc; |
758 | unsigned long flags; |
759 | int irq_guard; |
760 | int ret; |
761 | |
762 | irq_guard = atomic_add_return(1, &scc->irq_guard); |
763 | if (irq_guard == 1) { |
764 | ret = request_irq(zport->port.irq, zs_interrupt, |
765 | IRQF_SHARED, "scc", scc); |
766 | if (ret) { |
767 | atomic_add(-1, &scc->irq_guard); |
768 | printk(KERN_ERR "zs: can't get irq %d\n", |
769 | zport->port.irq); |
770 | return ret; |
771 | } |
772 | } |
773 | |
774 | spin_lock_irqsave(&scc->zlock, flags); |
775 | |
776 | /* Clear the receive FIFO. */ |
777 | zs_receive_drain(zport); |
778 | |
779 | /* Clear the interrupt registers. */ |
780 | write_zsreg(zport, R0, ERR_RES); |
781 | write_zsreg(zport, R0, RES_Tx_P); |
782 | /* But Ext only if not being handled already. */ |
783 | if (!(zport->regs[1] & EXT_INT_ENAB)) |
784 | write_zsreg(zport, R0, RES_EXT_INT); |
785 | |
786 | /* Finally, enable sequencing and interrupts. */ |
787 | zport->regs[1] &= ~RxINT_MASK; |
788 | zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB; |
789 | zport->regs[3] |= RxENABLE; |
790 | zport->regs[15] |= BRKIE; |
791 | write_zsreg(zport, R1, zport->regs[1]); |
792 | write_zsreg(zport, R3, zport->regs[3]); |
793 | write_zsreg(zport, R5, zport->regs[5]); |
794 | write_zsreg(zport, R15, zport->regs[15]); |
795 | |
796 | /* Record the current state of RR0. */ |
797 | zport->mctrl = zs_raw_get_mctrl(zport); |
798 | zport->brk = read_zsreg(zport, R0) & BRK_ABRT; |
799 | |
800 | zport->tx_stopped = 1; |
801 | |
802 | spin_unlock_irqrestore(&scc->zlock, flags); |
803 | |
804 | return 0; |
805 | } |
806 | |
807 | static void zs_shutdown(struct uart_port *uport) |
808 | { |
809 | struct zs_port *zport = to_zport(uport); |
810 | struct zs_scc *scc = zport->scc; |
811 | unsigned long flags; |
812 | int irq_guard; |
813 | |
814 | spin_lock_irqsave(&scc->zlock, flags); |
815 | |
816 | zport->regs[3] &= ~RxENABLE; |
817 | write_zsreg(zport, R5, zport->regs[5]); |
818 | write_zsreg(zport, R3, zport->regs[3]); |
819 | |
820 | spin_unlock_irqrestore(&scc->zlock, flags); |
821 | |
822 | irq_guard = atomic_add_return(-1, &scc->irq_guard); |
823 | if (!irq_guard) |
824 | free_irq(zport->port.irq, scc); |
825 | } |
826 | |
827 | |
828 | static void zs_reset(struct zs_port *zport) |
829 | { |
830 | struct zs_scc *scc = zport->scc; |
831 | int irq; |
832 | unsigned long flags; |
833 | |
834 | spin_lock_irqsave(&scc->zlock, flags); |
835 | irq = !irqs_disabled_flags(flags); |
836 | if (!scc->initialised) { |
837 | /* Reset the pointer first, just in case... */ |
838 | read_zsreg(zport, R0); |
839 | /* And let the current transmission finish. */ |
840 | zs_line_drain(zport, irq); |
841 | write_zsreg(zport, R9, FHWRES); |
842 | udelay(10); |
843 | write_zsreg(zport, R9, 0); |
844 | scc->initialised = 1; |
845 | } |
846 | load_zsregs(zport, zport->regs, irq); |
847 | spin_unlock_irqrestore(&scc->zlock, flags); |
848 | } |
849 | |
850 | static void zs_set_termios(struct uart_port *uport, struct ktermios *termios, |
851 | struct ktermios *old_termios) |
852 | { |
853 | struct zs_port *zport = to_zport(uport); |
854 | struct zs_scc *scc = zport->scc; |
855 | struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; |
856 | int irq; |
857 | unsigned int baud, brg; |
858 | unsigned long flags; |
859 | |
860 | spin_lock_irqsave(&scc->zlock, flags); |
861 | irq = !irqs_disabled_flags(flags); |
862 | |
863 | /* Byte size. */ |
864 | zport->regs[3] &= ~RxNBITS_MASK; |
865 | zport->regs[5] &= ~TxNBITS_MASK; |
866 | switch (termios->c_cflag & CSIZE) { |
867 | case CS5: |
868 | zport->regs[3] |= Rx5; |
869 | zport->regs[5] |= Tx5; |
870 | break; |
871 | case CS6: |
872 | zport->regs[3] |= Rx6; |
873 | zport->regs[5] |= Tx6; |
874 | break; |
875 | case CS7: |
876 | zport->regs[3] |= Rx7; |
877 | zport->regs[5] |= Tx7; |
878 | break; |
879 | case CS8: |
880 | default: |
881 | zport->regs[3] |= Rx8; |
882 | zport->regs[5] |= Tx8; |
883 | break; |
884 | } |
885 | |
886 | /* Parity and stop bits. */ |
887 | zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN); |
888 | if (termios->c_cflag & CSTOPB) |
889 | zport->regs[4] |= SB2; |
890 | else |
891 | zport->regs[4] |= SB1; |
892 | if (termios->c_cflag & PARENB) |
893 | zport->regs[4] |= PAR_ENA; |
894 | if (!(termios->c_cflag & PARODD)) |
895 | zport->regs[4] |= PAR_EVEN; |
896 | switch (zport->clk_mode) { |
897 | case 64: |
898 | zport->regs[4] |= X64CLK; |
899 | break; |
900 | case 32: |
901 | zport->regs[4] |= X32CLK; |
902 | break; |
903 | case 16: |
904 | zport->regs[4] |= X16CLK; |
905 | break; |
906 | case 1: |
907 | zport->regs[4] |= X1CLK; |
908 | break; |
909 | default: |
910 | BUG(); |
911 | } |
912 | |
913 | baud = uart_get_baud_rate(uport, termios, old_termios, 0, |
914 | uport->uartclk / zport->clk_mode / 4); |
915 | |
916 | brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode); |
917 | zport->regs[12] = brg & 0xff; |
918 | zport->regs[13] = (brg >> 8) & 0xff; |
919 | |
920 | uart_update_timeout(uport, termios->c_cflag, baud); |
921 | |
922 | uport->read_status_mask = Rx_OVR; |
923 | if (termios->c_iflag & INPCK) |
924 | uport->read_status_mask |= FRM_ERR | PAR_ERR; |
925 | if (termios->c_iflag & (BRKINT | PARMRK)) |
926 | uport->read_status_mask |= Rx_BRK; |
927 | |
928 | uport->ignore_status_mask = 0; |
929 | if (termios->c_iflag & IGNPAR) |
930 | uport->ignore_status_mask |= FRM_ERR | PAR_ERR; |
931 | if (termios->c_iflag & IGNBRK) { |
932 | uport->ignore_status_mask |= Rx_BRK; |
933 | if (termios->c_iflag & IGNPAR) |
934 | uport->ignore_status_mask |= Rx_OVR; |
935 | } |
936 | |
937 | if (termios->c_cflag & CREAD) |
938 | zport->regs[3] |= RxENABLE; |
939 | else |
940 | zport->regs[3] &= ~RxENABLE; |
941 | |
942 | if (zport != zport_a) { |
943 | if (!(termios->c_cflag & CLOCAL)) { |
944 | zport->regs[15] |= DCDIE; |
945 | } else |
946 | zport->regs[15] &= ~DCDIE; |
947 | if (termios->c_cflag & CRTSCTS) { |
948 | zport->regs[15] |= CTSIE; |
949 | } else |
950 | zport->regs[15] &= ~CTSIE; |
951 | zs_raw_xor_mctrl(zport); |
952 | } |
953 | |
954 | /* Load up the new values. */ |
955 | load_zsregs(zport, zport->regs, irq); |
956 | |
957 | spin_unlock_irqrestore(&scc->zlock, flags); |
958 | } |
959 | |
960 | /* |
961 | * Hack alert! |
962 | * Required solely so that the initial PROM-based console |
963 | * works undisturbed in parallel with this one. |
964 | */ |
965 | static void zs_pm(struct uart_port *uport, unsigned int state, |
966 | unsigned int oldstate) |
967 | { |
968 | struct zs_port *zport = to_zport(uport); |
969 | |
970 | if (state < 3) |
971 | zport->regs[5] |= TxENAB; |
972 | else |
973 | zport->regs[5] &= ~TxENAB; |
974 | write_zsreg(zport, R5, zport->regs[5]); |
975 | } |
976 | |
977 | |
978 | static const char *zs_type(struct uart_port *uport) |
979 | { |
980 | return "Z85C30 SCC"; |
981 | } |
982 | |
983 | static void zs_release_port(struct uart_port *uport) |
984 | { |
985 | iounmap(uport->membase); |
986 | uport->membase = 0; |
987 | release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE); |
988 | } |
989 | |
990 | static int zs_map_port(struct uart_port *uport) |
991 | { |
992 | if (!uport->membase) |
993 | uport->membase = ioremap_nocache(uport->mapbase, |
994 | ZS_CHAN_IO_SIZE); |
995 | if (!uport->membase) { |
996 | printk(KERN_ERR "zs: Cannot map MMIO\n"); |
997 | return -ENOMEM; |
998 | } |
999 | return 0; |
1000 | } |
1001 | |
1002 | static int zs_request_port(struct uart_port *uport) |
1003 | { |
1004 | int ret; |
1005 | |
1006 | if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) { |
1007 | printk(KERN_ERR "zs: Unable to reserve MMIO resource\n"); |
1008 | return -EBUSY; |
1009 | } |
1010 | ret = zs_map_port(uport); |
1011 | if (ret) { |
1012 | release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE); |
1013 | return ret; |
1014 | } |
1015 | return 0; |
1016 | } |
1017 | |
1018 | static void zs_config_port(struct uart_port *uport, int flags) |
1019 | { |
1020 | struct zs_port *zport = to_zport(uport); |
1021 | |
1022 | if (flags & UART_CONFIG_TYPE) { |
1023 | if (zs_request_port(uport)) |
1024 | return; |
1025 | |
1026 | uport->type = PORT_ZS; |
1027 | |
1028 | zs_reset(zport); |
1029 | } |
1030 | } |
1031 | |
1032 | static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser) |
1033 | { |
1034 | struct zs_port *zport = to_zport(uport); |
1035 | int ret = 0; |
1036 | |
1037 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS) |
1038 | ret = -EINVAL; |
1039 | if (ser->irq != uport->irq) |
1040 | ret = -EINVAL; |
1041 | if (ser->baud_base != uport->uartclk / zport->clk_mode / 4) |
1042 | ret = -EINVAL; |
1043 | return ret; |
1044 | } |
1045 | |
1046 | |
1047 | static struct uart_ops zs_ops = { |
1048 | .tx_empty = zs_tx_empty, |
1049 | .set_mctrl = zs_set_mctrl, |
1050 | .get_mctrl = zs_get_mctrl, |
1051 | .stop_tx = zs_stop_tx, |
1052 | .start_tx = zs_start_tx, |
1053 | .stop_rx = zs_stop_rx, |
1054 | .enable_ms = zs_enable_ms, |
1055 | .break_ctl = zs_break_ctl, |
1056 | .startup = zs_startup, |
1057 | .shutdown = zs_shutdown, |
1058 | .set_termios = zs_set_termios, |
1059 | .pm = zs_pm, |
1060 | .type = zs_type, |
1061 | .release_port = zs_release_port, |
1062 | .request_port = zs_request_port, |
1063 | .config_port = zs_config_port, |
1064 | .verify_port = zs_verify_port, |
1065 | }; |
1066 | |
1067 | /* |
1068 | * Initialize Z85C30 port structures. |
1069 | */ |
1070 | static int __init zs_probe_sccs(void) |
1071 | { |
1072 | static int probed; |
1073 | struct zs_parms zs_parms; |
1074 | int chip, side, irq; |
1075 | int n_chips = 0; |
1076 | int i; |
1077 | |
1078 | if (probed) |
1079 | return 0; |
1080 | |
1081 | irq = dec_interrupt[DEC_IRQ_SCC0]; |
1082 | if (irq >= 0) { |
1083 | zs_parms.scc[n_chips] = IOASIC_SCC0; |
1084 | zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0]; |
1085 | n_chips++; |
1086 | } |
1087 | irq = dec_interrupt[DEC_IRQ_SCC1]; |
1088 | if (irq >= 0) { |
1089 | zs_parms.scc[n_chips] = IOASIC_SCC1; |
1090 | zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1]; |
1091 | n_chips++; |
1092 | } |
1093 | if (!n_chips) |
1094 | return -ENXIO; |
1095 | |
1096 | probed = 1; |
1097 | |
1098 | for (chip = 0; chip < n_chips; chip++) { |
1099 | spin_lock_init(&zs_sccs[chip].zlock); |
1100 | for (side = 0; side < ZS_NUM_CHAN; side++) { |
1101 | struct zs_port *zport = &zs_sccs[chip].zport[side]; |
1102 | struct uart_port *uport = &zport->port; |
1103 | |
1104 | zport->scc = &zs_sccs[chip]; |
1105 | zport->clk_mode = 16; |
1106 | |
1107 | uport->irq = zs_parms.irq[chip]; |
1108 | uport->uartclk = ZS_CLOCK; |
1109 | uport->fifosize = 1; |
1110 | uport->iotype = UPIO_MEM; |
1111 | uport->flags = UPF_BOOT_AUTOCONF; |
1112 | uport->ops = &zs_ops; |
1113 | uport->line = chip * ZS_NUM_CHAN + side; |
1114 | uport->mapbase = dec_kn_slot_base + |
1115 | zs_parms.scc[chip] + |
1116 | (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE; |
1117 | |
1118 | for (i = 0; i < ZS_NUM_REGS; i++) |
1119 | zport->regs[i] = zs_init_regs[i]; |
1120 | } |
1121 | } |
1122 | |
1123 | return 0; |
1124 | } |
1125 | |
1126 | |
1127 | #ifdef CONFIG_SERIAL_ZS_CONSOLE |
1128 | static void zs_console_putchar(struct uart_port *uport, int ch) |
1129 | { |
1130 | struct zs_port *zport = to_zport(uport); |
1131 | struct zs_scc *scc = zport->scc; |
1132 | int irq; |
1133 | unsigned long flags; |
1134 | |
1135 | spin_lock_irqsave(&scc->zlock, flags); |
1136 | irq = !irqs_disabled_flags(flags); |
1137 | if (zs_transmit_drain(zport, irq)) |
1138 | write_zsdata(zport, ch); |
1139 | spin_unlock_irqrestore(&scc->zlock, flags); |
1140 | } |
1141 | |
1142 | /* |
1143 | * Print a string to the serial port trying not to disturb |
1144 | * any possible real use of the port... |
1145 | */ |
1146 | static void zs_console_write(struct console *co, const char *s, |
1147 | unsigned int count) |
1148 | { |
1149 | int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN; |
1150 | struct zs_port *zport = &zs_sccs[chip].zport[side]; |
1151 | struct zs_scc *scc = zport->scc; |
1152 | unsigned long flags; |
1153 | u8 txint, txenb; |
1154 | int irq; |
1155 | |
1156 | /* Disable transmit interrupts and enable the transmitter. */ |
1157 | spin_lock_irqsave(&scc->zlock, flags); |
1158 | txint = zport->regs[1]; |
1159 | txenb = zport->regs[5]; |
1160 | if (txint & TxINT_ENAB) { |
1161 | zport->regs[1] = txint & ~TxINT_ENAB; |
1162 | write_zsreg(zport, R1, zport->regs[1]); |
1163 | } |
1164 | if (!(txenb & TxENAB)) { |
1165 | zport->regs[5] = txenb | TxENAB; |
1166 | write_zsreg(zport, R5, zport->regs[5]); |
1167 | } |
1168 | spin_unlock_irqrestore(&scc->zlock, flags); |
1169 | |
1170 | uart_console_write(&zport->port, s, count, zs_console_putchar); |
1171 | |
1172 | /* Restore transmit interrupts and the transmitter enable. */ |
1173 | spin_lock_irqsave(&scc->zlock, flags); |
1174 | irq = !irqs_disabled_flags(flags); |
1175 | zs_line_drain(zport, irq); |
1176 | if (!(txenb & TxENAB)) { |
1177 | zport->regs[5] &= ~TxENAB; |
1178 | write_zsreg(zport, R5, zport->regs[5]); |
1179 | } |
1180 | if (txint & TxINT_ENAB) { |
1181 | zport->regs[1] |= TxINT_ENAB; |
1182 | write_zsreg(zport, R1, zport->regs[1]); |
1183 | } |
1184 | spin_unlock_irqrestore(&scc->zlock, flags); |
1185 | } |
1186 | |
1187 | /* |
1188 | * Setup serial console baud/bits/parity. We do two things here: |
1189 | * - construct a cflag setting for the first uart_open() |
1190 | * - initialise the serial port |
1191 | * Return non-zero if we didn't find a serial port. |
1192 | */ |
1193 | static int __init zs_console_setup(struct console *co, char *options) |
1194 | { |
1195 | int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN; |
1196 | struct zs_port *zport = &zs_sccs[chip].zport[side]; |
1197 | struct uart_port *uport = &zport->port; |
1198 | int baud = 9600; |
1199 | int bits = 8; |
1200 | int parity = 'n'; |
1201 | int flow = 'n'; |
1202 | int ret; |
1203 | |
1204 | ret = zs_map_port(uport); |
1205 | if (ret) |
1206 | return ret; |
1207 | |
1208 | zs_reset(zport); |
1209 | zs_pm(uport, 0, -1); |
1210 | |
1211 | if (options) |
1212 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
1213 | return uart_set_options(uport, co, baud, parity, bits, flow); |
1214 | } |
1215 | |
1216 | static struct uart_driver zs_reg; |
1217 | static struct console zs_console = { |
1218 | .name = "ttyS", |
1219 | .write = zs_console_write, |
1220 | .device = uart_console_device, |
1221 | .setup = zs_console_setup, |
1222 | .flags = CON_PRINTBUFFER, |
1223 | .index = -1, |
1224 | .data = &zs_reg, |
1225 | }; |
1226 | |
1227 | /* |
1228 | * Register console. |
1229 | */ |
1230 | static int __init zs_serial_console_init(void) |
1231 | { |
1232 | int ret; |
1233 | |
1234 | ret = zs_probe_sccs(); |
1235 | if (ret) |
1236 | return ret; |
1237 | register_console(&zs_console); |
1238 | |
1239 | return 0; |
1240 | } |
1241 | |
1242 | console_initcall(zs_serial_console_init); |
1243 | |
1244 | #define SERIAL_ZS_CONSOLE &zs_console |
1245 | #else |
1246 | #define SERIAL_ZS_CONSOLE NULL |
1247 | #endif /* CONFIG_SERIAL_ZS_CONSOLE */ |
1248 | |
1249 | static struct uart_driver zs_reg = { |
1250 | .owner = THIS_MODULE, |
1251 | .driver_name = "serial", |
1252 | .dev_name = "ttyS", |
1253 | .major = TTY_MAJOR, |
1254 | .minor = 64, |
1255 | .nr = ZS_NUM_SCCS * ZS_NUM_CHAN, |
1256 | .cons = SERIAL_ZS_CONSOLE, |
1257 | }; |
1258 | |
1259 | /* zs_init inits the driver. */ |
1260 | static int __init zs_init(void) |
1261 | { |
1262 | int i, ret; |
1263 | |
1264 | pr_info("%s%s\n", zs_name, zs_version); |
1265 | |
1266 | /* Find out how many Z85C30 SCCs we have. */ |
1267 | ret = zs_probe_sccs(); |
1268 | if (ret) |
1269 | return ret; |
1270 | |
1271 | ret = uart_register_driver(&zs_reg); |
1272 | if (ret) |
1273 | return ret; |
1274 | |
1275 | for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) { |
1276 | struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN]; |
1277 | struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN]; |
1278 | struct uart_port *uport = &zport->port; |
1279 | |
1280 | if (zport->scc) |
1281 | uart_add_one_port(&zs_reg, uport); |
1282 | } |
1283 | |
1284 | return 0; |
1285 | } |
1286 | |
1287 | static void __exit zs_exit(void) |
1288 | { |
1289 | int i; |
1290 | |
1291 | for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) { |
1292 | struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN]; |
1293 | struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN]; |
1294 | struct uart_port *uport = &zport->port; |
1295 | |
1296 | if (zport->scc) |
1297 | uart_remove_one_port(&zs_reg, uport); |
1298 | } |
1299 | |
1300 | uart_unregister_driver(&zs_reg); |
1301 | } |
1302 | |
1303 | module_init(zs_init); |
1304 | module_exit(zs_exit); |
1305 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9