Root/drivers/sh/intc.c

1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009, 2010 Paul Mundt
6 *
7 * Based on intc2.c and ipr.c
8 *
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19#include <linux/init.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22#include <linux/io.h>
23#include <linux/slab.h>
24#include <linux/interrupt.h>
25#include <linux/sh_intc.h>
26#include <linux/sysdev.h>
27#include <linux/list.h>
28#include <linux/topology.h>
29#include <linux/bitmap.h>
30#include <linux/cpumask.h>
31
32#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
33    ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
34     ((addr_e) << 16) | ((addr_d << 24)))
35
36#define _INTC_SHIFT(h) (h & 0x1f)
37#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
38#define _INTC_FN(h) ((h >> 9) & 0xf)
39#define _INTC_MODE(h) ((h >> 13) & 0x7)
40#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
41#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
42
43struct intc_handle_int {
44    unsigned int irq;
45    unsigned long handle;
46};
47
48struct intc_desc_int {
49    struct list_head list;
50    struct sys_device sysdev;
51    pm_message_t state;
52    unsigned long *reg;
53#ifdef CONFIG_SMP
54    unsigned long *smp;
55#endif
56    unsigned int nr_reg;
57    struct intc_handle_int *prio;
58    unsigned int nr_prio;
59    struct intc_handle_int *sense;
60    unsigned int nr_sense;
61    struct irq_chip chip;
62};
63
64static LIST_HEAD(intc_list);
65
66/*
67 * The intc_irq_map provides a global map of bound IRQ vectors for a
68 * given platform. Allocation of IRQs are either static through the CPU
69 * vector map, or dynamic in the case of board mux vectors or MSI.
70 *
71 * As this is a central point for all IRQ controllers on the system,
72 * each of the available sources are mapped out here. This combined with
73 * sparseirq makes it quite trivial to keep the vector map tightly packed
74 * when dynamically creating IRQs, as well as tying in to otherwise
75 * unused irq_desc positions in the sparse array.
76 */
77static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
78static DEFINE_SPINLOCK(vector_lock);
79
80#ifdef CONFIG_SMP
81#define IS_SMP(x) x.smp
82#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
83#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
84#else
85#define IS_SMP(x) 0
86#define INTC_REG(d, x, c) (d->reg[(x)])
87#define SMP_NR(d, x) 1
88#endif
89
90static unsigned int intc_prio_level[NR_IRQS]; /* for now */
91static unsigned long ack_handle[NR_IRQS];
92
93static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
94{
95    struct irq_chip *chip = get_irq_chip(irq);
96    return container_of(chip, struct intc_desc_int, chip);
97}
98
99static inline unsigned int set_field(unsigned int value,
100                     unsigned int field_value,
101                     unsigned int handle)
102{
103    unsigned int width = _INTC_WIDTH(handle);
104    unsigned int shift = _INTC_SHIFT(handle);
105
106    value &= ~(((1 << width) - 1) << shift);
107    value |= field_value << shift;
108    return value;
109}
110
111static void write_8(unsigned long addr, unsigned long h, unsigned long data)
112{
113    __raw_writeb(set_field(0, data, h), addr);
114    (void)__raw_readb(addr); /* Defeat write posting */
115}
116
117static void write_16(unsigned long addr, unsigned long h, unsigned long data)
118{
119    __raw_writew(set_field(0, data, h), addr);
120    (void)__raw_readw(addr); /* Defeat write posting */
121}
122
123static void write_32(unsigned long addr, unsigned long h, unsigned long data)
124{
125    __raw_writel(set_field(0, data, h), addr);
126    (void)__raw_readl(addr); /* Defeat write posting */
127}
128
129static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
130{
131    unsigned long flags;
132    local_irq_save(flags);
133    __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
134    (void)__raw_readb(addr); /* Defeat write posting */
135    local_irq_restore(flags);
136}
137
138static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
139{
140    unsigned long flags;
141    local_irq_save(flags);
142    __raw_writew(set_field(__raw_readw(addr), data, h), addr);
143    (void)__raw_readw(addr); /* Defeat write posting */
144    local_irq_restore(flags);
145}
146
147static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
148{
149    unsigned long flags;
150    local_irq_save(flags);
151    __raw_writel(set_field(__raw_readl(addr), data, h), addr);
152    (void)__raw_readl(addr); /* Defeat write posting */
153    local_irq_restore(flags);
154}
155
156enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
157
158static void (*intc_reg_fns[])(unsigned long addr,
159                  unsigned long h,
160                  unsigned long data) = {
161    [REG_FN_WRITE_BASE + 0] = write_8,
162    [REG_FN_WRITE_BASE + 1] = write_16,
163    [REG_FN_WRITE_BASE + 3] = write_32,
164    [REG_FN_MODIFY_BASE + 0] = modify_8,
165    [REG_FN_MODIFY_BASE + 1] = modify_16,
166    [REG_FN_MODIFY_BASE + 3] = modify_32,
167};
168
169enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
170    MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
171    MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
172    MODE_PRIO_REG, /* Priority value written to enable interrupt */
173    MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
174};
175
176static void intc_mode_field(unsigned long addr,
177                unsigned long handle,
178                void (*fn)(unsigned long,
179                       unsigned long,
180                       unsigned long),
181                unsigned int irq)
182{
183    fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
184}
185
186static void intc_mode_zero(unsigned long addr,
187               unsigned long handle,
188               void (*fn)(unsigned long,
189                       unsigned long,
190                       unsigned long),
191               unsigned int irq)
192{
193    fn(addr, handle, 0);
194}
195
196static void intc_mode_prio(unsigned long addr,
197               unsigned long handle,
198               void (*fn)(unsigned long,
199                       unsigned long,
200                       unsigned long),
201               unsigned int irq)
202{
203    fn(addr, handle, intc_prio_level[irq]);
204}
205
206static void (*intc_enable_fns[])(unsigned long addr,
207                 unsigned long handle,
208                 void (*fn)(unsigned long,
209                        unsigned long,
210                        unsigned long),
211                 unsigned int irq) = {
212    [MODE_ENABLE_REG] = intc_mode_field,
213    [MODE_MASK_REG] = intc_mode_zero,
214    [MODE_DUAL_REG] = intc_mode_field,
215    [MODE_PRIO_REG] = intc_mode_prio,
216    [MODE_PCLR_REG] = intc_mode_prio,
217};
218
219static void (*intc_disable_fns[])(unsigned long addr,
220                  unsigned long handle,
221                  void (*fn)(unsigned long,
222                         unsigned long,
223                         unsigned long),
224                  unsigned int irq) = {
225    [MODE_ENABLE_REG] = intc_mode_zero,
226    [MODE_MASK_REG] = intc_mode_field,
227    [MODE_DUAL_REG] = intc_mode_field,
228    [MODE_PRIO_REG] = intc_mode_zero,
229    [MODE_PCLR_REG] = intc_mode_field,
230};
231
232static inline void _intc_enable(unsigned int irq, unsigned long handle)
233{
234    struct intc_desc_int *d = get_intc_desc(irq);
235    unsigned long addr;
236    unsigned int cpu;
237
238    for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
239#ifdef CONFIG_SMP
240        if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
241            continue;
242#endif
243        addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
244        intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
245                            [_INTC_FN(handle)], irq);
246    }
247}
248
249static void intc_enable(unsigned int irq)
250{
251    _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
252}
253
254static void intc_disable(unsigned int irq)
255{
256    struct intc_desc_int *d = get_intc_desc(irq);
257    unsigned long handle = (unsigned long) get_irq_chip_data(irq);
258    unsigned long addr;
259    unsigned int cpu;
260
261    for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
262#ifdef CONFIG_SMP
263        if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
264            continue;
265#endif
266        addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
267        intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
268                             [_INTC_FN(handle)], irq);
269    }
270}
271
272static void (*intc_enable_noprio_fns[])(unsigned long addr,
273                    unsigned long handle,
274                    void (*fn)(unsigned long,
275                           unsigned long,
276                           unsigned long),
277                    unsigned int irq) = {
278    [MODE_ENABLE_REG] = intc_mode_field,
279    [MODE_MASK_REG] = intc_mode_zero,
280    [MODE_DUAL_REG] = intc_mode_field,
281    [MODE_PRIO_REG] = intc_mode_field,
282    [MODE_PCLR_REG] = intc_mode_field,
283};
284
285static void intc_enable_disable(struct intc_desc_int *d,
286                unsigned long handle, int do_enable)
287{
288    unsigned long addr;
289    unsigned int cpu;
290    void (*fn)(unsigned long, unsigned long,
291           void (*)(unsigned long, unsigned long, unsigned long),
292           unsigned int);
293
294    if (do_enable) {
295        for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
296            addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
297            fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
298            fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
299        }
300    } else {
301        for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
302            addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
303            fn = intc_disable_fns[_INTC_MODE(handle)];
304            fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
305        }
306    }
307}
308
309static int intc_set_wake(unsigned int irq, unsigned int on)
310{
311    return 0; /* allow wakeup, but setup hardware in intc_suspend() */
312}
313
314#ifdef CONFIG_SMP
315/*
316 * This is held with the irq desc lock held, so we don't require any
317 * additional locking here at the intc desc level. The affinity mask is
318 * later tested in the enable/disable paths.
319 */
320static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask)
321{
322    if (!cpumask_intersects(cpumask, cpu_online_mask))
323        return -1;
324
325    cpumask_copy(irq_to_desc(irq)->affinity, cpumask);
326
327    return 0;
328}
329#endif
330
331static void intc_mask_ack(unsigned int irq)
332{
333    struct intc_desc_int *d = get_intc_desc(irq);
334    unsigned long handle = ack_handle[irq];
335    unsigned long addr;
336
337    intc_disable(irq);
338
339    /* read register and write zero only to the assocaited bit */
340
341    if (handle) {
342        addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
343        switch (_INTC_FN(handle)) {
344        case REG_FN_MODIFY_BASE + 0: /* 8bit */
345            __raw_readb(addr);
346            __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
347            break;
348        case REG_FN_MODIFY_BASE + 1: /* 16bit */
349            __raw_readw(addr);
350            __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
351            break;
352        case REG_FN_MODIFY_BASE + 3: /* 32bit */
353            __raw_readl(addr);
354            __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
355            break;
356        default:
357            BUG();
358            break;
359        }
360    }
361}
362
363static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
364                         unsigned int nr_hp,
365                         unsigned int irq)
366{
367    int i;
368
369    /* this doesn't scale well, but...
370     *
371     * this function should only be used for cerain uncommon
372     * operations such as intc_set_priority() and intc_set_sense()
373     * and in those rare cases performance doesn't matter that much.
374     * keeping the memory footprint low is more important.
375     *
376     * one rather simple way to speed this up and still keep the
377     * memory footprint down is to make sure the array is sorted
378     * and then perform a bisect to lookup the irq.
379     */
380
381    for (i = 0; i < nr_hp; i++) {
382        if ((hp + i)->irq != irq)
383            continue;
384
385        return hp + i;
386    }
387
388    return NULL;
389}
390
391int intc_set_priority(unsigned int irq, unsigned int prio)
392{
393    struct intc_desc_int *d = get_intc_desc(irq);
394    struct intc_handle_int *ihp;
395
396    if (!intc_prio_level[irq] || prio <= 1)
397        return -EINVAL;
398
399    ihp = intc_find_irq(d->prio, d->nr_prio, irq);
400    if (ihp) {
401        if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
402            return -EINVAL;
403
404        intc_prio_level[irq] = prio;
405
406        /*
407         * only set secondary masking method directly
408         * primary masking method is using intc_prio_level[irq]
409         * priority level will be set during next enable()
410         */
411
412        if (_INTC_FN(ihp->handle) != REG_FN_ERR)
413            _intc_enable(irq, ihp->handle);
414    }
415    return 0;
416}
417
418#define VALID(x) (x | 0x80)
419
420static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
421    [IRQ_TYPE_EDGE_FALLING] = VALID(0),
422    [IRQ_TYPE_EDGE_RISING] = VALID(1),
423    [IRQ_TYPE_LEVEL_LOW] = VALID(2),
424    /* SH7706, SH7707 and SH7709 do not support high level triggered */
425#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
426    !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
427    !defined(CONFIG_CPU_SUBTYPE_SH7709)
428    [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
429#endif
430};
431
432static int intc_set_sense(unsigned int irq, unsigned int type)
433{
434    struct intc_desc_int *d = get_intc_desc(irq);
435    unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
436    struct intc_handle_int *ihp;
437    unsigned long addr;
438
439    if (!value)
440        return -EINVAL;
441
442    ihp = intc_find_irq(d->sense, d->nr_sense, irq);
443    if (ihp) {
444        addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
445        intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
446    }
447    return 0;
448}
449
450static unsigned int __init intc_get_reg(struct intc_desc_int *d,
451                 unsigned long address)
452{
453    unsigned int k;
454
455    for (k = 0; k < d->nr_reg; k++) {
456        if (d->reg[k] == address)
457            return k;
458    }
459
460    BUG();
461    return 0;
462}
463
464static intc_enum __init intc_grp_id(struct intc_desc *desc,
465                    intc_enum enum_id)
466{
467    struct intc_group *g = desc->hw.groups;
468    unsigned int i, j;
469
470    for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
471        g = desc->hw.groups + i;
472
473        for (j = 0; g->enum_ids[j]; j++) {
474            if (g->enum_ids[j] != enum_id)
475                continue;
476
477            return g->enum_id;
478        }
479    }
480
481    return 0;
482}
483
484static unsigned int __init _intc_mask_data(struct intc_desc *desc,
485                       struct intc_desc_int *d,
486                       intc_enum enum_id,
487                       unsigned int *reg_idx,
488                       unsigned int *fld_idx)
489{
490    struct intc_mask_reg *mr = desc->hw.mask_regs;
491    unsigned int fn, mode;
492    unsigned long reg_e, reg_d;
493
494    while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
495        mr = desc->hw.mask_regs + *reg_idx;
496
497        for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
498            if (mr->enum_ids[*fld_idx] != enum_id)
499                continue;
500
501            if (mr->set_reg && mr->clr_reg) {
502                fn = REG_FN_WRITE_BASE;
503                mode = MODE_DUAL_REG;
504                reg_e = mr->clr_reg;
505                reg_d = mr->set_reg;
506            } else {
507                fn = REG_FN_MODIFY_BASE;
508                if (mr->set_reg) {
509                    mode = MODE_ENABLE_REG;
510                    reg_e = mr->set_reg;
511                    reg_d = mr->set_reg;
512                } else {
513                    mode = MODE_MASK_REG;
514                    reg_e = mr->clr_reg;
515                    reg_d = mr->clr_reg;
516                }
517            }
518
519            fn += (mr->reg_width >> 3) - 1;
520            return _INTC_MK(fn, mode,
521                    intc_get_reg(d, reg_e),
522                    intc_get_reg(d, reg_d),
523                    1,
524                    (mr->reg_width - 1) - *fld_idx);
525        }
526
527        *fld_idx = 0;
528        (*reg_idx)++;
529    }
530
531    return 0;
532}
533
534static unsigned int __init intc_mask_data(struct intc_desc *desc,
535                      struct intc_desc_int *d,
536                      intc_enum enum_id, int do_grps)
537{
538    unsigned int i = 0;
539    unsigned int j = 0;
540    unsigned int ret;
541
542    ret = _intc_mask_data(desc, d, enum_id, &i, &j);
543    if (ret)
544        return ret;
545
546    if (do_grps)
547        return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
548
549    return 0;
550}
551
552static unsigned int __init _intc_prio_data(struct intc_desc *desc,
553                       struct intc_desc_int *d,
554                       intc_enum enum_id,
555                       unsigned int *reg_idx,
556                       unsigned int *fld_idx)
557{
558    struct intc_prio_reg *pr = desc->hw.prio_regs;
559    unsigned int fn, n, mode, bit;
560    unsigned long reg_e, reg_d;
561
562    while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
563        pr = desc->hw.prio_regs + *reg_idx;
564
565        for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
566            if (pr->enum_ids[*fld_idx] != enum_id)
567                continue;
568
569            if (pr->set_reg && pr->clr_reg) {
570                fn = REG_FN_WRITE_BASE;
571                mode = MODE_PCLR_REG;
572                reg_e = pr->set_reg;
573                reg_d = pr->clr_reg;
574            } else {
575                fn = REG_FN_MODIFY_BASE;
576                mode = MODE_PRIO_REG;
577                if (!pr->set_reg)
578                    BUG();
579                reg_e = pr->set_reg;
580                reg_d = pr->set_reg;
581            }
582
583            fn += (pr->reg_width >> 3) - 1;
584            n = *fld_idx + 1;
585
586            BUG_ON(n * pr->field_width > pr->reg_width);
587
588            bit = pr->reg_width - (n * pr->field_width);
589
590            return _INTC_MK(fn, mode,
591                    intc_get_reg(d, reg_e),
592                    intc_get_reg(d, reg_d),
593                    pr->field_width, bit);
594        }
595
596        *fld_idx = 0;
597        (*reg_idx)++;
598    }
599
600    return 0;
601}
602
603static unsigned int __init intc_prio_data(struct intc_desc *desc,
604                      struct intc_desc_int *d,
605                      intc_enum enum_id, int do_grps)
606{
607    unsigned int i = 0;
608    unsigned int j = 0;
609    unsigned int ret;
610
611    ret = _intc_prio_data(desc, d, enum_id, &i, &j);
612    if (ret)
613        return ret;
614
615    if (do_grps)
616        return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
617
618    return 0;
619}
620
621static void __init intc_enable_disable_enum(struct intc_desc *desc,
622                        struct intc_desc_int *d,
623                        intc_enum enum_id, int enable)
624{
625    unsigned int i, j, data;
626
627    /* go through and enable/disable all mask bits */
628    i = j = 0;
629    do {
630        data = _intc_mask_data(desc, d, enum_id, &i, &j);
631        if (data)
632            intc_enable_disable(d, data, enable);
633        j++;
634    } while (data);
635
636    /* go through and enable/disable all priority fields */
637    i = j = 0;
638    do {
639        data = _intc_prio_data(desc, d, enum_id, &i, &j);
640        if (data)
641            intc_enable_disable(d, data, enable);
642
643        j++;
644    } while (data);
645}
646
647static unsigned int __init intc_ack_data(struct intc_desc *desc,
648                      struct intc_desc_int *d,
649                      intc_enum enum_id)
650{
651    struct intc_mask_reg *mr = desc->hw.ack_regs;
652    unsigned int i, j, fn, mode;
653    unsigned long reg_e, reg_d;
654
655    for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
656        mr = desc->hw.ack_regs + i;
657
658        for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
659            if (mr->enum_ids[j] != enum_id)
660                continue;
661
662            fn = REG_FN_MODIFY_BASE;
663            mode = MODE_ENABLE_REG;
664            reg_e = mr->set_reg;
665            reg_d = mr->set_reg;
666
667            fn += (mr->reg_width >> 3) - 1;
668            return _INTC_MK(fn, mode,
669                    intc_get_reg(d, reg_e),
670                    intc_get_reg(d, reg_d),
671                    1,
672                    (mr->reg_width - 1) - j);
673        }
674    }
675
676    return 0;
677}
678
679static unsigned int __init intc_sense_data(struct intc_desc *desc,
680                       struct intc_desc_int *d,
681                       intc_enum enum_id)
682{
683    struct intc_sense_reg *sr = desc->hw.sense_regs;
684    unsigned int i, j, fn, bit;
685
686    for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
687        sr = desc->hw.sense_regs + i;
688
689        for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
690            if (sr->enum_ids[j] != enum_id)
691                continue;
692
693            fn = REG_FN_MODIFY_BASE;
694            fn += (sr->reg_width >> 3) - 1;
695
696            BUG_ON((j + 1) * sr->field_width > sr->reg_width);
697
698            bit = sr->reg_width - ((j + 1) * sr->field_width);
699
700            return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
701                    0, sr->field_width, bit);
702        }
703    }
704
705    return 0;
706}
707
708static void __init intc_register_irq(struct intc_desc *desc,
709                     struct intc_desc_int *d,
710                     intc_enum enum_id,
711                     unsigned int irq)
712{
713    struct intc_handle_int *hp;
714    unsigned int data[2], primary;
715
716    /*
717     * Register the IRQ position with the global IRQ map
718     */
719    set_bit(irq, intc_irq_map);
720
721    /* Prefer single interrupt source bitmap over other combinations:
722     * 1. bitmap, single interrupt source
723     * 2. priority, single interrupt source
724     * 3. bitmap, multiple interrupt sources (groups)
725     * 4. priority, multiple interrupt sources (groups)
726     */
727
728    data[0] = intc_mask_data(desc, d, enum_id, 0);
729    data[1] = intc_prio_data(desc, d, enum_id, 0);
730
731    primary = 0;
732    if (!data[0] && data[1])
733        primary = 1;
734
735    if (!data[0] && !data[1])
736        pr_warning("intc: missing unique irq mask for "
737               "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
738
739    data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
740    data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
741
742    if (!data[primary])
743        primary ^= 1;
744
745    BUG_ON(!data[primary]); /* must have primary masking method */
746
747    disable_irq_nosync(irq);
748    set_irq_chip_and_handler_name(irq, &d->chip,
749                      handle_level_irq, "level");
750    set_irq_chip_data(irq, (void *)data[primary]);
751
752    /* set priority level
753     * - this needs to be at least 2 for 5-bit priorities on 7780
754     */
755    intc_prio_level[irq] = 2;
756
757    /* enable secondary masking method if present */
758    if (data[!primary])
759        _intc_enable(irq, data[!primary]);
760
761    /* add irq to d->prio list if priority is available */
762    if (data[1]) {
763        hp = d->prio + d->nr_prio;
764        hp->irq = irq;
765        hp->handle = data[1];
766
767        if (primary) {
768            /*
769             * only secondary priority should access registers, so
770             * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
771             */
772
773            hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
774            hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
775        }
776        d->nr_prio++;
777    }
778
779    /* add irq to d->sense list if sense is available */
780    data[0] = intc_sense_data(desc, d, enum_id);
781    if (data[0]) {
782        (d->sense + d->nr_sense)->irq = irq;
783        (d->sense + d->nr_sense)->handle = data[0];
784        d->nr_sense++;
785    }
786
787    /* irq should be disabled by default */
788    d->chip.mask(irq);
789
790    if (desc->hw.ack_regs)
791        ack_handle[irq] = intc_ack_data(desc, d, enum_id);
792
793#ifdef CONFIG_ARM
794    set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
795#endif
796}
797
798static unsigned int __init save_reg(struct intc_desc_int *d,
799                    unsigned int cnt,
800                    unsigned long value,
801                    unsigned int smp)
802{
803    if (value) {
804        d->reg[cnt] = value;
805#ifdef CONFIG_SMP
806        d->smp[cnt] = smp;
807#endif
808        return 1;
809    }
810
811    return 0;
812}
813
814static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
815{
816    generic_handle_irq((unsigned int)get_irq_data(irq));
817}
818
819void __init register_intc_controller(struct intc_desc *desc)
820{
821    unsigned int i, k, smp;
822    struct intc_hw_desc *hw = &desc->hw;
823    struct intc_desc_int *d;
824
825    d = kzalloc(sizeof(*d), GFP_NOWAIT);
826
827    INIT_LIST_HEAD(&d->list);
828    list_add(&d->list, &intc_list);
829
830    d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
831    d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
832    d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
833    d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
834
835    d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
836#ifdef CONFIG_SMP
837    d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
838#endif
839    k = 0;
840
841    if (hw->mask_regs) {
842        for (i = 0; i < hw->nr_mask_regs; i++) {
843            smp = IS_SMP(hw->mask_regs[i]);
844            k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
845            k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
846        }
847    }
848
849    if (hw->prio_regs) {
850        d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
851                  GFP_NOWAIT);
852
853        for (i = 0; i < hw->nr_prio_regs; i++) {
854            smp = IS_SMP(hw->prio_regs[i]);
855            k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
856            k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
857        }
858    }
859
860    if (hw->sense_regs) {
861        d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
862                   GFP_NOWAIT);
863
864        for (i = 0; i < hw->nr_sense_regs; i++)
865            k += save_reg(d, k, hw->sense_regs[i].reg, 0);
866    }
867
868    d->chip.name = desc->name;
869    d->chip.mask = intc_disable;
870    d->chip.unmask = intc_enable;
871    d->chip.mask_ack = intc_disable;
872    d->chip.enable = intc_enable;
873    d->chip.disable = intc_disable;
874    d->chip.shutdown = intc_disable;
875    d->chip.set_type = intc_set_sense;
876    d->chip.set_wake = intc_set_wake;
877#ifdef CONFIG_SMP
878    d->chip.set_affinity = intc_set_affinity;
879#endif
880
881    if (hw->ack_regs) {
882        for (i = 0; i < hw->nr_ack_regs; i++)
883            k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
884
885        d->chip.mask_ack = intc_mask_ack;
886    }
887
888    /* disable bits matching force_disable before registering irqs */
889    if (desc->force_disable)
890        intc_enable_disable_enum(desc, d, desc->force_disable, 0);
891
892    /* disable bits matching force_enable before registering irqs */
893    if (desc->force_enable)
894        intc_enable_disable_enum(desc, d, desc->force_enable, 0);
895
896    BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
897
898    /* register the vectors one by one */
899    for (i = 0; i < hw->nr_vectors; i++) {
900        struct intc_vect *vect = hw->vectors + i;
901        unsigned int irq = evt2irq(vect->vect);
902        struct irq_desc *irq_desc;
903
904        if (!vect->enum_id)
905            continue;
906
907        irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
908        if (unlikely(!irq_desc)) {
909            pr_info("can't get irq_desc for %d\n", irq);
910            continue;
911        }
912
913        intc_register_irq(desc, d, vect->enum_id, irq);
914
915        for (k = i + 1; k < hw->nr_vectors; k++) {
916            struct intc_vect *vect2 = hw->vectors + k;
917            unsigned int irq2 = evt2irq(vect2->vect);
918
919            if (vect->enum_id != vect2->enum_id)
920                continue;
921
922            /*
923             * In the case of multi-evt handling and sparse
924             * IRQ support, each vector still needs to have
925             * its own backing irq_desc.
926             */
927            irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
928            if (unlikely(!irq_desc)) {
929                pr_info("can't get irq_desc for %d\n", irq2);
930                continue;
931            }
932
933            vect2->enum_id = 0;
934
935            /* redirect this interrupts to the first one */
936            set_irq_chip(irq2, &dummy_irq_chip);
937            set_irq_chained_handler(irq2, intc_redirect_irq);
938            set_irq_data(irq2, (void *)irq);
939        }
940    }
941
942    /* enable bits matching force_enable after registering irqs */
943    if (desc->force_enable)
944        intc_enable_disable_enum(desc, d, desc->force_enable, 1);
945}
946
947static int intc_suspend(struct sys_device *dev, pm_message_t state)
948{
949    struct intc_desc_int *d;
950    struct irq_desc *desc;
951    int irq;
952
953    /* get intc controller associated with this sysdev */
954    d = container_of(dev, struct intc_desc_int, sysdev);
955
956    switch (state.event) {
957    case PM_EVENT_ON:
958        if (d->state.event != PM_EVENT_FREEZE)
959            break;
960        for_each_irq_desc(irq, desc) {
961            if (desc->handle_irq == intc_redirect_irq)
962                continue;
963            if (desc->chip != &d->chip)
964                continue;
965            if (desc->status & IRQ_DISABLED)
966                intc_disable(irq);
967            else
968                intc_enable(irq);
969        }
970        break;
971    case PM_EVENT_FREEZE:
972        /* nothing has to be done */
973        break;
974    case PM_EVENT_SUSPEND:
975        /* enable wakeup irqs belonging to this intc controller */
976        for_each_irq_desc(irq, desc) {
977            if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
978                intc_enable(irq);
979        }
980        break;
981    }
982    d->state = state;
983
984    return 0;
985}
986
987static int intc_resume(struct sys_device *dev)
988{
989    return intc_suspend(dev, PMSG_ON);
990}
991
992static struct sysdev_class intc_sysdev_class = {
993    .name = "intc",
994    .suspend = intc_suspend,
995    .resume = intc_resume,
996};
997
998/* register this intc as sysdev to allow suspend/resume */
999static int __init register_intc_sysdevs(void)
1000{
1001    struct intc_desc_int *d;
1002    int error;
1003    int id = 0;
1004
1005    error = sysdev_class_register(&intc_sysdev_class);
1006    if (!error) {
1007        list_for_each_entry(d, &intc_list, list) {
1008            d->sysdev.id = id;
1009            d->sysdev.cls = &intc_sysdev_class;
1010            error = sysdev_register(&d->sysdev);
1011            if (error)
1012                break;
1013            id++;
1014        }
1015    }
1016
1017    if (error)
1018        pr_warning("intc: sysdev registration error\n");
1019
1020    return error;
1021}
1022device_initcall(register_intc_sysdevs);
1023
1024/*
1025 * Dynamic IRQ allocation and deallocation
1026 */
1027unsigned int create_irq_nr(unsigned int irq_want, int node)
1028{
1029    unsigned int irq = 0, new;
1030    unsigned long flags;
1031    struct irq_desc *desc;
1032
1033    spin_lock_irqsave(&vector_lock, flags);
1034
1035    /*
1036     * First try the wanted IRQ
1037     */
1038    if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
1039        new = irq_want;
1040    } else {
1041        /* .. then fall back to scanning. */
1042        new = find_first_zero_bit(intc_irq_map, nr_irqs);
1043        if (unlikely(new == nr_irqs))
1044            goto out_unlock;
1045
1046        __set_bit(new, intc_irq_map);
1047    }
1048
1049    desc = irq_to_desc_alloc_node(new, node);
1050    if (unlikely(!desc)) {
1051        pr_info("can't get irq_desc for %d\n", new);
1052        goto out_unlock;
1053    }
1054
1055    desc = move_irq_desc(desc, node);
1056    irq = new;
1057
1058out_unlock:
1059    spin_unlock_irqrestore(&vector_lock, flags);
1060
1061    if (irq > 0) {
1062        dynamic_irq_init(irq);
1063#ifdef CONFIG_ARM
1064        set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
1065#endif
1066    }
1067
1068    return irq;
1069}
1070
1071int create_irq(void)
1072{
1073    int nid = cpu_to_node(smp_processor_id());
1074    int irq;
1075
1076    irq = create_irq_nr(NR_IRQS_LEGACY, nid);
1077    if (irq == 0)
1078        irq = -1;
1079
1080    return irq;
1081}
1082
1083void destroy_irq(unsigned int irq)
1084{
1085    unsigned long flags;
1086
1087    dynamic_irq_cleanup(irq);
1088
1089    spin_lock_irqsave(&vector_lock, flags);
1090    __clear_bit(irq, intc_irq_map);
1091    spin_unlock_irqrestore(&vector_lock, flags);
1092}
1093
1094int reserve_irq_vector(unsigned int irq)
1095{
1096    unsigned long flags;
1097    int ret = 0;
1098
1099    spin_lock_irqsave(&vector_lock, flags);
1100    if (test_and_set_bit(irq, intc_irq_map))
1101        ret = -EBUSY;
1102    spin_unlock_irqrestore(&vector_lock, flags);
1103
1104    return ret;
1105}
1106
1107void reserve_irq_legacy(void)
1108{
1109    unsigned long flags;
1110    int i, j;
1111
1112    spin_lock_irqsave(&vector_lock, flags);
1113    j = find_first_bit(intc_irq_map, nr_irqs);
1114    for (i = 0; i < j; i++)
1115        __set_bit(i, intc_irq_map);
1116    spin_unlock_irqrestore(&vector_lock, flags);
1117}
1118

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