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1 | /* |
2 | * omap_uwire.c -- MicroWire interface driver for OMAP |
3 | * |
4 | * Copyright 2003 MontaVista Software Inc. <source@mvista.com> |
5 | * |
6 | * Ported to 2.6 OMAP uwire interface. |
7 | * Copyright (C) 2004 Texas Instruments. |
8 | * |
9 | * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com> |
10 | * |
11 | * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface) |
12 | * Copyright (C) 2006 Nokia |
13 | * |
14 | * Many updates by Imre Deak <imre.deak@nokia.com> |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify it |
17 | * under the terms of the GNU General Public License as published by the |
18 | * Free Software Foundation; either version 2 of the License, or (at your |
19 | * option) any later version. |
20 | * |
21 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
22 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
23 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
24 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
27 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
28 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
31 | * |
32 | * You should have received a copy of the GNU General Public License along |
33 | * with this program; if not, write to the Free Software Foundation, Inc., |
34 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
35 | */ |
36 | #include <linux/kernel.h> |
37 | #include <linux/init.h> |
38 | #include <linux/delay.h> |
39 | #include <linux/platform_device.h> |
40 | #include <linux/workqueue.h> |
41 | #include <linux/interrupt.h> |
42 | #include <linux/err.h> |
43 | #include <linux/clk.h> |
44 | #include <linux/slab.h> |
45 | |
46 | #include <linux/spi/spi.h> |
47 | #include <linux/spi/spi_bitbang.h> |
48 | |
49 | #include <asm/system.h> |
50 | #include <asm/irq.h> |
51 | #include <mach/hardware.h> |
52 | #include <asm/io.h> |
53 | #include <asm/mach-types.h> |
54 | |
55 | #include <plat/mux.h> |
56 | #include <plat/omap7xx.h> /* OMAP7XX_IO_CONF registers */ |
57 | |
58 | |
59 | /* FIXME address is now a platform device resource, |
60 | * and irqs should show there too... |
61 | */ |
62 | #define UWIRE_BASE_PHYS 0xFFFB3000 |
63 | |
64 | /* uWire Registers: */ |
65 | #define UWIRE_IO_SIZE 0x20 |
66 | #define UWIRE_TDR 0x00 |
67 | #define UWIRE_RDR 0x00 |
68 | #define UWIRE_CSR 0x01 |
69 | #define UWIRE_SR1 0x02 |
70 | #define UWIRE_SR2 0x03 |
71 | #define UWIRE_SR3 0x04 |
72 | #define UWIRE_SR4 0x05 |
73 | #define UWIRE_SR5 0x06 |
74 | |
75 | /* CSR bits */ |
76 | #define RDRB (1 << 15) |
77 | #define CSRB (1 << 14) |
78 | #define START (1 << 13) |
79 | #define CS_CMD (1 << 12) |
80 | |
81 | /* SR1 or SR2 bits */ |
82 | #define UWIRE_READ_FALLING_EDGE 0x0001 |
83 | #define UWIRE_READ_RISING_EDGE 0x0000 |
84 | #define UWIRE_WRITE_FALLING_EDGE 0x0000 |
85 | #define UWIRE_WRITE_RISING_EDGE 0x0002 |
86 | #define UWIRE_CS_ACTIVE_LOW 0x0000 |
87 | #define UWIRE_CS_ACTIVE_HIGH 0x0004 |
88 | #define UWIRE_FREQ_DIV_2 0x0000 |
89 | #define UWIRE_FREQ_DIV_4 0x0008 |
90 | #define UWIRE_FREQ_DIV_8 0x0010 |
91 | #define UWIRE_CHK_READY 0x0020 |
92 | #define UWIRE_CLK_INVERTED 0x0040 |
93 | |
94 | |
95 | struct uwire_spi { |
96 | struct spi_bitbang bitbang; |
97 | struct clk *ck; |
98 | }; |
99 | |
100 | struct uwire_state { |
101 | unsigned bits_per_word; |
102 | unsigned div1_idx; |
103 | }; |
104 | |
105 | /* REVISIT compile time constant for idx_shift? */ |
106 | /* |
107 | * Or, put it in a structure which is used throughout the driver; |
108 | * that avoids having to issue two loads for each bit of static data. |
109 | */ |
110 | static unsigned int uwire_idx_shift; |
111 | static void __iomem *uwire_base; |
112 | |
113 | static inline void uwire_write_reg(int idx, u16 val) |
114 | { |
115 | __raw_writew(val, uwire_base + (idx << uwire_idx_shift)); |
116 | } |
117 | |
118 | static inline u16 uwire_read_reg(int idx) |
119 | { |
120 | return __raw_readw(uwire_base + (idx << uwire_idx_shift)); |
121 | } |
122 | |
123 | static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags) |
124 | { |
125 | u16 w, val = 0; |
126 | int shift, reg; |
127 | |
128 | if (flags & UWIRE_CLK_INVERTED) |
129 | val ^= 0x03; |
130 | val = flags & 0x3f; |
131 | if (cs & 1) |
132 | shift = 6; |
133 | else |
134 | shift = 0; |
135 | if (cs <= 1) |
136 | reg = UWIRE_SR1; |
137 | else |
138 | reg = UWIRE_SR2; |
139 | |
140 | w = uwire_read_reg(reg); |
141 | w &= ~(0x3f << shift); |
142 | w |= val << shift; |
143 | uwire_write_reg(reg, w); |
144 | } |
145 | |
146 | static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch) |
147 | { |
148 | u16 w; |
149 | int c = 0; |
150 | unsigned long max_jiffies = jiffies + HZ; |
151 | |
152 | for (;;) { |
153 | w = uwire_read_reg(UWIRE_CSR); |
154 | if ((w & mask) == val) |
155 | break; |
156 | if (time_after(jiffies, max_jiffies)) { |
157 | printk(KERN_ERR "%s: timeout. reg=%#06x " |
158 | "mask=%#06x val=%#06x\n", |
159 | __func__, w, mask, val); |
160 | return -1; |
161 | } |
162 | c++; |
163 | if (might_not_catch && c > 64) |
164 | break; |
165 | } |
166 | return 0; |
167 | } |
168 | |
169 | static void uwire_set_clk1_div(int div1_idx) |
170 | { |
171 | u16 w; |
172 | |
173 | w = uwire_read_reg(UWIRE_SR3); |
174 | w &= ~(0x03 << 1); |
175 | w |= div1_idx << 1; |
176 | uwire_write_reg(UWIRE_SR3, w); |
177 | } |
178 | |
179 | static void uwire_chipselect(struct spi_device *spi, int value) |
180 | { |
181 | struct uwire_state *ust = spi->controller_state; |
182 | u16 w; |
183 | int old_cs; |
184 | |
185 | |
186 | BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0)); |
187 | |
188 | w = uwire_read_reg(UWIRE_CSR); |
189 | old_cs = (w >> 10) & 0x03; |
190 | if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) { |
191 | /* Deselect this CS, or the previous CS */ |
192 | w &= ~CS_CMD; |
193 | uwire_write_reg(UWIRE_CSR, w); |
194 | } |
195 | /* activate specfied chipselect */ |
196 | if (value == BITBANG_CS_ACTIVE) { |
197 | uwire_set_clk1_div(ust->div1_idx); |
198 | /* invert clock? */ |
199 | if (spi->mode & SPI_CPOL) |
200 | uwire_write_reg(UWIRE_SR4, 1); |
201 | else |
202 | uwire_write_reg(UWIRE_SR4, 0); |
203 | |
204 | w = spi->chip_select << 10; |
205 | w |= CS_CMD; |
206 | uwire_write_reg(UWIRE_CSR, w); |
207 | } |
208 | } |
209 | |
210 | static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t) |
211 | { |
212 | struct uwire_state *ust = spi->controller_state; |
213 | unsigned len = t->len; |
214 | unsigned bits = ust->bits_per_word; |
215 | unsigned bytes; |
216 | u16 val, w; |
217 | int status = 0; |
218 | |
219 | if (!t->tx_buf && !t->rx_buf) |
220 | return 0; |
221 | |
222 | /* Microwire doesn't read and write concurrently */ |
223 | if (t->tx_buf && t->rx_buf) |
224 | return -EPERM; |
225 | |
226 | w = spi->chip_select << 10; |
227 | w |= CS_CMD; |
228 | |
229 | if (t->tx_buf) { |
230 | const u8 *buf = t->tx_buf; |
231 | |
232 | /* NOTE: DMA could be used for TX transfers */ |
233 | |
234 | /* write one or two bytes at a time */ |
235 | while (len >= 1) { |
236 | /* tx bit 15 is first sent; we byteswap multibyte words |
237 | * (msb-first) on the way out from memory. |
238 | */ |
239 | val = *buf++; |
240 | if (bits > 8) { |
241 | bytes = 2; |
242 | val |= *buf++ << 8; |
243 | } else |
244 | bytes = 1; |
245 | val <<= 16 - bits; |
246 | |
247 | #ifdef VERBOSE |
248 | pr_debug("%s: write-%d =%04x\n", |
249 | dev_name(&spi->dev), bits, val); |
250 | #endif |
251 | if (wait_uwire_csr_flag(CSRB, 0, 0)) |
252 | goto eio; |
253 | |
254 | uwire_write_reg(UWIRE_TDR, val); |
255 | |
256 | /* start write */ |
257 | val = START | w | (bits << 5); |
258 | |
259 | uwire_write_reg(UWIRE_CSR, val); |
260 | len -= bytes; |
261 | |
262 | /* Wait till write actually starts. |
263 | * This is needed with MPU clock 60+ MHz. |
264 | * REVISIT: we may not have time to catch it... |
265 | */ |
266 | if (wait_uwire_csr_flag(CSRB, CSRB, 1)) |
267 | goto eio; |
268 | |
269 | status += bytes; |
270 | } |
271 | |
272 | /* REVISIT: save this for later to get more i/o overlap */ |
273 | if (wait_uwire_csr_flag(CSRB, 0, 0)) |
274 | goto eio; |
275 | |
276 | } else if (t->rx_buf) { |
277 | u8 *buf = t->rx_buf; |
278 | |
279 | /* read one or two bytes at a time */ |
280 | while (len) { |
281 | if (bits > 8) { |
282 | bytes = 2; |
283 | } else |
284 | bytes = 1; |
285 | |
286 | /* start read */ |
287 | val = START | w | (bits << 0); |
288 | uwire_write_reg(UWIRE_CSR, val); |
289 | len -= bytes; |
290 | |
291 | /* Wait till read actually starts */ |
292 | (void) wait_uwire_csr_flag(CSRB, CSRB, 1); |
293 | |
294 | if (wait_uwire_csr_flag(RDRB | CSRB, |
295 | RDRB, 0)) |
296 | goto eio; |
297 | |
298 | /* rx bit 0 is last received; multibyte words will |
299 | * be properly byteswapped on the way to memory. |
300 | */ |
301 | val = uwire_read_reg(UWIRE_RDR); |
302 | val &= (1 << bits) - 1; |
303 | *buf++ = (u8) val; |
304 | if (bytes == 2) |
305 | *buf++ = val >> 8; |
306 | status += bytes; |
307 | #ifdef VERBOSE |
308 | pr_debug("%s: read-%d =%04x\n", |
309 | dev_name(&spi->dev), bits, val); |
310 | #endif |
311 | |
312 | } |
313 | } |
314 | return status; |
315 | eio: |
316 | return -EIO; |
317 | } |
318 | |
319 | static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
320 | { |
321 | struct uwire_state *ust = spi->controller_state; |
322 | struct uwire_spi *uwire; |
323 | unsigned flags = 0; |
324 | unsigned bits; |
325 | unsigned hz; |
326 | unsigned long rate; |
327 | int div1_idx; |
328 | int div1; |
329 | int div2; |
330 | int status; |
331 | |
332 | uwire = spi_master_get_devdata(spi->master); |
333 | |
334 | if (spi->chip_select > 3) { |
335 | pr_debug("%s: cs%d?\n", dev_name(&spi->dev), spi->chip_select); |
336 | status = -ENODEV; |
337 | goto done; |
338 | } |
339 | |
340 | bits = spi->bits_per_word; |
341 | if (t != NULL && t->bits_per_word) |
342 | bits = t->bits_per_word; |
343 | |
344 | if (bits > 16) { |
345 | pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits); |
346 | status = -ENODEV; |
347 | goto done; |
348 | } |
349 | ust->bits_per_word = bits; |
350 | |
351 | /* mode 0..3, clock inverted separately; |
352 | * standard nCS signaling; |
353 | * don't treat DI=high as "not ready" |
354 | */ |
355 | if (spi->mode & SPI_CS_HIGH) |
356 | flags |= UWIRE_CS_ACTIVE_HIGH; |
357 | |
358 | if (spi->mode & SPI_CPOL) |
359 | flags |= UWIRE_CLK_INVERTED; |
360 | |
361 | switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { |
362 | case SPI_MODE_0: |
363 | case SPI_MODE_3: |
364 | flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE; |
365 | break; |
366 | case SPI_MODE_1: |
367 | case SPI_MODE_2: |
368 | flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE; |
369 | break; |
370 | } |
371 | |
372 | /* assume it's already enabled */ |
373 | rate = clk_get_rate(uwire->ck); |
374 | |
375 | hz = spi->max_speed_hz; |
376 | if (t != NULL && t->speed_hz) |
377 | hz = t->speed_hz; |
378 | |
379 | if (!hz) { |
380 | pr_debug("%s: zero speed?\n", dev_name(&spi->dev)); |
381 | status = -EINVAL; |
382 | goto done; |
383 | } |
384 | |
385 | /* F_INT = mpu_xor_clk / DIV1 */ |
386 | for (div1_idx = 0; div1_idx < 4; div1_idx++) { |
387 | switch (div1_idx) { |
388 | case 0: |
389 | div1 = 2; |
390 | break; |
391 | case 1: |
392 | div1 = 4; |
393 | break; |
394 | case 2: |
395 | div1 = 7; |
396 | break; |
397 | default: |
398 | case 3: |
399 | div1 = 10; |
400 | break; |
401 | } |
402 | div2 = (rate / div1 + hz - 1) / hz; |
403 | if (div2 <= 8) |
404 | break; |
405 | } |
406 | if (div1_idx == 4) { |
407 | pr_debug("%s: lowest clock %ld, need %d\n", |
408 | dev_name(&spi->dev), rate / 10 / 8, hz); |
409 | status = -EDOM; |
410 | goto done; |
411 | } |
412 | |
413 | /* we have to cache this and reset in uwire_chipselect as this is a |
414 | * global parameter and another uwire device can change it under |
415 | * us */ |
416 | ust->div1_idx = div1_idx; |
417 | uwire_set_clk1_div(div1_idx); |
418 | |
419 | rate /= div1; |
420 | |
421 | switch (div2) { |
422 | case 0: |
423 | case 1: |
424 | case 2: |
425 | flags |= UWIRE_FREQ_DIV_2; |
426 | rate /= 2; |
427 | break; |
428 | case 3: |
429 | case 4: |
430 | flags |= UWIRE_FREQ_DIV_4; |
431 | rate /= 4; |
432 | break; |
433 | case 5: |
434 | case 6: |
435 | case 7: |
436 | case 8: |
437 | flags |= UWIRE_FREQ_DIV_8; |
438 | rate /= 8; |
439 | break; |
440 | } |
441 | omap_uwire_configure_mode(spi->chip_select, flags); |
442 | pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n", |
443 | __func__, flags, |
444 | clk_get_rate(uwire->ck) / 1000, |
445 | rate / 1000); |
446 | status = 0; |
447 | done: |
448 | return status; |
449 | } |
450 | |
451 | static int uwire_setup(struct spi_device *spi) |
452 | { |
453 | struct uwire_state *ust = spi->controller_state; |
454 | |
455 | if (ust == NULL) { |
456 | ust = kzalloc(sizeof(*ust), GFP_KERNEL); |
457 | if (ust == NULL) |
458 | return -ENOMEM; |
459 | spi->controller_state = ust; |
460 | } |
461 | |
462 | return uwire_setup_transfer(spi, NULL); |
463 | } |
464 | |
465 | static void uwire_cleanup(struct spi_device *spi) |
466 | { |
467 | kfree(spi->controller_state); |
468 | } |
469 | |
470 | static void uwire_off(struct uwire_spi *uwire) |
471 | { |
472 | uwire_write_reg(UWIRE_SR3, 0); |
473 | clk_disable(uwire->ck); |
474 | clk_put(uwire->ck); |
475 | spi_master_put(uwire->bitbang.master); |
476 | } |
477 | |
478 | static int __init uwire_probe(struct platform_device *pdev) |
479 | { |
480 | struct spi_master *master; |
481 | struct uwire_spi *uwire; |
482 | int status; |
483 | |
484 | master = spi_alloc_master(&pdev->dev, sizeof *uwire); |
485 | if (!master) |
486 | return -ENODEV; |
487 | |
488 | uwire = spi_master_get_devdata(master); |
489 | |
490 | uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE); |
491 | if (!uwire_base) { |
492 | dev_dbg(&pdev->dev, "can't ioremap UWIRE\n"); |
493 | spi_master_put(master); |
494 | return -ENOMEM; |
495 | } |
496 | |
497 | dev_set_drvdata(&pdev->dev, uwire); |
498 | |
499 | uwire->ck = clk_get(&pdev->dev, "fck"); |
500 | if (IS_ERR(uwire->ck)) { |
501 | status = PTR_ERR(uwire->ck); |
502 | dev_dbg(&pdev->dev, "no functional clock?\n"); |
503 | spi_master_put(master); |
504 | return status; |
505 | } |
506 | clk_enable(uwire->ck); |
507 | |
508 | if (cpu_is_omap7xx()) |
509 | uwire_idx_shift = 1; |
510 | else |
511 | uwire_idx_shift = 2; |
512 | |
513 | uwire_write_reg(UWIRE_SR3, 1); |
514 | |
515 | /* the spi->mode bits understood by this driver: */ |
516 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
517 | |
518 | master->flags = SPI_MASTER_HALF_DUPLEX; |
519 | |
520 | master->bus_num = 2; /* "official" */ |
521 | master->num_chipselect = 4; |
522 | master->setup = uwire_setup; |
523 | master->cleanup = uwire_cleanup; |
524 | |
525 | uwire->bitbang.master = master; |
526 | uwire->bitbang.chipselect = uwire_chipselect; |
527 | uwire->bitbang.setup_transfer = uwire_setup_transfer; |
528 | uwire->bitbang.txrx_bufs = uwire_txrx; |
529 | |
530 | status = spi_bitbang_start(&uwire->bitbang); |
531 | if (status < 0) { |
532 | uwire_off(uwire); |
533 | iounmap(uwire_base); |
534 | } |
535 | return status; |
536 | } |
537 | |
538 | static int __exit uwire_remove(struct platform_device *pdev) |
539 | { |
540 | struct uwire_spi *uwire = dev_get_drvdata(&pdev->dev); |
541 | int status; |
542 | |
543 | // FIXME remove all child devices, somewhere ... |
544 | |
545 | status = spi_bitbang_stop(&uwire->bitbang); |
546 | uwire_off(uwire); |
547 | iounmap(uwire_base); |
548 | return status; |
549 | } |
550 | |
551 | /* work with hotplug and coldplug */ |
552 | MODULE_ALIAS("platform:omap_uwire"); |
553 | |
554 | static struct platform_driver uwire_driver = { |
555 | .driver = { |
556 | .name = "omap_uwire", |
557 | .owner = THIS_MODULE, |
558 | }, |
559 | .remove = __exit_p(uwire_remove), |
560 | // suspend ... unuse ck |
561 | // resume ... use ck |
562 | }; |
563 | |
564 | static int __init omap_uwire_init(void) |
565 | { |
566 | /* FIXME move these into the relevant board init code. also, include |
567 | * H3 support; it uses tsc2101 like H2 (on a different chipselect). |
568 | */ |
569 | |
570 | if (machine_is_omap_h2()) { |
571 | /* defaults: W21 SDO, U18 SDI, V19 SCL */ |
572 | omap_cfg_reg(N14_1610_UWIRE_CS0); |
573 | omap_cfg_reg(N15_1610_UWIRE_CS1); |
574 | } |
575 | if (machine_is_omap_perseus2()) { |
576 | /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */ |
577 | int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000; |
578 | omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9); |
579 | } |
580 | |
581 | return platform_driver_probe(&uwire_driver, uwire_probe); |
582 | } |
583 | |
584 | static void __exit omap_uwire_exit(void) |
585 | { |
586 | platform_driver_unregister(&uwire_driver); |
587 | } |
588 | |
589 | subsys_initcall(omap_uwire_init); |
590 | module_exit(omap_uwire_exit); |
591 | |
592 | MODULE_LICENSE("GPL"); |
593 | |
594 |
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