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1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
3 | * Copyright (C) 2008 Juergen Beisert |
4 | * |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License |
7 | * as published by the Free Software Foundation; either version 2 |
8 | * of the License, or (at your option) any later version. |
9 | * This program is distributed in the hope that it will be useful, |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
12 | * GNU General Public License for more details. |
13 | * |
14 | * You should have received a copy of the GNU General Public License |
15 | * along with this program; if not, write to the |
16 | * Free Software Foundation |
17 | * 51 Franklin Street, Fifth Floor |
18 | * Boston, MA 02110-1301, USA. |
19 | */ |
20 | |
21 | #include <linux/clk.h> |
22 | #include <linux/completion.h> |
23 | #include <linux/delay.h> |
24 | #include <linux/err.h> |
25 | #include <linux/gpio.h> |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> |
28 | #include <linux/io.h> |
29 | #include <linux/irq.h> |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> |
32 | #include <linux/platform_device.h> |
33 | #include <linux/slab.h> |
34 | #include <linux/spi/spi.h> |
35 | #include <linux/spi/spi_bitbang.h> |
36 | #include <linux/types.h> |
37 | |
38 | #include <mach/spi.h> |
39 | |
40 | #define DRIVER_NAME "spi_imx" |
41 | |
42 | #define MXC_CSPIRXDATA 0x00 |
43 | #define MXC_CSPITXDATA 0x04 |
44 | #define MXC_CSPICTRL 0x08 |
45 | #define MXC_CSPIINT 0x0c |
46 | #define MXC_RESET 0x1c |
47 | |
48 | #define MX3_CSPISTAT 0x14 |
49 | #define MX3_CSPISTAT_RR (1 << 3) |
50 | |
51 | /* generic defines to abstract from the different register layouts */ |
52 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ |
53 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ |
54 | |
55 | struct spi_imx_config { |
56 | unsigned int speed_hz; |
57 | unsigned int bpw; |
58 | unsigned int mode; |
59 | int cs; |
60 | }; |
61 | |
62 | struct spi_imx_data { |
63 | struct spi_bitbang bitbang; |
64 | |
65 | struct completion xfer_done; |
66 | void *base; |
67 | int irq; |
68 | struct clk *clk; |
69 | unsigned long spi_clk; |
70 | int *chipselect; |
71 | |
72 | unsigned int count; |
73 | void (*tx)(struct spi_imx_data *); |
74 | void (*rx)(struct spi_imx_data *); |
75 | void *rx_buf; |
76 | const void *tx_buf; |
77 | unsigned int txfifo; /* number of words pushed in tx FIFO */ |
78 | |
79 | /* SoC specific functions */ |
80 | void (*intctrl)(struct spi_imx_data *, int); |
81 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); |
82 | void (*trigger)(struct spi_imx_data *); |
83 | int (*rx_available)(struct spi_imx_data *); |
84 | }; |
85 | |
86 | #define MXC_SPI_BUF_RX(type) \ |
87 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
88 | { \ |
89 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
90 | \ |
91 | if (spi_imx->rx_buf) { \ |
92 | *(type *)spi_imx->rx_buf = val; \ |
93 | spi_imx->rx_buf += sizeof(type); \ |
94 | } \ |
95 | } |
96 | |
97 | #define MXC_SPI_BUF_TX(type) \ |
98 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
99 | { \ |
100 | type val = 0; \ |
101 | \ |
102 | if (spi_imx->tx_buf) { \ |
103 | val = *(type *)spi_imx->tx_buf; \ |
104 | spi_imx->tx_buf += sizeof(type); \ |
105 | } \ |
106 | \ |
107 | spi_imx->count -= sizeof(type); \ |
108 | \ |
109 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
110 | } |
111 | |
112 | MXC_SPI_BUF_RX(u8) |
113 | MXC_SPI_BUF_TX(u8) |
114 | MXC_SPI_BUF_RX(u16) |
115 | MXC_SPI_BUF_TX(u16) |
116 | MXC_SPI_BUF_RX(u32) |
117 | MXC_SPI_BUF_TX(u32) |
118 | |
119 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set |
120 | * (which is currently not the case in this driver) |
121 | */ |
122 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, |
123 | 256, 384, 512, 768, 1024}; |
124 | |
125 | /* MX21, MX27 */ |
126 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
127 | unsigned int fspi) |
128 | { |
129 | int i, max; |
130 | |
131 | if (cpu_is_mx21()) |
132 | max = 18; |
133 | else |
134 | max = 16; |
135 | |
136 | for (i = 2; i < max; i++) |
137 | if (fspi * mxc_clkdivs[i] >= fin) |
138 | return i; |
139 | |
140 | return max; |
141 | } |
142 | |
143 | /* MX1, MX31, MX35 */ |
144 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
145 | unsigned int fspi) |
146 | { |
147 | int i, div = 4; |
148 | |
149 | for (i = 0; i < 7; i++) { |
150 | if (fspi * div >= fin) |
151 | return i; |
152 | div <<= 1; |
153 | } |
154 | |
155 | return 7; |
156 | } |
157 | |
158 | #define MX31_INTREG_TEEN (1 << 0) |
159 | #define MX31_INTREG_RREN (1 << 3) |
160 | |
161 | #define MX31_CSPICTRL_ENABLE (1 << 0) |
162 | #define MX31_CSPICTRL_MASTER (1 << 1) |
163 | #define MX31_CSPICTRL_XCH (1 << 2) |
164 | #define MX31_CSPICTRL_POL (1 << 4) |
165 | #define MX31_CSPICTRL_PHA (1 << 5) |
166 | #define MX31_CSPICTRL_SSCTL (1 << 6) |
167 | #define MX31_CSPICTRL_SSPOL (1 << 7) |
168 | #define MX31_CSPICTRL_BC_SHIFT 8 |
169 | #define MX35_CSPICTRL_BL_SHIFT 20 |
170 | #define MX31_CSPICTRL_CS_SHIFT 24 |
171 | #define MX35_CSPICTRL_CS_SHIFT 12 |
172 | #define MX31_CSPICTRL_DR_SHIFT 16 |
173 | |
174 | #define MX31_CSPISTATUS 0x14 |
175 | #define MX31_STATUS_RR (1 << 3) |
176 | |
177 | /* These functions also work for the i.MX35, but be aware that |
178 | * the i.MX35 has a slightly different register layout for bits |
179 | * we do not use here. |
180 | */ |
181 | static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
182 | { |
183 | unsigned int val = 0; |
184 | |
185 | if (enable & MXC_INT_TE) |
186 | val |= MX31_INTREG_TEEN; |
187 | if (enable & MXC_INT_RR) |
188 | val |= MX31_INTREG_RREN; |
189 | |
190 | writel(val, spi_imx->base + MXC_CSPIINT); |
191 | } |
192 | |
193 | static void mx31_trigger(struct spi_imx_data *spi_imx) |
194 | { |
195 | unsigned int reg; |
196 | |
197 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
198 | reg |= MX31_CSPICTRL_XCH; |
199 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
200 | } |
201 | |
202 | static int mx31_config(struct spi_imx_data *spi_imx, |
203 | struct spi_imx_config *config) |
204 | { |
205 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; |
206 | |
207 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
208 | MX31_CSPICTRL_DR_SHIFT; |
209 | |
210 | if (cpu_is_mx31()) |
211 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; |
212 | else if (cpu_is_mx25() || cpu_is_mx35()) { |
213 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; |
214 | reg |= MX31_CSPICTRL_SSCTL; |
215 | } |
216 | |
217 | if (config->mode & SPI_CPHA) |
218 | reg |= MX31_CSPICTRL_PHA; |
219 | if (config->mode & SPI_CPOL) |
220 | reg |= MX31_CSPICTRL_POL; |
221 | if (config->mode & SPI_CS_HIGH) |
222 | reg |= MX31_CSPICTRL_SSPOL; |
223 | if (config->cs < 0) { |
224 | if (cpu_is_mx31()) |
225 | reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT; |
226 | else if (cpu_is_mx25() || cpu_is_mx35()) |
227 | reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; |
228 | } |
229 | |
230 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
231 | |
232 | return 0; |
233 | } |
234 | |
235 | static int mx31_rx_available(struct spi_imx_data *spi_imx) |
236 | { |
237 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
238 | } |
239 | |
240 | #define MX27_INTREG_RR (1 << 4) |
241 | #define MX27_INTREG_TEEN (1 << 9) |
242 | #define MX27_INTREG_RREN (1 << 13) |
243 | |
244 | #define MX27_CSPICTRL_POL (1 << 5) |
245 | #define MX27_CSPICTRL_PHA (1 << 6) |
246 | #define MX27_CSPICTRL_SSPOL (1 << 8) |
247 | #define MX27_CSPICTRL_XCH (1 << 9) |
248 | #define MX27_CSPICTRL_ENABLE (1 << 10) |
249 | #define MX27_CSPICTRL_MASTER (1 << 11) |
250 | #define MX27_CSPICTRL_DR_SHIFT 14 |
251 | #define MX27_CSPICTRL_CS_SHIFT 19 |
252 | |
253 | static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) |
254 | { |
255 | unsigned int val = 0; |
256 | |
257 | if (enable & MXC_INT_TE) |
258 | val |= MX27_INTREG_TEEN; |
259 | if (enable & MXC_INT_RR) |
260 | val |= MX27_INTREG_RREN; |
261 | |
262 | writel(val, spi_imx->base + MXC_CSPIINT); |
263 | } |
264 | |
265 | static void mx27_trigger(struct spi_imx_data *spi_imx) |
266 | { |
267 | unsigned int reg; |
268 | |
269 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
270 | reg |= MX27_CSPICTRL_XCH; |
271 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
272 | } |
273 | |
274 | static int mx27_config(struct spi_imx_data *spi_imx, |
275 | struct spi_imx_config *config) |
276 | { |
277 | unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; |
278 | |
279 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << |
280 | MX27_CSPICTRL_DR_SHIFT; |
281 | reg |= config->bpw - 1; |
282 | |
283 | if (config->mode & SPI_CPHA) |
284 | reg |= MX27_CSPICTRL_PHA; |
285 | if (config->mode & SPI_CPOL) |
286 | reg |= MX27_CSPICTRL_POL; |
287 | if (config->mode & SPI_CS_HIGH) |
288 | reg |= MX27_CSPICTRL_SSPOL; |
289 | if (config->cs < 0) |
290 | reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; |
291 | |
292 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
293 | |
294 | return 0; |
295 | } |
296 | |
297 | static int mx27_rx_available(struct spi_imx_data *spi_imx) |
298 | { |
299 | return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; |
300 | } |
301 | |
302 | #define MX1_INTREG_RR (1 << 3) |
303 | #define MX1_INTREG_TEEN (1 << 8) |
304 | #define MX1_INTREG_RREN (1 << 11) |
305 | |
306 | #define MX1_CSPICTRL_POL (1 << 4) |
307 | #define MX1_CSPICTRL_PHA (1 << 5) |
308 | #define MX1_CSPICTRL_XCH (1 << 8) |
309 | #define MX1_CSPICTRL_ENABLE (1 << 9) |
310 | #define MX1_CSPICTRL_MASTER (1 << 10) |
311 | #define MX1_CSPICTRL_DR_SHIFT 13 |
312 | |
313 | static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
314 | { |
315 | unsigned int val = 0; |
316 | |
317 | if (enable & MXC_INT_TE) |
318 | val |= MX1_INTREG_TEEN; |
319 | if (enable & MXC_INT_RR) |
320 | val |= MX1_INTREG_RREN; |
321 | |
322 | writel(val, spi_imx->base + MXC_CSPIINT); |
323 | } |
324 | |
325 | static void mx1_trigger(struct spi_imx_data *spi_imx) |
326 | { |
327 | unsigned int reg; |
328 | |
329 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
330 | reg |= MX1_CSPICTRL_XCH; |
331 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
332 | } |
333 | |
334 | static int mx1_config(struct spi_imx_data *spi_imx, |
335 | struct spi_imx_config *config) |
336 | { |
337 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; |
338 | |
339 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
340 | MX1_CSPICTRL_DR_SHIFT; |
341 | reg |= config->bpw - 1; |
342 | |
343 | if (config->mode & SPI_CPHA) |
344 | reg |= MX1_CSPICTRL_PHA; |
345 | if (config->mode & SPI_CPOL) |
346 | reg |= MX1_CSPICTRL_POL; |
347 | |
348 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
349 | |
350 | return 0; |
351 | } |
352 | |
353 | static int mx1_rx_available(struct spi_imx_data *spi_imx) |
354 | { |
355 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
356 | } |
357 | |
358 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
359 | { |
360 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
361 | int gpio = spi_imx->chipselect[spi->chip_select]; |
362 | int active = is_active != BITBANG_CS_INACTIVE; |
363 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); |
364 | |
365 | if (gpio < 0) |
366 | return; |
367 | |
368 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
369 | } |
370 | |
371 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
372 | { |
373 | while (spi_imx->txfifo < 8) { |
374 | if (!spi_imx->count) |
375 | break; |
376 | spi_imx->tx(spi_imx); |
377 | spi_imx->txfifo++; |
378 | } |
379 | |
380 | spi_imx->trigger(spi_imx); |
381 | } |
382 | |
383 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
384 | { |
385 | struct spi_imx_data *spi_imx = dev_id; |
386 | |
387 | while (spi_imx->rx_available(spi_imx)) { |
388 | spi_imx->rx(spi_imx); |
389 | spi_imx->txfifo--; |
390 | } |
391 | |
392 | if (spi_imx->count) { |
393 | spi_imx_push(spi_imx); |
394 | return IRQ_HANDLED; |
395 | } |
396 | |
397 | if (spi_imx->txfifo) { |
398 | /* No data left to push, but still waiting for rx data, |
399 | * enable receive data available interrupt. |
400 | */ |
401 | spi_imx->intctrl(spi_imx, MXC_INT_RR); |
402 | return IRQ_HANDLED; |
403 | } |
404 | |
405 | spi_imx->intctrl(spi_imx, 0); |
406 | complete(&spi_imx->xfer_done); |
407 | |
408 | return IRQ_HANDLED; |
409 | } |
410 | |
411 | static int spi_imx_setupxfer(struct spi_device *spi, |
412 | struct spi_transfer *t) |
413 | { |
414 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
415 | struct spi_imx_config config; |
416 | |
417 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; |
418 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; |
419 | config.mode = spi->mode; |
420 | config.cs = spi_imx->chipselect[spi->chip_select]; |
421 | |
422 | if (!config.speed_hz) |
423 | config.speed_hz = spi->max_speed_hz; |
424 | if (!config.bpw) |
425 | config.bpw = spi->bits_per_word; |
426 | if (!config.speed_hz) |
427 | config.speed_hz = spi->max_speed_hz; |
428 | |
429 | /* Initialize the functions for transfer */ |
430 | if (config.bpw <= 8) { |
431 | spi_imx->rx = spi_imx_buf_rx_u8; |
432 | spi_imx->tx = spi_imx_buf_tx_u8; |
433 | } else if (config.bpw <= 16) { |
434 | spi_imx->rx = spi_imx_buf_rx_u16; |
435 | spi_imx->tx = spi_imx_buf_tx_u16; |
436 | } else if (config.bpw <= 32) { |
437 | spi_imx->rx = spi_imx_buf_rx_u32; |
438 | spi_imx->tx = spi_imx_buf_tx_u32; |
439 | } else |
440 | BUG(); |
441 | |
442 | spi_imx->config(spi_imx, &config); |
443 | |
444 | return 0; |
445 | } |
446 | |
447 | static int spi_imx_transfer(struct spi_device *spi, |
448 | struct spi_transfer *transfer) |
449 | { |
450 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
451 | |
452 | spi_imx->tx_buf = transfer->tx_buf; |
453 | spi_imx->rx_buf = transfer->rx_buf; |
454 | spi_imx->count = transfer->len; |
455 | spi_imx->txfifo = 0; |
456 | |
457 | init_completion(&spi_imx->xfer_done); |
458 | |
459 | spi_imx_push(spi_imx); |
460 | |
461 | spi_imx->intctrl(spi_imx, MXC_INT_TE); |
462 | |
463 | wait_for_completion(&spi_imx->xfer_done); |
464 | |
465 | return transfer->len; |
466 | } |
467 | |
468 | static int spi_imx_setup(struct spi_device *spi) |
469 | { |
470 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
471 | int gpio = spi_imx->chipselect[spi->chip_select]; |
472 | |
473 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
474 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
475 | |
476 | if (gpio >= 0) |
477 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); |
478 | |
479 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
480 | |
481 | return 0; |
482 | } |
483 | |
484 | static void spi_imx_cleanup(struct spi_device *spi) |
485 | { |
486 | } |
487 | |
488 | static int __devinit spi_imx_probe(struct platform_device *pdev) |
489 | { |
490 | struct spi_imx_master *mxc_platform_info; |
491 | struct spi_master *master; |
492 | struct spi_imx_data *spi_imx; |
493 | struct resource *res; |
494 | int i, ret; |
495 | |
496 | mxc_platform_info = dev_get_platdata(&pdev->dev); |
497 | if (!mxc_platform_info) { |
498 | dev_err(&pdev->dev, "can't get the platform data\n"); |
499 | return -EINVAL; |
500 | } |
501 | |
502 | master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); |
503 | if (!master) |
504 | return -ENOMEM; |
505 | |
506 | platform_set_drvdata(pdev, master); |
507 | |
508 | master->bus_num = pdev->id; |
509 | master->num_chipselect = mxc_platform_info->num_chipselect; |
510 | |
511 | spi_imx = spi_master_get_devdata(master); |
512 | spi_imx->bitbang.master = spi_master_get(master); |
513 | spi_imx->chipselect = mxc_platform_info->chipselect; |
514 | |
515 | for (i = 0; i < master->num_chipselect; i++) { |
516 | if (spi_imx->chipselect[i] < 0) |
517 | continue; |
518 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); |
519 | if (ret) { |
520 | while (i > 0) { |
521 | i--; |
522 | if (spi_imx->chipselect[i] >= 0) |
523 | gpio_free(spi_imx->chipselect[i]); |
524 | } |
525 | dev_err(&pdev->dev, "can't get cs gpios\n"); |
526 | goto out_master_put; |
527 | } |
528 | } |
529 | |
530 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
531 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; |
532 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; |
533 | spi_imx->bitbang.master->setup = spi_imx_setup; |
534 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; |
535 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
536 | |
537 | init_completion(&spi_imx->xfer_done); |
538 | |
539 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
540 | if (!res) { |
541 | dev_err(&pdev->dev, "can't get platform resource\n"); |
542 | ret = -ENOMEM; |
543 | goto out_gpio_free; |
544 | } |
545 | |
546 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { |
547 | dev_err(&pdev->dev, "request_mem_region failed\n"); |
548 | ret = -EBUSY; |
549 | goto out_gpio_free; |
550 | } |
551 | |
552 | spi_imx->base = ioremap(res->start, resource_size(res)); |
553 | if (!spi_imx->base) { |
554 | ret = -EINVAL; |
555 | goto out_release_mem; |
556 | } |
557 | |
558 | spi_imx->irq = platform_get_irq(pdev, 0); |
559 | if (spi_imx->irq <= 0) { |
560 | ret = -EINVAL; |
561 | goto out_iounmap; |
562 | } |
563 | |
564 | ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); |
565 | if (ret) { |
566 | dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); |
567 | goto out_iounmap; |
568 | } |
569 | |
570 | if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) { |
571 | spi_imx->intctrl = mx31_intctrl; |
572 | spi_imx->config = mx31_config; |
573 | spi_imx->trigger = mx31_trigger; |
574 | spi_imx->rx_available = mx31_rx_available; |
575 | } else if (cpu_is_mx27() || cpu_is_mx21()) { |
576 | spi_imx->intctrl = mx27_intctrl; |
577 | spi_imx->config = mx27_config; |
578 | spi_imx->trigger = mx27_trigger; |
579 | spi_imx->rx_available = mx27_rx_available; |
580 | } else if (cpu_is_mx1()) { |
581 | spi_imx->intctrl = mx1_intctrl; |
582 | spi_imx->config = mx1_config; |
583 | spi_imx->trigger = mx1_trigger; |
584 | spi_imx->rx_available = mx1_rx_available; |
585 | } else |
586 | BUG(); |
587 | |
588 | spi_imx->clk = clk_get(&pdev->dev, NULL); |
589 | if (IS_ERR(spi_imx->clk)) { |
590 | dev_err(&pdev->dev, "unable to get clock\n"); |
591 | ret = PTR_ERR(spi_imx->clk); |
592 | goto out_free_irq; |
593 | } |
594 | |
595 | clk_enable(spi_imx->clk); |
596 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk); |
597 | |
598 | if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) |
599 | writel(1, spi_imx->base + MXC_RESET); |
600 | |
601 | /* drain receive buffer */ |
602 | if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) |
603 | while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR) |
604 | readl(spi_imx->base + MXC_CSPIRXDATA); |
605 | |
606 | spi_imx->intctrl(spi_imx, 0); |
607 | |
608 | ret = spi_bitbang_start(&spi_imx->bitbang); |
609 | if (ret) { |
610 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); |
611 | goto out_clk_put; |
612 | } |
613 | |
614 | dev_info(&pdev->dev, "probed\n"); |
615 | |
616 | return ret; |
617 | |
618 | out_clk_put: |
619 | clk_disable(spi_imx->clk); |
620 | clk_put(spi_imx->clk); |
621 | out_free_irq: |
622 | free_irq(spi_imx->irq, spi_imx); |
623 | out_iounmap: |
624 | iounmap(spi_imx->base); |
625 | out_release_mem: |
626 | release_mem_region(res->start, resource_size(res)); |
627 | out_gpio_free: |
628 | for (i = 0; i < master->num_chipselect; i++) |
629 | if (spi_imx->chipselect[i] >= 0) |
630 | gpio_free(spi_imx->chipselect[i]); |
631 | out_master_put: |
632 | spi_master_put(master); |
633 | kfree(master); |
634 | platform_set_drvdata(pdev, NULL); |
635 | return ret; |
636 | } |
637 | |
638 | static int __devexit spi_imx_remove(struct platform_device *pdev) |
639 | { |
640 | struct spi_master *master = platform_get_drvdata(pdev); |
641 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
642 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
643 | int i; |
644 | |
645 | spi_bitbang_stop(&spi_imx->bitbang); |
646 | |
647 | writel(0, spi_imx->base + MXC_CSPICTRL); |
648 | clk_disable(spi_imx->clk); |
649 | clk_put(spi_imx->clk); |
650 | free_irq(spi_imx->irq, spi_imx); |
651 | iounmap(spi_imx->base); |
652 | |
653 | for (i = 0; i < master->num_chipselect; i++) |
654 | if (spi_imx->chipselect[i] >= 0) |
655 | gpio_free(spi_imx->chipselect[i]); |
656 | |
657 | spi_master_put(master); |
658 | |
659 | release_mem_region(res->start, resource_size(res)); |
660 | |
661 | platform_set_drvdata(pdev, NULL); |
662 | |
663 | return 0; |
664 | } |
665 | |
666 | static struct platform_driver spi_imx_driver = { |
667 | .driver = { |
668 | .name = DRIVER_NAME, |
669 | .owner = THIS_MODULE, |
670 | }, |
671 | .probe = spi_imx_probe, |
672 | .remove = __devexit_p(spi_imx_remove), |
673 | }; |
674 | |
675 | static int __init spi_imx_init(void) |
676 | { |
677 | return platform_driver_register(&spi_imx_driver); |
678 | } |
679 | |
680 | static void __exit spi_imx_exit(void) |
681 | { |
682 | platform_driver_unregister(&spi_imx_driver); |
683 | } |
684 | |
685 | module_init(spi_imx_init); |
686 | module_exit(spi_imx_exit); |
687 | |
688 | MODULE_DESCRIPTION("SPI Master Controller driver"); |
689 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
690 | MODULE_LICENSE("GPL"); |
691 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9