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1 | /* |
2 | * arch/arm/mach-at91/at91cap9_devices.c |
3 | * |
4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> |
5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> |
6 | * Copyright (C) 2007 Atmel Corporation. |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; either version 2 of the License, or |
11 | * (at your option) any later version. |
12 | * |
13 | */ |
14 | #include <asm/mach/arch.h> |
15 | #include <asm/mach/map.h> |
16 | #include <asm/mach/irq.h> |
17 | |
18 | #include <linux/dma-mapping.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/i2c-gpio.h> |
21 | |
22 | #include <video/atmel_lcdc.h> |
23 | |
24 | #include <mach/board.h> |
25 | #include <mach/cpu.h> |
26 | #include <mach/gpio.h> |
27 | #include <mach/at91cap9.h> |
28 | #include <mach/at91cap9_matrix.h> |
29 | #include <mach/at91sam9_smc.h> |
30 | |
31 | #include "generic.h" |
32 | |
33 | |
34 | /* -------------------------------------------------------------------- |
35 | * USB Host |
36 | * -------------------------------------------------------------------- */ |
37 | |
38 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
39 | static u64 ohci_dmamask = DMA_BIT_MASK(32); |
40 | static struct at91_usbh_data usbh_data; |
41 | |
42 | static struct resource usbh_resources[] = { |
43 | [0] = { |
44 | .start = AT91CAP9_UHP_BASE, |
45 | .end = AT91CAP9_UHP_BASE + SZ_1M - 1, |
46 | .flags = IORESOURCE_MEM, |
47 | }, |
48 | [1] = { |
49 | .start = AT91CAP9_ID_UHP, |
50 | .end = AT91CAP9_ID_UHP, |
51 | .flags = IORESOURCE_IRQ, |
52 | }, |
53 | }; |
54 | |
55 | static struct platform_device at91_usbh_device = { |
56 | .name = "at91_ohci", |
57 | .id = -1, |
58 | .dev = { |
59 | .dma_mask = &ohci_dmamask, |
60 | .coherent_dma_mask = DMA_BIT_MASK(32), |
61 | .platform_data = &usbh_data, |
62 | }, |
63 | .resource = usbh_resources, |
64 | .num_resources = ARRAY_SIZE(usbh_resources), |
65 | }; |
66 | |
67 | void __init at91_add_device_usbh(struct at91_usbh_data *data) |
68 | { |
69 | int i; |
70 | |
71 | if (!data) |
72 | return; |
73 | |
74 | if (cpu_is_at91cap9_revB()) |
75 | set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); |
76 | |
77 | /* Enable VBus control for UHP ports */ |
78 | for (i = 0; i < data->ports; i++) { |
79 | if (data->vbus_pin[i]) |
80 | at91_set_gpio_output(data->vbus_pin[i], 0); |
81 | } |
82 | |
83 | usbh_data = *data; |
84 | platform_device_register(&at91_usbh_device); |
85 | } |
86 | #else |
87 | void __init at91_add_device_usbh(struct at91_usbh_data *data) {} |
88 | #endif |
89 | |
90 | |
91 | /* -------------------------------------------------------------------- |
92 | * USB HS Device (Gadget) |
93 | * -------------------------------------------------------------------- */ |
94 | |
95 | #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE) |
96 | |
97 | static struct resource usba_udc_resources[] = { |
98 | [0] = { |
99 | .start = AT91CAP9_UDPHS_FIFO, |
100 | .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1, |
101 | .flags = IORESOURCE_MEM, |
102 | }, |
103 | [1] = { |
104 | .start = AT91CAP9_BASE_UDPHS, |
105 | .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1, |
106 | .flags = IORESOURCE_MEM, |
107 | }, |
108 | [2] = { |
109 | .start = AT91CAP9_ID_UDPHS, |
110 | .end = AT91CAP9_ID_UDPHS, |
111 | .flags = IORESOURCE_IRQ, |
112 | }, |
113 | }; |
114 | |
115 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ |
116 | [idx] = { \ |
117 | .name = nam, \ |
118 | .index = idx, \ |
119 | .fifo_size = maxpkt, \ |
120 | .nr_banks = maxbk, \ |
121 | .can_dma = dma, \ |
122 | .can_isoc = isoc, \ |
123 | } |
124 | |
125 | static struct usba_ep_data usba_udc_ep[] = { |
126 | EP("ep0", 0, 64, 1, 0, 0), |
127 | EP("ep1", 1, 1024, 3, 1, 1), |
128 | EP("ep2", 2, 1024, 3, 1, 1), |
129 | EP("ep3", 3, 1024, 2, 1, 1), |
130 | EP("ep4", 4, 1024, 2, 1, 1), |
131 | EP("ep5", 5, 1024, 2, 1, 0), |
132 | EP("ep6", 6, 1024, 2, 1, 0), |
133 | EP("ep7", 7, 1024, 2, 0, 0), |
134 | }; |
135 | |
136 | #undef EP |
137 | |
138 | /* |
139 | * pdata doesn't have room for any endpoints, so we need to |
140 | * append room for the ones we need right after it. |
141 | */ |
142 | static struct { |
143 | struct usba_platform_data pdata; |
144 | struct usba_ep_data ep[8]; |
145 | } usba_udc_data; |
146 | |
147 | static struct platform_device at91_usba_udc_device = { |
148 | .name = "atmel_usba_udc", |
149 | .id = -1, |
150 | .dev = { |
151 | .platform_data = &usba_udc_data.pdata, |
152 | }, |
153 | .resource = usba_udc_resources, |
154 | .num_resources = ARRAY_SIZE(usba_udc_resources), |
155 | }; |
156 | |
157 | void __init at91_add_device_usba(struct usba_platform_data *data) |
158 | { |
159 | if (cpu_is_at91cap9_revB()) { |
160 | set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); |
161 | at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | |
162 | AT91_MATRIX_UDPHS_BYPASS_LOCK); |
163 | } |
164 | else |
165 | at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS); |
166 | |
167 | /* |
168 | * Invalid pins are 0 on AT91, but the usba driver is shared |
169 | * with AVR32, which use negative values instead. Once/if |
170 | * gpio_is_valid() is ported to AT91, revisit this code. |
171 | */ |
172 | usba_udc_data.pdata.vbus_pin = -EINVAL; |
173 | usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); |
174 | memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));; |
175 | |
176 | if (data && data->vbus_pin > 0) { |
177 | at91_set_gpio_input(data->vbus_pin, 0); |
178 | at91_set_deglitch(data->vbus_pin, 1); |
179 | usba_udc_data.pdata.vbus_pin = data->vbus_pin; |
180 | } |
181 | |
182 | /* Pullup pin is handled internally by USB device peripheral */ |
183 | |
184 | /* Clocks */ |
185 | at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk"); |
186 | at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk"); |
187 | |
188 | platform_device_register(&at91_usba_udc_device); |
189 | } |
190 | #else |
191 | void __init at91_add_device_usba(struct usba_platform_data *data) {} |
192 | #endif |
193 | |
194 | |
195 | /* -------------------------------------------------------------------- |
196 | * Ethernet |
197 | * -------------------------------------------------------------------- */ |
198 | |
199 | #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) |
200 | static u64 eth_dmamask = DMA_BIT_MASK(32); |
201 | static struct at91_eth_data eth_data; |
202 | |
203 | static struct resource eth_resources[] = { |
204 | [0] = { |
205 | .start = AT91CAP9_BASE_EMAC, |
206 | .end = AT91CAP9_BASE_EMAC + SZ_16K - 1, |
207 | .flags = IORESOURCE_MEM, |
208 | }, |
209 | [1] = { |
210 | .start = AT91CAP9_ID_EMAC, |
211 | .end = AT91CAP9_ID_EMAC, |
212 | .flags = IORESOURCE_IRQ, |
213 | }, |
214 | }; |
215 | |
216 | static struct platform_device at91cap9_eth_device = { |
217 | .name = "macb", |
218 | .id = -1, |
219 | .dev = { |
220 | .dma_mask = ð_dmamask, |
221 | .coherent_dma_mask = DMA_BIT_MASK(32), |
222 | .platform_data = ð_data, |
223 | }, |
224 | .resource = eth_resources, |
225 | .num_resources = ARRAY_SIZE(eth_resources), |
226 | }; |
227 | |
228 | void __init at91_add_device_eth(struct at91_eth_data *data) |
229 | { |
230 | if (!data) |
231 | return; |
232 | |
233 | if (data->phy_irq_pin) { |
234 | at91_set_gpio_input(data->phy_irq_pin, 0); |
235 | at91_set_deglitch(data->phy_irq_pin, 1); |
236 | } |
237 | |
238 | /* Pins used for MII and RMII */ |
239 | at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */ |
240 | at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */ |
241 | at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */ |
242 | at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */ |
243 | at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */ |
244 | at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */ |
245 | at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */ |
246 | at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */ |
247 | at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */ |
248 | at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */ |
249 | |
250 | if (!data->is_rmii) { |
251 | at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */ |
252 | at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ |
253 | at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ |
254 | at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ |
255 | at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ |
256 | at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ |
257 | at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ |
258 | at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ |
259 | } |
260 | |
261 | eth_data = *data; |
262 | platform_device_register(&at91cap9_eth_device); |
263 | } |
264 | #else |
265 | void __init at91_add_device_eth(struct at91_eth_data *data) {} |
266 | #endif |
267 | |
268 | |
269 | /* -------------------------------------------------------------------- |
270 | * MMC / SD |
271 | * -------------------------------------------------------------------- */ |
272 | |
273 | #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) |
274 | static u64 mmc_dmamask = DMA_BIT_MASK(32); |
275 | static struct at91_mmc_data mmc0_data, mmc1_data; |
276 | |
277 | static struct resource mmc0_resources[] = { |
278 | [0] = { |
279 | .start = AT91CAP9_BASE_MCI0, |
280 | .end = AT91CAP9_BASE_MCI0 + SZ_16K - 1, |
281 | .flags = IORESOURCE_MEM, |
282 | }, |
283 | [1] = { |
284 | .start = AT91CAP9_ID_MCI0, |
285 | .end = AT91CAP9_ID_MCI0, |
286 | .flags = IORESOURCE_IRQ, |
287 | }, |
288 | }; |
289 | |
290 | static struct platform_device at91cap9_mmc0_device = { |
291 | .name = "at91_mci", |
292 | .id = 0, |
293 | .dev = { |
294 | .dma_mask = &mmc_dmamask, |
295 | .coherent_dma_mask = DMA_BIT_MASK(32), |
296 | .platform_data = &mmc0_data, |
297 | }, |
298 | .resource = mmc0_resources, |
299 | .num_resources = ARRAY_SIZE(mmc0_resources), |
300 | }; |
301 | |
302 | static struct resource mmc1_resources[] = { |
303 | [0] = { |
304 | .start = AT91CAP9_BASE_MCI1, |
305 | .end = AT91CAP9_BASE_MCI1 + SZ_16K - 1, |
306 | .flags = IORESOURCE_MEM, |
307 | }, |
308 | [1] = { |
309 | .start = AT91CAP9_ID_MCI1, |
310 | .end = AT91CAP9_ID_MCI1, |
311 | .flags = IORESOURCE_IRQ, |
312 | }, |
313 | }; |
314 | |
315 | static struct platform_device at91cap9_mmc1_device = { |
316 | .name = "at91_mci", |
317 | .id = 1, |
318 | .dev = { |
319 | .dma_mask = &mmc_dmamask, |
320 | .coherent_dma_mask = DMA_BIT_MASK(32), |
321 | .platform_data = &mmc1_data, |
322 | }, |
323 | .resource = mmc1_resources, |
324 | .num_resources = ARRAY_SIZE(mmc1_resources), |
325 | }; |
326 | |
327 | void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) |
328 | { |
329 | if (!data) |
330 | return; |
331 | |
332 | /* input/irq */ |
333 | if (data->det_pin) { |
334 | at91_set_gpio_input(data->det_pin, 1); |
335 | at91_set_deglitch(data->det_pin, 1); |
336 | } |
337 | if (data->wp_pin) |
338 | at91_set_gpio_input(data->wp_pin, 1); |
339 | if (data->vcc_pin) |
340 | at91_set_gpio_output(data->vcc_pin, 0); |
341 | |
342 | if (mmc_id == 0) { /* MCI0 */ |
343 | /* CLK */ |
344 | at91_set_A_periph(AT91_PIN_PA2, 0); |
345 | |
346 | /* CMD */ |
347 | at91_set_A_periph(AT91_PIN_PA1, 1); |
348 | |
349 | /* DAT0, maybe DAT1..DAT3 */ |
350 | at91_set_A_periph(AT91_PIN_PA0, 1); |
351 | if (data->wire4) { |
352 | at91_set_A_periph(AT91_PIN_PA3, 1); |
353 | at91_set_A_periph(AT91_PIN_PA4, 1); |
354 | at91_set_A_periph(AT91_PIN_PA5, 1); |
355 | } |
356 | |
357 | mmc0_data = *data; |
358 | at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk"); |
359 | platform_device_register(&at91cap9_mmc0_device); |
360 | } else { /* MCI1 */ |
361 | /* CLK */ |
362 | at91_set_A_periph(AT91_PIN_PA16, 0); |
363 | |
364 | /* CMD */ |
365 | at91_set_A_periph(AT91_PIN_PA17, 1); |
366 | |
367 | /* DAT0, maybe DAT1..DAT3 */ |
368 | at91_set_A_periph(AT91_PIN_PA18, 1); |
369 | if (data->wire4) { |
370 | at91_set_A_periph(AT91_PIN_PA19, 1); |
371 | at91_set_A_periph(AT91_PIN_PA20, 1); |
372 | at91_set_A_periph(AT91_PIN_PA21, 1); |
373 | } |
374 | |
375 | mmc1_data = *data; |
376 | at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk"); |
377 | platform_device_register(&at91cap9_mmc1_device); |
378 | } |
379 | } |
380 | #else |
381 | void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} |
382 | #endif |
383 | |
384 | |
385 | /* -------------------------------------------------------------------- |
386 | * NAND / SmartMedia |
387 | * -------------------------------------------------------------------- */ |
388 | |
389 | #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) |
390 | static struct atmel_nand_data nand_data; |
391 | |
392 | #define NAND_BASE AT91_CHIPSELECT_3 |
393 | |
394 | static struct resource nand_resources[] = { |
395 | [0] = { |
396 | .start = NAND_BASE, |
397 | .end = NAND_BASE + SZ_256M - 1, |
398 | .flags = IORESOURCE_MEM, |
399 | }, |
400 | [1] = { |
401 | .start = AT91_BASE_SYS + AT91_ECC, |
402 | .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, |
403 | .flags = IORESOURCE_MEM, |
404 | } |
405 | }; |
406 | |
407 | static struct platform_device at91cap9_nand_device = { |
408 | .name = "atmel_nand", |
409 | .id = -1, |
410 | .dev = { |
411 | .platform_data = &nand_data, |
412 | }, |
413 | .resource = nand_resources, |
414 | .num_resources = ARRAY_SIZE(nand_resources), |
415 | }; |
416 | |
417 | void __init at91_add_device_nand(struct atmel_nand_data *data) |
418 | { |
419 | unsigned long csa; |
420 | |
421 | if (!data) |
422 | return; |
423 | |
424 | csa = at91_sys_read(AT91_MATRIX_EBICSA); |
425 | at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); |
426 | |
427 | /* enable pin */ |
428 | if (data->enable_pin) |
429 | at91_set_gpio_output(data->enable_pin, 1); |
430 | |
431 | /* ready/busy pin */ |
432 | if (data->rdy_pin) |
433 | at91_set_gpio_input(data->rdy_pin, 1); |
434 | |
435 | /* card detect pin */ |
436 | if (data->det_pin) |
437 | at91_set_gpio_input(data->det_pin, 1); |
438 | |
439 | nand_data = *data; |
440 | platform_device_register(&at91cap9_nand_device); |
441 | } |
442 | #else |
443 | void __init at91_add_device_nand(struct atmel_nand_data *data) {} |
444 | #endif |
445 | |
446 | |
447 | /* -------------------------------------------------------------------- |
448 | * TWI (i2c) |
449 | * -------------------------------------------------------------------- */ |
450 | |
451 | /* |
452 | * Prefer the GPIO code since the TWI controller isn't robust |
453 | * (gets overruns and underruns under load) and can only issue |
454 | * repeated STARTs in one scenario (the driver doesn't yet handle them). |
455 | */ |
456 | #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) |
457 | |
458 | static struct i2c_gpio_platform_data pdata = { |
459 | .sda_pin = AT91_PIN_PB4, |
460 | .sda_is_open_drain = 1, |
461 | .scl_pin = AT91_PIN_PB5, |
462 | .scl_is_open_drain = 1, |
463 | .udelay = 2, /* ~100 kHz */ |
464 | }; |
465 | |
466 | static struct platform_device at91cap9_twi_device = { |
467 | .name = "i2c-gpio", |
468 | .id = -1, |
469 | .dev.platform_data = &pdata, |
470 | }; |
471 | |
472 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) |
473 | { |
474 | at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */ |
475 | at91_set_multi_drive(AT91_PIN_PB4, 1); |
476 | |
477 | at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */ |
478 | at91_set_multi_drive(AT91_PIN_PB5, 1); |
479 | |
480 | i2c_register_board_info(0, devices, nr_devices); |
481 | platform_device_register(&at91cap9_twi_device); |
482 | } |
483 | |
484 | #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) |
485 | |
486 | static struct resource twi_resources[] = { |
487 | [0] = { |
488 | .start = AT91CAP9_BASE_TWI, |
489 | .end = AT91CAP9_BASE_TWI + SZ_16K - 1, |
490 | .flags = IORESOURCE_MEM, |
491 | }, |
492 | [1] = { |
493 | .start = AT91CAP9_ID_TWI, |
494 | .end = AT91CAP9_ID_TWI, |
495 | .flags = IORESOURCE_IRQ, |
496 | }, |
497 | }; |
498 | |
499 | static struct platform_device at91cap9_twi_device = { |
500 | .name = "at91_i2c", |
501 | .id = -1, |
502 | .resource = twi_resources, |
503 | .num_resources = ARRAY_SIZE(twi_resources), |
504 | }; |
505 | |
506 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) |
507 | { |
508 | /* pins used for TWI interface */ |
509 | at91_set_B_periph(AT91_PIN_PB4, 0); /* TWD */ |
510 | at91_set_multi_drive(AT91_PIN_PB4, 1); |
511 | |
512 | at91_set_B_periph(AT91_PIN_PB5, 0); /* TWCK */ |
513 | at91_set_multi_drive(AT91_PIN_PB5, 1); |
514 | |
515 | i2c_register_board_info(0, devices, nr_devices); |
516 | platform_device_register(&at91cap9_twi_device); |
517 | } |
518 | #else |
519 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} |
520 | #endif |
521 | |
522 | /* -------------------------------------------------------------------- |
523 | * SPI |
524 | * -------------------------------------------------------------------- */ |
525 | |
526 | #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) |
527 | static u64 spi_dmamask = DMA_BIT_MASK(32); |
528 | |
529 | static struct resource spi0_resources[] = { |
530 | [0] = { |
531 | .start = AT91CAP9_BASE_SPI0, |
532 | .end = AT91CAP9_BASE_SPI0 + SZ_16K - 1, |
533 | .flags = IORESOURCE_MEM, |
534 | }, |
535 | [1] = { |
536 | .start = AT91CAP9_ID_SPI0, |
537 | .end = AT91CAP9_ID_SPI0, |
538 | .flags = IORESOURCE_IRQ, |
539 | }, |
540 | }; |
541 | |
542 | static struct platform_device at91cap9_spi0_device = { |
543 | .name = "atmel_spi", |
544 | .id = 0, |
545 | .dev = { |
546 | .dma_mask = &spi_dmamask, |
547 | .coherent_dma_mask = DMA_BIT_MASK(32), |
548 | }, |
549 | .resource = spi0_resources, |
550 | .num_resources = ARRAY_SIZE(spi0_resources), |
551 | }; |
552 | |
553 | static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 }; |
554 | |
555 | static struct resource spi1_resources[] = { |
556 | [0] = { |
557 | .start = AT91CAP9_BASE_SPI1, |
558 | .end = AT91CAP9_BASE_SPI1 + SZ_16K - 1, |
559 | .flags = IORESOURCE_MEM, |
560 | }, |
561 | [1] = { |
562 | .start = AT91CAP9_ID_SPI1, |
563 | .end = AT91CAP9_ID_SPI1, |
564 | .flags = IORESOURCE_IRQ, |
565 | }, |
566 | }; |
567 | |
568 | static struct platform_device at91cap9_spi1_device = { |
569 | .name = "atmel_spi", |
570 | .id = 1, |
571 | .dev = { |
572 | .dma_mask = &spi_dmamask, |
573 | .coherent_dma_mask = DMA_BIT_MASK(32), |
574 | }, |
575 | .resource = spi1_resources, |
576 | .num_resources = ARRAY_SIZE(spi1_resources), |
577 | }; |
578 | |
579 | static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 }; |
580 | |
581 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) |
582 | { |
583 | int i; |
584 | unsigned long cs_pin; |
585 | short enable_spi0 = 0; |
586 | short enable_spi1 = 0; |
587 | |
588 | /* Choose SPI chip-selects */ |
589 | for (i = 0; i < nr_devices; i++) { |
590 | if (devices[i].controller_data) |
591 | cs_pin = (unsigned long) devices[i].controller_data; |
592 | else if (devices[i].bus_num == 0) |
593 | cs_pin = spi0_standard_cs[devices[i].chip_select]; |
594 | else |
595 | cs_pin = spi1_standard_cs[devices[i].chip_select]; |
596 | |
597 | if (devices[i].bus_num == 0) |
598 | enable_spi0 = 1; |
599 | else |
600 | enable_spi1 = 1; |
601 | |
602 | /* enable chip-select pin */ |
603 | at91_set_gpio_output(cs_pin, 1); |
604 | |
605 | /* pass chip-select pin to driver */ |
606 | devices[i].controller_data = (void *) cs_pin; |
607 | } |
608 | |
609 | spi_register_board_info(devices, nr_devices); |
610 | |
611 | /* Configure SPI bus(es) */ |
612 | if (enable_spi0) { |
613 | at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ |
614 | at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ |
615 | at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ |
616 | |
617 | at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk"); |
618 | platform_device_register(&at91cap9_spi0_device); |
619 | } |
620 | if (enable_spi1) { |
621 | at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ |
622 | at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ |
623 | at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ |
624 | |
625 | at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk"); |
626 | platform_device_register(&at91cap9_spi1_device); |
627 | } |
628 | } |
629 | #else |
630 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} |
631 | #endif |
632 | |
633 | |
634 | /* -------------------------------------------------------------------- |
635 | * Timer/Counter block |
636 | * -------------------------------------------------------------------- */ |
637 | |
638 | #ifdef CONFIG_ATMEL_TCLIB |
639 | |
640 | static struct resource tcb_resources[] = { |
641 | [0] = { |
642 | .start = AT91CAP9_BASE_TCB0, |
643 | .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1, |
644 | .flags = IORESOURCE_MEM, |
645 | }, |
646 | [1] = { |
647 | .start = AT91CAP9_ID_TCB, |
648 | .end = AT91CAP9_ID_TCB, |
649 | .flags = IORESOURCE_IRQ, |
650 | }, |
651 | }; |
652 | |
653 | static struct platform_device at91cap9_tcb_device = { |
654 | .name = "atmel_tcb", |
655 | .id = 0, |
656 | .resource = tcb_resources, |
657 | .num_resources = ARRAY_SIZE(tcb_resources), |
658 | }; |
659 | |
660 | static void __init at91_add_device_tc(void) |
661 | { |
662 | /* this chip has one clock and irq for all three TC channels */ |
663 | at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk"); |
664 | platform_device_register(&at91cap9_tcb_device); |
665 | } |
666 | #else |
667 | static void __init at91_add_device_tc(void) { } |
668 | #endif |
669 | |
670 | |
671 | /* -------------------------------------------------------------------- |
672 | * RTT |
673 | * -------------------------------------------------------------------- */ |
674 | |
675 | static struct resource rtt_resources[] = { |
676 | { |
677 | .start = AT91_BASE_SYS + AT91_RTT, |
678 | .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, |
679 | .flags = IORESOURCE_MEM, |
680 | } |
681 | }; |
682 | |
683 | static struct platform_device at91cap9_rtt_device = { |
684 | .name = "at91_rtt", |
685 | .id = 0, |
686 | .resource = rtt_resources, |
687 | .num_resources = ARRAY_SIZE(rtt_resources), |
688 | }; |
689 | |
690 | static void __init at91_add_device_rtt(void) |
691 | { |
692 | platform_device_register(&at91cap9_rtt_device); |
693 | } |
694 | |
695 | |
696 | /* -------------------------------------------------------------------- |
697 | * Watchdog |
698 | * -------------------------------------------------------------------- */ |
699 | |
700 | #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) |
701 | static struct platform_device at91cap9_wdt_device = { |
702 | .name = "at91_wdt", |
703 | .id = -1, |
704 | .num_resources = 0, |
705 | }; |
706 | |
707 | static void __init at91_add_device_watchdog(void) |
708 | { |
709 | platform_device_register(&at91cap9_wdt_device); |
710 | } |
711 | #else |
712 | static void __init at91_add_device_watchdog(void) {} |
713 | #endif |
714 | |
715 | |
716 | /* -------------------------------------------------------------------- |
717 | * PWM |
718 | * --------------------------------------------------------------------*/ |
719 | |
720 | #if defined(CONFIG_ATMEL_PWM) |
721 | static u32 pwm_mask; |
722 | |
723 | static struct resource pwm_resources[] = { |
724 | [0] = { |
725 | .start = AT91CAP9_BASE_PWMC, |
726 | .end = AT91CAP9_BASE_PWMC + SZ_16K - 1, |
727 | .flags = IORESOURCE_MEM, |
728 | }, |
729 | [1] = { |
730 | .start = AT91CAP9_ID_PWMC, |
731 | .end = AT91CAP9_ID_PWMC, |
732 | .flags = IORESOURCE_IRQ, |
733 | }, |
734 | }; |
735 | |
736 | static struct platform_device at91cap9_pwm0_device = { |
737 | .name = "atmel_pwm", |
738 | .id = -1, |
739 | .dev = { |
740 | .platform_data = &pwm_mask, |
741 | }, |
742 | .resource = pwm_resources, |
743 | .num_resources = ARRAY_SIZE(pwm_resources), |
744 | }; |
745 | |
746 | void __init at91_add_device_pwm(u32 mask) |
747 | { |
748 | if (mask & (1 << AT91_PWM0)) |
749 | at91_set_A_periph(AT91_PIN_PB19, 1); /* enable PWM0 */ |
750 | |
751 | if (mask & (1 << AT91_PWM1)) |
752 | at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */ |
753 | |
754 | if (mask & (1 << AT91_PWM2)) |
755 | at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */ |
756 | |
757 | if (mask & (1 << AT91_PWM3)) |
758 | at91_set_B_periph(AT91_PIN_PA11, 1); /* enable PWM3 */ |
759 | |
760 | pwm_mask = mask; |
761 | |
762 | platform_device_register(&at91cap9_pwm0_device); |
763 | } |
764 | #else |
765 | void __init at91_add_device_pwm(u32 mask) {} |
766 | #endif |
767 | |
768 | |
769 | |
770 | /* -------------------------------------------------------------------- |
771 | * AC97 |
772 | * -------------------------------------------------------------------- */ |
773 | |
774 | #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE) |
775 | static u64 ac97_dmamask = DMA_BIT_MASK(32); |
776 | static struct ac97c_platform_data ac97_data; |
777 | |
778 | static struct resource ac97_resources[] = { |
779 | [0] = { |
780 | .start = AT91CAP9_BASE_AC97C, |
781 | .end = AT91CAP9_BASE_AC97C + SZ_16K - 1, |
782 | .flags = IORESOURCE_MEM, |
783 | }, |
784 | [1] = { |
785 | .start = AT91CAP9_ID_AC97C, |
786 | .end = AT91CAP9_ID_AC97C, |
787 | .flags = IORESOURCE_IRQ, |
788 | }, |
789 | }; |
790 | |
791 | static struct platform_device at91cap9_ac97_device = { |
792 | .name = "atmel_ac97c", |
793 | .id = 1, |
794 | .dev = { |
795 | .dma_mask = &ac97_dmamask, |
796 | .coherent_dma_mask = DMA_BIT_MASK(32), |
797 | .platform_data = &ac97_data, |
798 | }, |
799 | .resource = ac97_resources, |
800 | .num_resources = ARRAY_SIZE(ac97_resources), |
801 | }; |
802 | |
803 | void __init at91_add_device_ac97(struct ac97c_platform_data *data) |
804 | { |
805 | if (!data) |
806 | return; |
807 | |
808 | at91_set_A_periph(AT91_PIN_PA6, 0); /* AC97FS */ |
809 | at91_set_A_periph(AT91_PIN_PA7, 0); /* AC97CK */ |
810 | at91_set_A_periph(AT91_PIN_PA8, 0); /* AC97TX */ |
811 | at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */ |
812 | |
813 | /* reset */ |
814 | if (data->reset_pin) |
815 | at91_set_gpio_output(data->reset_pin, 0); |
816 | |
817 | ac97_data = *data; |
818 | platform_device_register(&at91cap9_ac97_device); |
819 | } |
820 | #else |
821 | void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} |
822 | #endif |
823 | |
824 | |
825 | /* -------------------------------------------------------------------- |
826 | * LCD Controller |
827 | * -------------------------------------------------------------------- */ |
828 | |
829 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) |
830 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); |
831 | static struct atmel_lcdfb_info lcdc_data; |
832 | |
833 | static struct resource lcdc_resources[] = { |
834 | [0] = { |
835 | .start = AT91CAP9_LCDC_BASE, |
836 | .end = AT91CAP9_LCDC_BASE + SZ_4K - 1, |
837 | .flags = IORESOURCE_MEM, |
838 | }, |
839 | [1] = { |
840 | .start = AT91CAP9_ID_LCDC, |
841 | .end = AT91CAP9_ID_LCDC, |
842 | .flags = IORESOURCE_IRQ, |
843 | }, |
844 | }; |
845 | |
846 | static struct platform_device at91_lcdc_device = { |
847 | .name = "atmel_lcdfb", |
848 | .id = 0, |
849 | .dev = { |
850 | .dma_mask = &lcdc_dmamask, |
851 | .coherent_dma_mask = DMA_BIT_MASK(32), |
852 | .platform_data = &lcdc_data, |
853 | }, |
854 | .resource = lcdc_resources, |
855 | .num_resources = ARRAY_SIZE(lcdc_resources), |
856 | }; |
857 | |
858 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) |
859 | { |
860 | if (!data) |
861 | return; |
862 | |
863 | if (cpu_is_at91cap9_revB()) |
864 | set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); |
865 | |
866 | at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ |
867 | at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ |
868 | at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ |
869 | at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ |
870 | at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ |
871 | at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ |
872 | at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ |
873 | at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ |
874 | at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ |
875 | at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ |
876 | at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ |
877 | at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ |
878 | at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ |
879 | at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */ |
880 | at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ |
881 | at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ |
882 | at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ |
883 | at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ |
884 | at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ |
885 | at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */ |
886 | at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ |
887 | at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ |
888 | |
889 | lcdc_data = *data; |
890 | platform_device_register(&at91_lcdc_device); |
891 | } |
892 | #else |
893 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} |
894 | #endif |
895 | |
896 | |
897 | /* -------------------------------------------------------------------- |
898 | * SSC -- Synchronous Serial Controller |
899 | * -------------------------------------------------------------------- */ |
900 | |
901 | #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) |
902 | static u64 ssc0_dmamask = DMA_BIT_MASK(32); |
903 | |
904 | static struct resource ssc0_resources[] = { |
905 | [0] = { |
906 | .start = AT91CAP9_BASE_SSC0, |
907 | .end = AT91CAP9_BASE_SSC0 + SZ_16K - 1, |
908 | .flags = IORESOURCE_MEM, |
909 | }, |
910 | [1] = { |
911 | .start = AT91CAP9_ID_SSC0, |
912 | .end = AT91CAP9_ID_SSC0, |
913 | .flags = IORESOURCE_IRQ, |
914 | }, |
915 | }; |
916 | |
917 | static struct platform_device at91cap9_ssc0_device = { |
918 | .name = "ssc", |
919 | .id = 0, |
920 | .dev = { |
921 | .dma_mask = &ssc0_dmamask, |
922 | .coherent_dma_mask = DMA_BIT_MASK(32), |
923 | }, |
924 | .resource = ssc0_resources, |
925 | .num_resources = ARRAY_SIZE(ssc0_resources), |
926 | }; |
927 | |
928 | static inline void configure_ssc0_pins(unsigned pins) |
929 | { |
930 | if (pins & ATMEL_SSC_TF) |
931 | at91_set_A_periph(AT91_PIN_PB0, 1); |
932 | if (pins & ATMEL_SSC_TK) |
933 | at91_set_A_periph(AT91_PIN_PB1, 1); |
934 | if (pins & ATMEL_SSC_TD) |
935 | at91_set_A_periph(AT91_PIN_PB2, 1); |
936 | if (pins & ATMEL_SSC_RD) |
937 | at91_set_A_periph(AT91_PIN_PB3, 1); |
938 | if (pins & ATMEL_SSC_RK) |
939 | at91_set_A_periph(AT91_PIN_PB4, 1); |
940 | if (pins & ATMEL_SSC_RF) |
941 | at91_set_A_periph(AT91_PIN_PB5, 1); |
942 | } |
943 | |
944 | static u64 ssc1_dmamask = DMA_BIT_MASK(32); |
945 | |
946 | static struct resource ssc1_resources[] = { |
947 | [0] = { |
948 | .start = AT91CAP9_BASE_SSC1, |
949 | .end = AT91CAP9_BASE_SSC1 + SZ_16K - 1, |
950 | .flags = IORESOURCE_MEM, |
951 | }, |
952 | [1] = { |
953 | .start = AT91CAP9_ID_SSC1, |
954 | .end = AT91CAP9_ID_SSC1, |
955 | .flags = IORESOURCE_IRQ, |
956 | }, |
957 | }; |
958 | |
959 | static struct platform_device at91cap9_ssc1_device = { |
960 | .name = "ssc", |
961 | .id = 1, |
962 | .dev = { |
963 | .dma_mask = &ssc1_dmamask, |
964 | .coherent_dma_mask = DMA_BIT_MASK(32), |
965 | }, |
966 | .resource = ssc1_resources, |
967 | .num_resources = ARRAY_SIZE(ssc1_resources), |
968 | }; |
969 | |
970 | static inline void configure_ssc1_pins(unsigned pins) |
971 | { |
972 | if (pins & ATMEL_SSC_TF) |
973 | at91_set_A_periph(AT91_PIN_PB6, 1); |
974 | if (pins & ATMEL_SSC_TK) |
975 | at91_set_A_periph(AT91_PIN_PB7, 1); |
976 | if (pins & ATMEL_SSC_TD) |
977 | at91_set_A_periph(AT91_PIN_PB8, 1); |
978 | if (pins & ATMEL_SSC_RD) |
979 | at91_set_A_periph(AT91_PIN_PB9, 1); |
980 | if (pins & ATMEL_SSC_RK) |
981 | at91_set_A_periph(AT91_PIN_PB10, 1); |
982 | if (pins & ATMEL_SSC_RF) |
983 | at91_set_A_periph(AT91_PIN_PB11, 1); |
984 | } |
985 | |
986 | /* |
987 | * SSC controllers are accessed through library code, instead of any |
988 | * kind of all-singing/all-dancing driver. For example one could be |
989 | * used by a particular I2S audio codec's driver, while another one |
990 | * on the same system might be used by a custom data capture driver. |
991 | */ |
992 | void __init at91_add_device_ssc(unsigned id, unsigned pins) |
993 | { |
994 | struct platform_device *pdev; |
995 | |
996 | /* |
997 | * NOTE: caller is responsible for passing information matching |
998 | * "pins" to whatever will be using each particular controller. |
999 | */ |
1000 | switch (id) { |
1001 | case AT91CAP9_ID_SSC0: |
1002 | pdev = &at91cap9_ssc0_device; |
1003 | configure_ssc0_pins(pins); |
1004 | at91_clock_associate("ssc0_clk", &pdev->dev, "ssc"); |
1005 | break; |
1006 | case AT91CAP9_ID_SSC1: |
1007 | pdev = &at91cap9_ssc1_device; |
1008 | configure_ssc1_pins(pins); |
1009 | at91_clock_associate("ssc1_clk", &pdev->dev, "ssc"); |
1010 | break; |
1011 | default: |
1012 | return; |
1013 | } |
1014 | |
1015 | platform_device_register(pdev); |
1016 | } |
1017 | |
1018 | #else |
1019 | void __init at91_add_device_ssc(unsigned id, unsigned pins) {} |
1020 | #endif |
1021 | |
1022 | |
1023 | /* -------------------------------------------------------------------- |
1024 | * UART |
1025 | * -------------------------------------------------------------------- */ |
1026 | |
1027 | #if defined(CONFIG_SERIAL_ATMEL) |
1028 | static struct resource dbgu_resources[] = { |
1029 | [0] = { |
1030 | .start = AT91_VA_BASE_SYS + AT91_DBGU, |
1031 | .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, |
1032 | .flags = IORESOURCE_MEM, |
1033 | }, |
1034 | [1] = { |
1035 | .start = AT91_ID_SYS, |
1036 | .end = AT91_ID_SYS, |
1037 | .flags = IORESOURCE_IRQ, |
1038 | }, |
1039 | }; |
1040 | |
1041 | static struct atmel_uart_data dbgu_data = { |
1042 | .use_dma_tx = 0, |
1043 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ |
1044 | .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), |
1045 | }; |
1046 | |
1047 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
1048 | |
1049 | static struct platform_device at91cap9_dbgu_device = { |
1050 | .name = "atmel_usart", |
1051 | .id = 0, |
1052 | .dev = { |
1053 | .dma_mask = &dbgu_dmamask, |
1054 | .coherent_dma_mask = DMA_BIT_MASK(32), |
1055 | .platform_data = &dbgu_data, |
1056 | }, |
1057 | .resource = dbgu_resources, |
1058 | .num_resources = ARRAY_SIZE(dbgu_resources), |
1059 | }; |
1060 | |
1061 | static inline void configure_dbgu_pins(void) |
1062 | { |
1063 | at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ |
1064 | at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ |
1065 | } |
1066 | |
1067 | static struct resource uart0_resources[] = { |
1068 | [0] = { |
1069 | .start = AT91CAP9_BASE_US0, |
1070 | .end = AT91CAP9_BASE_US0 + SZ_16K - 1, |
1071 | .flags = IORESOURCE_MEM, |
1072 | }, |
1073 | [1] = { |
1074 | .start = AT91CAP9_ID_US0, |
1075 | .end = AT91CAP9_ID_US0, |
1076 | .flags = IORESOURCE_IRQ, |
1077 | }, |
1078 | }; |
1079 | |
1080 | static struct atmel_uart_data uart0_data = { |
1081 | .use_dma_tx = 1, |
1082 | .use_dma_rx = 1, |
1083 | }; |
1084 | |
1085 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
1086 | |
1087 | static struct platform_device at91cap9_uart0_device = { |
1088 | .name = "atmel_usart", |
1089 | .id = 1, |
1090 | .dev = { |
1091 | .dma_mask = &uart0_dmamask, |
1092 | .coherent_dma_mask = DMA_BIT_MASK(32), |
1093 | .platform_data = &uart0_data, |
1094 | }, |
1095 | .resource = uart0_resources, |
1096 | .num_resources = ARRAY_SIZE(uart0_resources), |
1097 | }; |
1098 | |
1099 | static inline void configure_usart0_pins(unsigned pins) |
1100 | { |
1101 | at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ |
1102 | at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ |
1103 | |
1104 | if (pins & ATMEL_UART_RTS) |
1105 | at91_set_A_periph(AT91_PIN_PA24, 0); /* RTS0 */ |
1106 | if (pins & ATMEL_UART_CTS) |
1107 | at91_set_A_periph(AT91_PIN_PA25, 0); /* CTS0 */ |
1108 | } |
1109 | |
1110 | static struct resource uart1_resources[] = { |
1111 | [0] = { |
1112 | .start = AT91CAP9_BASE_US1, |
1113 | .end = AT91CAP9_BASE_US1 + SZ_16K - 1, |
1114 | .flags = IORESOURCE_MEM, |
1115 | }, |
1116 | [1] = { |
1117 | .start = AT91CAP9_ID_US1, |
1118 | .end = AT91CAP9_ID_US1, |
1119 | .flags = IORESOURCE_IRQ, |
1120 | }, |
1121 | }; |
1122 | |
1123 | static struct atmel_uart_data uart1_data = { |
1124 | .use_dma_tx = 1, |
1125 | .use_dma_rx = 1, |
1126 | }; |
1127 | |
1128 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
1129 | |
1130 | static struct platform_device at91cap9_uart1_device = { |
1131 | .name = "atmel_usart", |
1132 | .id = 2, |
1133 | .dev = { |
1134 | .dma_mask = &uart1_dmamask, |
1135 | .coherent_dma_mask = DMA_BIT_MASK(32), |
1136 | .platform_data = &uart1_data, |
1137 | }, |
1138 | .resource = uart1_resources, |
1139 | .num_resources = ARRAY_SIZE(uart1_resources), |
1140 | }; |
1141 | |
1142 | static inline void configure_usart1_pins(unsigned pins) |
1143 | { |
1144 | at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ |
1145 | at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ |
1146 | |
1147 | if (pins & ATMEL_UART_RTS) |
1148 | at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */ |
1149 | if (pins & ATMEL_UART_CTS) |
1150 | at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */ |
1151 | } |
1152 | |
1153 | static struct resource uart2_resources[] = { |
1154 | [0] = { |
1155 | .start = AT91CAP9_BASE_US2, |
1156 | .end = AT91CAP9_BASE_US2 + SZ_16K - 1, |
1157 | .flags = IORESOURCE_MEM, |
1158 | }, |
1159 | [1] = { |
1160 | .start = AT91CAP9_ID_US2, |
1161 | .end = AT91CAP9_ID_US2, |
1162 | .flags = IORESOURCE_IRQ, |
1163 | }, |
1164 | }; |
1165 | |
1166 | static struct atmel_uart_data uart2_data = { |
1167 | .use_dma_tx = 1, |
1168 | .use_dma_rx = 1, |
1169 | }; |
1170 | |
1171 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
1172 | |
1173 | static struct platform_device at91cap9_uart2_device = { |
1174 | .name = "atmel_usart", |
1175 | .id = 3, |
1176 | .dev = { |
1177 | .dma_mask = &uart2_dmamask, |
1178 | .coherent_dma_mask = DMA_BIT_MASK(32), |
1179 | .platform_data = &uart2_data, |
1180 | }, |
1181 | .resource = uart2_resources, |
1182 | .num_resources = ARRAY_SIZE(uart2_resources), |
1183 | }; |
1184 | |
1185 | static inline void configure_usart2_pins(unsigned pins) |
1186 | { |
1187 | at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ |
1188 | at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ |
1189 | |
1190 | if (pins & ATMEL_UART_RTS) |
1191 | at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */ |
1192 | if (pins & ATMEL_UART_CTS) |
1193 | at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */ |
1194 | } |
1195 | |
1196 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
1197 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
1198 | |
1199 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) |
1200 | { |
1201 | struct platform_device *pdev; |
1202 | |
1203 | switch (id) { |
1204 | case 0: /* DBGU */ |
1205 | pdev = &at91cap9_dbgu_device; |
1206 | configure_dbgu_pins(); |
1207 | at91_clock_associate("mck", &pdev->dev, "usart"); |
1208 | break; |
1209 | case AT91CAP9_ID_US0: |
1210 | pdev = &at91cap9_uart0_device; |
1211 | configure_usart0_pins(pins); |
1212 | at91_clock_associate("usart0_clk", &pdev->dev, "usart"); |
1213 | break; |
1214 | case AT91CAP9_ID_US1: |
1215 | pdev = &at91cap9_uart1_device; |
1216 | configure_usart1_pins(pins); |
1217 | at91_clock_associate("usart1_clk", &pdev->dev, "usart"); |
1218 | break; |
1219 | case AT91CAP9_ID_US2: |
1220 | pdev = &at91cap9_uart2_device; |
1221 | configure_usart2_pins(pins); |
1222 | at91_clock_associate("usart2_clk", &pdev->dev, "usart"); |
1223 | break; |
1224 | default: |
1225 | return; |
1226 | } |
1227 | pdev->id = portnr; /* update to mapped ID */ |
1228 | |
1229 | if (portnr < ATMEL_MAX_UART) |
1230 | at91_uarts[portnr] = pdev; |
1231 | } |
1232 | |
1233 | void __init at91_set_serial_console(unsigned portnr) |
1234 | { |
1235 | if (portnr < ATMEL_MAX_UART) |
1236 | atmel_default_console_device = at91_uarts[portnr]; |
1237 | } |
1238 | |
1239 | void __init at91_add_device_serial(void) |
1240 | { |
1241 | int i; |
1242 | |
1243 | for (i = 0; i < ATMEL_MAX_UART; i++) { |
1244 | if (at91_uarts[i]) |
1245 | platform_device_register(at91_uarts[i]); |
1246 | } |
1247 | |
1248 | if (!atmel_default_console_device) |
1249 | printk(KERN_INFO "AT91: No default serial console defined.\n"); |
1250 | } |
1251 | #else |
1252 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} |
1253 | void __init at91_set_serial_console(unsigned portnr) {} |
1254 | void __init at91_add_device_serial(void) {} |
1255 | #endif |
1256 | |
1257 | |
1258 | /* -------------------------------------------------------------------- */ |
1259 | /* |
1260 | * These devices are always present and don't need any board-specific |
1261 | * setup. |
1262 | */ |
1263 | static int __init at91_add_standard_devices(void) |
1264 | { |
1265 | at91_add_device_rtt(); |
1266 | at91_add_device_watchdog(); |
1267 | at91_add_device_tc(); |
1268 | return 0; |
1269 | } |
1270 | |
1271 | arch_initcall(at91_add_standard_devices); |
1272 |
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