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1 | /* |
2 | * arch/arm/mach-ixp4xx/ixdp425-setup.c |
3 | * |
4 | * IXDP425/IXCDP1100 board-setup |
5 | * |
6 | * Copyright (C) 2003-2005 MontaVista Software, Inc. |
7 | * |
8 | * Author: Deepak Saxena <dsaxena@plexity.net> |
9 | */ |
10 | |
11 | #include <linux/kernel.h> |
12 | #include <linux/init.h> |
13 | #include <linux/device.h> |
14 | #include <linux/serial.h> |
15 | #include <linux/tty.h> |
16 | #include <linux/serial_8250.h> |
17 | #include <linux/i2c-gpio.h> |
18 | #include <linux/io.h> |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> |
21 | #include <linux/mtd/partitions.h> |
22 | #include <linux/delay.h> |
23 | #include <asm/types.h> |
24 | #include <asm/setup.h> |
25 | #include <asm/memory.h> |
26 | #include <mach/hardware.h> |
27 | #include <asm/mach-types.h> |
28 | #include <asm/irq.h> |
29 | #include <asm/mach/arch.h> |
30 | #include <asm/mach/flash.h> |
31 | |
32 | #define IXDP425_SDA_PIN 7 |
33 | #define IXDP425_SCL_PIN 6 |
34 | |
35 | /* NAND Flash pins */ |
36 | #define IXDP425_NAND_NCE_PIN 12 |
37 | |
38 | #define IXDP425_NAND_CMD_BYTE 0x01 |
39 | #define IXDP425_NAND_ADDR_BYTE 0x02 |
40 | |
41 | static struct flash_platform_data ixdp425_flash_data = { |
42 | .map_name = "cfi_probe", |
43 | .width = 2, |
44 | }; |
45 | |
46 | static struct resource ixdp425_flash_resource = { |
47 | .flags = IORESOURCE_MEM, |
48 | }; |
49 | |
50 | static struct platform_device ixdp425_flash = { |
51 | .name = "IXP4XX-Flash", |
52 | .id = 0, |
53 | .dev = { |
54 | .platform_data = &ixdp425_flash_data, |
55 | }, |
56 | .num_resources = 1, |
57 | .resource = &ixdp425_flash_resource, |
58 | }; |
59 | |
60 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
61 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) |
62 | |
63 | #ifdef CONFIG_MTD_PARTITIONS |
64 | const char *part_probes[] = { "cmdlinepart", NULL }; |
65 | |
66 | static struct mtd_partition ixdp425_partitions[] = { |
67 | { |
68 | .name = "ixp400 NAND FS 0", |
69 | .offset = 0, |
70 | .size = SZ_8M |
71 | }, { |
72 | .name = "ixp400 NAND FS 1", |
73 | .offset = MTDPART_OFS_APPEND, |
74 | .size = MTDPART_SIZ_FULL |
75 | }, |
76 | }; |
77 | #endif |
78 | |
79 | static void |
80 | ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
81 | { |
82 | struct nand_chip *this = mtd->priv; |
83 | int offset = (int)this->priv; |
84 | |
85 | if (ctrl & NAND_CTRL_CHANGE) { |
86 | if (ctrl & NAND_NCE) { |
87 | gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW); |
88 | udelay(5); |
89 | } else |
90 | gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH); |
91 | |
92 | offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0; |
93 | offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0; |
94 | this->priv = (void *)offset; |
95 | } |
96 | |
97 | if (cmd != NAND_CMD_NONE) |
98 | writeb(cmd, this->IO_ADDR_W + offset); |
99 | } |
100 | |
101 | static struct platform_nand_data ixdp425_flash_nand_data = { |
102 | .chip = { |
103 | .nr_chips = 1, |
104 | .chip_delay = 30, |
105 | .options = NAND_NO_AUTOINCR, |
106 | #ifdef CONFIG_MTD_PARTITIONS |
107 | .part_probe_types = part_probes, |
108 | .partitions = ixdp425_partitions, |
109 | .nr_partitions = ARRAY_SIZE(ixdp425_partitions), |
110 | #endif |
111 | }, |
112 | .ctrl = { |
113 | .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl |
114 | } |
115 | }; |
116 | |
117 | static struct resource ixdp425_flash_nand_resource = { |
118 | .flags = IORESOURCE_MEM, |
119 | }; |
120 | |
121 | static struct platform_device ixdp425_flash_nand = { |
122 | .name = "gen_nand", |
123 | .id = -1, |
124 | .dev = { |
125 | .platform_data = &ixdp425_flash_nand_data, |
126 | }, |
127 | .num_resources = 1, |
128 | .resource = &ixdp425_flash_nand_resource, |
129 | }; |
130 | #endif /* CONFIG_MTD_NAND_PLATFORM */ |
131 | |
132 | static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = { |
133 | .sda_pin = IXDP425_SDA_PIN, |
134 | .scl_pin = IXDP425_SCL_PIN, |
135 | }; |
136 | |
137 | static struct platform_device ixdp425_i2c_gpio = { |
138 | .name = "i2c-gpio", |
139 | .id = 0, |
140 | .dev = { |
141 | .platform_data = &ixdp425_i2c_gpio_data, |
142 | }, |
143 | }; |
144 | |
145 | static struct resource ixdp425_uart_resources[] = { |
146 | { |
147 | .start = IXP4XX_UART1_BASE_PHYS, |
148 | .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, |
149 | .flags = IORESOURCE_MEM |
150 | }, |
151 | { |
152 | .start = IXP4XX_UART2_BASE_PHYS, |
153 | .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, |
154 | .flags = IORESOURCE_MEM |
155 | } |
156 | }; |
157 | |
158 | static struct plat_serial8250_port ixdp425_uart_data[] = { |
159 | { |
160 | .mapbase = IXP4XX_UART1_BASE_PHYS, |
161 | .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, |
162 | .irq = IRQ_IXP4XX_UART1, |
163 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
164 | .iotype = UPIO_MEM, |
165 | .regshift = 2, |
166 | .uartclk = IXP4XX_UART_XTAL, |
167 | }, |
168 | { |
169 | .mapbase = IXP4XX_UART2_BASE_PHYS, |
170 | .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, |
171 | .irq = IRQ_IXP4XX_UART2, |
172 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
173 | .iotype = UPIO_MEM, |
174 | .regshift = 2, |
175 | .uartclk = IXP4XX_UART_XTAL, |
176 | }, |
177 | { }, |
178 | }; |
179 | |
180 | static struct platform_device ixdp425_uart = { |
181 | .name = "serial8250", |
182 | .id = PLAT8250_DEV_PLATFORM, |
183 | .dev.platform_data = ixdp425_uart_data, |
184 | .num_resources = 2, |
185 | .resource = ixdp425_uart_resources |
186 | }; |
187 | |
188 | /* Built-in 10/100 Ethernet MAC interfaces */ |
189 | static struct eth_plat_info ixdp425_plat_eth[] = { |
190 | { |
191 | .phy = 0, |
192 | .rxq = 3, |
193 | .txreadyq = 20, |
194 | }, { |
195 | .phy = 1, |
196 | .rxq = 4, |
197 | .txreadyq = 21, |
198 | } |
199 | }; |
200 | |
201 | static struct platform_device ixdp425_eth[] = { |
202 | { |
203 | .name = "ixp4xx_eth", |
204 | .id = IXP4XX_ETH_NPEB, |
205 | .dev.platform_data = ixdp425_plat_eth, |
206 | }, { |
207 | .name = "ixp4xx_eth", |
208 | .id = IXP4XX_ETH_NPEC, |
209 | .dev.platform_data = ixdp425_plat_eth + 1, |
210 | } |
211 | }; |
212 | |
213 | static struct platform_device *ixdp425_devices[] __initdata = { |
214 | &ixdp425_i2c_gpio, |
215 | &ixdp425_flash, |
216 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
217 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) |
218 | &ixdp425_flash_nand, |
219 | #endif |
220 | &ixdp425_uart, |
221 | &ixdp425_eth[0], |
222 | &ixdp425_eth[1], |
223 | }; |
224 | |
225 | static void __init ixdp425_init(void) |
226 | { |
227 | ixp4xx_sys_init(); |
228 | |
229 | ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
230 | ixdp425_flash_resource.end = |
231 | IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; |
232 | |
233 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
234 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) |
235 | ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3), |
236 | ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1; |
237 | |
238 | gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT); |
239 | |
240 | /* Configure expansion bus for NAND Flash */ |
241 | *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN | |
242 | IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */ |
243 | IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */ |
244 | IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/ |
245 | IXP4XX_EXP_BUS_WR_EN | |
246 | IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */ |
247 | #endif |
248 | |
249 | if (cpu_is_ixp43x()) { |
250 | ixdp425_uart.num_resources = 1; |
251 | ixdp425_uart_data[1].flags = 0; |
252 | } |
253 | |
254 | platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices)); |
255 | } |
256 | |
257 | #ifdef CONFIG_ARCH_IXDP425 |
258 | MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") |
259 | /* Maintainer: MontaVista Software, Inc. */ |
260 | .map_io = ixp4xx_map_io, |
261 | .init_irq = ixp4xx_init_irq, |
262 | .timer = &ixp4xx_timer, |
263 | .boot_params = 0x0100, |
264 | .init_machine = ixdp425_init, |
265 | MACHINE_END |
266 | #endif |
267 | |
268 | #ifdef CONFIG_MACH_IXDP465 |
269 | MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") |
270 | /* Maintainer: MontaVista Software, Inc. */ |
271 | .map_io = ixp4xx_map_io, |
272 | .init_irq = ixp4xx_init_irq, |
273 | .timer = &ixp4xx_timer, |
274 | .boot_params = 0x0100, |
275 | .init_machine = ixdp425_init, |
276 | MACHINE_END |
277 | #endif |
278 | |
279 | #ifdef CONFIG_ARCH_PRPMC1100 |
280 | MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") |
281 | /* Maintainer: MontaVista Software, Inc. */ |
282 | .map_io = ixp4xx_map_io, |
283 | .init_irq = ixp4xx_init_irq, |
284 | .timer = &ixp4xx_timer, |
285 | .boot_params = 0x0100, |
286 | .init_machine = ixdp425_init, |
287 | MACHINE_END |
288 | #endif |
289 | |
290 | #ifdef CONFIG_MACH_KIXRP435 |
291 | MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") |
292 | /* Maintainer: MontaVista Software, Inc. */ |
293 | .map_io = ixp4xx_map_io, |
294 | .init_irq = ixp4xx_init_irq, |
295 | .timer = &ixp4xx_timer, |
296 | .boot_params = 0x0100, |
297 | .init_machine = ixdp425_init, |
298 | MACHINE_END |
299 | #endif |
300 |
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