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1 | /* |
2 | * |
3 | * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> |
4 | * |
5 | * based on board-mx51_babbage.c which is |
6 | * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. |
7 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> |
8 | * |
9 | * The code contained herein is licensed under the GNU General Public |
10 | * License. You may obtain a copy of the GNU General Public License |
11 | * Version 2 or later at the following locations: |
12 | * |
13 | * http://www.opensource.org/licenses/gpl-license.html |
14 | * http://www.gnu.org/copyleft/gpl.html |
15 | */ |
16 | |
17 | #include <linux/init.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/serial_8250.h> |
20 | #include <linux/i2c.h> |
21 | #include <linux/gpio.h> |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> |
24 | #include <linux/interrupt.h> |
25 | #include <linux/irq.h> |
26 | #include <linux/fsl_devices.h> |
27 | |
28 | #include <mach/eukrea-baseboards.h> |
29 | #include <mach/common.h> |
30 | #include <mach/hardware.h> |
31 | #include <mach/iomux-mx51.h> |
32 | #include <mach/mxc_ehci.h> |
33 | |
34 | #include <asm/irq.h> |
35 | #include <asm/setup.h> |
36 | #include <asm/mach-types.h> |
37 | #include <asm/mach/arch.h> |
38 | #include <asm/mach/time.h> |
39 | |
40 | #include "devices-imx51.h" |
41 | #include "devices.h" |
42 | |
43 | #define CPUIMX51_USBH1_STP (0*32 + 27) |
44 | #define CPUIMX51_QUARTA_GPIO (2*32 + 28) |
45 | #define CPUIMX51_QUARTB_GPIO (2*32 + 25) |
46 | #define CPUIMX51_QUARTC_GPIO (2*32 + 26) |
47 | #define CPUIMX51_QUARTD_GPIO (2*32 + 27) |
48 | #define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) |
49 | #define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) |
50 | #define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) |
51 | #define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO) |
52 | #define CPUIMX51_QUART_XTAL 14745600 |
53 | #define CPUIMX51_QUART_REGSHIFT 17 |
54 | |
55 | /* USB_CTRL_1 */ |
56 | #define MX51_USB_CTRL_1_OFFSET 0x10 |
57 | #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) |
58 | |
59 | #define MX51_USB_PLLDIV_12_MHZ 0x00 |
60 | #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 |
61 | #define MX51_USB_PLL_DIV_24_MHZ 0x02 |
62 | |
63 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
64 | static struct plat_serial8250_port serial_platform_data[] = { |
65 | { |
66 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), |
67 | .irq = CPUIMX51_QUARTA_IRQ, |
68 | .irqflags = IRQF_TRIGGER_HIGH, |
69 | .uartclk = CPUIMX51_QUART_XTAL, |
70 | .regshift = CPUIMX51_QUART_REGSHIFT, |
71 | .iotype = UPIO_MEM, |
72 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, |
73 | }, { |
74 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), |
75 | .irq = CPUIMX51_QUARTB_IRQ, |
76 | .irqflags = IRQF_TRIGGER_HIGH, |
77 | .uartclk = CPUIMX51_QUART_XTAL, |
78 | .regshift = CPUIMX51_QUART_REGSHIFT, |
79 | .iotype = UPIO_MEM, |
80 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, |
81 | }, { |
82 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), |
83 | .irq = CPUIMX51_QUARTC_IRQ, |
84 | .irqflags = IRQF_TRIGGER_HIGH, |
85 | .uartclk = CPUIMX51_QUART_XTAL, |
86 | .regshift = CPUIMX51_QUART_REGSHIFT, |
87 | .iotype = UPIO_MEM, |
88 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, |
89 | }, { |
90 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), |
91 | .irq = CPUIMX51_QUARTD_IRQ, |
92 | .irqflags = IRQF_TRIGGER_HIGH, |
93 | .uartclk = CPUIMX51_QUART_XTAL, |
94 | .regshift = CPUIMX51_QUART_REGSHIFT, |
95 | .iotype = UPIO_MEM, |
96 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, |
97 | }, { |
98 | } |
99 | }; |
100 | |
101 | static struct platform_device serial_device = { |
102 | .name = "serial8250", |
103 | .id = 0, |
104 | .dev = { |
105 | .platform_data = serial_platform_data, |
106 | }, |
107 | }; |
108 | #endif |
109 | |
110 | static struct platform_device *devices[] __initdata = { |
111 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
112 | &serial_device, |
113 | #endif |
114 | }; |
115 | |
116 | static struct pad_desc eukrea_cpuimx51_pads[] = { |
117 | /* UART1 */ |
118 | MX51_PAD_UART1_RXD__UART1_RXD, |
119 | MX51_PAD_UART1_TXD__UART1_TXD, |
120 | MX51_PAD_UART1_RTS__UART1_RTS, |
121 | MX51_PAD_UART1_CTS__UART1_CTS, |
122 | |
123 | /* I2C2 */ |
124 | MX51_PAD_GPIO_1_2__I2C2_SCL, |
125 | MX51_PAD_GPIO_1_3__I2C2_SDA, |
126 | MX51_PAD_NANDF_D10__GPIO_3_30, |
127 | |
128 | /* QUART IRQ */ |
129 | MX51_PAD_NANDF_D15__GPIO_3_25, |
130 | MX51_PAD_NANDF_D14__GPIO_3_26, |
131 | MX51_PAD_NANDF_D13__GPIO_3_27, |
132 | MX51_PAD_NANDF_D12__GPIO_3_28, |
133 | |
134 | /* USB HOST1 */ |
135 | MX51_PAD_USBH1_CLK__USBH1_CLK, |
136 | MX51_PAD_USBH1_DIR__USBH1_DIR, |
137 | MX51_PAD_USBH1_NXT__USBH1_NXT, |
138 | MX51_PAD_USBH1_DATA0__USBH1_DATA0, |
139 | MX51_PAD_USBH1_DATA1__USBH1_DATA1, |
140 | MX51_PAD_USBH1_DATA2__USBH1_DATA2, |
141 | MX51_PAD_USBH1_DATA3__USBH1_DATA3, |
142 | MX51_PAD_USBH1_DATA4__USBH1_DATA4, |
143 | MX51_PAD_USBH1_DATA5__USBH1_DATA5, |
144 | MX51_PAD_USBH1_DATA6__USBH1_DATA6, |
145 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, |
146 | MX51_PAD_USBH1_STP__USBH1_STP, |
147 | }; |
148 | |
149 | static const struct mxc_nand_platform_data |
150 | eukrea_cpuimx51_nand_board_info __initconst = { |
151 | .width = 1, |
152 | .hw_ecc = 1, |
153 | .flash_bbt = 1, |
154 | }; |
155 | |
156 | static const struct imxuart_platform_data uart_pdata __initconst = { |
157 | .flags = IMXUART_HAVE_RTSCTS, |
158 | }; |
159 | |
160 | static const |
161 | struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = { |
162 | .bitrate = 100000, |
163 | }; |
164 | |
165 | static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = { |
166 | { |
167 | I2C_BOARD_INFO("pcf8563", 0x51), |
168 | }, |
169 | }; |
170 | |
171 | /* This function is board specific as the bit mask for the plldiv will also |
172 | be different for other Freescale SoCs, thus a common bitmask is not |
173 | possible and cannot get place in /plat-mxc/ehci.c.*/ |
174 | static int initialize_otg_port(struct platform_device *pdev) |
175 | { |
176 | u32 v; |
177 | void __iomem *usb_base; |
178 | void __iomem *usbother_base; |
179 | |
180 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
181 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
182 | |
183 | /* Set the PHY clock to 19.2MHz */ |
184 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); |
185 | v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; |
186 | v |= MX51_USB_PLL_DIV_19_2_MHZ; |
187 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); |
188 | iounmap(usb_base); |
189 | return 0; |
190 | } |
191 | |
192 | static int initialize_usbh1_port(struct platform_device *pdev) |
193 | { |
194 | u32 v; |
195 | void __iomem *usb_base; |
196 | void __iomem *usbother_base; |
197 | |
198 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
199 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
200 | |
201 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ |
202 | v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); |
203 | __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); |
204 | iounmap(usb_base); |
205 | return 0; |
206 | } |
207 | |
208 | static struct mxc_usbh_platform_data dr_utmi_config = { |
209 | .init = initialize_otg_port, |
210 | .portsc = MXC_EHCI_UTMI_16BIT, |
211 | .flags = MXC_EHCI_INTERNAL_PHY, |
212 | }; |
213 | |
214 | static struct fsl_usb2_platform_data usb_pdata = { |
215 | .operating_mode = FSL_USB2_DR_DEVICE, |
216 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, |
217 | }; |
218 | |
219 | static struct mxc_usbh_platform_data usbh1_config = { |
220 | .init = initialize_usbh1_port, |
221 | .portsc = MXC_EHCI_MODE_ULPI, |
222 | .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), |
223 | }; |
224 | |
225 | static int otg_mode_host; |
226 | |
227 | static int __init eukrea_cpuimx51_otg_mode(char *options) |
228 | { |
229 | if (!strcmp(options, "host")) |
230 | otg_mode_host = 1; |
231 | else if (!strcmp(options, "device")) |
232 | otg_mode_host = 0; |
233 | else |
234 | pr_info("otg_mode neither \"host\" nor \"device\". " |
235 | "Defaulting to device\n"); |
236 | return 0; |
237 | } |
238 | __setup("otg_mode=", eukrea_cpuimx51_otg_mode); |
239 | |
240 | /* |
241 | * Board specific initialization. |
242 | */ |
243 | static void __init eukrea_cpuimx51_init(void) |
244 | { |
245 | mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, |
246 | ARRAY_SIZE(eukrea_cpuimx51_pads)); |
247 | |
248 | imx51_add_imx_uart(0, &uart_pdata); |
249 | imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info); |
250 | |
251 | gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); |
252 | gpio_direction_input(CPUIMX51_QUARTA_GPIO); |
253 | gpio_free(CPUIMX51_QUARTA_GPIO); |
254 | gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq"); |
255 | gpio_direction_input(CPUIMX51_QUARTB_GPIO); |
256 | gpio_free(CPUIMX51_QUARTB_GPIO); |
257 | gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq"); |
258 | gpio_direction_input(CPUIMX51_QUARTC_GPIO); |
259 | gpio_free(CPUIMX51_QUARTC_GPIO); |
260 | gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq"); |
261 | gpio_direction_input(CPUIMX51_QUARTD_GPIO); |
262 | gpio_free(CPUIMX51_QUARTD_GPIO); |
263 | |
264 | imx51_add_fec(NULL); |
265 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
266 | |
267 | imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data); |
268 | i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, |
269 | ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); |
270 | |
271 | if (otg_mode_host) |
272 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); |
273 | else { |
274 | initialize_otg_port(NULL); |
275 | mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); |
276 | } |
277 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); |
278 | |
279 | #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD |
280 | eukrea_mbimx51_baseboard_init(); |
281 | #endif |
282 | } |
283 | |
284 | static void __init eukrea_cpuimx51_timer_init(void) |
285 | { |
286 | mx51_clocks_init(32768, 24000000, 22579200, 0); |
287 | } |
288 | |
289 | static struct sys_timer mxc_timer = { |
290 | .init = eukrea_cpuimx51_timer_init, |
291 | }; |
292 | |
293 | MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") |
294 | /* Maintainer: Eric Bénard <eric@eukrea.com> */ |
295 | .boot_params = PHYS_OFFSET + 0x100, |
296 | .map_io = mx51_map_io, |
297 | .init_irq = mx51_init_irq, |
298 | .init_machine = eukrea_cpuimx51_init, |
299 | .timer = &mxc_timer, |
300 | MACHINE_END |
301 |
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