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1 | /* |
2 | * Hardware modules present on the OMAP44xx chips |
3 | * |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * |
7 | * Paul Walmsley |
8 | * Benoit Cousson |
9 | * |
10 | * This file is automatically generated from the OMAP hardware databases. |
11 | * We respectfully ask that any modifications to this file be coordinated |
12 | * with the public linux-omap@vger.kernel.org mailing list and the |
13 | * authors above to ensure that the autogeneration scripts are kept |
14 | * up-to-date with the file contents. |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify |
17 | * it under the terms of the GNU General Public License version 2 as |
18 | * published by the Free Software Foundation. |
19 | */ |
20 | |
21 | #include <linux/io.h> |
22 | |
23 | #include <plat/omap_hwmod.h> |
24 | #include <plat/cpu.h> |
25 | |
26 | #include "omap_hwmod_common_data.h" |
27 | |
28 | #include "cm.h" |
29 | #include "prm-regbits-44xx.h" |
30 | |
31 | /* Base offset for all OMAP4 interrupts external to MPUSS */ |
32 | #define OMAP44XX_IRQ_GIC_START 32 |
33 | |
34 | /* Base offset for all OMAP4 dma requests */ |
35 | #define OMAP44XX_DMA_REQ_START 1 |
36 | |
37 | /* Backward references (IPs with Bus Master capability) */ |
38 | static struct omap_hwmod omap44xx_dmm_hwmod; |
39 | static struct omap_hwmod omap44xx_emif_fw_hwmod; |
40 | static struct omap_hwmod omap44xx_l3_instr_hwmod; |
41 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; |
42 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; |
43 | static struct omap_hwmod omap44xx_l3_main_3_hwmod; |
44 | static struct omap_hwmod omap44xx_l4_abe_hwmod; |
45 | static struct omap_hwmod omap44xx_l4_cfg_hwmod; |
46 | static struct omap_hwmod omap44xx_l4_per_hwmod; |
47 | static struct omap_hwmod omap44xx_l4_wkup_hwmod; |
48 | static struct omap_hwmod omap44xx_mpu_hwmod; |
49 | static struct omap_hwmod omap44xx_mpu_private_hwmod; |
50 | |
51 | /* |
52 | * Interconnects omap_hwmod structures |
53 | * hwmods that compose the global OMAP interconnect |
54 | */ |
55 | |
56 | /* |
57 | * 'dmm' class |
58 | * instance(s): dmm |
59 | */ |
60 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { |
61 | .name = "dmm", |
62 | }; |
63 | |
64 | /* dmm interface data */ |
65 | /* l3_main_1 -> dmm */ |
66 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { |
67 | .master = &omap44xx_l3_main_1_hwmod, |
68 | .slave = &omap44xx_dmm_hwmod, |
69 | .clk = "l3_div_ck", |
70 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
71 | }; |
72 | |
73 | /* mpu -> dmm */ |
74 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { |
75 | .master = &omap44xx_mpu_hwmod, |
76 | .slave = &omap44xx_dmm_hwmod, |
77 | .clk = "l3_div_ck", |
78 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
79 | }; |
80 | |
81 | /* dmm slave ports */ |
82 | static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { |
83 | &omap44xx_l3_main_1__dmm, |
84 | &omap44xx_mpu__dmm, |
85 | }; |
86 | |
87 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { |
88 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, |
89 | }; |
90 | |
91 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
92 | .name = "dmm", |
93 | .class = &omap44xx_dmm_hwmod_class, |
94 | .slaves = omap44xx_dmm_slaves, |
95 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), |
96 | .mpu_irqs = omap44xx_dmm_irqs, |
97 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), |
98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
99 | }; |
100 | |
101 | /* |
102 | * 'emif_fw' class |
103 | * instance(s): emif_fw |
104 | */ |
105 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { |
106 | .name = "emif_fw", |
107 | }; |
108 | |
109 | /* emif_fw interface data */ |
110 | /* dmm -> emif_fw */ |
111 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { |
112 | .master = &omap44xx_dmm_hwmod, |
113 | .slave = &omap44xx_emif_fw_hwmod, |
114 | .clk = "l3_div_ck", |
115 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
116 | }; |
117 | |
118 | /* l4_cfg -> emif_fw */ |
119 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { |
120 | .master = &omap44xx_l4_cfg_hwmod, |
121 | .slave = &omap44xx_emif_fw_hwmod, |
122 | .clk = "l4_div_ck", |
123 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
124 | }; |
125 | |
126 | /* emif_fw slave ports */ |
127 | static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { |
128 | &omap44xx_dmm__emif_fw, |
129 | &omap44xx_l4_cfg__emif_fw, |
130 | }; |
131 | |
132 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
133 | .name = "emif_fw", |
134 | .class = &omap44xx_emif_fw_hwmod_class, |
135 | .slaves = omap44xx_emif_fw_slaves, |
136 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), |
137 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
138 | }; |
139 | |
140 | /* |
141 | * 'l3' class |
142 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 |
143 | */ |
144 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { |
145 | .name = "l3", |
146 | }; |
147 | |
148 | /* l3_instr interface data */ |
149 | /* l3_main_3 -> l3_instr */ |
150 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { |
151 | .master = &omap44xx_l3_main_3_hwmod, |
152 | .slave = &omap44xx_l3_instr_hwmod, |
153 | .clk = "l3_div_ck", |
154 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
155 | }; |
156 | |
157 | /* l3_instr slave ports */ |
158 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { |
159 | &omap44xx_l3_main_3__l3_instr, |
160 | }; |
161 | |
162 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
163 | .name = "l3_instr", |
164 | .class = &omap44xx_l3_hwmod_class, |
165 | .slaves = omap44xx_l3_instr_slaves, |
166 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), |
167 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
168 | }; |
169 | |
170 | /* l3_main_2 -> l3_main_1 */ |
171 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { |
172 | .master = &omap44xx_l3_main_2_hwmod, |
173 | .slave = &omap44xx_l3_main_1_hwmod, |
174 | .clk = "l3_div_ck", |
175 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
176 | }; |
177 | |
178 | /* l4_cfg -> l3_main_1 */ |
179 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { |
180 | .master = &omap44xx_l4_cfg_hwmod, |
181 | .slave = &omap44xx_l3_main_1_hwmod, |
182 | .clk = "l4_div_ck", |
183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
184 | }; |
185 | |
186 | /* mpu -> l3_main_1 */ |
187 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { |
188 | .master = &omap44xx_mpu_hwmod, |
189 | .slave = &omap44xx_l3_main_1_hwmod, |
190 | .clk = "l3_div_ck", |
191 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
192 | }; |
193 | |
194 | /* l3_main_1 slave ports */ |
195 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { |
196 | &omap44xx_l3_main_2__l3_main_1, |
197 | &omap44xx_l4_cfg__l3_main_1, |
198 | &omap44xx_mpu__l3_main_1, |
199 | }; |
200 | |
201 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
202 | .name = "l3_main_1", |
203 | .class = &omap44xx_l3_hwmod_class, |
204 | .slaves = omap44xx_l3_main_1_slaves, |
205 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), |
206 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
207 | }; |
208 | |
209 | /* l3_main_2 interface data */ |
210 | /* l3_main_1 -> l3_main_2 */ |
211 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { |
212 | .master = &omap44xx_l3_main_1_hwmod, |
213 | .slave = &omap44xx_l3_main_2_hwmod, |
214 | .clk = "l3_div_ck", |
215 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
216 | }; |
217 | |
218 | /* l4_cfg -> l3_main_2 */ |
219 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { |
220 | .master = &omap44xx_l4_cfg_hwmod, |
221 | .slave = &omap44xx_l3_main_2_hwmod, |
222 | .clk = "l4_div_ck", |
223 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
224 | }; |
225 | |
226 | /* l3_main_2 slave ports */ |
227 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { |
228 | &omap44xx_l3_main_1__l3_main_2, |
229 | &omap44xx_l4_cfg__l3_main_2, |
230 | }; |
231 | |
232 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
233 | .name = "l3_main_2", |
234 | .class = &omap44xx_l3_hwmod_class, |
235 | .slaves = omap44xx_l3_main_2_slaves, |
236 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), |
237 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
238 | }; |
239 | |
240 | /* l3_main_3 interface data */ |
241 | /* l3_main_1 -> l3_main_3 */ |
242 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { |
243 | .master = &omap44xx_l3_main_1_hwmod, |
244 | .slave = &omap44xx_l3_main_3_hwmod, |
245 | .clk = "l3_div_ck", |
246 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
247 | }; |
248 | |
249 | /* l3_main_2 -> l3_main_3 */ |
250 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { |
251 | .master = &omap44xx_l3_main_2_hwmod, |
252 | .slave = &omap44xx_l3_main_3_hwmod, |
253 | .clk = "l3_div_ck", |
254 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
255 | }; |
256 | |
257 | /* l4_cfg -> l3_main_3 */ |
258 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { |
259 | .master = &omap44xx_l4_cfg_hwmod, |
260 | .slave = &omap44xx_l3_main_3_hwmod, |
261 | .clk = "l4_div_ck", |
262 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
263 | }; |
264 | |
265 | /* l3_main_3 slave ports */ |
266 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { |
267 | &omap44xx_l3_main_1__l3_main_3, |
268 | &omap44xx_l3_main_2__l3_main_3, |
269 | &omap44xx_l4_cfg__l3_main_3, |
270 | }; |
271 | |
272 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
273 | .name = "l3_main_3", |
274 | .class = &omap44xx_l3_hwmod_class, |
275 | .slaves = omap44xx_l3_main_3_slaves, |
276 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), |
277 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
278 | }; |
279 | |
280 | /* |
281 | * 'l4' class |
282 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup |
283 | */ |
284 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { |
285 | .name = "l4", |
286 | }; |
287 | |
288 | /* l4_abe interface data */ |
289 | /* l3_main_1 -> l4_abe */ |
290 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { |
291 | .master = &omap44xx_l3_main_1_hwmod, |
292 | .slave = &omap44xx_l4_abe_hwmod, |
293 | .clk = "l3_div_ck", |
294 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
295 | }; |
296 | |
297 | /* mpu -> l4_abe */ |
298 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { |
299 | .master = &omap44xx_mpu_hwmod, |
300 | .slave = &omap44xx_l4_abe_hwmod, |
301 | .clk = "ocp_abe_iclk", |
302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
303 | }; |
304 | |
305 | /* l4_abe slave ports */ |
306 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { |
307 | &omap44xx_l3_main_1__l4_abe, |
308 | &omap44xx_mpu__l4_abe, |
309 | }; |
310 | |
311 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
312 | .name = "l4_abe", |
313 | .class = &omap44xx_l4_hwmod_class, |
314 | .slaves = omap44xx_l4_abe_slaves, |
315 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), |
316 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
317 | }; |
318 | |
319 | /* l4_cfg interface data */ |
320 | /* l3_main_1 -> l4_cfg */ |
321 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { |
322 | .master = &omap44xx_l3_main_1_hwmod, |
323 | .slave = &omap44xx_l4_cfg_hwmod, |
324 | .clk = "l3_div_ck", |
325 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
326 | }; |
327 | |
328 | /* l4_cfg slave ports */ |
329 | static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { |
330 | &omap44xx_l3_main_1__l4_cfg, |
331 | }; |
332 | |
333 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
334 | .name = "l4_cfg", |
335 | .class = &omap44xx_l4_hwmod_class, |
336 | .slaves = omap44xx_l4_cfg_slaves, |
337 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), |
338 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
339 | }; |
340 | |
341 | /* l4_per interface data */ |
342 | /* l3_main_2 -> l4_per */ |
343 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { |
344 | .master = &omap44xx_l3_main_2_hwmod, |
345 | .slave = &omap44xx_l4_per_hwmod, |
346 | .clk = "l3_div_ck", |
347 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
348 | }; |
349 | |
350 | /* l4_per slave ports */ |
351 | static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { |
352 | &omap44xx_l3_main_2__l4_per, |
353 | }; |
354 | |
355 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
356 | .name = "l4_per", |
357 | .class = &omap44xx_l4_hwmod_class, |
358 | .slaves = omap44xx_l4_per_slaves, |
359 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), |
360 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
361 | }; |
362 | |
363 | /* l4_wkup interface data */ |
364 | /* l4_cfg -> l4_wkup */ |
365 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { |
366 | .master = &omap44xx_l4_cfg_hwmod, |
367 | .slave = &omap44xx_l4_wkup_hwmod, |
368 | .clk = "l4_div_ck", |
369 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
370 | }; |
371 | |
372 | /* l4_wkup slave ports */ |
373 | static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { |
374 | &omap44xx_l4_cfg__l4_wkup, |
375 | }; |
376 | |
377 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
378 | .name = "l4_wkup", |
379 | .class = &omap44xx_l4_hwmod_class, |
380 | .slaves = omap44xx_l4_wkup_slaves, |
381 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), |
382 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
383 | }; |
384 | |
385 | /* |
386 | * 'mpu_bus' class |
387 | * instance(s): mpu_private |
388 | */ |
389 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
390 | .name = "mpu_bus", |
391 | }; |
392 | |
393 | /* mpu_private interface data */ |
394 | /* mpu -> mpu_private */ |
395 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { |
396 | .master = &omap44xx_mpu_hwmod, |
397 | .slave = &omap44xx_mpu_private_hwmod, |
398 | .clk = "l3_div_ck", |
399 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
400 | }; |
401 | |
402 | /* mpu_private slave ports */ |
403 | static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { |
404 | &omap44xx_mpu__mpu_private, |
405 | }; |
406 | |
407 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
408 | .name = "mpu_private", |
409 | .class = &omap44xx_mpu_bus_hwmod_class, |
410 | .slaves = omap44xx_mpu_private_slaves, |
411 | .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), |
412 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
413 | }; |
414 | |
415 | /* |
416 | * 'mpu' class |
417 | * mpu sub-system |
418 | */ |
419 | |
420 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { |
421 | .name = "mpu", |
422 | }; |
423 | |
424 | /* mpu */ |
425 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { |
426 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, |
427 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, |
428 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, |
429 | }; |
430 | |
431 | /* mpu master ports */ |
432 | static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { |
433 | &omap44xx_mpu__l3_main_1, |
434 | &omap44xx_mpu__l4_abe, |
435 | &omap44xx_mpu__dmm, |
436 | }; |
437 | |
438 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
439 | .name = "mpu", |
440 | .class = &omap44xx_mpu_hwmod_class, |
441 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
442 | .mpu_irqs = omap44xx_mpu_irqs, |
443 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), |
444 | .main_clk = "dpll_mpu_m2_ck", |
445 | .prcm = { |
446 | .omap4 = { |
447 | .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, |
448 | }, |
449 | }, |
450 | .masters = omap44xx_mpu_masters, |
451 | .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), |
452 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
453 | }; |
454 | |
455 | /* |
456 | * 'wd_timer' class |
457 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
458 | * overflow condition |
459 | */ |
460 | |
461 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { |
462 | .rev_offs = 0x0000, |
463 | .sysc_offs = 0x0010, |
464 | .syss_offs = 0x0014, |
465 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | |
466 | SYSC_HAS_SOFTRESET), |
467 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
468 | .sysc_fields = &omap_hwmod_sysc_type1, |
469 | }; |
470 | |
471 | /* |
472 | * 'uart' class |
473 | * universal asynchronous receiver/transmitter (uart) |
474 | */ |
475 | |
476 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
477 | .rev_offs = 0x0050, |
478 | .sysc_offs = 0x0054, |
479 | .syss_offs = 0x0058, |
480 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
481 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
482 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
483 | .sysc_fields = &omap_hwmod_sysc_type1, |
484 | }; |
485 | |
486 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
487 | .name = "wd_timer", |
488 | .sysc = &omap44xx_wd_timer_sysc, |
489 | }; |
490 | |
491 | /* wd_timer2 */ |
492 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; |
493 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
494 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, |
495 | }; |
496 | |
497 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
498 | { |
499 | .pa_start = 0x4a314000, |
500 | .pa_end = 0x4a31407f, |
501 | .flags = ADDR_TYPE_RT |
502 | }, |
503 | }; |
504 | |
505 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
506 | .name = "uart", |
507 | .sysc = &omap44xx_uart_sysc, |
508 | }; |
509 | |
510 | /* uart1 */ |
511 | static struct omap_hwmod omap44xx_uart1_hwmod; |
512 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
513 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, |
514 | }; |
515 | |
516 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
517 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, |
518 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, |
519 | }; |
520 | |
521 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
522 | { |
523 | .pa_start = 0x4806a000, |
524 | .pa_end = 0x4806a0ff, |
525 | .flags = ADDR_TYPE_RT |
526 | }, |
527 | }; |
528 | |
529 | /* l4_per -> uart1 */ |
530 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { |
531 | .master = &omap44xx_l4_per_hwmod, |
532 | .slave = &omap44xx_uart1_hwmod, |
533 | .clk = "l4_div_ck", |
534 | .addr = omap44xx_uart1_addrs, |
535 | .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), |
536 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
537 | }; |
538 | |
539 | /* uart1 slave ports */ |
540 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { |
541 | &omap44xx_l4_per__uart1, |
542 | }; |
543 | |
544 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
545 | .name = "uart1", |
546 | .class = &omap44xx_uart_hwmod_class, |
547 | .mpu_irqs = omap44xx_uart1_irqs, |
548 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), |
549 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
550 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), |
551 | .main_clk = "uart1_fck", |
552 | .prcm = { |
553 | .omap4 = { |
554 | .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
555 | }, |
556 | }, |
557 | .slaves = omap44xx_uart1_slaves, |
558 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), |
559 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
560 | }; |
561 | |
562 | /* uart2 */ |
563 | static struct omap_hwmod omap44xx_uart2_hwmod; |
564 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
565 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, |
566 | }; |
567 | |
568 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
569 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, |
570 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, |
571 | }; |
572 | |
573 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
574 | { |
575 | .pa_start = 0x4806c000, |
576 | .pa_end = 0x4806c0ff, |
577 | .flags = ADDR_TYPE_RT |
578 | }, |
579 | }; |
580 | |
581 | /* l4_wkup -> wd_timer2 */ |
582 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { |
583 | .master = &omap44xx_l4_wkup_hwmod, |
584 | .slave = &omap44xx_wd_timer2_hwmod, |
585 | .clk = "l4_wkup_clk_mux_ck", |
586 | .addr = omap44xx_wd_timer2_addrs, |
587 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), |
588 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
589 | }; |
590 | |
591 | /* wd_timer2 slave ports */ |
592 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { |
593 | &omap44xx_l4_wkup__wd_timer2, |
594 | }; |
595 | |
596 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
597 | .name = "wd_timer2", |
598 | .class = &omap44xx_wd_timer_hwmod_class, |
599 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
600 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), |
601 | .main_clk = "wd_timer2_fck", |
602 | .prcm = { |
603 | .omap4 = { |
604 | .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
605 | }, |
606 | }, |
607 | .slaves = omap44xx_wd_timer2_slaves, |
608 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), |
609 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
610 | }; |
611 | |
612 | /* wd_timer3 */ |
613 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; |
614 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
615 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, |
616 | }; |
617 | |
618 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
619 | { |
620 | .pa_start = 0x40130000, |
621 | .pa_end = 0x4013007f, |
622 | .flags = ADDR_TYPE_RT |
623 | }, |
624 | }; |
625 | |
626 | /* l4_per -> uart2 */ |
627 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { |
628 | .master = &omap44xx_l4_per_hwmod, |
629 | .slave = &omap44xx_uart2_hwmod, |
630 | .clk = "l4_div_ck", |
631 | .addr = omap44xx_uart2_addrs, |
632 | .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), |
633 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
634 | }; |
635 | |
636 | /* uart2 slave ports */ |
637 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { |
638 | &omap44xx_l4_per__uart2, |
639 | }; |
640 | |
641 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
642 | .name = "uart2", |
643 | .class = &omap44xx_uart_hwmod_class, |
644 | .mpu_irqs = omap44xx_uart2_irqs, |
645 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), |
646 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
647 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), |
648 | .main_clk = "uart2_fck", |
649 | .prcm = { |
650 | .omap4 = { |
651 | .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
652 | }, |
653 | }, |
654 | .slaves = omap44xx_uart2_slaves, |
655 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), |
656 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
657 | }; |
658 | |
659 | /* uart3 */ |
660 | static struct omap_hwmod omap44xx_uart3_hwmod; |
661 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
662 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, |
663 | }; |
664 | |
665 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
666 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, |
667 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, |
668 | }; |
669 | |
670 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
671 | { |
672 | .pa_start = 0x48020000, |
673 | .pa_end = 0x480200ff, |
674 | .flags = ADDR_TYPE_RT |
675 | }, |
676 | }; |
677 | |
678 | /* l4_abe -> wd_timer3 */ |
679 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { |
680 | .master = &omap44xx_l4_abe_hwmod, |
681 | .slave = &omap44xx_wd_timer3_hwmod, |
682 | .clk = "ocp_abe_iclk", |
683 | .addr = omap44xx_wd_timer3_addrs, |
684 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), |
685 | .user = OCP_USER_MPU, |
686 | }; |
687 | |
688 | /* l4_abe -> wd_timer3 (dma) */ |
689 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
690 | { |
691 | .pa_start = 0x49030000, |
692 | .pa_end = 0x4903007f, |
693 | .flags = ADDR_TYPE_RT |
694 | }, |
695 | }; |
696 | |
697 | /* l4_per -> uart3 */ |
698 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { |
699 | .master = &omap44xx_l4_per_hwmod, |
700 | .slave = &omap44xx_uart3_hwmod, |
701 | .clk = "l4_div_ck", |
702 | .addr = omap44xx_uart3_addrs, |
703 | .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), |
704 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
705 | }; |
706 | |
707 | /* uart3 slave ports */ |
708 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { |
709 | &omap44xx_l4_per__uart3, |
710 | }; |
711 | |
712 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
713 | .name = "uart3", |
714 | .class = &omap44xx_uart_hwmod_class, |
715 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
716 | .mpu_irqs = omap44xx_uart3_irqs, |
717 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), |
718 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
719 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), |
720 | .main_clk = "uart3_fck", |
721 | .prcm = { |
722 | .omap4 = { |
723 | .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
724 | }, |
725 | }, |
726 | .slaves = omap44xx_uart3_slaves, |
727 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), |
728 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
729 | }; |
730 | |
731 | /* uart4 */ |
732 | static struct omap_hwmod omap44xx_uart4_hwmod; |
733 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
734 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, |
735 | }; |
736 | |
737 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
738 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, |
739 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, |
740 | }; |
741 | |
742 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
743 | { |
744 | .pa_start = 0x4806e000, |
745 | .pa_end = 0x4806e0ff, |
746 | .flags = ADDR_TYPE_RT |
747 | }, |
748 | }; |
749 | |
750 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { |
751 | .master = &omap44xx_l4_abe_hwmod, |
752 | .slave = &omap44xx_wd_timer3_hwmod, |
753 | .clk = "ocp_abe_iclk", |
754 | .addr = omap44xx_wd_timer3_dma_addrs, |
755 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), |
756 | .user = OCP_USER_SDMA, |
757 | }; |
758 | |
759 | /* wd_timer3 slave ports */ |
760 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { |
761 | &omap44xx_l4_abe__wd_timer3, |
762 | &omap44xx_l4_abe__wd_timer3_dma, |
763 | }; |
764 | |
765 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
766 | .name = "wd_timer3", |
767 | .class = &omap44xx_wd_timer_hwmod_class, |
768 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
769 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), |
770 | .main_clk = "wd_timer3_fck", |
771 | .prcm = { |
772 | .omap4 = { |
773 | .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
774 | }, |
775 | }, |
776 | .slaves = omap44xx_wd_timer3_slaves, |
777 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), |
778 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
779 | }; |
780 | |
781 | /* l4_per -> uart4 */ |
782 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { |
783 | .master = &omap44xx_l4_per_hwmod, |
784 | .slave = &omap44xx_uart4_hwmod, |
785 | .clk = "l4_div_ck", |
786 | .addr = omap44xx_uart4_addrs, |
787 | .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), |
788 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
789 | }; |
790 | |
791 | /* uart4 slave ports */ |
792 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { |
793 | &omap44xx_l4_per__uart4, |
794 | }; |
795 | |
796 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
797 | .name = "uart4", |
798 | .class = &omap44xx_uart_hwmod_class, |
799 | .mpu_irqs = omap44xx_uart4_irqs, |
800 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), |
801 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
802 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), |
803 | .main_clk = "uart4_fck", |
804 | .prcm = { |
805 | .omap4 = { |
806 | .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
807 | }, |
808 | }, |
809 | .slaves = omap44xx_uart4_slaves, |
810 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), |
811 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
812 | }; |
813 | |
814 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
815 | /* dmm class */ |
816 | &omap44xx_dmm_hwmod, |
817 | /* emif_fw class */ |
818 | &omap44xx_emif_fw_hwmod, |
819 | /* l3 class */ |
820 | &omap44xx_l3_instr_hwmod, |
821 | &omap44xx_l3_main_1_hwmod, |
822 | &omap44xx_l3_main_2_hwmod, |
823 | &omap44xx_l3_main_3_hwmod, |
824 | /* l4 class */ |
825 | &omap44xx_l4_abe_hwmod, |
826 | &omap44xx_l4_cfg_hwmod, |
827 | &omap44xx_l4_per_hwmod, |
828 | &omap44xx_l4_wkup_hwmod, |
829 | /* mpu_bus class */ |
830 | &omap44xx_mpu_private_hwmod, |
831 | |
832 | /* mpu class */ |
833 | &omap44xx_mpu_hwmod, |
834 | /* wd_timer class */ |
835 | &omap44xx_wd_timer2_hwmod, |
836 | &omap44xx_wd_timer3_hwmod, |
837 | |
838 | /* uart class */ |
839 | &omap44xx_uart1_hwmod, |
840 | &omap44xx_uart2_hwmod, |
841 | &omap44xx_uart3_hwmod, |
842 | &omap44xx_uart4_hwmod, |
843 | NULL, |
844 | }; |
845 | |
846 | int __init omap44xx_hwmod_init(void) |
847 | { |
848 | return omap_hwmod_init(omap44xx_hwmods); |
849 | } |
850 | |
851 |
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