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1 | /* |
2 | * OMAP2 Power Management Routines |
3 | * |
4 | * Copyright (C) 2005 Texas Instruments, Inc. |
5 | * Copyright (C) 2006-2008 Nokia Corporation |
6 | * |
7 | * Written by: |
8 | * Richard Woodruff <r-woodruff2@ti.com> |
9 | * Tony Lindgren |
10 | * Juha Yrjola |
11 | * Amit Kucheria <amit.kucheria@nokia.com> |
12 | * Igor Stoppa <igor.stoppa@nokia.com> |
13 | * |
14 | * Based on pm.c for omap1 |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify |
17 | * it under the terms of the GNU General Public License version 2 as |
18 | * published by the Free Software Foundation. |
19 | */ |
20 | |
21 | #include <linux/suspend.h> |
22 | #include <linux/sched.h> |
23 | #include <linux/proc_fs.h> |
24 | #include <linux/interrupt.h> |
25 | #include <linux/sysfs.h> |
26 | #include <linux/module.h> |
27 | #include <linux/delay.h> |
28 | #include <linux/clk.h> |
29 | #include <linux/io.h> |
30 | #include <linux/irq.h> |
31 | #include <linux/time.h> |
32 | #include <linux/gpio.h> |
33 | #include <linux/console.h> |
34 | |
35 | #include <asm/mach/time.h> |
36 | #include <asm/mach/irq.h> |
37 | #include <asm/mach-types.h> |
38 | |
39 | #include <mach/irqs.h> |
40 | #include <plat/clock.h> |
41 | #include <plat/sram.h> |
42 | #include <plat/dma.h> |
43 | #include <plat/board.h> |
44 | |
45 | #include "prm.h" |
46 | #include "prm-regbits-24xx.h" |
47 | #include "cm.h" |
48 | #include "cm-regbits-24xx.h" |
49 | #include "sdrc.h" |
50 | #include "pm.h" |
51 | #include "control.h" |
52 | |
53 | #include <plat/powerdomain.h> |
54 | #include <plat/clockdomain.h> |
55 | |
56 | #ifdef CONFIG_SUSPEND |
57 | static suspend_state_t suspend_state = PM_SUSPEND_ON; |
58 | static inline bool is_suspending(void) |
59 | { |
60 | return (suspend_state != PM_SUSPEND_ON); |
61 | } |
62 | #else |
63 | static inline bool is_suspending(void) |
64 | { |
65 | return false; |
66 | } |
67 | #endif |
68 | |
69 | static void (*omap2_sram_idle)(void); |
70 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, |
71 | void __iomem *sdrc_power); |
72 | |
73 | static struct powerdomain *mpu_pwrdm, *core_pwrdm; |
74 | static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; |
75 | |
76 | static struct clk *osc_ck, *emul_ck; |
77 | |
78 | static int omap2_fclks_active(void) |
79 | { |
80 | u32 f1, f2; |
81 | |
82 | f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
83 | f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
84 | |
85 | /* Ignore UART clocks. These are handled by UART core (serial.c) */ |
86 | f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); |
87 | f2 &= ~OMAP24XX_EN_UART3_MASK; |
88 | |
89 | if (f1 | f2) |
90 | return 1; |
91 | return 0; |
92 | } |
93 | |
94 | static void omap2_enter_full_retention(void) |
95 | { |
96 | u32 l; |
97 | struct timespec ts_preidle, ts_postidle, ts_idle; |
98 | |
99 | /* There is 1 reference hold for all children of the oscillator |
100 | * clock, the following will remove it. If no one else uses the |
101 | * oscillator itself it will be disabled if/when we enter retention |
102 | * mode. |
103 | */ |
104 | clk_disable(osc_ck); |
105 | |
106 | /* Clear old wake-up events */ |
107 | /* REVISIT: These write to reserved bits? */ |
108 | prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
109 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); |
110 | prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); |
111 | |
112 | /* |
113 | * Set MPU powerdomain's next power state to RETENTION; |
114 | * preserve logic state during retention |
115 | */ |
116 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); |
117 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
118 | |
119 | /* Workaround to kill USB */ |
120 | l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; |
121 | omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); |
122 | |
123 | omap2_gpio_prepare_for_idle(PWRDM_POWER_RET); |
124 | |
125 | if (omap2_pm_debug) { |
126 | omap2_pm_dump(0, 0, 0); |
127 | getnstimeofday(&ts_preidle); |
128 | } |
129 | |
130 | /* One last check for pending IRQs to avoid extra latency due |
131 | * to sleeping unnecessarily. */ |
132 | if (omap_irq_pending()) |
133 | goto no_sleep; |
134 | |
135 | /* Block console output in case it is on one of the OMAP UARTs */ |
136 | if (!is_suspending()) |
137 | if (try_acquire_console_sem()) |
138 | goto no_sleep; |
139 | |
140 | omap_uart_prepare_idle(0); |
141 | omap_uart_prepare_idle(1); |
142 | omap_uart_prepare_idle(2); |
143 | |
144 | /* Jump to SRAM suspend code */ |
145 | omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), |
146 | OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), |
147 | OMAP_SDRC_REGADDR(SDRC_POWER)); |
148 | |
149 | omap_uart_resume_idle(2); |
150 | omap_uart_resume_idle(1); |
151 | omap_uart_resume_idle(0); |
152 | |
153 | if (!is_suspending()) |
154 | release_console_sem(); |
155 | |
156 | no_sleep: |
157 | if (omap2_pm_debug) { |
158 | unsigned long long tmp; |
159 | |
160 | getnstimeofday(&ts_postidle); |
161 | ts_idle = timespec_sub(ts_postidle, ts_preidle); |
162 | tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; |
163 | omap2_pm_dump(0, 1, tmp); |
164 | } |
165 | omap2_gpio_resume_after_idle(); |
166 | |
167 | clk_enable(osc_ck); |
168 | |
169 | /* clear CORE wake-up events */ |
170 | prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
171 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); |
172 | |
173 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ |
174 | prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); |
175 | |
176 | /* MPU domain wake events */ |
177 | l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
178 | if (l & 0x01) |
179 | prm_write_mod_reg(0x01, OCP_MOD, |
180 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
181 | if (l & 0x20) |
182 | prm_write_mod_reg(0x20, OCP_MOD, |
183 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
184 | |
185 | /* Mask future PRCM-to-MPU interrupts */ |
186 | prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
187 | } |
188 | |
189 | static int omap2_i2c_active(void) |
190 | { |
191 | u32 l; |
192 | |
193 | l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
194 | return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); |
195 | } |
196 | |
197 | static int sti_console_enabled; |
198 | |
199 | static int omap2_allow_mpu_retention(void) |
200 | { |
201 | u32 l; |
202 | |
203 | /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ |
204 | l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
205 | if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | |
206 | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | |
207 | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) |
208 | return 0; |
209 | /* Check for UART3. */ |
210 | l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
211 | if (l & OMAP24XX_EN_UART3_MASK) |
212 | return 0; |
213 | if (sti_console_enabled) |
214 | return 0; |
215 | |
216 | return 1; |
217 | } |
218 | |
219 | static void omap2_enter_mpu_retention(void) |
220 | { |
221 | int only_idle = 0; |
222 | struct timespec ts_preidle, ts_postidle, ts_idle; |
223 | |
224 | /* Putting MPU into the WFI state while a transfer is active |
225 | * seems to cause the I2C block to timeout. Why? Good question. */ |
226 | if (omap2_i2c_active()) |
227 | return; |
228 | |
229 | /* The peripherals seem not to be able to wake up the MPU when |
230 | * it is in retention mode. */ |
231 | if (omap2_allow_mpu_retention()) { |
232 | /* REVISIT: These write to reserved bits? */ |
233 | prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
234 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); |
235 | prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); |
236 | |
237 | /* Try to enter MPU retention */ |
238 | prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | |
239 | OMAP_LOGICRETSTATE_MASK, |
240 | MPU_MOD, OMAP2_PM_PWSTCTRL); |
241 | } else { |
242 | /* Block MPU retention */ |
243 | |
244 | prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, |
245 | OMAP2_PM_PWSTCTRL); |
246 | only_idle = 1; |
247 | } |
248 | |
249 | if (omap2_pm_debug) { |
250 | omap2_pm_dump(only_idle ? 2 : 1, 0, 0); |
251 | getnstimeofday(&ts_preidle); |
252 | } |
253 | |
254 | omap2_sram_idle(); |
255 | |
256 | if (omap2_pm_debug) { |
257 | unsigned long long tmp; |
258 | |
259 | getnstimeofday(&ts_postidle); |
260 | ts_idle = timespec_sub(ts_postidle, ts_preidle); |
261 | tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; |
262 | omap2_pm_dump(only_idle ? 2 : 1, 1, tmp); |
263 | } |
264 | } |
265 | |
266 | static int omap2_can_sleep(void) |
267 | { |
268 | if (omap2_fclks_active()) |
269 | return 0; |
270 | if (!omap_uart_can_sleep()) |
271 | return 0; |
272 | if (osc_ck->usecount > 1) |
273 | return 0; |
274 | if (omap_dma_running()) |
275 | return 0; |
276 | |
277 | return 1; |
278 | } |
279 | |
280 | static void omap2_pm_idle(void) |
281 | { |
282 | local_irq_disable(); |
283 | local_fiq_disable(); |
284 | |
285 | if (!omap2_can_sleep()) { |
286 | if (omap_irq_pending()) |
287 | goto out; |
288 | omap2_enter_mpu_retention(); |
289 | goto out; |
290 | } |
291 | |
292 | if (omap_irq_pending()) |
293 | goto out; |
294 | |
295 | omap2_enter_full_retention(); |
296 | |
297 | out: |
298 | local_fiq_enable(); |
299 | local_irq_enable(); |
300 | } |
301 | |
302 | static int omap2_pm_begin(suspend_state_t state) |
303 | { |
304 | suspend_state = state; |
305 | return 0; |
306 | } |
307 | |
308 | static int omap2_pm_prepare(void) |
309 | { |
310 | /* We cannot sleep in idle until we have resumed */ |
311 | disable_hlt(); |
312 | return 0; |
313 | } |
314 | |
315 | static int omap2_pm_suspend(void) |
316 | { |
317 | u32 wken_wkup, mir1; |
318 | |
319 | wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); |
320 | wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; |
321 | prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); |
322 | |
323 | /* Mask GPT1 */ |
324 | mir1 = omap_readl(0x480fe0a4); |
325 | omap_writel(1 << 5, 0x480fe0ac); |
326 | |
327 | omap_uart_prepare_suspend(); |
328 | omap2_enter_full_retention(); |
329 | |
330 | omap_writel(mir1, 0x480fe0a4); |
331 | prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); |
332 | |
333 | return 0; |
334 | } |
335 | |
336 | static int omap2_pm_enter(suspend_state_t state) |
337 | { |
338 | int ret = 0; |
339 | |
340 | switch (state) { |
341 | case PM_SUSPEND_STANDBY: |
342 | case PM_SUSPEND_MEM: |
343 | ret = omap2_pm_suspend(); |
344 | break; |
345 | default: |
346 | ret = -EINVAL; |
347 | } |
348 | |
349 | return ret; |
350 | } |
351 | |
352 | static void omap2_pm_finish(void) |
353 | { |
354 | enable_hlt(); |
355 | } |
356 | |
357 | static void omap2_pm_end(void) |
358 | { |
359 | suspend_state = PM_SUSPEND_ON; |
360 | } |
361 | |
362 | static struct platform_suspend_ops omap_pm_ops = { |
363 | .begin = omap2_pm_begin, |
364 | .prepare = omap2_pm_prepare, |
365 | .enter = omap2_pm_enter, |
366 | .finish = omap2_pm_finish, |
367 | .end = omap2_pm_end, |
368 | .valid = suspend_valid_only_mem, |
369 | }; |
370 | |
371 | /* XXX This function should be shareable between OMAP2xxx and OMAP3 */ |
372 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
373 | { |
374 | clkdm_clear_all_wkdeps(clkdm); |
375 | clkdm_clear_all_sleepdeps(clkdm); |
376 | |
377 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) |
378 | omap2_clkdm_allow_idle(clkdm); |
379 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
380 | atomic_read(&clkdm->usecount) == 0) |
381 | omap2_clkdm_sleep(clkdm); |
382 | return 0; |
383 | } |
384 | |
385 | static void __init prcm_setup_regs(void) |
386 | { |
387 | int i, num_mem_banks; |
388 | struct powerdomain *pwrdm; |
389 | |
390 | /* Enable autoidle */ |
391 | prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, |
392 | OMAP2_PRCM_SYSCONFIG_OFFSET); |
393 | |
394 | /* |
395 | * Set CORE powerdomain memory banks to retain their contents |
396 | * during RETENTION |
397 | */ |
398 | num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm); |
399 | for (i = 0; i < num_mem_banks; i++) |
400 | pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); |
401 | |
402 | /* Set CORE powerdomain's next power state to RETENTION */ |
403 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); |
404 | |
405 | /* |
406 | * Set MPU powerdomain's next power state to RETENTION; |
407 | * preserve logic state during retention |
408 | */ |
409 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); |
410 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
411 | |
412 | /* Force-power down DSP, GFX powerdomains */ |
413 | |
414 | pwrdm = clkdm_get_pwrdm(dsp_clkdm); |
415 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); |
416 | omap2_clkdm_sleep(dsp_clkdm); |
417 | |
418 | pwrdm = clkdm_get_pwrdm(gfx_clkdm); |
419 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); |
420 | omap2_clkdm_sleep(gfx_clkdm); |
421 | |
422 | /* |
423 | * Clear clockdomain wakeup dependencies and enable |
424 | * hardware-supervised idle for all clkdms |
425 | */ |
426 | clkdm_for_each(clkdms_setup, NULL); |
427 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); |
428 | |
429 | /* Enable clock autoidle for all domains */ |
430 | cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | |
431 | OMAP24XX_AUTO_MAILBOXES_MASK | |
432 | OMAP24XX_AUTO_WDT4_MASK | |
433 | OMAP2420_AUTO_WDT3_MASK | |
434 | OMAP24XX_AUTO_MSPRO_MASK | |
435 | OMAP2420_AUTO_MMC_MASK | |
436 | OMAP24XX_AUTO_FAC_MASK | |
437 | OMAP2420_AUTO_EAC_MASK | |
438 | OMAP24XX_AUTO_HDQ_MASK | |
439 | OMAP24XX_AUTO_UART2_MASK | |
440 | OMAP24XX_AUTO_UART1_MASK | |
441 | OMAP24XX_AUTO_I2C2_MASK | |
442 | OMAP24XX_AUTO_I2C1_MASK | |
443 | OMAP24XX_AUTO_MCSPI2_MASK | |
444 | OMAP24XX_AUTO_MCSPI1_MASK | |
445 | OMAP24XX_AUTO_MCBSP2_MASK | |
446 | OMAP24XX_AUTO_MCBSP1_MASK | |
447 | OMAP24XX_AUTO_GPT12_MASK | |
448 | OMAP24XX_AUTO_GPT11_MASK | |
449 | OMAP24XX_AUTO_GPT10_MASK | |
450 | OMAP24XX_AUTO_GPT9_MASK | |
451 | OMAP24XX_AUTO_GPT8_MASK | |
452 | OMAP24XX_AUTO_GPT7_MASK | |
453 | OMAP24XX_AUTO_GPT6_MASK | |
454 | OMAP24XX_AUTO_GPT5_MASK | |
455 | OMAP24XX_AUTO_GPT4_MASK | |
456 | OMAP24XX_AUTO_GPT3_MASK | |
457 | OMAP24XX_AUTO_GPT2_MASK | |
458 | OMAP2420_AUTO_VLYNQ_MASK | |
459 | OMAP24XX_AUTO_DSS_MASK, |
460 | CORE_MOD, CM_AUTOIDLE1); |
461 | cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | |
462 | OMAP24XX_AUTO_SSI_MASK | |
463 | OMAP24XX_AUTO_USB_MASK, |
464 | CORE_MOD, CM_AUTOIDLE2); |
465 | cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | |
466 | OMAP24XX_AUTO_GPMC_MASK | |
467 | OMAP24XX_AUTO_SDMA_MASK, |
468 | CORE_MOD, CM_AUTOIDLE3); |
469 | cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | |
470 | OMAP24XX_AUTO_AES_MASK | |
471 | OMAP24XX_AUTO_RNG_MASK | |
472 | OMAP24XX_AUTO_SHA_MASK | |
473 | OMAP24XX_AUTO_DES_MASK, |
474 | CORE_MOD, OMAP24XX_CM_AUTOIDLE4); |
475 | |
476 | cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, |
477 | CM_AUTOIDLE); |
478 | |
479 | /* Put DPLL and both APLLs into autoidle mode */ |
480 | cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | |
481 | (0x03 << OMAP24XX_AUTO_96M_SHIFT) | |
482 | (0x03 << OMAP24XX_AUTO_54M_SHIFT), |
483 | PLL_MOD, CM_AUTOIDLE); |
484 | |
485 | cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | |
486 | OMAP24XX_AUTO_WDT1_MASK | |
487 | OMAP24XX_AUTO_MPU_WDT_MASK | |
488 | OMAP24XX_AUTO_GPIOS_MASK | |
489 | OMAP24XX_AUTO_32KSYNC_MASK | |
490 | OMAP24XX_AUTO_GPT1_MASK, |
491 | WKUP_MOD, CM_AUTOIDLE); |
492 | |
493 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk |
494 | * stabilisation */ |
495 | prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
496 | OMAP2_PRCM_CLKSSETUP_OFFSET); |
497 | |
498 | /* Configure automatic voltage transition */ |
499 | prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
500 | OMAP2_PRCM_VOLTSETUP_OFFSET); |
501 | prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | |
502 | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | |
503 | OMAP24XX_MEMRETCTRL_MASK | |
504 | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | |
505 | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), |
506 | OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); |
507 | |
508 | /* Enable wake-up events */ |
509 | prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, |
510 | WKUP_MOD, PM_WKEN); |
511 | } |
512 | |
513 | static int __init omap2_pm_init(void) |
514 | { |
515 | u32 l; |
516 | |
517 | if (!cpu_is_omap24xx()) |
518 | return -ENODEV; |
519 | |
520 | printk(KERN_INFO "Power Management for OMAP2 initializing\n"); |
521 | l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); |
522 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
523 | |
524 | /* Look up important powerdomains */ |
525 | |
526 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); |
527 | if (!mpu_pwrdm) |
528 | pr_err("PM: mpu_pwrdm not found\n"); |
529 | |
530 | core_pwrdm = pwrdm_lookup("core_pwrdm"); |
531 | if (!core_pwrdm) |
532 | pr_err("PM: core_pwrdm not found\n"); |
533 | |
534 | /* Look up important clockdomains */ |
535 | |
536 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); |
537 | if (!mpu_clkdm) |
538 | pr_err("PM: mpu_clkdm not found\n"); |
539 | |
540 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); |
541 | if (!wkup_clkdm) |
542 | pr_err("PM: wkup_clkdm not found\n"); |
543 | |
544 | dsp_clkdm = clkdm_lookup("dsp_clkdm"); |
545 | if (!dsp_clkdm) |
546 | pr_err("PM: dsp_clkdm not found\n"); |
547 | |
548 | gfx_clkdm = clkdm_lookup("gfx_clkdm"); |
549 | if (!gfx_clkdm) |
550 | pr_err("PM: gfx_clkdm not found\n"); |
551 | |
552 | |
553 | osc_ck = clk_get(NULL, "osc_ck"); |
554 | if (IS_ERR(osc_ck)) { |
555 | printk(KERN_ERR "could not get osc_ck\n"); |
556 | return -ENODEV; |
557 | } |
558 | |
559 | if (cpu_is_omap242x()) { |
560 | emul_ck = clk_get(NULL, "emul_ck"); |
561 | if (IS_ERR(emul_ck)) { |
562 | printk(KERN_ERR "could not get emul_ck\n"); |
563 | clk_put(osc_ck); |
564 | return -ENODEV; |
565 | } |
566 | } |
567 | |
568 | prcm_setup_regs(); |
569 | |
570 | /* Hack to prevent MPU retention when STI console is enabled. */ |
571 | { |
572 | const struct omap_sti_console_config *sti; |
573 | |
574 | sti = omap_get_config(OMAP_TAG_STI_CONSOLE, |
575 | struct omap_sti_console_config); |
576 | if (sti != NULL && sti->enable) |
577 | sti_console_enabled = 1; |
578 | } |
579 | |
580 | /* |
581 | * We copy the assembler sleep/wakeup routines to SRAM. |
582 | * These routines need to be in SRAM as that's the only |
583 | * memory the MPU can see when it wakes up. |
584 | */ |
585 | if (cpu_is_omap24xx()) { |
586 | omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend, |
587 | omap24xx_idle_loop_suspend_sz); |
588 | |
589 | omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, |
590 | omap24xx_cpu_suspend_sz); |
591 | } |
592 | |
593 | suspend_set_ops(&omap_pm_ops); |
594 | pm_idle = omap2_pm_idle; |
595 | |
596 | return 0; |
597 | } |
598 | |
599 | late_initcall(omap2_pm_init); |
600 |
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
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v3.9